FET dram with backside bit lines

Abstract

A semiconductor structure is provided that includes a backside bit line connected to a dynamic random access memory (DRAM) cell including a plurality of field effect transistors (FETs) and a plurality of DRAM capacitors present in a front side of the structure.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and more particularly to a semiconductor structure including a dynamic random access memory (DRAM) cell and a bit line connected to the back side of the DRAM cell. Background Art

[0002] A conventional vertical field effect transistor (VFET) is a device in which the source-drain current flows in a direction perpendicular to the substrate surface. In such a device, a vertical semiconductor fin (or pillar) defines a channel, with the source and drain located at opposite ends of the semiconductor fin (or pillar). VFETs are an attractive option for technology scaling beyond 7nm technology and have potential advantages over conventional FinFETs in terms of density, performance, power consumption, and integration. For example, VFETs can be used as components of DRAM cells, especially for 4F 2 DRAM cell of the cell structure. Summary of the invention

[0003] A semiconductor structure is provided that includes a backside bit line connected to a DRAM cell that includes a plurality of FETs and a plurality of DRAM capacitors present in the front side of the structure. The backside bit line is a conductive metal-containing material, so the structure of the present application has a low bit line resistance that meets current performance specifications. 2 In a conventional DRAM cell with a 3D-type structure, the bit line connected to the DRAM cell is a doped polysilicon layer, which results in a high bit line resistance, which does not meet current performance specifications.

[0004] In one aspect of the present application, a semiconductor structure is provided. In one embodiment of the present application, the semiconductor structure includes a DRAM cell, which includes a plurality of FETs and a plurality of DRAM capacitors, and at least one bit line composed of a conductive metal-containing material located on the back side of the DRAM cell. The term "back side" refers to a portion of the structure including backside wiring components (e.g., bit lines) that are located on a side of the wafer that does not include active devices (i.e., DRAM cells); active devices are present on the front side of the wafer, and the structure of the present application has low bit line capacitance as described above.

[0005] In the embodiment of the present application, the DRAM cell has a 4F 2 The unit cell area of ​​​​the present invention is , where F is equal to the gate half pitch. In the present application, F represents the characteristic size of the gate structure, and the gate pitch is determined by measuring the distance between one point of the gate structure and the same point of the adjacent gate structure. Therefore, the DRAM cell of the present invention has a high density.

[0006] In an embodiment of the present application, each DRAM capacitor in the plurality of DRAM capacitors is a stacked capacitor. Stacked capacitors allow a method of scaling DRAM cells and providing higher density in a smaller unit area.

[0007] In an embodiment of the present application, the structure may further include a back-end-of-line (BEOL) structure contacting the at least one bit line, wherein the back-end BEOL structure is a back-side power distribution network that delivers power to the FET.

[0008] In an embodiment of the present application, each FET in the plurality of FETs is a vertical FET (VFET) including a vertical semiconductor channel material structure, a gate structure located on each side of the vertical semiconductor channel material structure, a first source / drain region located at a first end of the vertical semiconductor channel material structure, and a second source / drain region located at a second end of the vertical semiconductor channel material structure, the second end of the vertical semiconductor channel material structure being opposite to the first end of the vertical semiconductor channel material structure. The FET including the vertical semiconductor channel material structure allows the formation of the above-mentioned 4F 2 Structure. In a VFET, current flows in a vertical direction through a vertical semiconductor channel material structure.

[0009] In an embodiment of the present application, the vertical semiconductor channel material structure, the first source / drain region and the second source / drain region are integrally constructed and are composed of the same semiconductor material. In other embodiments, the first source / drain region and the second source / drain region are formed (e.g., by epitaxial growth) at opposite ends of the vertical semiconductor channel material structure.

[0010] In an embodiment of the present application, the structure may further include a front side source / drain contact structure that contacts the first source / drain region and connects the first source / drain region to one of the DRAM capacitors in the plurality of DRAM capacitors.

[0011] In some embodiments of the present application, the at least one bit line is in direct contact with the second source / drain region. In other embodiments of the present application, the at least one bit line is in direct contact with a backside source / drain contact structure located on the second source / drain region.

[0012] In some embodiments of the present application, both the first source / drain region and the second source / drain region have non-faceted surfaces, which are opposite to the surfaces of the first source / drain region and the second source / drain region that are in contact with the vertical semiconductor channel material structure.

[0013] In some embodiments of the present application, the structure may further include a dielectric spacer positioned along a sidewall of the first source / drain region.

[0014] In some embodiments of the present application, each of the plurality of DRAM capacitors is embedded in a front-side back-end-of-line (BEOL) structure. In such embodiments, the structure may further include a carrier wafer located on the front-side BEOL structure. In such embodiments, the carrier wafer is separated from each of the plurality of DRAM capacitors by a portion of the front-side BEOL structure.

[0015] In some embodiments of the present application, each DRAM capacitor in the plurality of DRAM capacitors is present in the front-side interlayer dielectric material layer. In such embodiments, each DRAM capacitor extends completely through the front-side interlayer dielectric material layer. In such embodiments, the structure may further include a carrier wafer located on the front-side interlayer dielectric material layer.

[0016] In some embodiments of the present application, each FET includes a gate structure located on each side of a vertical semiconductor channel material structure, wherein the gate structure includes a gate dielectric material layer directly in contact with a sidewall of the vertical semiconductor channel material structure and a gate electrode positioned laterally adjacent to the gate dielectric material layer, wherein the gate electrode includes at least a work function metal layer. In such an embodiment, a gate polysilicon layer may be located between the gate dielectric material layer and the gate electrode.

[0017] In some embodiments of the present application, the structure may also include a first dielectric spacer located on the surface of the gate structure and in contact with the sidewall of the vertical semiconductor channel material structure and a second dielectric spacer located on the other surface of the gate structure and in contact with the sidewall of the vertical semiconductor channel material structure.

[0018] In addition to providing a semiconductor structure, the present application also provides a method of forming a semiconductor structure. The method of the present application including the backside and backside processing will be described in more detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a cross-sectional view of an exemplary structure that may be employed according to embodiments of the present application, the exemplary structure including a plurality of vertical semiconductor channel material structures extending upward from a surface of an etch stop layer located on a surface of a base semiconductor substrate.

[0020] Figure 2 After forming the first dielectric spacer Figure 1 In the cross-sectional view of the exemplary structure shown in , a first dielectric spacer contacts a lower portion of each of a plurality of vertical semiconductor channel material structures.

[0021] Figure 3After forming a gate structure material layer on the first dielectric spacer, along the sidewalls and on top of each vertical semiconductor channel material structure Figure 2 A cross-sectional view of an exemplary structure is shown.

[0022] Figure 4 After patterning the gate structure material layer to provide a gate structure along the sidewalls of each of the plurality of vertical semiconductor channel material structures Figure 3 A cross-sectional view of an exemplary structure shown in FIG.

[0023] Figure 5 After forming a first front-side interlayer dielectric (ILD) material layer laterally adjacent to each gate structure Figure 4 A cross-sectional view of an exemplary structure shown in FIG.

[0024] Figure 6 After removing the hard mask cap present on top of each of the plurality of vertical semiconductor channel material structures Figure 5 A cross-sectional view of an exemplary structure shown in FIG.

[0025] Figure 7 After recessing each gate structure to physically expose an upper sidewall portion of each vertical semiconductor channel material structure of the plurality of vertical semiconductor channel material structures Figure 6 A cross-sectional view of an exemplary structure shown in FIG.

[0026] Figure 8 after forming a second dielectric spacer laterally adjacent to a physically exposed upper sidewall portion of each of the plurality of vertical semiconductor channel material structures and forming a first source / drain region extending upwardly from a top surface of each of the plurality of vertical semiconductor channel material structures, Figure 7 A cross-sectional view of an exemplary structure shown in FIG.

[0027] Fig. 9 After forming a second front side ILD material layer having a front side contact structure embedded therein Figure 8 In the cross-sectional view of the exemplary structure shown in , each front side contact structure is in contact with one of the first source / drain regions.

[0028] Fig.10 After forming a front-side back-end-of-line (BEOL) structure in which the DRAM capacitors are embedded and forming a carrier wafer on the front-side BEOL structure, Fig. 9 A cross-sectional view of an exemplary structure is shown in which each DRAM capacitor contacts one of the front-side contact structures.

[0029] Fig.11After flipping the wafer 180° to physically expose the backside of the base semiconductor substrate Fig.10 A cross-sectional view of an exemplary structure shown in FIG.

[0030] Fig.12 After the base semiconductor substrate is removed to physically expose the etch stop layer Fig.11 A cross-sectional view of an exemplary structure shown in FIG.

[0031] Fig.13 After removing the etch stop layer to physically expose the horizontal surface of each vertical semiconductor channel material structure of the plurality of vertical semiconductor channel material structures Fig.12 A cross-sectional view of an exemplary structure shown in FIG.

[0032] Fig.14 After forming a second source / drain region on the physically exposed horizontal surface of each of the plurality of vertical semiconductor channel material structures Fig.13 A cross-sectional view of an exemplary structure shown in FIG.

[0033] Fig.15 yes Fig.14 The illustrated exemplary structure is a cross-sectional view after forming a backside bitline in contact with each second source / drain region and forming a backside BEOL structure on the backside bitlines.

[0034] Fig.16 is a cross-sectional view of an exemplary structure that may be employed in another embodiment of the present application, the exemplary structure including a base semiconductor substrate, an etch stop layer located on the base semiconductor substrate, and a semiconductor material layer having a plurality of upper platform portions located on the etch stop layer.

[0035] Fig.17 After forming a dielectric spacer along the sidewalls of at least each upper mesa portion of the semiconductor material layer Fig.16 A cross-sectional view of an exemplary structure is shown.

[0036] Fig.18 After patterning the semiconductor material layer using the dielectric spacer and the upper platform portion of the semiconductor material layer as a combined etch mask Fig.17 A cross-sectional view of the exemplary structure shown in FIG. 1 , wherein patterning forms a plurality of pillars of semiconductor material on a remaining portion of the semiconductor material layer.

[0037] Fig.19 After trimming each semiconductor material column to provide a vertical semiconductor material channel structure Fig.18 In the cross-sectional view of the exemplary structure shown in , each vertical semiconductor material channel structure is located between an upper mesa portion of the semiconductor material layer and a remaining portion of the semiconductor material layer.

[0038] Fig. 20 After the gate dielectric material layer and gate polysilicon layer are formed Fig.19 A cross-sectional view of an exemplary structure shown in FIG.

[0039] Fig.21 After performing a through etch process that removes the gate dielectric material layer, the remaining portion of the semiconductor material layer, the etch stop layer, and a portion of the base semiconductor substrate Fig. 20 A cross-sectional view of the exemplary structure shown in FIG. 1 ; the remaining semiconductor material layer that is not etched and protected by the combined etch mask provides a bottom mesa portion of the semiconductor material layer.

[0040] Fig. 22 After forming the gap filling dielectric material layer Fig.21 A cross-sectional view of an exemplary structure shown in FIG.

[0041] Fig.23 After recessing the gap-fill dielectric material layer Fig. 22 A cross-sectional view of an exemplary structure shown in FIG.

[0042] Fig.24 After forming a gate metal layer on the recessed gap filling dielectric material layer Fig.23 A cross-sectional view of an exemplary structure is shown, wherein the gate metal layer is laterally adjacent to and in direct physical contact with the gate polysilicon layer.

[0043] Fig.25 After forming the first front side ILD material layer Fig.24 A cross-sectional view of an exemplary structure shown in FIG.

[0044] Fig.26 After each upper platform portion of the semiconductor material layer is transformed into a first source / drain region Fig.25 A cross-sectional view of an exemplary structure is shown.

[0045] Fig. 27 After forming a front side source / drain contact structure on each first source / drain region Fig.26 A cross-sectional view of an exemplary structure is shown.

[0046] Fig.28 After forming a second front side ILD material layer and forming a front side BEOL structure and a carrier wafer on the second front side ILD material layer Fig. 27 In the cross-sectional view of the exemplary structure shown in , the second front side ILD material layer includes a plurality of DRAM capacitors embedded therein, wherein each DRAM capacitor extends completely through the second front side ILD material layer and is in direct contact with one of the front side source / drain contact structures.

[0047] Fig.29 After flipping the structure 180° to physically expose the remaining base semiconductor substrate Fig.28 A cross-sectional view of an exemplary structure shown in FIG.

[0048] Fig.30 after removing the physically exposed remaining portion of the base semiconductor substrate to physically expose at least a remaining portion of the etch stop layer Fig.29 A cross-sectional view of an exemplary structure shown in FIG.

[0049] Fig.31 after removing the physically exposed remaining portion of the etch stop layer to physically expose each bottom terrace portion of the semiconductor material layer and converting each physically exposed bottom terrace portion of the semiconductor material layer into a second source / drain region, Fig.30 A cross-sectional view of an exemplary structure is shown.

[0050] Fig.32 After forming a backside source / drain contact structure on each second source / drain region Fig.31 A cross-sectional view of an exemplary structure is shown.

[0051] Fig.33 After forming the backside ILD material layer Fig.32 A cross-sectional view of an exemplary structure shown in FIG.

[0052] Fig.34 After forming the bit line in the backside ILD material layer Fig.33 A cross-sectional view of an exemplary structure is shown in which each bit line extends completely through the backside ILD material layer and is in direct physical contact with one of the backside source / drain contact structures.

[0053] Fig.35 After the backside BEOL structure is formed on the backside ILD material layer Fig.34 A cross-sectional view of an exemplary structure is shown. DETAILED DESCRIPTION

[0054] The present application will now be described in more detail by reference to the following discussion and the accompanying drawings of the present application. Note that the drawings of the present application are for illustrative purposes only and therefore the drawings are not drawn to scale. It should also be noted that identical and corresponding elements are represented by identical reference numerals.

[0055] In the following description, many specific details, such as specific structures, components, materials, dimensions, processing steps and techniques are set forth to provide an understanding of the various embodiments of the present application. However, it will be appreciated by those of ordinary skill in the art that the various embodiments of the present application can be practiced without these specific details. In other cases, in order to avoid obscuring the present application, known structures or processing steps are not described in detail.

[0056] It will be understood that when an element as a layer, region, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "below" or "under" another element, it can be directly below or under the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly below" or "directly under" another element, there are no intervening elements.

[0057] As described above, one aspect of the present application relates to a semiconductor structure including a DRAM cell and a backside metal-containing bitline. Notably, the semiconductor structure includes a DRAM cell including a plurality of FETs and a plurality of DRAM capacitors, and at least one bitline composed of a conductive metal-containing material located on the backside of the DRAM cell. As described above, the term "backside" refers to a portion of the structure including backside wiring components, such as a bitline located on a side of the structure that does not include active devices (i.e., DRAM cells). As described above, such a structure has low bitline capacitance. In an embodiment of the present application, the DRAM cell has a capacitance defined as 4F. 2 The unit cell area of ​​4F is 400W, where F is equal to the gate half pitch. In the present application, F represents the characteristic size of the gate structure. Therefore, the DRAM cell of the present invention has a high density. In an embodiment, the FET is a vertical FET including a vertical semiconductor channel material structure. The VFET helps to form a 4F 2 Structure. In an embodiment, the DRAM capacitor is a stacked capacitor which allows for higher density cells. These and other aspects of the present application will now be described in more detail.

[0058] First reference Figure 1-Figure 15 , which shows the first embodiment of the present application. The first embodiment starts with forming Figure 1 The exemplary structure shown. It is worth noting that Figure 1 The exemplary structure shown includes a plurality of vertical semiconductor channel material structures 14 extending upward from a surface of an etch stop layer 12 located on a surface of a base semiconductor substrate 10 . Figure 1 The exemplary structure shown may also include a hard mask cap 16 located on top of each vertical semiconductor channel material structure 14 , and shallow trench isolation structures 18 / 20 located in the etch stop layer 12 and the base semiconductor substrate 10 .

[0059] The base semiconductor substrate 10 is composed of a first semiconductor material having semiconductor properties. Examples of the first semiconductor material that can be used to provide the base semiconductor substrate 10 include, but are not limited to, silicon (Si), silicon-germanium (SiGe) alloys, silicon-germanium carbide (SiGeC) alloys, germanium (Ge), III / V compound semiconductors, or II / VI compound semiconductors.

[0060] Each vertical semiconductor channel material structure 14 is composed of a second semiconductor material. The second semiconductor material providing each vertical semiconductor channel material structure 14 may be the same or different in composition from the first semiconductor material providing the base semiconductor substrate 10. In some embodiments, the second semiconductor material providing each vertical semiconductor channel material structure 14 is capable of providing high channel mobility for nFET devices. In other embodiments, the second semiconductor material providing each vertical semiconductor channel material structure 14 is capable of providing high channel mobility for pFET devices. In the present application, each vertical semiconductor channel material structure 14 will be used as a vertical channel structure, and in this first embodiment, source / drain regions will subsequently be formed on two horizontal surfaces of each vertical semiconductor channel material structure 14, and gate structures will subsequently be formed along the sidewalls of each vertical semiconductor channel material structure to form multiple VFETs.

[0061] In the present application, the vertical height of each vertical semiconductor channel material structure 14 measured from the bottommost horizontal surface to the topmost horizontal surface is greater than the width of each vertical semiconductor channel material structure 14 measured from one sidewall of the vertical semiconductor channel material structure 14 to the opposite sidewall of the vertical semiconductor channel material structure 14. In one example, the vertical height of each vertical semiconductor channel material structure 14 is from 10 nm to 200 nm, and the width of each vertical semiconductor channel material structure 14 is from 5 nm to 50 nm.

[0062] In some embodiments of the present application, the etch stop layer 12 may be composed of a dielectric material (e.g., silicon dioxide and / or boron nitride). In other embodiments of the present application, the etch stop layer 12 is composed of a semiconductor material that is different in composition from the semiconductor material that provides both the base semiconductor substrate 10 and the vertical semiconductor channel material structure 14. In one example, the base semiconductor substrate 10 is composed of silicon, the etch stop layer 12 is composed of silicon dioxide, and each vertical semiconductor channel material structure 14 is composed of silicon. In another example, the base semiconductor substrate 10 is composed of silicon, the etch stop layer 12 is composed of silicon germanium, and each vertical semiconductor channel material structure 14 is composed of silicon.

[0063] Each hard mask cap 16 may be composed of a dielectric hard mask material such as silicon nitride and / or silicon oxynitride. In the illustrated embodiment, each hard mask cap 16 has sidewalls that are vertically aligned with sidewalls of one of the vertical semiconductor channel material structures 14.

[0064] The shallow trench isolation structure 18 / 20 includes a trench liner 18 and a trench dielectric material 20. Figure 1 As shown, the trench liner 18 is present along the sidewalls and bottom wall of the trench dielectric material 20. The trench dielectric material 20 can be composed of any trench dielectric, such as silicon oxide, and the trench liner 18 can be composed of any trench liner material, such as silicon nitride. Figure 1 As shown, shallow trench isolation structures 18 / 20 extend completely through etch stop layer 12 and partially through base semiconductor substrate 10. In some embodiments, trench liner 18 may be omitted.

[0065] Figure 1 The exemplary structure shown in can be prepared by the following steps: first, a substrate is formed, which includes a base semiconductor substrate 10, an etch stop layer 12, and a semiconductor material layer composed of the above-mentioned second semiconductor material; the semiconductor material layer will then be processed into a vertical semiconductor channel material structure 14. The substrate can be formed using techniques known to those skilled in the art. Next, a hard mask layer composed of the above-mentioned dielectric hard mask material is formed on the semiconductor material layer. The hard mask layer can be formed using a deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD). In some embodiments, the hard mask layer can be formed by a thermal process, such as thermal oxidation and / or thermal nitridation. Next, the hard mask layer and the underlying semiconductor material layer are patterned to provide Figure 1 The hard mask shown in FIG. 1 covers a vertical semiconductor channel material structure.

[0066] In some embodiments, patterning may include photolithography and etching. Photolithography includes forming a photoresist material on the material or stack of materials to be patterned, exposing the deposited photoresist material to a desired illumination pattern, and thereafter developing the exposed photoresist material. Etching may include a dry etching process and / or a chemical wet etching process. Dry etching may include one of reactive ion etching (RIE), plasma etching, or ion beam etching.

[0067] In some embodiments, patterning may include a sidewall image transfer (SIT) process. The SIT process includes forming a mandrel material layer (not shown) on one or more material layers to be patterned. The mandrel material layer (not shown) may include any material (semiconductor, dielectric or conductive material) that can be selectively removed from the structure during a subsequent etching process. In one embodiment, the mandrel material layer (not shown) may be composed of amorphous silicon or polycrystalline silicon. In another embodiment, the mandrel material layer (not shown) may be composed of a metal such as Al, W or Cu. For example, the mandrel material layer (not shown) may be formed by CVD or PECVD. After depositing the mandrel material layer (not shown), the mandrel material layer (not shown) may be patterned by photolithography and etching to form a plurality of mandrel structures (also not shown) on the uppermost surface of the structure. The SIT process continues by forming a spacer (not shown) on each sidewall of each mandrel structure. The spacer may be formed by depositing a spacer material and then etching the deposited spacer material. The spacer material may include any material having an etching selectivity different from that of the mandrel material. Examples of deposition processes that can be used to provide the spacer material include, for example, CVD, PECVD, or atomic layer deposition (ALD). Examples of etching that can be used to provide the spacer include any etching process, such as RIE. After forming the spacer, the SIT process is continued by removing each mandrel structure. Each mandrel structure can be removed by an etching process that selectively removes the mandrel material. After the mandrel structure is removed, the SIT process continues to transfer the pattern provided by the spacer to the underlying material or material layer. Pattern transfer can be achieved by utilizing at least one etching process. Examples of etching processes that can be used to transfer the pattern may include dry etching and / or chemical wet etching processes. In one example, the etching process for transferring the pattern may include one or more reactive ion etching steps. When the pattern transfer is completed, the SIT process ends by removing the spacer from the structure. Each spacer can be removed by an etching or planarization process.

[0068] In other embodiments, patterning may include a direct self-assembly (DSA) process, wherein copolymers capable of direct self-assembly are used. Other known patterning processes may also be used to form Figure 1 The hard mask shown covers the vertical semiconductor channel material structure.

[0069] In the formation Figure 1After the vertical semiconductor channel material structure covered by the hard mask as shown, a shallow trench isolation structure 18 / 20 is formed using a conventional shallow trench isolation process known to those skilled in the art. The shallow trench isolation process may include forming trenches in the etch stop layer 12 and the base semiconductor substrate 10 by photolithography and etching, and then filling the trenches with a trench dielectric liner material and a trench dielectric as described above; the filling of the trenches may include depositing the trench dielectric liner material and the trench dielectric, and recessing those deposited materials.

[0070] Reference now Figure 2 , showing the first dielectric spacer 22 after forming Figure 1 In the exemplary structure shown in , the first dielectric spacer 22 contacts the lower portion of each vertical semiconductor channel material structure 14 in the plurality of vertical semiconductor channel material structures. In the present application, the first dielectric spacer 22 may be referred to as a bottom spacer. The first dielectric spacer 22 may be made of any dielectric spacer material, including, for example, silicon dioxide, silicon nitride, or silicon oxynitride. The first dielectric spacer 22 may be formed using a deposition process such as CVD or PECVD. In some examples, an etch-back process may be performed after depositing the dielectric spacer material to provide the first dielectric spacer 22. The first dielectric spacer 22 may have a thickness from 5 nm to 15 nm. Other thicknesses less than or greater than the above thickness ranges may also be used in the present application as the thickness of the first dielectric spacer 22, as long as the height of the first dielectric spacer 22 is not greater than the height of the vertical semiconductor channel material structure 14 and there is sufficient space along the sidewalls of the vertical semiconductor channel material structure 14 to form a gate structure and a second dielectric spacer. As Figure 2 As shown, a first dielectric spacer 22 is formed on top of the shallow trench isolation structure 18 / 20 and the etch stop layer 12 .

[0071] Reference now Figure 3 , showing the gate structure material layer 24L after forming the gate structure material layer 24L on the first dielectric spacer 22, along the sidewalls and on the top of each vertical semiconductor channel material structure 14. Figure 2 ; in the embodiment shown, the gate structure material layer 24L also exists along the sidewalls and top surface of the hard mask cap 16. The gate structure material layer 24L is generally a conformal layer. The term "conformal" refers to a material layer having a vertical thickness along a horizontal surface that is substantially the same as the lateral thickness along a vertical surface (i.e., within ±5%).

[0072] In the present application, the gate structure material layer 24L includes a gate dielectric material and a gate electrode, which are not separated but are within the gate structure material layer 24L. As known to those skilled in the art, the gate dielectric material is in direct contact with the sidewall of the vertical semiconductor channel material structure 14 and a gate electrode is formed on the gate dielectric material.

[0073] The gate dielectric material of the gate structure material layer 24L has a dielectric constant of 4.0 or greater. Unless otherwise specified, all dielectric constants mentioned herein are measured in a vacuum. Illustrative examples of gate dielectric materials include, but are not limited to, silicon dioxide, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO4), zirconium silicon oxynitride (ZrSiO x N y ), tantalum oxide (TaO x ), titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc, Ta)O3) and / or lead zinc niobium (Pb(Zn, Nb)O). The gate dielectric material may further include dopants, such as lanthanum (La), aluminum (Al) and / or magnesium (Mg). The gate dielectric material can be formed using any conformal deposition process, such as CVD, PECVD or ALD.

[0074] The gate electrode of the gate structure material layer 24L may include a work function metal (WFM) and an optional conductive metal. The WFM may be used to set the threshold voltage of the transistor to a desired value. In some embodiments, the WFM may be selected to achieve an n-type threshold voltage shift. As used herein, "n-type threshold voltage shift" means the shift of the effective work function of the work function metal-containing material toward the conduction band of silicon in the silicon-containing material. In one embodiment, the work function of the n-type work function metal is 4.1eV-4.3eV. Examples of such materials that can achieve an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or a combination thereof. In other embodiments, the WFM may be selected to achieve a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal is in the range of 4.9eV to 5.2eV. As used herein, "threshold voltage" is the lowest achievable gate voltage that will turn on the semiconductor device (e.g., transistor) by turning on the channel of the device. As used herein, the term "p-type threshold voltage shift" refers to the shift of the effective work function of the material containing the work function metal toward the valence band of silicon in the silicon-containing material. Examples of such materials that can achieve a p-type threshold voltage shift include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof. Optional conductive metals may include, but are not limited to, aluminum (Al), tungsten (W), or cobalt (Co). The gate electrode may be formed by a deposition process such as CVD, PECVD, sputtering, or electroplating.

[0075] Reference now Figure 4 , showing the gate structure material layer 24L after patterning to provide a gate structure 24 along the sidewalls of each vertical semiconductor channel material structure 14 of the plurality of vertical semiconductor channel material structures Figure 3 ; in the illustrated embodiment, the gate structure 24 also exists along the sidewalls of the hard mask cap 16, but not along its top surface. As described above, the gate structure 24 includes the gate dielectric material and the unetched portion of the gate electrode. The patterning includes using a gate pattern mask (not shown) that protects a portion of the gate structure material layer 24L and etching. The etching may include a dry etching process such as RIE or a chemical wet etching process. The gate structure 24 has a height that is less than the combined height of the vertical semiconductor channel material structure covered by the hard mask.

[0076] Reference now Figure 5 , showing the first front side interlayer dielectric (ILD) material layer 26 after forming a first front side interlayer dielectric (ILD) material layer 26 laterally adjacent to each gate structure 24. Figure 4. In the illustrated embodiment, the first front side ILD material layer 26 has a top surface coplanar with the top surface of each hard mask cap 16; therefore, a portion of the first front side ILD material layer 26 may be present on top of each gate structure 24. The first front side ILD material layer 26 may be composed of a dielectric material, which includes, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. The term "low-k" used throughout this application refers to a dielectric material having a dielectric constant of less than 4.0. The first front side ILD material layer 26 may be formed by depositing a dielectric material followed by a planarization process such as chemical mechanical polishing (CMP). The deposition of the dielectric material may include, for example, CVD, PECVD, ALD, or spin coating.

[0077] Reference now Figure 6 , showing the hard mask cap 16 present on top of each vertical semiconductor channel material structure 14 of the plurality of vertical semiconductor channel material structures after removal Figure 5 . Removing the hard mask caps 16 from the exemplary structure includes an etching process that is selective in removing the hard mask material that provides each hard mask cap 16. After removing the hard mask caps 16 from the exemplary structure, the top surface of each vertical semiconductor channel material structure 14 is physically exposed, and an opening 28 is formed above each vertical semiconductor channel material structure 14, as shown in FIG. Figure 6 shown.

[0078] Reference now Figure 7 , showing after each gate structure 24 is recessed to physically expose an upper sidewall portion of each vertical semiconductor channel material structure 14 in a plurality of vertical semiconductor channel material structures Figure 6 . The recessing of each gate structure 24 can be performed using a recess etching process that selectively removes a portion of each gate structure 24. This step of the present application provides space along the upper sidewall portion of the vertical semiconductor channel material structure 14, where the second dielectric spacer (or top dielectric spacer) will be formed later. Now, the height of the recessed gate structure 24 is less than the height of the vertical semiconductor channel material structure 14.

[0079] Reference now Figure 8, showing the structure after forming a second dielectric spacer 30 laterally adjacent to the physically exposed upper sidewall portion of each of the plurality of vertical semiconductor channel material structures 14, and forming a first source / drain region (or top source / drain region) 32 extending upward from the top surface of each of the plurality of vertical semiconductor channel material structures 14. Figure 7 The exemplary structure shown in .

[0080] The second dielectric spacer 30 is formed of one of the dielectric spacer materials described above for providing the first dielectric spacer 22. The second dielectric spacer 30 can be formed using the process techniques described when forming the first dielectric spacer 22. The second dielectric spacer 30 can have a top surface that is coplanar or slightly offset with the top surface of the vertical semiconductor channel material structure 14. When offset, the second dielectric spacer 30 has a top surface that is generally below the top surface of the vertical semiconductor channel material structure 14; such an embodiment will allow the first source / drain region 32 to be formed along the sidewalls of each vertical semiconductor channel material structure 14 as well.

[0081] The first source / drain region 32 includes a semiconductor material and a dopant. The semiconductor material providing the first source / drain region 32 includes one of the semiconductor materials mentioned above when providing the base semiconductor substrate 10. The semiconductor material providing the first source / drain region 32 may be the same or different in composition from the second semiconductor material providing each vertical semiconductor channel material structure 14. The dopant may be an n-type dopant or a p-type dopant. The term "n-type" refers to the addition of impurities that contribute free electrons to an intrinsic semiconductor. In silicon-containing semiconductor materials, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus. The term "p-type" refers to the addition of impurities that will produce defects in valence electrons to an intrinsic semiconductor. In silicon-containing semiconductor materials, examples of p-type dopants, i.e., impurities, include, but are not limited to boron, aluminum, gallium, and indium. The concentration of the first dopant in the first source / drain region 32 may be between 1×10 18 Atom / cm 3 Up to 1×10 21 Atom / cm 3 However, it is also possible to consider dopant concentrations greater than 1×10 21 Atom / cm 3 or less than 1×10 18 Atom / cm 3 The first source / drain region 32 may extend above the uppermost surface of the first front-side ILD material layer 26, and the first source / drain region 32 may have a faceted or non-faceted surface. Figure 8, each first source / drain region 32 has a triangular surface extending above the uppermost surface of the first front-side ILD material layer 26. Note that the first source / drain region 32 is formed on the second dielectric spacer 30 and on the physically exposed surface of the vertical semiconductor channel material structure 14. In this embodiment, the first source / drain region 32 and the second source / drain region (formed later) may both have a non-faceted surface that is opposite to the surface of the first source / drain region 32 and the second source / drain region (formed later) that contacts the vertical semiconductor channel material structure 14.

[0082] The first source / drain region 32 can be formed using a deposition process, such as CVD, PECVD or epitaxial growth. The term "epitaxial growth" or "epitaxial growth" refers to growing a second semiconductor material on the growth surface of a first semiconductor material, wherein the grown second semiconductor material has the same crystal properties as the first semiconductor material. In the epitaxial deposition process, the chemical reactants provided by the source gas are controlled and the system parameters are set so that the deposited atoms reach the growth surface of the first semiconductor material with sufficient energy to move back and forth on the growth surface and orient themselves to the crystal arrangement of the atoms on the growth surface. Examples of various epitaxial growth process equipment that can be used in the present application include, for example, rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD) and molecular beam epitaxy (MBE). The temperature used for epitaxial deposition is generally in the range of 550°C to 900°C. Although higher temperatures generally result in faster deposition, faster deposition may result in crystal defects and film rupture. In some embodiments, the dopant is added to the deposited semiconductor material using ion implantation or another similar dopant introduction process. In other embodiments, the dopant is present during the deposition of the semiconductor material, for example, an epitaxial growth process may be used, in which the semiconductor material reactant and the dopant are introduced simultaneously.

[0083] Reference now Fig. 9 , showing the second front side ILD material layer 34 after forming the front side contact structure 36 embedded therein Figure 8 In the exemplary structure shown in FIG. 1 , each front side contact structure 36 contacts one of the first source / drain regions 32. The second front side ILD material layer 34 includes one of the dielectric materials mentioned above for the first front side ILD material layer 26. The dielectric material providing the second front side ILD material layer 34 may be the same or different in composition from the dielectric material providing the first front side ILD material layer 26. The second front side ILD material layer 34 may be formed using one of the deposition processes mentioned above when forming the first front side ILD material layer 26.

[0084] The front side contact structure 36 is formed by any conventional metallization process. Since each front side contact structure 36 contacts the first source / drain region 32, the front side contact structure 36 can be referred to as a front side source / drain contact structure. The front side contact structure 36 includes at least a contact conductor material, such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh or an alloy thereof. In an embodiment, the front side contact structure 36 can also include a silicide liner such as TiSi, NiSi, NiPtSi, etc., and an adhesion metal liner such as TiN. Each front side contact structure 36 can be formed by forming a contact opening in the second front side ILD material layer 34 by photolithography and etching. The contact conductor material can be formed in the contact opening by any suitable deposition method, such as ALD, CVD, PVD or electroplating. In some embodiments (not shown), before forming the contact conductor material, a metal semiconductor alloy region can be formed in each contact opening. The metal semiconductor alloy region can be composed of silicide or germanide. In one or more embodiments of the present application, the metal semiconductor alloy region can be formed by first depositing a metal layer (not shown) in the trench. The metal layer may include a metal, such as Ni, Co, Pt, W, Ti, Ta, a rare earth metal (e.g., Er, Yt, La), an alloy thereof, or any combination thereof. The metal layer may be deposited by ALD, CVD, or PVD. The thickness of the metal layer may be 2nm to 10nm, although a smaller or larger thickness may also be used. Then, a diffusion barrier layer (not shown), such as TiN or TaN, may be formed on the metal layer. An annealing process may then be performed at an elevated temperature to cause a reaction of the semiconductor material of the source / drain region, thereby providing a metal semiconductor alloy region. Then, the unreacted portion of the metal layer is removed, and if present, the diffusion barrier layer is removed, for example, by an etching process (or multiple etching processes). In one embodiment, the etching process may be a wet etch that selectively removes the metal in the metal layer relative to the metal semiconductor alloy in the metal semiconductor alloy region. Each front side contact structure 36 may also include one or more contact pads (not shown). In one or more embodiments, the contact pads (not shown) may include a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof, such as Ti / TiN and Ti / WC. The contact pads may be formed using a conformal deposition process including CVD or ALD. The formed contact pads may have a thickness ranging from 1 nm to 5 nm, but lesser or greater thicknesses may also be employed. Each front side contact structure 36 has a top surface coplanar with a top surface of the second front side ILD material layer 34.

[0085] Reference now Fig.10, showing a front side back end of line (BEOL) structure 40 in which DRAM capacitors 38 are embedded, and a carrier wafer 42 is formed on the front side BEOL structure 40. Fig. 9 In the exemplary structure shown in FIG. 1 , each DRAM capacitor 38 contacts one of the front side contact structures 36. Fig.10 As shown, each DRAM capacitor 36 is electrically connected to one of the first source / drain regions 32 through a front side contact structure 36. Fig.10 As further shown, each DRAM capacitor 36 is separated from the carrier wafer 42 by a portion of the front side BEOL structure 40 .

[0086] The front side BEOL structure 40 includes one or more interconnected dielectric material layers, which include one or more wiring areas and DRAM capacitors 38 embedded therein. The front side BEOL structure 40 can be formed using BEOL processing techniques known to those skilled in the art; and the embedded DRAM capacitors 38 can be formed using known BEOL capacitor formation techniques known to those skilled in the art. The DRAM capacitor 38 includes two conductive material plates (or electrodes) separated by a dielectric material. The conductive material plates can be composed of any capacitor electrode material, such as copper (Cu), tantalum (Ta), W, Al, ruthenium (Ru), rhodium (Rh), Co, molybdenum (Mo), titanium nitride (TiN), or tantalum nitride (TiN). The two conductive material plates can be composed of capacitor electrode materials of the same composition or different compositions. The dielectric material located between the two conductive plates can include one of the dielectric materials described above for the gate dielectric material of the gate structure material layer 24L. The DRAM capacitor 38 is typically a stacked capacitor, which includes a bottom conductive plate and a top conductive plate separated from each other by a dielectric material; therefore, the dielectric material is sandwiched between the bottom conductive plate and the top conductive plate. This stacking configuration improves the density of the DRAM cell.

[0087] The carrier wafer 42 may include one of the semiconductor materials described above for the base semiconductor substrate 10 . In the present application, the carrier wafer 42 is bonded to the front-side BEOL structure 40 .

[0088] Reference now Fig.11 , showing the back side of the base semiconductor substrate 10 after the wafer is flipped 180° to physically expose the back side of the base semiconductor substrate 10 Fig.10 The exemplary structure shown in . This flipping will allow back-side processing of the exemplary structure. In the present application, the structure is flipped 180°. The flipping of the structure can be performed manually or by using a mechanical device such as a robot arm.

[0089] Reference now Fig.12 , showing after removing the base semiconductor substrate 10 to physically expose the etch stop layer 12 Fig.11The exemplary structure shown in . The removal of the base semiconductor substrate 10 may be performed using a material removal process that is selective in removing the first semiconductor material that provides the base semiconductor substrate 10. Note that this removal step does not remove any portion of the shallow trench isolation structures 18 / 20.

[0090] Reference now Fig.13 , showing after the etch stop layer 12 is removed to physically expose the horizontal surface of each of the plurality of vertical semiconductor channel material structures 14 Fig.12 Note that the physically exposed horizontal surface of the vertical semiconductor channel material structure 14 is opposite to the horizontal surface of the vertical semiconductor channel material structure 14 that forms the interface with the first source / drain region 32. The removal of the etch stop layer 12 includes a selective material removal process in removing the etch stop layer 12.

[0091] Reference now Fig.14 , showing the second source / drain region 44 after forming the second source / drain region 44 on the physically exposed horizontal surface of each vertical semiconductor channel material structure 14 of the plurality of vertical semiconductor channel material structures 14 Fig.13 The exemplary structure shown in . Each second source / drain region 44 is surrounded by shallow trench isolation structures 18 / 20 on both sides. Each second source / drain region 44 may be referred to herein as a bottom source / drain region.

[0092] The second source / drain regions 44 are comprised of the semiconductor material and dopants described above for the first source / drain regions 32. The semiconductor material providing the second source / drain regions 44 may be compositionally the same or different than the semiconductor material providing the first source / drain regions 32 and / or the second semiconductor material providing the vertical semiconductor channel material structure 14. The dopant within the second source / drain regions 44 has the same conductivity type as the dopant present in the first source / drain regions 32. The dopant concentration within the second source / drain regions 44 is within the range described above for the first source / drain regions 32. Each second source / drain region 44 may have a faceted or non-faceted surface, and each second source / drain region 44 may extend above the height of each shallow trench isolation structure 18, 20, as shown. Fig.14 As shown. Fig.14 In the embodiment, each second source / drain region 44 has a triangular surface. The second source / drain region 44 can be formed using one of the techniques for forming the first source / drain region 32 described above.

[0093] Reference now Fig.15 , which shows the backside bit line 46 after forming the backside bit line 46 in contact with each second source / drain region 44 and forming the backside BEOL structure 48 on the backside bit line 46. Fig.141. In some embodiments (not shown), before forming the backside bit line 46, a backside source / drain contact may be formed on the second source / drain region 44 (see the second embodiment of the present application). Although a single backside bit line 46 is shown, the present application contemplates forming a plurality of such backside bit lines 46; Fig.15 In the drawings, for example, the backside bit line 46 will appear both outside and within the plane of the drawing. The backside bit line 46 is composed of any conductive metal-containing material, including but not limited to W, Co, Ru, Al, Cu, platinum (Pt), Rh or palladium (Pd), and a thin metal adhesion layer (e.g., TiN, TaN) is usually formed before the conductive metal is deposited; for clarity, the metal adhesion layer is not separately shown in the drawings of the present application. The backside bit line 46 is usually embedded in the backside ILD material layer (not shown in the cross-sectional view), and it can be formed by forming a backside bit line opening in the backside ILD material layer; the backside bit line opening physically exposes the surface of the second source / drain region 44. The backside bit line opening is then filled with at least one of the above-mentioned conductive materials, and a planarization process can be performed after filling the backside bit line opening. The filling can include CVD, PECVD, ALD, sputtering or electroplating. The resulting backside bit line 46 contacts the second source / drain region 44 of each VFET. Each VFET includes a vertical semiconductor channel material structure 14, a gate structure 24 located on each side of the vertical semiconductor channel material structure 14, a first source / drain region 32 located at a first end of the vertical semiconductor channel material structure 14, and a second source / drain region 44 located at a second end of the vertical semiconductor channel material structure 14 opposite to the first end. The first source / drain region 32 of each VFET is electrically connected to a DRAM capacitor 38 present in the front side BEOL structure 40 through one of the front side contact structures 36. In the present application, current flows vertically in the vertical semiconductor channel material structure 14 of each VFET. In the present application, the DRAM capacitor 38 and the VFET together provide a DRAM cell; the DRAM capacitor serves as a storage node of the DRAM cell. The DRAM cell is typically a 4F as described above. 2 unit.

[0094] The backside BEOL structure 48 may be a backside power distribution network that delivers power to the VFET. The backside BEOL structure 48 includes one or more interconnected dielectric material layers (in Fig.15 50), which includes one or more wiring areas (in Fig.15 Backside BEOL structure 48 may be formed using techniques known to those skilled in the art.

[0095] Reference now Figure 16-Figure 35 , which shows the second embodiment of the present application. The second embodiment starts with forming Fig.16The exemplary structure shown. It is worth noting that Fig.16 The exemplary structure shown includes a base semiconductor substrate 10, an etch stop layer 12 located on the base semiconductor substrate 10, and a semiconductor material layer 14L having a plurality of upper terrace portions 14U located on the etch stop layer 12. The exemplary structure of this embodiment of the present application may further include a hard mask cap 16 located on top of each upper terrace portion 14U of the semiconductor material layer 14L.

[0096] The base semiconductor substrate 10, the etch stop layer 12 and the hard mask cap 16 are the same as those in the first embodiment of the present application. The semiconductor material layer 14L having a plurality of upper mesas 14U is composed of the second semiconductor material mentioned above when providing the vertical semiconductor channel material structure 14 of the first embodiment of the present application.

[0097] Fig.16 The exemplary structure shown in can be prepared by first forming a substrate, which includes a base semiconductor substrate 10, an etch stop layer 12, and a semiconductor material layer 14L composed of the above-mentioned second semiconductor material. The substrate can be formed using techniques known to those skilled in the art. For example, the preparation of the substrate can include epitaxial growth of the etch stop layer 12 and the semiconductor material layer 14L. Next, a hard mask layer composed of the above-mentioned dielectric hard mask material is formed on the semiconductor material layer. As described above, the hard mask layer can be formed using a deposition process or a thermal process. Next, the hard mask layer and the semiconductor material layer 14L thereunder are patterned to provide Fig.16 In this embodiment, patterning generally includes lithography and etching. Etching may include a dry etching process and / or a chemical wet etching process, etching completely through the hard mask layer and partially through the semiconductor material layer 14L to provide Fig.16 The term "mesa portion" is used herein to describe a portion of a material having a width greater than that of a base material.

[0098] Reference now Fig.17 , showing the dielectric liner 60 after forming the dielectric liner 60 along the sidewalls of at least each upper platform portion 14U of the semiconductor material layer 14L. Fig.16 The exemplary structure shown; dielectric spacers 60 are also present along the sidewalls of each hard mask cap 16, and the dielectric spacers 60 typically have a topmost surface coplanar with the hard mask cap 16. The dielectric spacers 60 are composed of any dielectric spacer material including the dielectric spacer materials described above when forming the first dielectric spacer 22. The dielectric spacers 60 can be formed by deposition of a dielectric spacer material followed by spacer etching.

[0099] Reference now Fig.18, showing the semiconductor material layer 14L after patterning using the dielectric spacer 60 and the upper platform portion 14U of the semiconductor material layer 14L as a combined etch mask Fig.17 , wherein patterning forms a plurality of semiconductor material pillars 14P on the remaining portion of the semiconductor material layer 14L; an upper mesa portion 14U is located on top of each semiconductor material pillar 14P. The patterning includes etching that selectively removes the second semiconductor material that provides the semiconductor material layer 14L. Fig.18 As shown, the etch stops on a sub-surface of semiconductor material layer 14L. Note that the width of each semiconductor material pillar 14P may be substantially equal to (± 10%) the width of the overlying mesa portion 14U.

[0100] Reference now Fig.19 , showing the semiconductor material pillars 14P after trimming each to provide a vertical semiconductor material channel structure 14 Fig.18 In the exemplary structure shown in , each vertical semiconductor material channel structure 14 is located between the upper mesa portion 14U of the semiconductor material layer 14L and the remaining portion of the semiconductor material layer 14L. In some embodiments, the trimming of the semiconductor material pillars 14P can be performed using a combination of oxidation and etching (this step can be repeated multiple times to provide the desired width to each vertical semiconductor material channel structure 14). In other embodiments, this trimming can be performed by a dry etching process.

[0101] Now refer to Fig. 20 , showing the gate dielectric material layer 62 and the gate polysilicon layer 64 after forming Fig.19 . The exemplary structure shown. The gate dielectric material layer 62 includes one of the gate dielectric materials of the gate structure material layer 24L of the previous embodiment of the present invention described above. The gate polysilicon layer 64 is composed of polysilicon, in which n-type or p-type dopants may be present. The gate dielectric material layer 62 and the gate polysilicon layer 64 are formed by first depositing (e.g., CVD, PECVD or ALD) a dielectric material, second depositing (e.g., CVD, PECVD or PVD) polysilicon, and then using etching to remove any polysilicon extending beyond the outermost surface of the dielectric spacer 60. The gate dielectric material layer 62 is a conformal layer present on the exposed surface of each vertical semiconductor material channel structure 14 and the remaining semiconductor material layer 14L, and the gate polysilicon layer 64 is located on the gate dielectric material layer 62.

[0102] Reference now Fig.21 , showing the Fig. 20, the breakthrough etching process removes at least a portion of the gate dielectric material layer 62, the remaining portion of the semiconductor material layer 14L, the etch stop layer 12, and a portion of the base semiconductor substrate 10; the remaining semiconductor material layer that is not etched and protected by the combined etching mask provides a bottom mesa portion 14B of the semiconductor material layer 14L. Note that in addition to the portion of the semiconductor material layer 14L that remains after the etching, a portion of the etch stop layer 12 and a portion of the base semiconductor substrate 10 remain after performing the breakthrough etching. In one embodiment, the breakthrough etching is RIE etching.

[0103] Reference now Fig. 22 , showing the gap filling dielectric material layer 66 after forming Fig.21 . The gap-fill dielectric material layer 66 is composed of any gap-fill dielectric material, including, for example, one of the dielectric materials mentioned above for the first front-side ILD material layer 26 of the first embodiment of the present application. The gap-fill dielectric material layer 66 can be formed by a deposition process utilizing one of the above-mentioned deposition processes included in forming the first front-side ILD material layer 26 of the first embodiment of the present application. A planarization process can follow the deposition of the dielectric material that provides the gap-fill dielectric material layer 66. At this point in the present application, the gap-fill dielectric material layer 66 has a top surface that is coplanar with the top surface of the dielectric spacer 60 and the top surface of the hard mask cap 16.

[0104] Reference now Fig.23 , showing the gap filling dielectric material layer after recessing 66 Fig. 22 The recessed gap-fill dielectric material layer 66 has a top surface that is generally, but not necessarily always, coplanar with the top surface of the bottom mesa portion 14B of the semiconductor material layer 14L. The recessing of the gap-fill dielectric material layer 66 may be performed using a recess etching process that is selective in removing the dielectric material that provides the gap-fill dielectric material layer 66.

[0105] Reference now Fig.24 , showing the gate metal layer 68 after forming the gate metal layer 68 on the recessed gap filling dielectric material layer 66 Fig.23 In the exemplary structure shown, the gate metal layer is laterally adjacent to and in direct physical contact with the gate polysilicon layer 64; the gate metal layer 68 is also in direct physical contact with the end wall of the gate dielectric material layer 62, such as Fig.24As shown. The gate metal layer 68 may include one of the above-mentioned WFM or selective conductive metals for use in the gate electrode in the gate structure material layer 24L. The gate metal layer 68 may be formed by a deposition process, such as CVD, PECVD, sputtering, or electroplating. After the gate metal material providing the gate metal layer 68 is deposited, an etch-back process may be performed.

[0106] Reference now Fig.25 , showing the first front side ILD material layer 70 after forming Fig.24 . The first front side ILD material layer 70 is composed of one of the dielectric materials mentioned above for the first front side ILD material layer 26 of the first embodiment of the present application. The first front side ILD material layer 70 can be formed by utilizing a deposition process including one of the above-mentioned deposition processes when forming the first front side ILD material layer 26 of the first embodiment of the present application. A planarization process can be performed after the dielectric material providing the first front side ILD material layer 70 is deposited. At this node of the present application, the first front side ILD material layer 70 has a top surface that is coplanar with the top surface of the dielectric spacer 60 and the top surface of the hard mask cap 16.

[0107] Reference now Fig.26 , showing the state after each upper platform portion 14U of the semiconductor material layer 14L is transformed into a first source / drain region 15 Fig.25 . Prior to the conversion, each hard mask cap 16 is removed from the structure using a material removal process, such as a planarization process (CMP and / or grinding). During the planarization process, the upper portions of both the dielectric spacer 60 and the first front side ILD material layer 70 may be removed together with each hard mask cap 16 to physically expose the upper mesa portion 14U. Converting the upper platform portion 14U to the first source / drain region 15 includes introducing a dopant (n-type or p-type as described above) into the physically exposed upper platform portion 14U. Introducing the dopant may include one of ion implantation, gas phase doping, or diffusion of a dopant from a dopant source material. The concentration of the dopant introduced into each upper mesa portion 14U is within the above-described dopant range when forming the first source / drain region 32 of the first embodiment of the present application.

[0108] Reference now Fig. 27 , which is after forming the front side source / drain contact structure 72 on each first source / drain region 15 Fig.26 The front side source / drain contact structure 72 comprises any material, such as the contact conductor material as described above for the front side contact structure 36 in the previous embodiment of the present application. Fig. 27In the exemplary embodiment shown, the front side source / drain contact structure 72 can be formed by recessing (i.e., etching) the upper portion of each first source / drain region 15 and then forming the front side source / drain contact structure 72 in the recessed region. In some embodiments (not shown), the front side source / drain contact structure 72 can be formed on the non-recessed surface of each first source / drain region 15 by deposition and etching.

[0109] Reference now Fig.28 , showing the second front side ILD material layer 74 after forming the front side BEOL structure 40 and the carrier wafer 42 on the second front side ILD material layer 74 Fig. 27 In the exemplary structure shown in FIG. 1 , the second front side ILD material layer 74 includes a plurality of DRAM capacitors 76 embedded therein, wherein each DRAM capacitor 76 extends completely through the second front side ILD material layer 74 and is in direct contact with one of the front side source / drain contact structures 72. In this embodiment, the DRAM capacitors 76 are in contact with the front side BEOL structure 40.

[0110] The second front side ILD material layer 74 may include one of the dielectric materials described above for the first front side ILD material layer 26 of the first embodiment of the present application. The second front side ILD material layer 74 may include a dielectric material that is the same as or different in composition from the first front side ILD material layer 70. The second front side ILD material layer 74 may be formed by utilizing a deposition process using one of the deposition processes described above in forming the first front side ILD material layer 26 of the first embodiment of the present application.

[0111] Then, capacitor openings are first formed in the second front side dielectric material layer 74 by photolithography and etching, and DRAM capacitors 76 are formed in the second front side dielectric material layer 74. Each capacitor opening is then filled with a material that provides a capacitor, such as the first conductive plate material, dielectric material, and second conductive plate material for the DRAM capacitor 38 in the previous embodiment of the present application as described above. Filling may include depositing various materials followed by a planarization process. The DRAM capacitors 76 may be referred to as trench capacitors.

[0112] The front side BEOL structure 40 of this embodiment includes one or more interconnect dielectric material layers, which contain one or more wiring regions embedded therein. The front side BEOL structure 40 can be formed using BEOL processing techniques known to those skilled in the art. The carrier wafer 42 of this embodiment is the same as described in the previous embodiments of the present application. The carrier wafer 42 can be bonded to the front side BEOL structure 40.

[0113] Reference now Fig.29 , showing the structure after flipping 180° to physically expose the remaining base semiconductor substrate 10 Fig.28 The exemplary structure shown in . This flipping will allow back-side processing of the exemplary structure. In the present application, the structure is flipped 180°. The flipping of the structure can be performed manually or by using a mechanical device such as a robot arm.

[0114] Reference now Fig.30 , showing after removing the physically exposed remaining portion of the base semiconductor substrate 10 to physically expose at least a remaining portion of the etch stop layer 12 Fig.29 The exemplary structure shown in FIG. 1 also physically exposes the gap-fill dielectric material layer 66 after removing the remaining portion of the base semiconductor substrate 10. The remaining portion of the base semiconductor substrate 10 may be removed using an etching process that is selective in removing the base semiconductor substrate 10.

[0115] Reference now Fig.31 , showing the physical exposure of the remaining portion of the etching stop layer 12 after removing the physical exposure to the semiconductor material layer 14L each bottom platform portion 14B, and each physically exposed bottom platform portion 14B into the second source / drain region 17 after Fig.30 The exemplary structure shown. The removal of the physically exposed remaining portion of the etch stop layer 12 includes a selective etching process. The conversion of the bottom mesa portion 14B to the second source / drain region 17 is the same as the conversion of the upper mesa portion 14A to the first source / drain region 15. In this embodiment, the first source / drain region 15, the vertical semiconductor material channel structure 14, and the second source / drain region 16 are an integral structure (i.e., a single workpiece) and are composed of the same semiconductor material. In this embodiment, the VFET includes a vertical semiconductor material channel structure 14, a first source / drain region 15 located at a first end of the vertical semiconductor material channel structure 14, a second source / drain region 17 located at a second end (opposite to the first end) of the vertical semiconductor material channel structure 14, and a gate structure including a gate dielectric material layer 62, a gate polysilicon layer 64, and a gate metal layer 68. In this embodiment, the first source / drain region 15 and the second source / drain region 17 have faceted surfaces for connecting to the front side and the back side, respectively.

[0116] Reference now Fig.32 , showing the back side source / drain contact structure 78 after forming the back side source / drain contact structure 78 on each second source / drain region 17 Fig.31 The backside source / drain contact structure 78 includes the materials described above for the frontside source / drain contact structure 36. Fig.32In the exemplary embodiment shown, the rear source / drain contact structure 78 may be formed by recessing (i.e., etching) the upper portion of each second source / drain region 17 and then forming the rear source / drain contact structure 78 in the recessed region. In some embodiments (not shown), the backside source / drain contact structure 78 may be formed on the non-recessed surface of each second source / drain region 17 by deposition and etching.

[0117] Reference now Fig.33 , showing the back side ILD material layer 80 after forming Fig.32 The exemplary structure shown in . The backside ILD material layer 80 may include one of the dielectric materials mentioned above for the first frontside ILD material layer 26 of the previous embodiment of the present application. The backside ILD material layer 80 may be formed using one of the deposition processes described above in forming the first frontside ILD material layer 26 of the previous embodiment of the present application.

[0118] Reference now Fig.34 , showing the backside ILD material layer 80 after forming the bit line 46 Fig.33 , wherein each bit line 46 extends completely through the backside ILD material layer 80 and is in direct physical contact with one of the backside source / drain contact structures 78. The bit lines 46 of this embodiment include any conductive metal-containing material as described in the first embodiment of the present application, and the bit lines 46 of this embodiment can be formed using the techniques described above for forming the bit lines in the previous embodiments of the present application.

[0119] Reference now Fig.35 , showing the backside BEOL structure 48 formed on the backside ILD material layer 80 and on top of each bit line 46 Fig.34 The backside BEOL structure 48 of this embodiment is the same as the backside BEOL structure 48 of the previous embodiment; note that Fig.35 The interconnect dielectric material layers and various wiring layers are not shown in the illustrated backside BEOL structure 48 .

[0120] Although the present application has been specifically shown and described with reference to the preferred embodiments of the present application, it should be understood by those skilled in the art that the foregoing and other changes may be made in form and detail without departing from the scope of the present application. Therefore, the present application should not be limited to the exact form and details described and shown, but fall within the scope of the appended claims.

Claims

1. A semiconductor structure comprising: A dynamic random access memory DRAM cell includes a plurality of field effect transistors FET and a plurality of DRAM capacitors; as well as At least one bit line is formed of a conductive material including a conductive metal and is located on a back side of the DRAM cell.

2. The semiconductor structure of claim 1, wherein the DRAM cell has a structure defined as 4F 2 Unit cell area, where F is equal to half the gate pitch.

3. The semiconductor structure of claim 1, wherein each DRAM capacitor of the plurality of DRAM capacitors is a stacked capacitor.

4. The semiconductor structure according to claim 1, further comprising: A backside back-end-of-line (BEOL) structure is in contact with the at least one bit line, wherein the backside BEOL structure is a backside power distribution network.

5. The semiconductor structure of claim 1 , wherein each of the plurality of FETs is a vertical FET, the vertical FET comprising a vertical semiconductor channel material structure, a gate structure located on each side of the vertical semiconductor channel material structure, a first source / drain region located at a first end of the vertical semiconductor channel material structure, and a second source / drain region located at a second end of the vertical semiconductor channel material structure opposite to the first end of the vertical semiconductor channel material structure. 6 . The semiconductor structure of claim 5 , wherein the vertical semiconductor channel material structure, the first source / drain region, and the second source / drain region are of unitary construction and are composed of the same semiconductor material.

7. The semiconductor structure according to claim 5, further comprising: A front side source / drain contact structure contacts the first source / drain region and connects the first source / drain region to one of the plurality of DRAM capacitors.

8. The semiconductor structure of claim 7, wherein the at least one bit line is in direct contact with the second source / drain region. 9 . The semiconductor structure of claim 7 , wherein the at least one bit line is in direct contact with a backside source / drain contact structure located on the second source / drain region.

10. The semiconductor structure of claim 5, wherein both the first source / drain region and the second source / drain region have non-faceted surfaces opposite to surfaces of the first source / drain region and the second source / drain region that are in contact with the vertical semiconductor channel material structure.

11. The semiconductor structure according to claim 5, further comprising: A dielectric spacer is positioned along sidewalls of the first source / drain region.

12. The semiconductor structure of claim 1, wherein each DRAM capacitor of the plurality of DRAM capacitors is embedded in a front-side back-end-of-line (BEOL) structure.

13. The semiconductor structure of claim 12, further comprising: A carrier wafer is located on the front-end back-end-of-line (BEOL) structure.

14. The semiconductor structure of claim 13, wherein the carrier wafer is spaced apart from each of the plurality of DRAM capacitors by a portion of the frontside BEOL structure.

15. The semiconductor structure of claim 1, wherein each DRAM capacitor of the plurality of DRAM capacitors is present in a front-side interlayer dielectric material layer.

16. The semiconductor structure of claim 15, wherein each DRAM capacitor extends completely through the front-side interlayer dielectric material layer.

17. The semiconductor structure of claim 16, further comprising: A carrier wafer is located on the front-side interlayer dielectric material layer.

18. A semiconductor structure according to claim 1, wherein each FET includes a gate structure located on each side of a vertical semiconductor channel material structure, wherein the gate structure includes a gate dielectric material layer directly in contact with a sidewall of the vertical semiconductor channel material structure and a gate electrode positioned laterally adjacent to the gate dielectric material layer, wherein the gate electrode includes at least a work function metal layer.

19. The semiconductor structure of claim 18, further comprising: A gate polysilicon layer is located between the gate dielectric material layer and the gate electrode.

20. The semiconductor structure of claim 18, further comprising: A first dielectric spacer is located on a surface of the gate structure and in contact with the sidewalls of the vertical semiconductor channel material structure, and a second dielectric spacer is located on another surface of the gate structure and in contact with the sidewalls of the vertical semiconductor channel material structure.

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