Fault analysis method and system suitable for master control circuit board
By performing multi-stage detection and fault isolation of the input signals, logic processing and output signals of the main control circuit board, the problem of difficulty in accurately detecting the faults of the main control circuit board in the prior art is solved, and fast and efficient fault diagnosis and system stability are achieved.
Patent Information
- Application Number
- CN202510105994.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2025-05-16
AI Technical Summary
The prior art is difficult to quickly, efficiently and accurately detect the failure problems of input signals, logic processing or output signals in the main control circuit board, especially when internal logic states are difficult to monitor.
A fault analysis method is adopted to determine whether the sampling circuit is abnormal by receiving input signals of detection parameters, sampling and reading data, and comparing errors, and to perform logical state detection and fault positioning based on the fault isolation algorithm. At the same time, the output signal is comprehensively detected, including time and frequency domain analysis, and a detailed detection report is generated.
It realizes multi-stage fault detection and precise positioning of the main control circuit board, improves the accuracy and efficiency of fault diagnosis, and enhances the reliability and stability of the system.
Smart Images
Figure CN120009701A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of fault detection and diagnosis of a main control circuit board, and in particular to a fault analysis method and system suitable for a main control circuit board. Background Art
[0002] As the core component of electronic equipment, the main control circuit board has functions including signal acquisition, internal logic operation and signal output. Ensuring the normal function of the main control circuit board is the basis for the stable operation of the equipment. With the increasing complexity of the main control circuit board, traditional manual detection or single signal detection methods can no longer meet the needs of modern industry for fast, efficient and accurate detection, especially in the following scenarios: Input signal sampling verification: The sampling of external input signals by the main control circuit board is the basis of its operation. Deviations in the sampling circuit will directly lead to subsequent logical judgment errors.
[0003] Internal logic status monitoring: The operating status of the internal logic of the main control chip (such as registers, execution algorithms) is usually difficult to monitor directly from the outside, and logical anomalies are often difficult to detect in a timely manner.
[0004] Output signal verification: The output signal is a direct reflection of the overall performance of the main control circuit board, but only detecting the output cannot accurately determine the root cause of the fault.
[0005] Therefore, how to design a method that can accurately locate the fault problem of input signal, logic processing or output signal in the main control circuit board is a technical problem that needs to be solved urgently. Summary of the invention
[0006] The purpose of this application is to overcome the above-mentioned technical problems and provide a fault analysis method and system suitable for a main control circuit board, which can accurately locate the fault problems of input signals, logic processing or output signals in the main control circuit board.
[0007] In a first aspect, an embodiment of the present application discloses a fault analysis method applicable to a main control circuit board, which adopts the following scheme: A fault analysis method suitable for a main control circuit board comprises: receiving an input signal of a detection parameter; sampling and reading the input signal on the main control circuit board, and comparing the errors between the sampled data and the read data; comparing the error with a first preset threshold value to determine whether the sampling circuit of the input signal is abnormal, and taking it as a first detection result; if the first detection result is abnormal, detecting the internal logic state of the main control chip, and locating the fault based on a fault isolation algorithm, and taking it as a second detection result; detecting the performance of the output signal, and comparing it with preset parameters, to determine whether the output signal circuit is abnormal, and taking it as a third detection result; if the third detection result is abnormal, detecting the internal logic state of the main control chip again, and locating the fault based on the fault isolation algorithm, and taking it as a fourth detection result; collating the first detection result, the second detection result, the third detection result and the fourth detection result to generate a detection report.
[0008] By adopting the above technical solution, multi-stage fault detection and precise positioning of the main control circuit board can be achieved. First, by comparing the sampling data of the input signal with the read data, it is possible to accurately determine whether the sampling circuit of the input signal is abnormal, and generate a first detection result. When the first detection result shows an abnormality, the internal logic state of the main control chip is further detected in detail, and the fault isolation algorithm is used to accurately locate the fault, and a second detection result is generated. At the same time, the performance of the output signal is comprehensively tested and compared with the preset parameters to ensure that the output signal circuit is in good condition, and a third detection result is generated. If the third detection result still shows an abnormality, the internal logic state of the main control chip is detected again and the fault is located to generate a fourth detection result. Finally, all the test results are integrated to generate a detailed test report, providing a reliable basis for subsequent repairs and maintenance.
[0009] Optionally, when the first test result is normal, the performance of the output signal is directly tested and compared with the preset parameters to determine whether there is an abnormality in the output signal circuit, and use it as the third test result; when the third test result is normal, the test report is directly generated.
[0010] By adopting the above technical solution, when the sampling circuit of the input signal is confirmed to be normal, the detection of the internal logic state of the main control chip can be directly skipped, thereby saving time and resources for fault diagnosis. At the same time, when the output signal performance test result is also normal, the final test report can be quickly generated, improving the efficiency of the entire fault analysis process.
[0011] Optionally, the sampling and reading of the input signal of the main control circuit board and comparing the errors of the sampled data and the read data include: collecting the input signal in the main control circuit board through an independent sampling circuit as sampled data; reading the input signal in the main control chip through the communication interface of the main control circuit board as read data; comparing the sampled data and the read data to obtain the error.
[0012] By adopting the above technical solution, accurate fault detection of the main control circuit board can be achieved. Specifically: the input signal in the main control circuit board collected by the independent sampling circuit is used as sampling data to ensure that the real signal state in the external environment is accurately captured. The input signal in the main control chip is read as read data through the communication interface to ensure that the signal state after internal processing can also be obtained synchronously. Comparing the sampled data and the read data and obtaining the comparison error between the two helps to identify potential problems caused by internal and external differences, thereby improving the accuracy of fault detection. The combined effect of these measures not only improves the accuracy of fault detection, but also enhances the reliability and stability of the system.
[0013] Optionally, the detecting of the internal logic state of the main control chip includes: acquiring internal register data and task execution data of the main control chip via a communication interface; and comparing and detecting the internal register data and the task execution data with a preset logic model respectively.
[0014] By adopting the above technical solution, the internal register data and task execution data of the main control chip can be accurately obtained, and compared with the preset logic model, so as to effectively detect whether the logic state of the main control chip is normal.
[0015] Optionally, the internal register data and the task execution data are respectively compared and detected with a preset logic model, including: comparing the internal register data with the preset logic model to obtain a first deviation value; comparing the task execution data with the preset logic model to obtain a second deviation value; if either the first deviation value or the second deviation value exceeds a preset logic threshold, a logic abnormality occurs, otherwise, the logic is normal.
[0016] By adopting the above technical solution, it is possible to accurately evaluate whether the internal register data and task execution data of the main control chip meet the requirements of the preset logic model. Specifically: compare the internal register data with the preset logic model to obtain the first deviation value, so as to confirm whether the state of the internal register is normal; compare the task execution data with the preset logic model to obtain the second deviation value, so as to verify whether the logic in the task execution process is correct; if either the first deviation value or the second deviation value exceeds the preset logic threshold, it is determined that the main control chip has a logical abnormality, so as to timely discover potential problems; on the contrary, if both deviation values do not exceed the preset logic threshold, it is considered that the logic of the main control chip is normal, ensuring the stable operation of the system.
[0017] Optionally, the performance of the output signal is detected and compared with preset parameters to determine whether the output signal circuit is abnormal, and as a third detection result, it includes: acquiring the output signal; performing time domain analysis on the output signal to calculate the signal amplitude and deviation data; performing frequency domain analysis on the output signal to decompose the signal, and comparing it with the preset parameters to obtain a comparison result; based on the signal amplitude, the deviation data and the comparison result, obtaining the third detection result.
[0018] By adopting the above technical solution, comprehensive performance testing of the output signal can be achieved. Specifically: obtaining the output signal ensures that the object to be tested clearly performs time domain analysis on the output signal to calculate the signal amplitude and deviation data, which can accurately evaluate the temporal variation characteristics and stability of the signal; performing frequency domain analysis on the output signal to decompose the signal and compare it with the preset parameters, which helps to identify possible interference or distortion components in the signal, thereby more accurately judging the signal quality; based on the signal amplitude, deviation data and comparison results, a third test result is obtained, and the results of multiple data analysis are combined to improve the accuracy of fault diagnosis, making it easier to promptly discover and deal with problems in the output signal circuit.
[0019] Optionally, the fault isolation algorithm includes: defining a data set of detection results, in which target data corresponds to signal status, internal logic status and output signal status respectively; constructing a fault location decision tree to perform path judgment based on the target data to obtain fault information; based on the fault information, outputting the fault point and the corresponding solution.
[0020] By adopting the above technical solution, it is possible to accurately isolate and diagnose the fault of the main control circuit board. Specifically: by defining the data set of the test results, the target data in the data set corresponds to the signal state, internal logic state and output signal state respectively, which ensures the comprehensiveness and accuracy of the fault information. Constructing a fault location decision tree and making path judgments based on the target data improves the speed and accuracy of fault location and helps to quickly identify the specific fault point. Outputting the fault point and the corresponding solution based on the fault information not only clarifies the fault location, but also provides effective solutions, which facilitates maintenance personnel to take timely action and reduce downtime and maintenance costs.
[0021] Optionally, it also includes: displaying the detection results, highlighting abnormal situations, and displaying corresponding solutions. The abnormal situations include abnormalities in the input signal acquisition circuit, abnormalities in the main control chip logic, and abnormalities in the output signal circuit.
[0022] By adopting the above technical solutions, this function can display various intermediate results and final conclusions of the detection process in real time, so that operators can quickly understand the current operating status of the system. When circuit abnormalities, main control chip logic abnormalities, or output signal circuit abnormalities are detected, the system will automatically highlight these abnormalities to ensure that operators do not miss important fault information. For each abnormal situation, the system not only provides clear diagnostic results, but also comes with corresponding solution suggestions to help operators take quick measures to fix the problem and improve maintenance efficiency.
[0023] Optionally, the method further includes: classifying and storing the detection results corresponding to timestamps and device numbers.
[0024] By adopting the above technical solution, detailed recording and management of the main control circuit board fault detection results can be achieved. Specifically: the detection results are classified and stored according to the timestamp and device number, which can facilitate subsequent query and analysis of historical data and improve maintenance efficiency. This classified storage method helps to quickly locate the fault situation of a specific time period or a specific device, which is convenient for problem tracking and resolution. At the same time, this function can also provide support for long-term data analysis, help identify potential problem trends and patterns, and further improve the reliability and stability of the system.
[0025] In a second aspect, another embodiment of the present application discloses a fault analysis system applicable to a main control circuit board, which adopts the following scheme: A fault analysis system suitable for a main control circuit board comprises: a receiving module for receiving an input signal of a detection parameter; a sampling module for sampling and reading the input signal of the main control circuit board, and comparing the error between the sampled data and the read data; a first comparison and determination module for comparing the error with a first preset threshold value to determine whether the sampling circuit of the input signal is abnormal, and taking it as a first detection result; a first execution module for detecting the internal logic state of the main control chip if the first detection result is abnormal, and locating the fault based on a fault isolation algorithm as a second detection result; a second comparison and determination module for detecting the performance of the output signal, and comparing it with the preset parameters to determine whether the output signal circuit is abnormal, and taking it as a third detection result; a second execution module for detecting the internal logic state of the main control chip again if the third detection result is abnormal, and locating the fault based on the fault isolation algorithm as a fourth detection result; and a report generation module for collating the first detection result, the second detection result, the third detection result and the fourth detection result to generate a detection report.
[0026] By adopting the above technical solution, comprehensive fault detection of the main control circuit board can be achieved. First, by comparing the sampling and reading data of the input signal, it is possible to effectively identify whether there is an abnormality in the input signal acquisition circuit. Then, for the detected input signal abnormality, the internal logic state of the main control chip is further tested in detail, and the fault point is accurately located using the fault isolation algorithm, thereby improving the accuracy of fault diagnosis. At the same time, the system also conducts a comprehensive test on the performance of the output signal to ensure the normal operation of the output signal circuit. If the output signal circuit is found to be abnormal, the internal logic state of the main control chip is tested again to further confirm the cause of the fault. Finally, the system integrates all test results to generate a detailed test report, which is convenient for users to quickly understand and deal with fault problems.
[0027] In summary, the present application includes at least one of the following beneficial technical effects: 1. The input signal is collected and read respectively through the independent sampling circuit and the communication interface of the main control circuit board, and the errors of the two are compared, which can accurately detect whether the sampling circuit of the input signal is abnormal, thereby improving the accuracy of fault detection; 2. After confirming that the input signal sampling circuit is abnormal, the internal logic state of the main control chip is further tested, and the fault isolation algorithm is used to locate the fault, which can quickly and accurately find the specific fault point and its cause, improving the speed and accuracy of fault diagnosis; 3. Comprehensively test the performance of the output signal, including time domain analysis and frequency domain analysis, and compare it with the preset parameters, which can effectively identify abnormal conditions in the output signal circuit and enhance the reliability and stability of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 A schematic flow chart of a fault analysis method applicable to a main control circuit board disclosed in an embodiment of the present application; Figure 2 This is a schematic diagram of an example flow of a fault analysis method applicable to a main control circuit board disclosed in an embodiment of the present application; Figure 3 A structural schematic diagram of a fault analysis system applicable to a main control circuit board disclosed in another embodiment of the present application; Figure 4 This is a schematic diagram of the structure of an electronic device disclosed in yet another embodiment of the present application. DETAILED DESCRIPTION
[0029] The present application is further described in detail below in conjunction with the accompanying drawings.
[0030] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.
[0031] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "an" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.
[0032] It should be understood that although the terms "first", "second", etc. may be used in the present application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.
[0033] The technical solution of the embodiments of the present application is described in detail below with reference to the accompanying drawings.
[0034] [First embodiment] A fault analysis method suitable for a main control circuit board is disclosed in this embodiment, which is used to perform full-link comprehensive detection of the input signal, internal logic and output signal of the main control circuit board to accurately locate the fault problem of the main control circuit board and improve the efficiency of automated detection.
[0035] See also Figure 1 , a fault analysis method applicable to a main control circuit board comprises the following steps: S10, receiving an input signal of a detection parameter; Among them, the detection parameters are input through the LCD interface, such as voltage, current, frequency, signal amplitude range, etc. At the same time, when the main control circuit board is started, the system initialization will be performed.
[0036] S20, sampling and reading the input signal of the main control circuit board, and comparing the error between the sampled data and the read data; Among them, one sampling is to sample through an external independent sampling circuit to sample the real input signal, and one reading is to read the input signal in the main control chip from the communication interface on the main control circuit board, and the two results are compared to calculate the error of the sampling circuit. The specific step S20 includes the following steps: S21, collecting input signals in the main control circuit board via an independent sampling circuit as sampling data; The independent sampling circuit is directly connected to the input end of the main control circuit board to directly obtain the input signal as the sampling data, that is, the real input signal. It should be noted that the independent sampling circuit is not limited to a structure, and can achieve the same function.
[0037] S22, reading the input signal in the main control chip via the main control circuit board communication interface as read data; S23. Compare the sampled data and the read data to obtain an error.
[0038] The sampled data and the read data are, for example, current values, and the error value is the difference between the two. If there is a difference, it means that the two sampling results are different and an abnormality may occur.
[0039] S30, comparing the error with a first preset threshold to determine whether a sampling circuit of the input signal is abnormal, and taking the result as a first detection result; If the error exceeds the first preset threshold, it can be determined that the sampling circuit of the input signal is abnormal, otherwise, it is normal. In this way, whether the sampling circuit of the input signal is abnormal can be accurately detected based on the error, thereby improving the accuracy of fault detection.
[0040] For example, the sampling circuit detection method of the input signal is as follows: 1. The sampling data collected by the independent sampling circuit is Sreal(t); 2. The data read from the main control chip through the communication interface is Schip(t); 3. Calculate the error between the two: Error(t)=|Sreal(t)-Schip(t)|; 4. If Error(t) exceeds the first preset threshold, it is determined that the sampling circuit of the input signal is abnormal.
[0041] S40, if the first detection result is abnormal, then detect the internal logic state of the main control chip, and locate the fault based on the fault isolation algorithm as the second detection result; Among them, if an abnormality occurs in the input signal sampling circuit, continuing to detect the internal logic state of the main control chip can timely diagnose whether there is a problem inside the main control chip, thereby improving the reliability of the system.
[0042] Specifically, the internal logic state of the main control chip is detected in step S40, which specifically includes the following steps: S41, obtaining internal register data and task execution data of the main control chip through the communication interface; S42: Compare and detect the internal register data and the task execution data with the preset logic model respectively.
[0043] Among them, the internal register data and task execution data of the main control chip are read through a communication interface (such as SPI, I2C or UART). These data reflect the working state of the main control chip at a certain moment, such as the current value of each register and the list of tasks being executed. These data are compared with the preset logic model, that is, the pre-set standard model, to obtain the comparison result. In this embodiment, if any item deviates from the standard value, it is considered that the internal logic state of the main control chip is abnormal.
[0044] In another embodiment, step S42 includes the following steps: S421, comparing the internal register data with a preset logic model to obtain a first deviation value; S422, comparing the task execution data with a preset logic model to obtain a second deviation value; S423: If any one of the first deviation value and the second deviation value exceeds the preset logic threshold, a logic abnormality occurs; otherwise, the logic is normal.
[0045] Among them, the steps S421 to S423 compare the data in the internal register and the task execution data with the preset logic model respectively to obtain deviation values respectively, wherein if either of the two deviation values exceeds the preset logic threshold, it can be directly judged that there is an abnormality in the logic state of the main control chip, such as an abnormal value of a certain field of the register, a timeout of the task execution time, etc. In this way, the logic problem of the main control chip can be ensured to be discovered and located in time through this step, thereby effectively improving the stability and security of the system.
[0046] For example, the internal logic anomaly detection steps are as follows: 1. Get the register data set R={r1, r2, ...r n}; 2. Get the task execution status T={t1, t2, ...t n}, including completion rate, timeout flag, etc.; 3. Compare the data sets R and T with the preset logical model, △R=RM R , △T=T–M T ; 4. If △R or △T exceeds the threshold, it is marked as a logical abnormality; 5. Return the cause of the exception and suggestions.
[0047] For example: the value of a field in the returned register is abnormal, the task execution time has timed out, etc.
[0048] Additionally, fault isolation algorithms include: S43, defining a data set of detection results; Among them, the data set such as D={d1, d2, d3}, d1, d2, d3 as target data represent the input signal state, internal logic state and output signal state respectively.
[0049] S44, constructing a fault location decision tree to perform path judgment based on target data and obtain fault information; The specific location of the fault can be determined by using the fault location decision tree to determine the path of the target data in the data set. The fault location decision tree is an existing related technology and will not be described in detail here.
[0050] When d1 is abnormal, the problem is concentrated in the sampling circuit of the input signal. When d2 is abnormal, the problem is concentrated in the logic of the main control chip. When d3 is abnormal, the problem is concentrated in the output signal circuit.
[0051] S45. Based on the fault information, output the fault point and the corresponding solution.
[0052] The output fault point is the sampling circuit, the logic of the main control chip or the output signal circuit. The solution is the pre-stored information corresponding to the fault point, which not only clarifies the fault location, but also provides effective solutions, so that maintenance personnel can take timely actions to reduce downtime and maintenance costs.
[0053] S50, detecting the performance of the output signal and comparing it with the preset parameters to determine whether the output signal circuit is abnormal, and use it as the third detection result.
[0054] The output signal is a direct reflection of the overall performance of the main control board. Step S50 can comprehensively evaluate the quality of the output signal of the main control board to accurately detect the state of the output signal circuit. Specifically, it includes the following steps: S51, obtaining an output signal; Among them, the output signal can be obtained through the ADC module of the test equipment.
[0055] S52, performing time domain analysis on the output signal to calculate the signal amplitude and deviation data; Among them, by performing time domain analysis on the output signal, the amplitude and deviation data of the signal can be accurately calculated, thereby determining the stability of the signal in time.
[0056] S53, performing frequency domain analysis on the output signal to decompose the signal, and comparing the signal with the preset parameters to obtain a comparison result; Among them, by performing frequency domain analysis on the output signal, the signal components can be decomposed and compared with preset parameters, which can further verify whether the frequency characteristics of the signal meet expectations.
[0057] S54. Obtain a third detection result based on the signal amplitude, deviation data and comparison result.
[0058] Among them, based on the signal amplitude, deviation data and comparison results, they can be compared with the preset standard to obtain the result as the third detection result. In this way, it can be ensured that the output signal meets the standards in multiple dimensions, thereby improving the accuracy and reliability of fault diagnosis.
[0059] For example, the steps for output signal performance detection are as follows: 1. Get the output signal Sout(t); 2. Perform time domain analysis to calculate the signal amplitude and deviation: AmplitudeError=|Aout-Adesign|; 3. Perform frequency domain analysis and use fast Fourier transform (FFT) to decompose the signal: Sfreq(f)=FFT(Sout(t)); 4. Compare the spectrum characteristics Sfreq(f) with the design parameters Fdesign(f): △F=|Sfreq(f)-Fdesign(f)|; 5. Determine whether the signal performance meets the requirements based on the results of AmplitudeError and △F.
[0060] S60: If the third detection result is abnormal, the internal logic state of the main control chip is detected again, and the fault is located based on the fault isolation algorithm as the fourth detection result; Among them, the third detection result is abnormal, that is, the output signal circuit is abnormal. In order to find the specific fault, the operating state of the internal logic of the main control chip is detected again, and the fault is located based on the fault isolation algorithm. Here, the detection of the internal logic state of the main control chip and the fault isolation algorithm can be referred to the relevant description of the above step S40, which will not be repeated here.
[0061] S70, sorting out the first test result, the second test result, the third test result and the fourth test result, and generating a test report.
[0062] If the test report is output in PDF format, maintenance personnel can conduct a detailed analysis of the cause of the fault to facilitate subsequent maintenance and repair work.
[0063] Furthermore, in this embodiment, it also includes: S80, display the test results, highlight the abnormal situation, and display the corresponding solution; Among them, abnormal conditions include abnormal input signal acquisition circuit, abnormal main control chip logic, and abnormal output signal circuit. During the detection process, once a problem is found in a certain part, the abnormal condition will be immediately highlighted on the display screen. At the same time, the screen will also display recommended solutions to help maintenance personnel take quick action. This instant feedback mechanism helps reduce the risk of misjudgment and missed detection, and improves system reliability and user experience.
[0064] Furthermore, in this embodiment, it also includes: S90: Classify and store the detection results corresponding to the timestamps and device numbers.
[0065] After each test is completed, the system will automatically save the test results, timestamp, equipment number and other related information into the database. This allows historical records to be traced back for subsequent statistical analysis and quality management. In addition, by mining a large amount of data, potential trends and rules can be discovered, providing a reference for further optimizing product design.
[0066] In order to more clearly explain the technical solutions in the embodiments of the present application, please refer to Figure 2 , specifically including the following steps: S101, start detection; S102, setting parameters and system initialization; Please refer to the detailed description of step S10 above, which will not be repeated here.
[0067] S103, sampling and reading the input signal, and comparing it to obtain an error; Please refer to the detailed description of the above steps S21 to S23, which will not be repeated here.
[0068] S104, determining whether the error exceeds a first preset threshold, if so, executing step S105, if not, executing step S107; S105, perform internal logic state detection, and execute the following step S106; Please refer to the detailed description of the above steps S41-S42, S421-S423, which will not be repeated here.
[0069] S106, perform fault isolation and diagnosis, and execute the following step S107; Please refer to the detailed description of the above steps S43 to S45, which will not be repeated here.
[0070] S107, perform output signal performance detection, and execute the following step S108; S108, comparing the output signal with the preset parameters to determine whether it is normal, if so, executing step S111, if not, executing step S109; Please refer to the detailed description of the above steps S51 to S54, which will not be repeated here.
[0071] S109, perform internal logic state detection and execute the following step S110; Please refer to the detailed description of the above steps S41-S42, S421-S423, which will not be repeated here.
[0072] S110, perform fault isolation and diagnosis, and execute the following step S111; Please refer to the detailed description of the above steps S43 to S45, which will not be repeated here.
[0073] S111, generating a report and storing data; Please refer to the detailed description of the above steps S70 and S90, which will not be repeated here.
[0074] S112: Detection completed.
[0075] In summary, the first embodiment of the present invention discloses a fault analysis method suitable for a main control circuit board. By collecting and reading input signals respectively through an independent sampling circuit and a communication interface of the main control circuit board and comparing the errors between the two, it is possible to accurately detect whether the sampling circuit of the input signal is abnormal, thereby improving the accuracy and reliability of fault detection. When an abnormality is detected in the input signal sampling circuit, the internal logic state of the main control chip is further detected in detail, and the fault is located using a fault isolation algorithm, so that the specific fault point and its cause can be found, significantly improving the accuracy of fault diagnosis. The performance of the output signal is comprehensively detected, and the results of time domain analysis and frequency domain analysis are combined and compared with preset parameters, so that the abnormality of the output signal circuit can be effectively identified, thereby enhancing the overall stability and safety of the system.
[0076] [Second embodiment] See also Figure 3 In the second embodiment of the present application, a fault analysis system suitable for a main control circuit board is disclosed, the system including: a receiving module 210, a sampling module 220, a first comparison and determination module 230, a first execution module 240, a second comparison and determination module 250, a second execution module 260 and a report generation module 270.
[0077] Among them, the receiving module 210 is used to receive the input signal of the detection parameter; the sampling module 220 is used to sample and read the input signal of the main control circuit board, and compare the errors of the sampled data and the read data; the first comparison and determination module 230 is used to compare the error with the first preset threshold value to determine whether the sampling circuit of the input signal is abnormal, and use it as the first detection result; the first execution module 240 is used to detect the internal logic state of the main control chip if the first detection result is abnormal, and locate the fault based on the fault isolation algorithm as the second detection result; the second comparison and determination module 250 is used to detect the performance of the output signal and compare it with the preset parameters to determine whether the output signal circuit is abnormal, and use it as the third detection result: the second execution module 260 is used to detect the internal logic state of the main control chip again if the third detection result is abnormal, and locate the fault based on the fault isolation algorithm as the fourth detection result; the report generation module 270 is used to organize the first detection result, the second detection result, the third detection result and the fourth detection result to generate a detection report.
[0078] It should be noted that the fault analysis method applicable to the main control circuit board implemented by the fault analysis system applicable to the main control circuit board disclosed in the second embodiment of the present application is the same as the first embodiment, so it will not be described in detail here.
[0079] Optionally, the various modules in this embodiment and the above-mentioned other operations or functions are respectively for implementing the methods in the aforementioned embodiments.
[0080] [Third embodiment] See also Figure 4 In the third embodiment of the present application, an electronic device is disclosed, which includes: a memory 310 and a processor 320, the memory 310 is used to store computer programs; the processor 320 is used to implement the steps of a fault analysis method applicable to a main control circuit board described in the first embodiment when executing the computer program. For details, please refer to the above, so it will not be described in detail here.
[0081] The technical effect of an electronic device provided by this embodiment in actual application is the same as the technical effect of a fault analysis method applicable to a main control circuit board in the first embodiment.
[0082] [Fourth embodiment] In the fourth embodiment of the present application, a computer-readable storage medium is disclosed. The computer-readable storage medium is, for example, a non-volatile memory, such as: a magnetic medium (such as a hard disk, a floppy disk, and a magnetic tape), an optical medium (such as a CDROM disk and a DVD), a magneto-optical medium (such as an optical disk), and a hardware device specially constructed to store and execute computer-executable instructions (such as a read-only memory (ROM), a random access memory (RAM), a flash memory, etc.). A computer program is stored on the computer-readable storage medium. The computer-readable storage medium can be executed by one or more processors or processing devices to implement a fault analysis method suitable for a main control circuit board in the aforementioned embodiment.
[0083] In addition, it can be understood that the aforementioned embodiments are only exemplary descriptions of the present invention. Under the premise that the technical features do not conflict, the structures do not contradict, and the purpose of the present invention is not violated, the technical solutions of the various embodiments can be arbitrarily combined and used in combination.
[0084] In the several embodiments provided by the present invention, it should be understood that the disclosed methods, systems and devices can be implemented in other ways. For example, the modules included in the system described above are only schematic, and the division of modules is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.
[0085] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.
[0086] In addition, each functional unit / module in each embodiment of the present invention may be integrated into one processing unit / module, or each unit / module may exist physically separately, or two or more units / modules may be integrated into one unit / module. The above-mentioned integrated unit / module may be implemented in the form of hardware or in the form of hardware plus software functional units / modules.
[0087] The above-mentioned integrated unit / module implemented in the form of a software functional unit / module can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for enabling one or more processors of a computer device (which can be a personal computer, a server, or a network device, etc.) to perform some steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store program codes.
[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A fault analysis method applicable to a main control circuit board, characterized in that: include: receiving an input signal of a detection parameter; Sampling and reading the input signal from the main control circuit board, and comparing the errors between the sampled data and the read data; Comparing the error with a first preset threshold to determine whether a sampling circuit of the input signal is abnormal, and taking the result as a first detection result; If the first detection result is abnormal, the internal logic state of the main control chip is detected, and the fault is located based on the fault isolation algorithm as the second detection result; The performance of the output signal is tested and compared with the preset parameters to determine whether the output signal circuit is abnormal and serve as the third test result: If the third detection result is abnormal, the internal logic state of the main control chip is detected again, and the fault is located based on the fault isolation algorithm as the fourth detection result; The first test result, the second test result, the third test result and the fourth test result are collated to generate a test report.
2. The method according to claim 1, characterized in that When the first detection result is normal, the performance of the output signal is directly detected and compared with the preset parameters to determine whether the output signal circuit is abnormal, and the result is used as the third detection result; When the third test result is normal, the test report is directly generated.
3. The method according to claim 1, characterized in that: The sampling and reading of the input signal from the main control circuit board and comparing the errors between the sampled data and the read data include: The input signal in the main control circuit board is collected via an independent sampling circuit as sampling data; Reading the input signal in the main control chip via the main control circuit board communication interface as read data; The sampled data and the read data are compared to obtain the error.
4. The method according to claim 1, characterized in that: The detecting of the internal logic state of the main control chip includes: Obtaining the internal register data and task execution data of the main control chip through the communication interface; The internal register data and the task execution data are respectively compared and detected with a preset logic model.
5. The method according to claim 4, characterized in that The comparing and detecting the internal register data and the task execution data with a preset logic model respectively includes: Comparing the internal register data with a preset logic model to obtain a first deviation value; Comparing the task execution data with a preset logic model to obtain a second deviation value; If any one of the first deviation value and the second deviation value exceeds a preset logic threshold, a logic abnormality occurs; otherwise, the logic is normal.
6. The method according to claim 1, characterized in that The performance of the output signal is detected and compared with the preset parameters to determine whether the output signal circuit is abnormal and take it as the third detection result, including: Acquire the output signal; Performing time domain analysis on the output signal to calculate signal amplitude and deviation data; Performing frequency domain analysis on the output signal to decompose the signal, and comparing the signal with the preset parameters to obtain a comparison result; The third detection result is obtained based on the signal amplitude, the deviation data and the comparison result.
7. The method according to claim 4, characterized in that The fault isolation algorithm includes: Defining a data set of the detection results, wherein the target data in the data set respectively correspond to the signal state, the internal logic state and the output signal state; Construct a fault location decision tree to perform path judgment based on the target data and obtain fault information; Based on the fault information, the fault point and the corresponding solution are output.
8. The method according to claim 1, characterized in that Also includes: The detection results are displayed, and abnormal situations are highlighted, and corresponding solutions are displayed. The abnormal situations include abnormalities in the acquisition circuit of the input signal, abnormalities in the logic of the main control chip, and abnormalities in the output signal circuit.
9. The method according to claim 8, characterized in that Also includes: The detection results are classified and stored corresponding to the timestamp and the device number.
10. A fault analysis system suitable for a main control circuit board, characterized in that: include: A receiving module, used for receiving an input signal of a detection parameter; A sampling module, used for sampling and reading the input signal from the main control circuit board, and comparing the error between the sampled data and the read data; A first comparison and determination module, used for comparing the error with a first preset threshold value to determine whether a sampling circuit of the input signal is abnormal, and taking the result as a first detection result; A first execution module, configured to detect the internal logic state of the main control chip and locate the fault based on a fault isolation algorithm as a second detection result if the first detection result is abnormal; The second comparison and determination module is used to detect the performance of the output signal and compare it with the preset parameters to determine whether the output signal circuit is abnormal and use it as the third detection result: A second execution module is used for, if the third detection result is abnormal, re-detecting the internal logic state of the main control chip and locating the fault based on the fault isolation algorithm as a fourth detection result; The report generation module is used to organize the first test result, the second test result, the third test result and the fourth test result to generate a test report.