End-to-end compilation method for coarse-grained reconfigurable arrays based on hierarchical data flow

Abstract

The present invention provides an end-to-end compilation method for a coarse-grained reconfigurable array based on hierarchical data flow, which relates to the field of automated compilation technology. The method includes: converting the programming code to be compiled into an optimized intermediate representation of MLIR, and converting it into a front-end data stream of multiple hierarchical data streams, and then converting it into a CGRA back-end data stream according to a preset unloading strategy, and then unloading it through the Kernel kernel code to obtain the target kernel code, and then generate the CGRA mapping configuration information of the kernel code data flow graph. Finally, the host object file generated by the host side code is combined to construct an executable file. Through this application, the problem of manually marking the accelerated kernel code through progma annotation during CGRA end-to-end compilation is solved, which makes code editing time-consuming and labor-intensive, and ignores the data transmission and linking of the host side code and the CGRA kernel side code, and cannot effectively exert the CGRA acceleration performance.

Description

Technical Field

[0001] The present invention relates to the field of automated compilation technology, and in particular to an end-to-end compilation method of a coarse-grained reconfigurable array based on hierarchical data flow. Background Art

[0002] A coarse-grained reconfigurable array (CGRA) is a computing architecture that combines the flexibility of a general-purpose processor with the efficiency of an application-specific integrated circuit (ASIC). The CGRA workflow generally consists of two major steps: data flow graph extraction and data flow graph mapping and configuration generation. CGRA compilation begins with source code input, which can be written in a general-purpose high-level language (such as C++) or a domain-specific language (DSL) to describe task information. Subsequently, code separation is performed based on software and hardware. Generally speaking, CGRA is suitable for executing loop-based code. Therefore, the goal of this separation is to treat the loop-based code as hardware code and the remaining code as software code. Compilation yields a general-purpose processor executable file. The hardware code requires front-end processing, code transformation, and optimization. The resulting optimized code then undergoes memory allocation and time / space domain partitioning. After these transformations, the resulting optimized intermediate representation is used for task scheduling and control module generation. The final intermediate representation (IR) is then used to generate a data flow graph. This data flow graph, along with the hardware description file, serves as input to the mapping module.

[0003] CGRA's end-to-end compilation consists of two main parts: front-end code partitioning, modification, optimization, and scheduling mapping, and back-end scheduling and mapping. For the front-end, existing solutions in the field of coarse-grained reconfiguration only use manual progma annotation to annotate the kernel code that needs to be accelerated for specific applications. The annotated kernel code is processed by the Low Level Virtual Machine (LLVM) front-end, which is the framework system for the compiler, to generate the corresponding intermediate code. The intermediate code is then converted into a data flow graph and input into the corresponding CGRA mapper to map the corresponding configuration information. However, manual progma annotation requires programmers to expend significant effort on code editing and only generates data flow graphs for the annotated kernel code. CGRA scheduling is primarily based on loops as the basic unit. Since manual annotation treats each annotated code as an independent kernel code for offloading, it ignores the data transmission and linking between the host-side code and the CGRA kernel-side code. Summary of the Invention

[0004] The present invention provides an end-to-end compilation method for a coarse-grained reconfigurable array based on hierarchical data flow, which is used to solve the problem in the prior art that, during the end-to-end compilation of CGRA, the kernel code that needs to be accelerated is marked by manual progma annotation. Not only is the code editing process time-consuming and labor-intensive, but the data transmission and linking between the host-side code and the CGRA kernel-side code are ignored, and the CGRA acceleration performance cannot be effectively utilized.

[0005] The present invention provides an end-to-end compilation method for a coarse-grained reconfigurable array based on hierarchical data flow, the method comprising the following steps:

[0006] Converting the programming code to be compiled into an optimized intermediate representation of MLIR, and converting the optimized intermediate representation into a front-end data stream through a CGRA data stream operator, wherein the data structure of the front-end data stream is a tree structure of multiple hierarchical data streams, and the hierarchical data streams are generated according to the nested loop structure in the programming code to be compiled;

[0007] Converting the front-end data stream into a back-end data stream of CGRA according to a preset offloading strategy;

[0008] Performing automated kernel code unloading on the backend data flow to obtain target kernel code, and generating a corresponding kernel code data flow graph based on the target kernel code;

[0009] Generate a host object file based on the host side code without the Kernel kernel code, and generate corresponding CGRA mapping configuration information according to the kernel code data flow graph,

[0010] The host object file and the CGRA mapping configuration information are compiled to obtain an executable file of the programming code to be compiled.

[0011] In some embodiments, converting the optimized intermediate representation into a front-end data flow through a CGRA data flow operator includes:

[0012] determining a nested loop structure in the optimized intermediate representation;

[0013] According to the task operator in the CGRA data flow operator, the nested loop structure is reused as a task node, wherein each same-level loop structure in the nested loop structure is reused as a task node;

[0014] The optimized intermediate representation is layered according to the task nodes to obtain a corresponding hierarchical data flow.

[0015] In some embodiments, converting the front-end data stream into a back-end data stream of CGRA according to a preset offloading policy includes:

[0016] Performing a validity check on the front-end data stream, and converting the front-end data stream into a CGRA back-end data stream when the front-end data stream meets the validity conditions included in the preset offloading policy;

[0017] The legal conditions include:

[0018] The hardware parameter information of the Kernel kernel code in the front-end data stream meets the PE computing resource restrictions and I / O port restrictions of CGRA;

[0019] The operators included in the Kernel kernel code in the front-end data stream meet the back-end hardware support of CGRA;

[0020] In the Kernel kernel code in the front-end data stream, the ratio of the number of memory read and write operations to the total number of computing operations is not greater than a preset ratio threshold.

[0021] In some embodiments, the memory access mode of the backend data stream of the CGRA in the CGRA is a dual-layer access mode, and the dual-layer access mode includes: software dual-layer access and hardware dual-layer access;

[0022] The software dual-layer access includes:

[0023] Extract the memory subview corresponding to the backend data stream of the CGRA, and configure the L / S controller of the CGRA according to the cache access mode of the memory subview to transfer the block memory corresponding to the memory subview to the cache area of ​​the CGRA;

[0024] Reading a corresponding data stream from a block memory in a cache area of ​​the CGRA to an I / O port of the CGRA for PE operation according to memory access mode information of an L / S instruction in a node area, wherein the node area is an area storing kernel code in the backend data stream;

[0025] The hardware dual-layer access includes:

[0026] Read the target memory configuration information of the backend data stream to the memory configuration management module of the L / S controller and the I / O control of the CGRA respectively;

[0027] The target memory configuration information is read from the memory configuration management module through CGRA, and a controller unit corresponding to the CGRA is configured according to the target memory configuration information to perform memory access on the back-end data stream.

[0028] In some embodiments, performing automated kernel code unloading on the backend data stream to obtain target kernel code includes:

[0029] Determining, among the task nodes of the hierarchical data flow in the backend data flow, a target node representing the innermost loop body code in the nested loop structure;

[0030] Uninstall the kernel code corresponding to the target node to obtain the target kernel code.

[0031] In some embodiments, generating a host object file based on the host-side code without the kernel code includes:

[0032] The host-side code without the kernel code is lowered to the MLIR intermediate representation through the MLIR descent channel;

[0033] Lowering the MLIR intermediate representation to an LLVM compiler dialect, and converting the LLVM compiler dialect to an LLVM compiler intermediate representation;

[0034] Build host object files based on the LLVM compiler intermediate representation.

[0035] The present invention also provides an end-to-end compilation device for a coarse-grained reconfigurable array based on hierarchical data flow, the device comprising the following modules:

[0036] a conversion module, configured to convert the programming code to be compiled into an optimized intermediate representation of MLIR, and convert the optimized intermediate representation into a front-end data stream through a CGRA data stream operator, wherein the data structure of the front-end data stream is a tree structure of multiple hierarchical data streams, and the hierarchical data streams are generated according to the nested loop structure in the programming code to be compiled;

[0037] The conversion module is further configured to convert the front-end data stream into a back-end data stream of CGRA according to a preset offloading strategy;

[0038] An unloading module is used to perform automatic kernel code unloading on the backend data flow to obtain a target kernel code and generate a corresponding kernel code data flow graph based on the target kernel code;

[0039] A generation module, configured to generate a host object file based on the host side code without the kernel code, and generate corresponding CGRA mapping configuration information according to the kernel code data flow graph;

[0040] A compiling module is used to compile the host object file and the CGRA mapping configuration information to obtain an executable file of the programming code to be compiled.

[0041] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the end-to-end compilation method for a coarse-grained reconfigurable array based on hierarchical data flow as described above is implemented.

[0042] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the end-to-end compilation method of the coarse-grained reconfigurable array based on hierarchical data flow as described above is implemented.

[0043] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned end-to-end compilation methods for a coarse-grained reconfigurable array based on hierarchical data flow.

[0044] The end-to-end compilation method for a coarse-grained reconfigurable array based on hierarchical data flow provided by the present invention implements automated kernel code offloading through CGRA after the front-end data flow is converted to the back-end data flow. Furthermore, the code is optimized through a hierarchical data flow based on a nested loop structure, capable of handling a variety of complex, large-scale application codes. This eliminates the need for programmers to perform code editing on kernel code that needs to be accelerated, and programmers do not need to be aware of the existence of CGRA, saving time and effort. Furthermore, the host-side code and kernel code are first separated and then linked and compiled to ultimately generate an executable file, achieving joint optimization of the host and CGRA sides and effectively leveraging the optimization performance of CGRA. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced one by one below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 It is a flow chart of an end-to-end compilation method of a coarse-grained reconfigurable array based on hierarchical data flow provided by the present invention.

[0047] Figure 2 This is a schematic diagram of the framework of the end-to-end compilation method for the coarse-grained reconfigurable array based on hierarchical data flow provided by the present invention.

[0048] Figure 3 This is an example diagram of the CGRA data flow operator provided by the present invention.

[0049] Figure 4This is an example diagram of the visualization of the Kernel kernel code data flow graph provided by the present invention.

[0050] Figure 5 This is a schematic diagram of generating a hierarchical data stream provided by the present invention.

[0051] Figure 6 It is a structural diagram of an end-to-end compilation device of a coarse-grained reconfigurable array based on hierarchical data flow provided by the present invention.

[0052] Figure 7 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0053] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0054] The end-to-end compilation method for a coarse-grained reconfigurable array based on hierarchical dataflow, provided by the present invention, can be implemented in compilers for various programming languages. The compiler optimizes the compiled programming code and generates a corresponding executable file for computer execution. By implementing the end-to-end compilation method for a coarse-grained reconfigurable array based on hierarchical dataflow in a compiler, the present invention also implements a hierarchical dataflow-oriented multi-stage optimizing CGRA compiler (HDCC) for reconfigurable computing arrays.

[0055] Taking the compiler HDCC as an example, the end-to-end compilation method of the coarse-grained reconfigurable array based on hierarchical data flow implemented on the compiler HDCC is described below with reference to the accompanying drawings. Figure 1 This is a flow chart of an end-to-end compilation method for a coarse-grained reconfigurable array based on hierarchical data flow provided by the present invention. Figure 1 As shown, the method includes the following steps 101 to 105.

[0056] Step 101: Convert the programming code to be compiled into an optimized intermediate representation of MLIR, and convert the optimized intermediate representation into a front-end data stream through a CGRA data stream operator.

[0057] First, when a programmer edits programming code in the compiler (HDCC), the compiled code is retrieved as the programming code to be compiled. In this embodiment of the present invention, the compiler is implemented based on the Multi-Level Intermediate Representation (MLIR) compilation infrastructure, so the compiler here is called a multi-level intermediate representation compilation system. Of course, there are many programming languages ​​and encoding codes, such as C / C++ and PyTorch.

[0058] After obtaining the programming code to be compiled, the programming code to be compiled is converted into the optimized intermediate representation of MLIR. Depending on the programming language, it will also be converted into different optimized intermediate representations of MLIR. Figure 2 As shown, Figure 2 This diagram illustrates the framework of the end-to-end compilation method for a coarse-grained reconfigurable array based on hierarchical dataflow. The programming code to be compiled can be in either C / C++ or PyTorch. For C / C++, the multi-level intermediate representation used for the conversion is Polygeist, while for PyTorch, the multi-level intermediate representation used is Torch-MLIR.

[0059] Next, the optimized intermediate representation is converted to the front-end data stream using the CGRA dataflow operator. However, before this conversion, dialect conversion is performed on the multi-level intermediate representations of certain programming languages. Here, the multi-level intermediate representation's Linalg dialect is further downgraded to the Affine dialect using MLIR built-in conversion. This downgrade is achieved using MLIR built-in optimization technology.

[0060] Continue to see Figure 2 After the Linalg dialect is uniformly converted to the optimized intermediate representation of the Affine dialect, the optimized intermediate representation is converted into the front-end data stream through the CGRA data stream operator at the front end of the data stream. The CGRA data stream operator is specifically some processing functions for processing the Affine dialect. The processing function example can be as follows Figure 3 As shown, these CGRA data flow operators are used to perform some specific operations of the front-end data flow.

[0061] The process of converting to the front-end data flow is to lower the optimized intermediate representation of the Affine dialect to the front-end data flow (Lower to Frontend Dataflow). The data structure of the front-end data flow is a tree structure of multiple hierarchical data flows, and the hierarchical data flow is generated based on the nested loop structure in the programming code to be compiled.

[0062] Specifically, at the data flow front end, the cgra.task and cgra.dispatch operators in the CGRA data flow operators are first used to hierarchically construct the nested loop structures in the optimized intermediate representation of the Affine dialect, resulting in multiple hierarchical data flows. Loop optimization and data flow optimization are then performed on the hierarchical data flows to construct a corresponding hierarchical data flow tree structure. Loop optimization can be performed based on the number of processing elements (PEs), the number of input / output (I / O) ports, and the cache size of the CGRA hardware parameter information, using block optimization and loop unrolling. Block optimization and loop unrolling can be implemented using MLIR. In the final MLIR tool command line options, a json file describing the CGRA hardware parameter information can be specified, and the relevant information can be read to perform block optimization and loop unrolling. This ensures that the converted front-end data flow is legal when subsequently converted to the back end.

[0063] Data flow optimization determines the load balance of different kernel codes in the optimized intermediate representation of the Affine dialect while satisfying CGRA hardware constraints. This ensures that CGRA can execute different kernel codes simultaneously to the maximum extent possible and fully utilize all computing resources. This ensures that kernels with different loads receive different numbers of PE resources based on their kernel size. The number of computational operations per kernel is counted to estimate the number of PEs and time required for each kernel, and this data is used to schedule resources for each kernel code.

[0064] Step 102: Convert the front-end data stream into a CGRA back-end data stream according to a preset offloading policy.

[0065] like Figure 2 As shown in the figure, after the optimized intermediate representation is converted into the front-end data flow at the front-end of the data flow, the front-end data flow is lowered to the back-end data flow (Lower to Backend Dataflow), that is, the front-end data flow is lowered to the back-end data flow, specifically, the intermediate representation of the front-end data flow is converted into the intermediate representation of the back-end of the data flow.

[0066] At the data flow backend, the frontend data stream needs to be converted to the CGRA backend data stream according to the preset offloading strategy. However, before the conversion, the intermediate representation of the frontend data stream should be checked for validity. This process reads the CGRA hardware parameter description JSON file and determines whether the corresponding kernel code can be successfully offloaded to CGRA based on the PE data, I / O port information, and other information in the file. It also needs to check whether the operators contained in the kernel code are supported by the CGRA backend hardware. Even if the current kernel code meets all hardware constraints, this only ensures that CGRA can correctly execute the current kernel code. However, because CGRA's execution efficiency is significantly affected by the mapping effect of the CGRA mapper, not all kernel code can achieve better execution performance than the CPU. Therefore, heuristic offloading methods can be used to tailor the characteristics of different kernel codes. Therefore, corresponding offloading strategies can be formulated based on the characteristics of the kernel code, such as the proportion of memory read and write operations to the total number of computational operations, and the proportion of computational resources required for memory read and write operations to the total allocated computational resources.

[0067] After the intermediate representation of the front-end data stream has been checked for legality and is determined to meet the corresponding offloading policy, it can be converted into the intermediate representation of the back-end data stream of CGRA at the data stream back-end.

[0068] Step 103: Automated kernel code unloading is performed on the backend data stream to obtain the target kernel code, and a corresponding kernel code data flow graph is generated based on the target kernel code.

[0069] After the intermediate representation conversion of the backend data stream of CGRA is completed, the kernel code is automatically unloaded on the backend data stream to obtain the target kernel code. Figure 2 As shown, first the intermediate representation of the backend data stream is lowered to CGRA (Lower to CGRA), with the goal of converting the intermediate representation of the backend data stream belonging to the Affine dialect into the corresponding coarse-grained reconfigurable array dialect (CGRA Dialect). Then, automatic kernel code unloading is performed, which means that automatic kernel code unloading (Auto Kernel Offloading) is performed on the backend data stream. During the unloading process, hardware and software separation is performed on the current compiler HDCC to separate the kernel code from the host side (CPU side) code. As shown Figure 2As shown in the figure, by kernel code unloading, the host side code (MLIR Host Code) without the kernel code belonging to the software aspect and the target kernel code (MLIR Kernels) belonging to the hardware aspect are separated.

[0070] Specifically, the intermediate representation of the back-end data flow is still multiple hierarchical data streams, which are constructed based on the nested loop structure. Therefore, during the offloading process, the separation of the MLIR host-side code and the Kernel kernel code obtained by the compiler HDCC offloading can be performed according to each hierarchical data stream.

[0071] In terms of hardware, the corresponding kernel code data flow graph can be generated based on the target kernel code (MLIR Kernels). The unloaded target kernel code is input into the data flow graph generation module of the compiler HDCC to generate the corresponding kernel code data flow graph. For example, the data flow graph of the kernel code can be seen in Figure 4 .

[0072] The data flow graph generation module analyzes the MLIR intermediate representation of the target kernel code in the cgra.node / launch region. Using the built-in MLIR interface, it hierarchically analyzes the loop structure and memory access patterns of the nested loops in the target kernel code, as well as the relevant operators to be executed. It then maps the corresponding MLIR IR to the target architecture instruction parameters to generate a data flow graph that can replace the original MLIR IR nested loops.

[0073] This embodiment of the present invention provides an implementation for directly generating a data flow graph containing the information required by the CGRA mapping module from the MLIR intermediate representation. This solution does not directly pass the MLIR intermediate representation down to the LLVM compiler to generate the data flow graph. Because the LLVM intermediate representation is more low-level, the relevant information is converted to the most basic instruction representation in the LLVM intermediate representation. Therefore, when obtaining information such as memory addresses and memory offsets, the LLVM intermediate representation is more difficult to analyze and obtain. Compared to solutions that generate data flow graphs based on the LLVM intermediate representation, the solution of the present invention that directly generates data flow graphs using the MLIR intermediate representation is simpler and easier to expand.

[0074] Step 104: Generate a host object file based on the host-side code without the kernel code, and generate corresponding CGRA mapping configuration information according to the kernel code data flow graph.

[0075] In step 103, when the kernel code is uninstalled, the host side code without the kernel code is separated. Here, on the host side (CPU side) of the software, a host object file can be generated based on the host side code without the kernel code. Figure 2 As shown in the figure, the host-side code (MLIR Host Code) without the kernel code can be descended to the LLVM side (Lower to LLVM) through the descent path and converted into the LLVM intermediate representation (LLVM IR). Then, the LLVM backend generation tool is used to generate the corresponding host object file, that is, the host module object file, from the LLVM compiler intermediate representation corresponding to the host-side code.

[0076] On the hardware side, the CGRA generates the kernel code data flow graph for the target kernel code (MLIR Kernels), and then builds the corresponding CGRA mapping configuration information. The target kernel code data flow graph is saved in DOT format after generation, and converted into JSON format through the dot-Tdot_json command of graphviz. Together with the CGRA architecture information file, it is used as the input of the mapping unit, and the data flow graph can also be visualized (such as Figure 4 ). The kernel code data flow graph is mapped through the coarse-grained reconfigurable array mapping module (CGRA Mapper) to obtain the coarse-grained reconfigurable array mapping configuration information (Configuration), and the corresponding CGRA interface is encapsulated into a C language call function based on the coarse-grained reconfigurable array mapping configuration information. After the host side code is lowered, the corresponding CGRA call interface can be generated through the cgra.node interface. This CGRA call interface is used to call this C language call function, thereby obtaining the CGRA mapping configuration information to configure the CGRA, including PE configuration and memory / IO port configuration, for subsequent compilation execution.

[0077] Step 105: compile the host object file and the CGRA mapping configuration information to obtain an executable file of the programming code to be compiled.

[0078] like Figure 2As shown, after generating the host object file and the coarse-grained reconfigurable array mapping configuration information through step 104, the last step is the compilation and linking process. According to the CGRA mapping module (CGRA Mapper), the CGRA mapping configuration information (Configuration) can be generated into a corresponding configuration template (Config Template). Then, the host object file and the configuration template are input into the host compilation tool chain (for example, RISCV-GNU-Toolchain). The two are first linked, and then the linked file is compiled to obtain an executable file of the programming code to be compiled for execution by the computer host. The executable file under the coarse-grained reconfigurable array is as follows: Figure 2 As shown, in the coarse-grained reconfigurable array, the PE processing units are controlled simultaneously by the memory controller and the configuration controller, so that when the executable file is executed on the computer host, the PE processing units are controlled to perform related calculations.

[0079] In this embodiment of the present invention, after the front-end data stream is converted to the back-end data stream, CGRA is used to automatically offload the kernel code. Furthermore, the code is optimized through a hierarchical data stream based on a nested loop structure. This allows for processing a variety of complex, large-scale application codes, eliminating the need for programmers to edit the kernel code required for acceleration. Programmers do not need to be aware of the existence of CGRA, saving time and effort. Furthermore, the host-side code and the kernel code are first separated and then linked and compiled to ultimately generate an executable file. This achieves joint optimization of the host and CGRA sides from both the hardware and software perspectives, effectively leveraging the optimization capabilities of CGRA.

[0080] In some embodiments, at the data flow front end, the optimized intermediate representation is converted into a front-end data flow through the CGRA data flow operator, and its main process is to determine the corresponding hierarchical data flow. Specifically, the nested loop structure in the optimized intermediate representation is first determined, and the compiler HDCC can be used to query and determine the nested loop structure in the optimized intermediate representation. The nested loop structure is a multi-layer nested loop structure code of the programming code to be compiled. After being converted into the optimized intermediate representation of MLIR, the compiler HDCC can determine the nested loop structure in the optimized intermediate representation one by one.

[0081] Next, according to the task operator in the CGRA data flow operator, the nested loop structure is reused as a task node, and each loop structure at the same level in the nested loop structure is reused as a task node.

[0082] Here, the CGRA data flow operators can be the two task operators cgra.task and cgra.dispatch. cgra.task can reuse the nested loop structure as a task node, while cgra.dispatch is responsible for counting cgra.task and distributing it.

[0083] like Figure 5 As shown, since the compiled programming code may contain multiple nested loop structures, a complete nested loop structure in the optimized intermediate representation of MLIR can be represented as a cgra.schedule function through cgra.dispatch. Two nested loop structures cgra.node exist within this function, indicating the need to reuse two cgra.tasks. Each cgra.task corresponds to a nested loop structure cgra.node. These two nested loop structures are at the same level and not nested, so the two cgra.tasks are also at the same level. Because each loop structure at the same level is reused as a task node, two task nodes are expanded under the task list (Schedule) corresponding to the cgra.schedule function. These two task nodes are at the same level, forming a tree structure.

[0084] like Figure 5 As shown, each cgra.task corresponds to a nested loop structure cgra.node. After entering the next layer of the nested loop, the task node Node corresponding to this cgra.node will be used as the task list (Schedule) corresponding to the cgra.schedule function in the next layer. Figure 5 As shown, the two task nodes Node are used as two task lists Schedule respectively.

[0085] After constructing the cgra.schedule function through cgra.dispatch, it continues to distribute the corresponding cgra.task to the next layer of loop cgra.node. At the same time, it continues to expand the corresponding multiple task nodes Node under each task list (Schedule), so that the tree structure continues to extend downward until it reaches the innermost code layer of the nested loop structure, that is, the bottom layer of the tree structure.

[0086] Through the above steps, the optimized intermediate representation is layered according to the task nodes, resulting in a corresponding hierarchical data flow. Using the task nodes, the entire MLIR optimized intermediate representation is converted into a multi-layered tree structure according to the hierarchical data flow. This converts the nested loop structure in the optimized intermediate representation into multiple hierarchical data flows as the front-end data flow.

[0087] In an embodiment of the present invention, at the front end of the data flow, the optimized intermediate representation of MLIR of the programming code to be compiled is hierarchically processed, and the optimized intermediate representation of MLIR is converted into a hierarchical data structure according to a nested loop structure, which can provide a larger optimization space for the programming code.

[0088] In some embodiments, the front-end data stream is converted into the back-end data stream of CGRA according to a preset offloading policy, including: performing a legitimacy check on the front-end data stream, and when the front-end data stream meets the legitimacy conditions included in the preset offloading policy, converting the front-end data stream into the back-end data stream of CGRA.

[0089] The purpose of the validity check is to ensure that the subsequent kernel code can be successfully offloaded to the CGRA. The preset offload policy includes the legal conditions that need to be met during the validity check. The legal conditions include the following three points, which are explained one by one below.

[0090] First, the hardware parameter information of the kernel code in the front-end data stream must meet the CGRA's PE computing resource and I / O port restrictions. This means that the PE computing resources and I / O ports required to execute the kernel code must not exceed the restrictions. Second, the operators contained in the kernel code in the front-end data stream must meet the CGRA back-end hardware support requirements. This means that the operators contained in the kernel code must be supported by the CGRA back-end hardware. If the hardware conditions do not support the operators, offloading cannot be achieved.

[0091] In general, if the above two points are met, it can be determined that the front-end data stream is legal. However, judging it as legal only ensures that CGRA can correctly execute the current Kernel code. Since the execution efficiency of CGRA is greatly affected by the mapping effect of the CGRA mapper, not all Kernels can achieve better execution performance than the CPU. The compiler HDCC allows the use of heuristic unloading according to different code characteristics. For example, some programming codes have many calculation operations, and some programming codes occupy a large amount of memory. Therefore, in some embodiments, the unloading of the Kernel code must also meet the third point, that is, the ratio of the number of memory read and write operations to the total number of calculation operations in the Kernel code in the front-end data stream is not greater than the preset ratio threshold. In this way, the number of memory read and write operations can be limited, and more PE calculation operations of the I / O port can be executed, so that CGRA can achieve better execution performance than the CPU.

[0092] This offloading strategy is to perform heuristic offloading of kernel code based on its different characteristics, which can be expressed as:

[0093]

[0094] In the above formula, Indicates whether the front-end data stream can be offloaded to CGRA after being converted to the back-end data stream of CGRA. Indicates the number of memory read and write operations, Indicates the total number of calculation operations, Indicates the preset ratio threshold, It means that the first and second points of the above legal conditions are met.

[0095] In an embodiment of the present invention, when converting a front-end data stream into a back-end data stream of a CGRA, an offload strategy is formulated based on whether the data stream can be offloaded to the CGRA, and a legitimacy check is performed on the front-end data stream. This not only ensures that the data stream can be successfully offloaded to the CGRA, but also further screens the data stream when comparing the performance of the CGRA and the CPU, so that the execution performance of the data stream that meets the legitimacy conditions on the CGRA is better than that on the traditional CPU.

[0096] In some embodiments, when converting the front-end data stream into the back-end data stream of CGRA, considering that the intermediate representation of the front-end data stream is non-regionally isolated, the Node area of ​​the Kernel kernel code needs to be isolated from the outside during the conversion process. Therefore, for external variables outside the Node area, they need to be used as parameters of the Node node of the back-end data stream. In addition, regarding memory access to external variables, since the CGRA side needs to determine the corresponding access mode during compilation, such external variables can obtain the corresponding sub-memory area by extracting the memory sub-view, which can avoid accessing these external variables. However, this also causes corresponding external additional storage during the front-end data stream conversion process, and correspondingly causes huge memory access overhead.

[0097] Based on the above scenario, when converting the front-end data stream into the back-end data stream of CGRA, the embodiment of the present invention sets the memory access mode of the back-end data stream of CGRA in CGRA to a dual-layer access mode, which includes two aspects: software dual-layer access and hardware dual-layer access.

[0098] For software dual-layer access, at the first layer, the memory subview corresponding to the CGRA's backend data stream is first extracted, and the CGRA's read / write (Load / Store, L / S) controller is configured according to the cache access mode of the memory subview to transfer the block memory corresponding to the memory subview to the CGRA's cache area. The cache area can be the scraptch banks module defined in the CGRA. At the second layer, based on the memory access mode information of the L / S instruction in the node area, the corresponding data stream is read from the block memory in the CGRA's cache area to the CGRA's I / O port for PE operation. The node area here is the node area that stores the kernel kernel code in the backend data stream.

[0099] Specifically, the first layer first extracts the memory subview corresponding to the back-end data stream of CGRA, and determines the parameters such as offloading (offset), size (size), and stride (stride) of the cache access mode. Specifically, it can be to extract the parameters in the affine.store function in the back-end data stream. These parameter information are used to configure the L / S controller of CGRA, and the block memory corresponding to the memory subview is transferred to the cache area of ​​CGRA, such as the scraptch banks module defined in CGRA. Then the second layer further configures the I / O controller of CGRA according to the memory access mode information of the L / S instruction in the Node area, and reads the corresponding data stream from the block memory of the scraptch banks module in CGRA to the corresponding CGRA I / O port for calculation by the PE processing unit.

[0100] For hardware double-layer access, the target memory configuration information of the back-end data stream is first read into the memory configuration management module of the L / S controller and the CGRA's I / O control respectively, and then the target memory configuration information is read from the memory configuration management module through the CGRA, and the controller unit corresponding to the CGRA is configured according to the target memory configuration information to perform memory access to the back-end data stream.

[0101] Specifically, hardware dual-layer access is mainly for the implementation of the configuration access mode of Load / Store Controller and CGRA I / OControl. One is used for read and write control of data flow, and the other is used for calculation and processing control of data flow. Both parts have a ConfigMem module as a memory configuration management module. Through the corresponding call interface on the host side, the target memory configuration information of the back-end data flow is first read into the ConfigMem modules of these two parts. Then, when the CGRA execution call interface is started, the corresponding target memory configuration information can be read from the ConfigMem module to configure the corresponding controller unit in CGRA for memory access.

[0102] In this embodiment of the present invention, a dual-layer access mode is designed for the memory access method of the back-end data flow of CGRA in CGRA, from both software and hardware aspects. Specifically, by configuring the L / S controller and I / O controller of CGRA, dual-layer storage access is achieved, effectively reducing storage access overhead and additional storage usage overhead.

[0103] In some embodiments, when performing automated kernel code unloading on a backend data stream, to achieve separation between host-side code and kernel code, the method employed is to perform automated kernel code unloading on the backend data stream to obtain target kernel code. Specifically, a target node representing the innermost loop body code in a nested loop structure is first determined from task nodes in a hierarchical data stream within the backend data stream. The kernel code corresponding to the target node in the backend data stream is then unloaded to obtain the target kernel code.

[0104] The backend data stream is composed of multiple hierarchical data streams, which are layered according to the nested loop structure to form a tree structure. Each nested loop structure is reused as a task node. Therefore, when unloading, the target node representing the innermost loop body code in the nested loop structure is first determined in the task nodes of the hierarchical data stream in the backend data stream. The innermost loop body code has no inter-loop dependencies and no longer contains nested loop structures. Therefore, this code is at the bottom of the task nodes in the hierarchical data stream, which can also be said to be the leaf nodes of the tree structure. These task nodes belonging to the leaf nodes of the tree structure are the target nodes of the innermost loop body code. The task nodes in the other intermediate layers of the tree structure are all loop statements and loop condition codes, not kernel code.

[0105] Of course, the bottom-level task nodes may also have the same level, so the tree structure may have multiple leaf nodes. These bottom-level and same-level leaf nodes all belong to the target nodes of the innermost loop body code.

[0106] Therefore, in the data flow backend, the kernel code corresponding to the target node is directly determined as the final offload code. Therefore, when offloading the backend data flow to CGRA, the kernel code corresponding to the target node is directly offloaded to obtain the target kernel code. The entire offload process is automated by the HDCC compiler, eliminating the need for manual intervention.

[0107] This embodiment of the present invention effectively separates host-side code from kernel code when offloading back-end data streams to CGRA, thereby determining the software / hardware partitioning scheme. This enables automatic kernel code extraction, eliminating the need for programmers to manually edit and annotate kernel code, saving time and effort. Furthermore, this automatic separation of host-side and kernel code lays the foundation for subsequent joint optimization of both the host and CGRA sides.

[0108] In some embodiments, to generate an executable file of the compiled code, after separating the host code from the kernel code, a host object file is generated based on the host code minus the kernel code. The host code is typically CPU-side code and software-related. Therefore, generating the host object file also achieves code optimization on the software side.

[0109] First, the host-side code, minus the kernel code, must be lowered to the LLVM (Low Level Virtual Machine) compiler. Because the backend data stream is converted to the CGRA dialect during offloading to CGRA, the host-side code, minus the kernel code, is lowered to the MLIR intermediate representation (IR) through the MLIR descent pipeline. The MLIR IR is then lowered to the LLVM compiler dialect, and finally, the LLVM compiler dialect is converted to the LLVM compiler IR. These lowering and conversion operations are performed by the LLVM compiler's backend generation tool.

[0110] Finally, the host object file is built based on the LLVM compiler intermediate representation. The LLVM compiler's back-end generation tool generates the host module object file based on the LLVM compiler intermediate representation. This file is then relinked with the CGRA mapping configuration information and compiled into an executable file for the compiled code.

[0111] In an embodiment of the present invention, for the host-side code without the kernel code, the MLIR intermediate representation is first converted into the LLVM compiler intermediate representation, and then the host object file is implemented on the LLVM side, thereby realizing independent optimization processes of the host-side code and the kernel code, facilitating subsequent linking with the CGRA mapping configuration information constructed by the kernel code, and realizing the final software / hardware partitioning solution.

[0112] The following describes an end-to-end compilation apparatus for a coarse-grained reconfigurable array based on hierarchical data flow provided by the present invention. The end-to-end compilation apparatus for a coarse-grained reconfigurable array based on hierarchical data flow described below and the end-to-end compilation method for a coarse-grained reconfigurable array based on hierarchical data flow described above can be referenced to each other.

[0113] like Figure 6 As shown, the end-to-end compilation device of the coarse-grained reconfigurable array based on hierarchical data flow includes: a conversion module 601, an offloading module 602, a generation module 603, and a compilation module 604. Specifically, the conversion module 601 is used to convert the programming code to be compiled into an optimized intermediate representation of MLIR, and convert the optimized intermediate representation into a front-end data flow through the CGRA data flow operator. The data structure of the front-end data flow is a tree structure of multiple hierarchical data flows, and the hierarchical data flow is generated according to the nested loop structure in the programming code to be compiled; the conversion module 601 is also used to convert the front-end data flow into a CGRA back-end data flow according to a preset offloading strategy;

[0114] The unloading module 602 is used to perform automatic kernel code unloading on the backend data flow to obtain the target kernel code and generate a corresponding kernel code data flow graph based on the target kernel code; the generating module 603 is used to generate a host object file based on the host side code without the kernel code and generate corresponding CGRA mapping configuration information according to the kernel code data flow graph;

[0115] The compiling module 604 is configured to compile the host object file and the CGRA mapping configuration information to obtain an executable file of the programming code to be compiled.

[0116] It should be noted that the beneficial effects of the end-to-end compilation apparatus for a coarse-grained reconfigurable array based on hierarchical data flow herein correspond to the beneficial effects of the end-to-end compilation method for a coarse-grained reconfigurable array based on hierarchical data flow described above. Therefore, the beneficial effects of the end-to-end compilation apparatus for a coarse-grained reconfigurable array based on hierarchical data flow are not further described here.

[0117] Figure 7 An example of a physical structure diagram of an electronic device is shown below. Figure 7 As shown, the electronic device may include: a processor (processor) 710 , a communication interface (Communications Interface) 720 , a memory (memory) 730 and a communication bus 740 , wherein the processor 710 , the communication interface 720 and the memory 730 communicate with each other via the communication bus 740 . The processor 710 can call the logic instructions in the memory 730 to execute an end-to-end compilation method for a coarse-grained reconfigurable array based on a hierarchical data flow, the method including: converting the programming code to be compiled into an optimized intermediate representation of MLIR, and converting the optimized intermediate representation into a front-end data stream through a CGRA data flow operator, wherein the data structure of the front-end data stream is a tree structure of multiple hierarchical data streams, and the hierarchical data stream is generated according to the nested loop structure in the programming code to be compiled; converting the front-end data stream into a back-end data stream of CGRA according to a preset unloading strategy; performing automatic kernel code unloading on the back-end data stream to obtain a target kernel code, and generating a corresponding kernel code data flow graph based on the target kernel code; generating a host object file based on the host-side code without the kernel code, and generating corresponding CGRA mapping configuration information according to the kernel code data flow graph, compiling the host object file and the CGRA mapping configuration information to obtain an executable file of the programming code to be compiled.

[0118] Furthermore, the logic instructions in the aforementioned memory 730 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product, stored in a storage medium, includes instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0119] On the other hand, the present invention also provides a computer program product, comprising a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the end-to-end compilation method for a coarse-grained reconfigurable array based on hierarchical data flow provided by the above methods, the method comprising: converting the programming code to be compiled into an optimized intermediate representation of MLIR, and converting the optimized intermediate representation into a front-end data flow through a CGRA data flow operator, wherein the data structure of the front-end data flow is a tree structure of multiple hierarchical data flows, and the hierarchical data flow is generated based on a nested loop structure in the programming code to be compiled; converting the front-end data flow into a CGRA back-end data flow according to a preset offloading strategy; performing automatic kernel code offloading on the back-end data flow to obtain a target kernel code, and generating a corresponding kernel code data flow graph based on the target kernel code; generating a host object file based on the host-side code without the kernel code, generating corresponding CGRA mapping configuration information based on the kernel code data flow graph, and compiling the host object file and the CGRA mapping configuration information to obtain an executable file of the programming code to be compiled.

[0120] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the end-to-end compilation method for a coarse-grained reconfigurable array based on hierarchical data flow provided by the above methods, the method comprising: converting the programming code to be compiled into an optimized intermediate representation of MLIR, and converting the optimized intermediate representation into a front-end data stream through a CGRA data flow operator, wherein the data structure of the front-end data stream is a tree structure of multiple hierarchical data streams, and the hierarchical data stream is generated according to the nested loop structure in the programming code to be compiled; converting the front-end data stream into a CGRA back-end data stream according to a preset offloading strategy; performing automatic kernel code offloading on the back-end data stream to obtain a target kernel code, and generating a corresponding kernel code data flow graph based on the target kernel code; generating a host object file based on the host-side code without the kernel code, and generating corresponding CGRA mapping configuration information according to the kernel code data flow graph, and compiling the host object file and the CGRA mapping configuration information to obtain an executable file of the programming code to be compiled.

[0121] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0122] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in each embodiment or certain portions of the embodiments.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. An end-to-end compilation method for a coarse-grained reconfigurable array based on hierarchical data flow, characterized in that: The method comprises: Converting the programming code to be compiled into an optimized intermediate representation of MLIR, and converting the optimized intermediate representation into a front-end data stream through a CGRA data stream operator, wherein the data structure of the front-end data stream is a tree structure of multiple hierarchical data streams, and the hierarchical data streams are generated according to the nested loop structure in the programming code to be compiled; Performing a validity check on the front-end data stream, and converting the front-end data stream into a CGRA back-end data stream when the front-end data stream meets the validity conditions included in the preset offloading policy; Performing automated kernel code unloading on the backend data flow to obtain target kernel code, and generating a corresponding kernel code data flow graph based on the target kernel code; Generate a host object file based on the host side code without the Kernel kernel code, and generate corresponding CGRA mapping configuration information according to the kernel code data flow graph, Compiling the host object file and the CGRA mapping configuration information to obtain an executable file of the programming code to be compiled; The memory access mode of the backend data stream of the CGRA in the CGRA is a dual-layer access mode, and the dual-layer access mode includes: software dual-layer access and hardware dual-layer access; The software dual-layer access includes: Extract the memory subview corresponding to the backend data stream of the CGRA, and configure the L / S controller of the CGRA according to the cache access mode of the memory subview to transfer the block memory corresponding to the memory subview to the cache area of ​​the CGRA; Reading a corresponding data stream from a block memory in a cache area of ​​the CGRA to an I / O port of the CGRA for PE operation according to memory access mode information of an L / S instruction in a node area, wherein the node area is an area storing kernel code in the backend data stream; The hardware dual-layer access includes: Read the target memory configuration information of the backend data stream to the memory configuration management module of the L / S controller and the I / O control of the CGRA respectively; The target memory configuration information is read from the memory configuration management module through CGRA, and a controller unit corresponding to the CGRA is configured according to the target memory configuration information to perform memory access on the back-end data stream.

2. The end-to-end compilation method of the coarse-grained reconfigurable array based on hierarchical data flow according to claim 1, characterized in that: The converting the optimized intermediate representation into a front-end data stream through a CGRA data stream operator includes: determining a nested loop structure in the optimized intermediate representation; According to the task operator in the CGRA data flow operator, the nested loop structure is reused as a task node, wherein each same-level loop structure in the nested loop structure is reused as a task node; The optimized intermediate representation is layered according to the task nodes to obtain a corresponding hierarchical data flow.

3. The end-to-end compilation method of the coarse-grained reconfigurable array based on hierarchical data flow according to claim 1, characterized in that: The legal conditions include: The hardware parameter information of the Kernel kernel code in the front-end data stream meets the PE computing resource restrictions and I / O port restrictions of CGRA; The operators contained in the Kernel kernel code in the front-end data stream meet the back-end hardware support of CGRA; In the Kernel kernel code in the front-end data stream, the ratio of the number of memory read and write operations to the total number of computing operations is not greater than a preset ratio threshold.

4. The end-to-end compilation method of the coarse-grained reconfigurable array based on hierarchical data flow according to claim 1, characterized in that: The step of performing automated Kernel code unloading on the backend data stream to obtain target kernel code includes: Determining, among the task nodes of the hierarchical data flow in the backend data flow, a target node representing the innermost loop body code in the nested loop structure; Uninstall the kernel code corresponding to the target node to obtain the target kernel code.

5. The end-to-end compilation method of the coarse-grained reconfigurable array based on hierarchical data flow according to claim 1, characterized in that: The generating of the host object file based on the host side code without the Kernel kernel code includes: The host-side code without the kernel code is lowered to the MLIR intermediate representation through the MLIR descent channel; Lowering the MLIR intermediate representation to an LLVM compiler dialect, and converting the LLVM compiler dialect to an LLVM compiler intermediate representation; Build host object files based on the LLVM compiler intermediate representation.

6. An end-to-end compilation device for a coarse-grained reconfigurable array based on hierarchical data flow, characterized in that: The device comprises: a conversion module, configured to convert the programming code to be compiled into an optimized intermediate representation of MLIR, and convert the optimized intermediate representation into a front-end data stream through a CGRA data stream operator, wherein the data structure of the front-end data stream is a tree structure of multiple hierarchical data streams, and the hierarchical data streams are generated according to the nested loop structure in the programming code to be compiled; The conversion module is further configured to perform a validity check on the front-end data stream, and convert the front-end data stream into a CGRA back-end data stream when the front-end data stream satisfies a validity condition included in a preset offloading policy; An unloading module is used to perform automatic kernel code unloading on the backend data flow to obtain a target kernel code and generate a corresponding kernel code data flow graph based on the target kernel code; A generation module, configured to generate a host object file based on the host side code without the kernel code, and generate corresponding CGRA mapping configuration information according to the kernel code data flow graph; a compiling module, configured to compile the host object file and the CGRA mapping configuration information to obtain an executable file of the programming code to be compiled; The memory access mode of the backend data stream of the CGRA in the CGRA is a dual-layer access mode, and the dual-layer access mode includes: software dual-layer access and hardware dual-layer access; The software dual-layer access includes: Extract the memory subview corresponding to the backend data stream of the CGRA, and configure the L / S controller of the CGRA according to the cache access mode of the memory subview to transfer the block memory corresponding to the memory subview to the cache area of ​​the CGRA; Reading a corresponding data stream from a block memory in a cache area of ​​the CGRA to an I / O port of the CGRA for PE operation according to memory access mode information of an L / S instruction in a node area, wherein the node area is an area storing kernel code in the backend data stream; The hardware dual-layer access includes: Read the target memory configuration information of the backend data stream to the memory configuration management module of the L / S controller and the I / O control of the CGRA respectively; The target memory configuration information is read from the memory configuration management module through CGRA, and a controller unit corresponding to the CGRA is configured according to the target memory configuration information to perform memory access on the back-end data stream.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the end-to-end compilation method of the coarse-grained reconfigurable array based on hierarchical data flow according to any one of claims 1 to 5 is implemented.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the end-to-end compilation method of the coarse-grained reconfigurable array based on hierarchical data flow as claimed in any one of claims 1 to 5 is implemented.

9. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the end-to-end compilation method of the coarse-grained reconfigurable array based on hierarchical data flow as claimed in any one of claims 1 to 5 is implemented.

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