A heterogeneous dual-core processor system for power electronic devices and power electronic devices.

Abstract

This disclosure provides a heterogeneous dual-core processor system for power electronic devices and the power electronic device itself. The system includes: a main processor and a coprocessor communicating with the main processor via a bus, a general-purpose peripheral subsystem, a dedicated peripheral subsystem, a dedicated acceleration subsystem, an interrupt subsystem, and a storage subsystem. This disclosure constructs a heterogeneous dual-core dedicated processor architecture for the main processor and coprocessor. The main processor executes high real-time and high-reliability control algorithms and expands the dedicated peripheral subsystem via a standard bus to meet the needs of control-intensive applications such as high switching frequencies and multi-level topologies. The dedicated acceleration subsystem enables hardware-based accelerated control. The coprocessor executes computationally intensive edge intelligent algorithms to meet the computationally intensive application needs of future power electronic devices for edge intelligent computing such as fault prediction and health management.

Description

Technical Field

[0001] This disclosure relates to the field of industrial control technology, and in particular to a heterogeneous dual-core processor system for power electronic equipment and power electronic equipment. Background Technology

[0002] With the rapid development of the global economy and the continuous advancement of technology, the demand for highly reliable, high-quality, and controllable electrical energy is becoming increasingly urgent in many fields, including smart grids, rail transportation, new energy vehicles, distributed renewable energy, and military equipment. Power electronic equipment, as a core component of energy conversion, is receiving widespread attention from various countries. Its reliability, automation, and intelligence levels will significantly impact the safe, stable operation and overall intelligence of the entire power grid system. Therefore, research on the key technologies of power electronic equipment is of great importance.

[0003] Next-generation wide-bandgap power semiconductor devices, represented by SiC (silicon carbide) and GaN (gallium nitride), possess advantages such as high voltage withstand capability, high junction temperature stability, and high reliability, and will become an important development direction for future power electronic devices. Compared with silicon-based power semiconductor devices, wide-bandgap power semiconductor devices improve power quality through a more than tenfold increase in switching frequency. The deployment of control-intensive applications in power electronic devices, such as novel topologies, high-precision control algorithms, and the high switching frequencies brought by wide-bandgap power semiconductors, places higher demands on the control performance of core processors. Furthermore, the application of edge intelligent algorithms in power electronic devices also places higher demands on the computational efficiency of core processors for computationally intensive applications. Simple selection and hardware stacking of existing processors are insufficient to meet the requirements of control-intensive applications such as multi-level topologies, high-performance control algorithms, and the high switching frequencies brought by future wide-bandgap power semiconductors, nor are they sufficient to meet the requirements of computationally intensive applications such as edge intelligent computing. Therefore, the core processor has become a crucial factor restricting the deployment of control-intensive applications and the edge intelligent computing capabilities of future power electronic devices. Summary of the Invention

[0004] The purpose of this disclosure is to provide a heterogeneous dual-core processor system and a power electronic device to solve the problems existing in the prior art.

[0005] The embodiments of this disclosure adopt the following technical solution: a heterogeneous dual-core processor system for power electronic equipment, comprising at least: a main processor and a coprocessor communicating with the main processor via a bus, a general-purpose peripheral subsystem, a dedicated peripheral subsystem, a dedicated acceleration subsystem, an interrupt subsystem, and a storage subsystem; wherein, the main processor is designed and implemented based on the RISC-CV instruction set and is configured to execute the complete control flow of the power electronic equipment; the coprocessor is configured to perform edge computing on the data transmitted by the main processor and feed back the computing results to the main processor; the general-purpose peripheral subsystem is configured to realize data communication between the main processor and general-purpose external devices; the dedicated peripheral subsystem is configured to generate multiple control pulse signals for the multi-level topology device according to the control requirements of the main processor for the multi-level topology device; the dedicated acceleration subsystem is configured to perform accelerated calculation on the input data according to the control algorithm selected by the main processor; and the interrupt subsystem is configured to handle interrupt requests.

[0006] In some embodiments, the coprocessor includes at least: a prefetch and write-back module, an intermediate memory, a first data movement and formatting module, a first-in-first-out queue, a processing unit array, and a second data movement and formatting module; wherein, the prefetch and write-back module communicates with the main processor via a bus interface to obtain data to be processed and sends it to the intermediate memory, the intermediate memory sends the data to the first data movement and formatting module, the first data movement and formatting module sends the data to the first-in-first-out queue, the first-in-first-out queue inputs the data into the processing unit array corresponding to the current operation type, and after the current processing unit completes the calculation, it moves the calculation result to the right or down. The process continues until the iterative calculation result is written into the first data movement and formatting module. The first data movement and formatting module determines whether edge computing is complete based on the iterative calculation result. If it is complete, the iterative calculation result is written into the intermediate memory. The prefetch and write-back module writes the calculation result in the intermediate memory back to the main processor. If edge computing is not complete, the first data movement and formatting module writes the iterative calculation result into the second data movement and formatting module. The second data movement and formatting module writes the iterative calculation result into the processing unit array to complete the next round of iterative calculation, until the first data movement and formatting module determines that edge computing is complete.

[0007] In some embodiments, the operation type includes at least: stepwise operation, activation operation, RNN activation operation, normalization operation, pooling operation, and systolic operation.

[0008] In some embodiments, the dedicated peripheral subsystem includes at least: a PWM pulse generation module, an ADC pulse generation module, and a QEP pulse generation module.

[0009] In some embodiments, the PWM pulse generation module includes at least: a time base unit for generating a basic time reference and control logic required for PWM pulses; a counting and comparison unit for starting a counter according to the configuration of the time base unit and generating a current counter status signal based on the period register, comparison value register, and comparison logic register set by the kernel; an action unit for generating multiple PWM pulse signals according to the status signal and the basic time reference; a dead-time control unit for performing dead-time control on the multiple PWM pulse signals; an error control unit for monitoring whether the pulse signals output by the dedicated peripheral subsystem need to be urgently blocked, and outputting the multiple PWM pulse signals to a multi-level topology device through a general-purpose input / output interface if no emergency blocking is required; and an event triggering unit for generating an interrupt request based on the current status of the time base unit, the counting and comparison unit, and the action unit.

[0010] In some embodiments, the multi-channel PWM pulse signal is an 8-channel PWM pulse signal.

[0011] In some embodiments, the control algorithm includes at least: a vector control algorithm, a PID control algorithm, an adaptive control algorithm, a fuzzy logic control algorithm, a predictive control algorithm, and a sliding diaphragm control algorithm; the dedicated acceleration subsystem includes at least: a vector control acceleration module, a PID control acceleration module, an adaptive control acceleration module, a fuzzy logic control acceleration module, a predictive control acceleration module, and a sliding diaphragm control acceleration module.

[0012] In some embodiments, the general peripheral subsystem includes at least: a general input / output interface, a serial communication interface, a multi-master bus interface, and a full-duplex synchronous serial communication interface.

[0013] In some embodiments, the bus is an Advanced Microcontroller Bus (AMBA).

[0014] This disclosure also provides a power electronic device, which includes at least the heterogeneous dual-core processor system described above.

[0015] The beneficial effects of the embodiments disclosed herein are as follows: a heterogeneous dual-core dedicated processor architecture of a main processor and a coprocessor is constructed. The main processor is used to execute high real-time and high-reliability control algorithms and expands a dedicated peripheral subsystem through a standard bus to meet the control-intensive application requirements such as high switching frequency and multi-level topology. Hardware-based accelerated control is realized through a dedicated acceleration subsystem. The coprocessor is used to execute computationally intensive edge intelligent algorithms to meet the computationally intensive application requirements of future power electronic equipment for edge intelligent computing such as fault prediction and health management. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in one or more embodiments of this specification or in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of the architecture of a heterogeneous dual-core processor system for a power electronic device provided for one or more embodiments of this specification;

[0018] Figure 2 This is a schematic diagram of the structure of a coprocessor provided in one or more embodiments of this specification;

[0019] Figure 3 This is a schematic diagram of the structure of a PWM pulse generation module provided in one or more embodiments of this specification. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this document.

[0021] With the rapid development of the global economy and the continuous advancement of technology, the demand for highly reliable, high-quality, and controllable electrical energy is becoming increasingly urgent in many fields, including smart grids, rail transportation, new energy vehicles, distributed renewable energy, and military equipment. Power electronic equipment, as a core component of energy conversion, is receiving widespread attention from various countries. Its reliability, automation, and intelligence levels will significantly impact the safe, stable operation and overall intelligence of the entire power grid system. Therefore, research on the key technologies of power electronic equipment is of great importance.

[0022] Next-generation wide-bandgap power semiconductor devices, represented by SiC (silicon carbide) and GaN (gallium nitride), possess advantages such as high voltage withstand capability, high junction temperature stability, and high reliability, and will become an important development direction for future power electronic devices. Compared with silicon-based power semiconductor devices, wide-bandgap power semiconductor devices improve power quality through a more than tenfold increase in switching frequency. The deployment of control-intensive applications in power electronic devices, such as novel topologies, high-precision control algorithms, and the high switching frequencies brought by wide-bandgap power semiconductors, places higher demands on the control performance of core processors. Furthermore, the application of edge intelligent algorithms in power electronic devices also places higher demands on the computational efficiency of core processors for computationally intensive applications. Simple selection and hardware stacking of existing processors are insufficient to meet the requirements of control-intensive applications such as multi-level topologies, high-performance control algorithms, and the high switching frequencies brought by future wide-bandgap power semiconductors, nor are they sufficient to meet the requirements of computationally intensive applications such as edge intelligent computing. Therefore, the core processor has become a crucial factor restricting the deployment of control-intensive applications and the edge intelligent computing capabilities of future power electronic devices.

[0023] To address the aforementioned issues, dedicated processor architectures for future power electronic devices need to meet not only the control-intensive application requirements of multi-level topologies, high-performance control algorithms, and high switching frequencies brought about by future wide-bandgap power semiconductors, but also the computationally intensive application requirements of future edge intelligence algorithms. The first embodiment of this disclosure provides a heterogeneous dual-core processor system for power electronic devices, the schematic diagram of which is shown below. Figure 1As shown, the system mainly includes a main processor 10 and a coprocessor 20, a general-purpose peripheral subsystem 30, a dedicated peripheral subsystem 40, a dedicated acceleration subsystem 50, an interrupt subsystem 60, and a storage subsystem 70, all of which communicate with the main processor via a bus. The main processor 10 is designed and implemented based on the RISC V instruction set and is configured to execute the complete control flow of the power electronic equipment. The coprocessor 20 is configured to perform edge computing on the data transmitted by the main processor 10 and feed the calculation results back to the main processor 10. The general-purpose peripheral subsystem 30 is configured to realize data communication between the main processor 10 and general-purpose peripheral devices. The dedicated peripheral subsystem 40 is configured to generate multiple control pulse signals for the multi-level topology devices according to the control requirements of the main processor 10. The dedicated acceleration subsystem 50 is configured to accelerate the calculation of the input data according to the control algorithm selected by the main processor 10. The interrupt subsystem 60 is configured to handle interrupt requests.

[0024] Specifically, as a bridge between the processor's underlying hardware and the application software running on it, the choice of instruction set architecture is crucial to the processor's hardware and software design, application software execution efficiency, and compatibility between different processor series versions. Based on the advantages of the RISC V instruction set in terms of open source, modularity, scalability, power consumption, cost, performance, and security, the main processor 10 in this embodiment is a high-performance embedded processor core built on the RISC V instruction set. It adopts a 5-stage pipeline design and uses the standard Advanced Microcontroller Bus Architecture (AMBA) to expand various functional peripherals such as communication and control. It is mainly used to realize the entire control process of power electronic equipment, including but not limited to: peripheral initialization, algorithm control process, communication with the upper-level system, and display functions.

[0025] Introducing computationally intensive edge intelligent algorithms into power electronic devices to achieve fault diagnosis, fault prediction, and health management has become one of the important trends in the future development of power electronic devices. The coprocessor 20 in this embodiment implements fault diagnosis, fault prediction, and health management functions by introducing computationally intensive edge intelligent algorithms to meet the functional requirements of power electronic devices. Specifically, the coprocessor 20 in this embodiment is designed based on an instruction set constructed from edge intelligent computing operators to perform different types of operations on data, including but not limited to: step-by-step operations, activation operations, RNN activation operations, normalization operations, pooling operations, and pulsation operations.

[0026] The edge intelligent computing instruction set of the coprocessor 20 is shown in Table 1. Among them, step-by-step operations refer to performing the same or similar operations on each element of a data structure (such as vectors, matrices, tensors, etc.). Although most of these operations can be implemented on general-purpose cores, this embodiment utilizes the processing unit array in the coprocessor 20 to achieve parallel execution of multiple computational cores, which can significantly improve data bandwidth and thus greatly improve performance. Activation operations are used to implement activation functions in the field of machine learning. Activation functions are a class of functions used to introduce nonlinear characteristics into neural networks, and they are usually applied to each neuron in the neural network. RNN activation operations mainly include Long Short-Term Memory Network Activation (LSTMACT) and Gated Recurrent Unit Activation (GRUACT) operations, used to implement all activation functions of the LSTM or GRU layer at once. Normalization operations are mainly used to convert the model's output into a probability distribution. The edge intelligent computing coprocessor for power electronic devices mainly includes two operations: SOFTMAX and BATCH NORMALIZATION. SOFTMAX is usually used in multi-class classification problems to convert the model's original output into a probability distribution, while BATCH... NORMALIZATION normalizes each mini-batch of samples, ensuring the input features have zero mean and unit variance. This helps reduce gradient vanishing and exploding problems, thus accelerating the convergence of neural networks. Pooling operations in convolutional neural networks have multiple important functions, including feature dimensionality reduction, improving model invariance, reducing overfitting, suppressing noise, and improving computational efficiency. Edge intelligent computing coprocessors for power electronic devices mainly include AVERAGEPOOL2D and MAXPOOL2D operations. AVERAGEPOOL2D averages the values ​​of all pixels (or feature values) within a specified pooling window and uses this average as the output value for that window region. MAXPOOL2D selects the maximum value in each pooling window as the output, achieving downsampling and dimensionality reduction of the input feature map. Pulsation operations allow data to flow rhythmically and regularly between processing units in the array and be processed in parallel, offering advantages such as high parallelism, high modularity, and reduced memory access. These operations mainly include FUSED. The two operations, CONVOLUTION and MATMUL-OP, are used to implement fused convolution operations and matrix multiplication operations, respectively.

[0027] Table 1

[0028]

[0029]

[0030] Figure 2A schematic diagram of the coprocessor 20 in this embodiment is shown. It mainly includes: a prefetch and write-back module 21, an intermediate memory 22, a first data movement and formatting module 23, a first-in-first-out queue 24, a processing unit array 25, and a second data movement and formatting module 26. The functions of each module are explained below in conjunction with the data processing flow of the coprocessor 20.

[0031] S1, the prefetch and write-back module 21 communicates with the main processor 10 through the bus interface, and obtains the data that needs to be used for edge computing from the main processor 10 and sends it to the intermediate memory 22;

[0032] S2, intermediate memory 22 sends data to first data movement and formatting module 23;

[0033] S3, the first data movement and formatting module 23 sends the data to the first-in-first-out queue 24;

[0034] S4, the first-in-first-out queue 24 sends the input into the processing unit array 25 composed of processing elements (PEs) according to the current operation type. Each PE is a simple processor composed of a three-stage pipeline, which can implement element-wise operations and activation operations through instructions. After the current PE completes the calculation, it will pass the calculation result to the right or down. The specific operation and whether the calculation result is passed to the right or down are determined by the instructions executed in the PE.

[0035] S5, the processing unit array 25 writes the calculation results of this iteration into the first data moving and formatting module 23;

[0036] S6, the first data moving and formatting module 23 determines whether edge computing is completed based on the iterative calculation results. If it is completed, the iterative calculation results are written to the intermediate memory 22, and the prefetch and write-back module 21 writes the iterative calculation results in the intermediate memory 22 back to the main processor 10. If the first data moving and formatting module 23 determines that edge computing is not completed, the current iterative calculation results are sent to the second data moving and formatting module 26.

[0037] S7, the second data moving and formatting module 26 rewrites the current iterative calculation result into the processing unit array 25 for the next round of iterative calculation, until the first data moving and formatting module 23 determines that the edge calculation is complete.

[0038] In this embodiment, when the computing power required for this calculation is high and cannot be met by a single iteration, the coprocessor 20 sends the data back to the processing unit array 25 through the first data movement and formatting module 23 and the second data movement and formatting module 26 for the next round of iteration calculation until the entire target operation is completed; when the computing power required for the calculation is low and can be met by a single iteration, the processing unit array 25 greatly improves the target operation bandwidth through a pulse array.

[0039] It should be noted that the instructions implemented by each PE in the processing unit array 25 are not exactly the same, and calculations under any operation type can be completed through collaborative processing by multiple different PEs. After the current PE completes its calculation, it can determine whether to pass the calculation result to other PEs to the right or down for subsequent calculations, based on the current operation type and the instructions executed. The number of PEs and the array arrangement in this embodiment can be determined according to actual calculation needs, and this embodiment does not impose specific limitations.

[0040] The general peripheral subsystem 30 transmits data with the main processor 10 via a standard AMBA bus. This subsystem integrates common SOC peripherals such as general-purpose input / output interfaces (GPIO), serial communication interfaces (USART), multi-master bus interfaces (CAN), and full-duplex synchronous serial communication interfaces (SPI), enabling the main processor 10 to communicate with other conventional modules or devices.

[0041] The dedicated peripheral subsystem 40 also interacts with the main processor 10 based on the standard AMBA bus. This subsystem is designed to meet the specific needs of power electronic equipment and mainly includes commonly used modules in the field of power electronic control, such as PWM (Pulse Width Modulation) pulse generation module, QEP (Quadrature Encoder Pulse) pulse generation module, and ADC (Analog-to-Digital Converter) pulse generation module, to drive corresponding multi-level topology devices. The modules are linked through signal lines to achieve linkage control between the two modules, thereby improving control efficiency.

[0042] Figure 3The diagram shows the structure of the PWM pulse generation module in this embodiment, which mainly includes: a time base unit, a counting and comparison unit, an action unit, a dead-time control unit, an error control unit, and an event triggering unit. The system comprises the following components: a time base unit for generating the basic time reference and control logic required for PWM pulses, and a register for synchronizing the time base modules of multiple multi-level topology dedicated peripherals; a counter comparison unit for starting the counter according to the time base unit configuration and generating the current counter status signal based on the period register, comparison value register, and comparison logic register set by the kernel; an action unit for generating multiple PWM pulse signals based on the status signal and the basic time reference; a dead-time control unit for dead-time control of multiple PWM pulse signals, mainly to solve the problem that the switching transistors on the same bridge arm cannot be turned on simultaneously, and outputting the action module output signal after processing it according to the dead-time control register; an error control unit for monitoring whether the dedicated peripheral subsystem needs to urgently block the output pulse signal to put the device into a protection state, and outputting the multiple PWM pulse signals to the multi-level topology device through the general-purpose input / output interface if no emergency blocking is required; and an event trigger unit for generating interrupt requests and ADC sampling signals based on the current status of the time base unit, the counter comparison unit, and the action unit.

[0043] In practical use, a mature two-level topology requires each bridge arm to control 2 switching transistors, a three-level topology requires each bridge arm to control 4 switching transistors, and a five-level topology requires each bridge arm to control 8 switching transistors. This embodiment is designed for conventional two-level, three-level, and five-level topologies. Therefore, the multi-channel PWM pulse signal in this embodiment is 8-channel PWM pulse signal to meet the control implementation of the above-mentioned multi-level topology devices.

[0044] The dedicated acceleration subsystem 50 is designed to meet the high real-time control requirements of wide-bandgap power semiconductor devices. It implements commonly used control algorithms in power electronic equipment in hardware to improve the execution speed of these algorithms and meet the demands of high-performance, high-frequency control. Specifically, the control algorithms that the dedicated acceleration subsystem 50 can execute include at least vector control, PID control, adaptive control, fuzzy logic control, predictive control, and sliding mode control. Therefore, the dedicated acceleration subsystem 50 integrates at least the following acceleration modules: vector control acceleration module, PID control acceleration module, adaptive control acceleration module, fuzzy logic control acceleration module, predictive control acceleration module, and sliding mode control acceleration module. Each acceleration module is used for the corresponding control algorithm of the actuator. In practical use, the main processor 10 first issues instructions to select the control algorithm, then issues parameters to configure the corresponding acceleration module, and finally, the main processor 10 reads the output data of the acceleration module while simultaneously sending data via the bus.

[0045] The interrupt subsystem 60 in this embodiment is used to handle interrupt requests, ensuring that the system can respond to and handle internal or external events in a timely manner. The interrupt sources mainly include external interrupt sources such as GPIO and DMA (Direct Memory Access) and internal interrupt sources such as program exceptions and hardware failures.

[0046] The storage subsystem 70 is responsible for storing program code and data, and participates in various aspects such as system startup, runtime management, and performance optimization. Because cache structures based on the temporal and spatial locality of software programs suffer from cache misses that compromise real-time performance, and because processor software for power electronic devices is typically small in scale, the storage subsystem 70 in this embodiment is designed using delay-deterministic ITCM (Instruction Tightly Coupled Memory) and DTCM (Data Tightly Coupled Memory) structures. The main processor 10 accesses ROM (Read-Only Memory), RAM (Random Access Memory), and Flash memory via the storage bus.

[0047] This embodiment constructs a heterogeneous dual-core dedicated processor architecture consisting of a main processor and a coprocessor. The main processor executes high real-time and high-reliability control algorithms and expands a dedicated peripheral subsystem via a standard bus to meet the needs of control-intensive applications such as high switching frequencies and multi-level topologies. A dedicated acceleration subsystem enables hardware-based accelerated control. The coprocessor executes computationally intensive edge intelligent algorithms to meet the computationally intensive application requirements of future power electronic devices for edge intelligent computing such as fault prediction and health management. Furthermore, the main processor and coprocessor communicate via a bus, facilitating decoupling between them during the design process.

[0048] Based on the same inventive concept, the second embodiment of this disclosure provides a power electronic device, which includes at least the heterogeneous dual-core processor system provided in the first embodiment of this disclosure. The main processor executes high real-time and high-reliability control algorithms, and the dedicated peripheral subsystem is extended through a standard bus to meet the control-intensive application requirements such as high switching frequency and multi-level topology. The dedicated acceleration subsystem realizes hardware-based accelerated control, and the coprocessor is used to execute computationally intensive edge intelligent algorithms to meet the computationally intensive application requirements of future power electronic devices for edge intelligent computing such as fault prediction and health management.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A heterogeneous dual-core processor system for power electronic equipment, characterized in that, At least including: The main processor, along with a coprocessor communicating with the main processor via a bus, a general-purpose peripheral subsystem, a dedicated peripheral subsystem, a dedicated acceleration subsystem, an interrupt subsystem, and a memory subsystem; wherein, The main processor is designed and implemented based on the RISC V instruction set and is configured to execute the complete control flow of power electronic devices. The coprocessor is configured to perform edge computing on the data transmitted by the main processor and feed the computing results back to the main processor. The general peripheral subsystem is configured to enable data communication between the main processor and general peripheral devices; The dedicated peripheral subsystem is configured to generate multiple control pulse signals for the multilevel topology device according to the main processor's control requirements for the multilevel topology device; The dedicated acceleration subsystem is configured to perform accelerated computation on the input data according to the control algorithm selected by the main processor; The interrupt subsystem is configured to handle interrupt requests.

2. The heterogeneous dual-core processor system according to claim 1, characterized in that, The coprocessor includes at least: The system includes a prefetch and write-back module, an intermediate memory, a first data movement and formatting module, a first-in-first-out queue, a processing unit array, and a second data movement and formatting module; among which, The prefetch and write-back module communicates with the main processor via a bus interface to obtain the data to be processed and sends it to the intermediate memory. The intermediate memory sends the data to the first data movement and formatting module, which then sends the data to the first-in-first-out queue. The first-in-first-out queue inputs the data into the processing unit array corresponding to the current operation type. After the current processing unit completes the calculation, it passes the calculation result to the right or down until an iterative calculation result is formed and written into the first data movement and formatting module. The first data movement and formatting module determines whether edge computing is complete based on the iterative calculation result. If it is complete, it writes the iterative calculation result into the intermediate memory, and the prefetch and write-back module writes the calculation result in the intermediate memory back to the main processor. If edge computing is not complete, the first data movement and formatting module writes the iterative calculation result into the second data movement and formatting module, which then writes the iterative calculation result into the processing unit array to complete the next round of iterative calculation until the first data movement and formatting module determines that edge computing is complete.

3. The heterogeneous dual-core processor system according to claim 2, characterized in that, The operation types include at least: stepwise operation, activation operation, RNN activation operation, normalization operation, pooling operation, and systolic operation.

4. The heterogeneous dual-core processor system according to claim 1, characterized in that, The dedicated peripheral subsystem includes at least: a PWM pulse generation module, an ADC pulse generation module, and a QEP pulse generation module.

5. The heterogeneous dual-core processor system according to claim 4, characterized in that, The PWM pulse generation module includes at least: The time base unit is used to generate the basic time base and control logic required for PWM pulses; The counting comparison unit is used to start the counter according to the configuration of the time base unit, and generate the current counter status signal according to the period register, comparison value register and comparison logic register set by the kernel. Action unit, used to generate multiple PWM pulse signals according to the status signal and the basic time base; Dead-time control unit, used to perform dead-time control on the multi-channel PWM pulse signals; The error control unit is used to monitor whether the pulse signal output of the dedicated peripheral subsystem needs to be blocked urgently. If no emergency blocking is required, the multi-channel PWM pulse signal is output to the multi-level topology device through the general input / output interface. The event triggering unit is used to generate an interrupt request based on the current state of the time base unit, the counting comparison unit, and the action unit.

6. The heterogeneous dual-core processor system according to claim 5, characterized in that, The multi-channel PWM pulse signal is an 8-channel PWM pulse signal.

7. The heterogeneous dual-core processor system according to claim 1, characterized in that, The control algorithm includes at least: vector control algorithm, PID control algorithm, adaptive control algorithm, fuzzy logic control algorithm, predictive control algorithm, and sliding mode control algorithm; The dedicated acceleration subsystem includes at least: a vector control acceleration module, a PID control acceleration module, an adaptive control acceleration module, a fuzzy logic control acceleration module, a predictive control acceleration module, and a sliding diaphragm control acceleration module.

8. The heterogeneous dual-core processor system according to claim 1, characterized in that, The general peripheral subsystem includes at least: a general input / output interface, a serial communication interface, a multi-master bus interface, and a full-duplex synchronous serial communication interface.

9. The heterogeneous dual-core processor system according to any one of claims 1 to 8, characterized in that, The bus is the Advanced Microcontroller Bus (AMBA).

10. A power electronic device, characterized in that, It includes at least the heterogeneous dual-core processor system as described in any one of claims 1 to 9.

Images