RTL information flow-based time domain and security attribute joint modeling method

Abstract

The invention discloses a time domain and security attribute joint modeling method based on RTL information flow, belongs to the technical field of hardware security, and solves the problems of how to model time domain attributes from the perspective of information flow to design security behaviors and detect time sequence channel attacks. The security behavior is modeled and designed by the security attribute and the time domain attribute from the angle of information flow, the additional time domain attribute tracking logic circuit is used for capturing data flow and the updating time of a signal in the process, the security attribute and the time domain attribute of RTLIFT are modeled in a dual mode, and the security behavior is modeled and designed by analyzing propagation of a time label. According to the method, how the input change affects the output time change can be determined, so that the model can capture and analyze the time difference caused by the imbalance of the execution path, and the hardware time side channel possibly causing sensitive information leakage can be effectively identified.

Description

Technical Field

[0001] The invention belongs to the technical field of hardware security and relates to a time domain and security attribute joint modeling method based on RTL information flow. Background Art

[0002] Existing researchers have been exploring the field of software and hardware security for decades, but current computing technology is still threatened by various security vulnerabilities, such as side-channel attacks, hardware Trojans, and side-channel attacks. This is mainly because many basic computing models and traditional design processes fail to fully consider security. Security attention is usually insufficient during the hardware design process. Security vulnerabilities may arise from design defects, and the large scale of modern chips makes comprehensive verification extremely difficult. In addition, hardware design often relies on third-party IP cores, which may contain hidden malicious design modifications (such as backdoors). Information flow tracking (IFT) technology provides an effective method to detect various security vulnerabilities, including design defects, malicious modifications, timing side-channel attacks, and access control violations. Therefore, studying information flow modeling methods has important practical significance in the field of hardware security.

[0003] Information flow tracing (IFT) models how information propagates through a system as it computes, e.g. Figure 1 This is a technical schematic diagram of information flow tracking under the existing technology. This technology assigns a label to each data object to reflect its security attributes (such as trusted / untrusted) or time domain attributes (such as the time when the data changes). During the data operation process, these labels are also propagated in the system. The information flow attributes can be verified by observing the status of the labels. In addition to the data operation unit of the original system, an additional label propagation unit is required. This unit determines the label of the operation result according to the current operation type and the label of the operation object according to the predefined label propagation strategy. By statically analyzing or dynamically checking the label of the operation result, it can effectively prevent violations of the information flow security policy. At present, the mainstream hardware security information flow analysis methods are gate level information flow tracking (GLIFT) and register transfer level information flow tracking (RTLIFT). These methods can track all information flows (explicit and implicit flows).

[0004] The gate-level information flow tracing method uses a single-bit label to mark the security attribute of data, considers the impact of contaminated input on output, and constructs a gate-level information flow tracing logic model of a standard gate-level netlist. When modeling implicit flow, the gate-level information flow tracing logic model is more conservative in dealing with single variable flipping situations, which may lead to capturing information flows that do not actually exist, thereby causing false alarms. Compared with the gate-level method, the RTL information flow tracing method can more accurately understand all logical information flows in the RTL code. By defining precise label propagation rules for RTL expressions, the RTLIFT model achieves higher accuracy; in addition, the RTLIFT model can be completely described in standard RTL syntax without introducing a new type-enforced language. When constructing the RTLIFT model, the RTL design needs to be divided into data flow operation statements and control flow operation statements, and RTLIFT labels need to be added to them respectively. This process includes building a data flow operation logic library and a control flow operation logic library, and mapping the RTL code to the basic RTLIFT logic library to obtain the RTL information flow tracing logic model.

[0005] For example, the document "CELLIFT: Leveraging Cells for Scalable and Precise Dynamic Information Flow Tracking in RTL" (Solt, Flavien; Gras, Ben; Razavi, Kaveh, 31st USENIX Security Symposium, 2022: 2549-2566.) discloses a new design point CellIFT in the field of hardware dynamic IFT. When detecting a given register transfer level (RTL) hardware design, CellIFT uses logic macrocell abstractions (such as adders) to achieve scalability, accuracy, and completeness. Cell-level dynamic IFT does not have the scalability issues inherent in lower abstraction levels such as gates, but it achieves completeness given a limited number of cell types.

[0006] For example, the document "Automated Assertion Checker Generator and Information Flow Tracking for Security Verification" (Zapata, Miguel Angel Alfaro; Shahshahani, Amirhossein; Zilic, Zeljko, 2024 25th International Symposium on Quality Electronic Design, IEEE, 2024: 1-6.) discloses an automated tool that integrates information flow tracking (IFT), automated assertion generation, and hardware assertion checkers to detect information leakage vulnerabilities in hardware designs. The tool uses IFT technology to generate marked RTL models and automatically generates security assertions based on specified security assets. The security assertions are then converted into hardware assertion checkers. The tool was evaluated on various RTL designs and measured the impact on FPGA resource utilization.

[0007] As can be seen from the above, existing research on RTL information flow tracing technology mainly focuses on improving model accuracy, reducing computational complexity, and automatic assertion generation in the formal verification process, and pays more attention to the security properties of the model, such as confidentiality, integrity, and isolation. However, studying the time domain properties of the RTL information flow model can more accurately capture the timing flow and more effectively detect the timing channel, thereby strengthening security verification and providing defense against new attacks, such as timing-based attacks. After extensive research, it was found that existing research has great limitations in the time domain properties of the RTL information flow model, and has not yet modeled the time domain properties from the perspective of information flow to design secure behaviors. Therefore, there is currently a lack of effective detection methods for new attacks such as timing channel attacks. Summary of the invention

[0008] The technical problem to be solved by the present invention is how to model the time domain attributes from the perspective of information flow to design security behaviors and detect attacks against timing channels.

[0009] The present invention solves the above technical problems through the following technical solutions:

[0010] The time domain and security attribute joint modeling method based on RTL information flow includes the following steps:

[0011] Step 1: Establish the definition of RTLIFT composite attribute tag, wherein the composite attribute tag includes a security attribute tag and a time domain attribute tag;

[0012] Step 2: Formulate a composite attribute label propagation strategy;

[0013] Step 3: Define label formulas for basic logical operations;

[0014] Step 4: synthesize the RTL design of the control flow operation into a gate-level netlist and draw a gate-level circuit diagram;

[0015] Step 5: Abstract the propagation rules of the composite attribute labels based on the gate-level circuit diagram;

[0016] Step 6: Build and update the logic library of data flow and control flow operations;

[0017] Step 7: Single variable label definition and bit width processing;

[0018] Step 8: Use Verilog to design an abstract syntax tree to distinguish between data flow and control flow;

[0019] Step 9: Map the RTL code of the circuit to be tested to the logic library and add RTLIFT logic;

[0020] Step 10: Combine the composite attribute labels and the original variables to complete the modeling;

[0021] Step 11: Generate composite attribute assertion;

[0022] Step 12: Execute assertion verification;

[0023] Step 13: Select different test benchmarks for model evaluation and analysis.

[0024] Furthermore, the security attribute label in step 1 adopts single-bit binary encoding, the time domain attribute label adopts multi-bit binary encoding, and the composite attribute label adopts N-bit binary encoding, wherein the highest bit of the composite attribute label is the security attribute label, and the 0th to N-2th bits of the composite attribute label are the time domain attribute label, wherein N represents the number of bits of the composite attribute label.

[0025] Furthermore, the step 2 is specifically as follows: the label is propagated only when the update of the input can affect the output.

[0026] Furthermore, the step 3 is specifically as follows: defining the propagation rules of the composite attribute labels of basic logical operations through mathematical formulas, constructing the truth table and Karnaugh map of each logical operation, and deriving the logical expression of the composite attribute label of each logical operation, wherein the basic logical operations include logical AND operation, logical OR operation and logical NOT operation.

[0027] Furthermore, the logical expression of the security attribute of the logical AND operation is:

[0028] o x =a x b x +B·ax +A·b x

[0029] Denoted as:

[0030] o x =and x {A,a x ,B,b x}

[0031] In the formula, O x Indicates the output security attribute label, a x Indicates the security attribute label of data object A, b x Represents the security attribute label of data object B, A represents the input data object A, and B represents the input data object B;

[0032] The logical expression of the time attribute of the logical AND operation is:

[0033]

[0034] Denoted as:

[0035] o t =and t {A,a t ,B,b t}

[0036] In the formula, O t Represents the output time domain attribute label, a t Indicates the time domain attribute label of data object A, b t Represents the time domain attribute label of data object B;

[0037] The logical expression of the security attribute of the logical OR operation is:

[0038]

[0039] Denoted as:

[0040] o x =or x {A,a x ,B,b x}

[0041] The logical expression of the time domain attribute of the logical OR operation is:

[0042]

[0043] Denoted as:

[0044] o t =or t {A,a t ,B,bt}

[0045] The logical expression of the safety attribute of the logical NOT operation is:

[0046] o x =a x

[0047] The logical expression of the time domain attribute of the logical NOT operation is:

[0048] o t =a t .

[0049] Furthermore, the step 5 comprises the following steps:

[0050] Step 51, defining propagation rules for data flow operations, wherein the data flow operations include logical operations and unconditional assignment statements, and using the label formula defined in step 3 to propagate the security attributes and time domain attributes of the input signal;

[0051] Step 52: define propagation rules for control flow operations, where the control flow operations include conditional assignment statements and continuous assignment statements, determine the composite attribute label of each node based on the gate-level circuit diagram drawn in step 4 and the label formula defined in step 3, and consider the impact of different paths on the final output label;

[0052] Step 53: define the propagation rules of the Always block, wherein the Always block includes the Always statement, the security attribute label a of the Always statement x_always =a x , the time domain attribute label a of the Always statement t_always =max{a t ,clk}.

[0053] Furthermore, the step 51 is specifically as follows:

[0054] When OUT = A[N:0]·B[N:0], OUT[i] = A[i]·B[i], the i-th bit outputs the security attribute label o x [i]=and x {A[i],a x [i],B[i],b x [i]}, the i-th output time attribute label o t [i]=and t {A[i],a t [i],B[i],b t [i]}, where OUT represents output, OUT[i] represents the output of the i-th bit, A[i] represents the i-th bit of data object A, B[i] represents the i-th bit of data object B, and a x[i] represents the i-th bit of the security attribute label of data object A, b x [i] represents the i-th bit of the security attribute label of data object B;

[0055] When OUT=A[N:0]+B[N:0], OUT[i]=A[i]+B[i], the i-th bit outputs the security attribute label o x [i]=or x {A[i],a x [i],B[i],b x [i]}, the i-th output time attribute label o t [i]=or t {A[i],a t [i],B[i],b t [i]};

[0056] When OUT={A[N:0],B[N:0]}, OUT[i]=A[i] / B[iN], and the i-th bit outputs the security attribute label o x [i] = a x [i] / b x [iN], the i-th output time attribute label o t [i] = a t [i] / b t [iN];

[0057] When OUT=A[N:0], OUT[i]=A[i], the i-th bit outputs the security attribute label o x [i] = a x [i], the i-th output time attribute label o t [i] = a t [i];

[0058] When OUT = ~A[N:0], OUT[i] = ~A[i], the i-th bit outputs the security attribute label o x [i] = a x [i], the i-th output time attribute label o t [i] = a t [i];

[0059] When OUT = {n{A[i]}}, OUT[i] = A[i], and the i-th bit outputs the security attribute label o x [i] = a x [i], the i-th output time attribute label o t [i] = a t [i].

[0060] Furthermore, the step 52 is specifically as follows:

[0061] The security attribute label of output OUT[i] is represented by the following logic:

[0062]

[0063] The time domain attribute label of output OUT[i] is represented by the following logic:

[0064]

[0065] In the formula, s represents the selected node, s = sel[0] + sel[1], s x Indicates the security attribute label of the selected node s, s t Indicates the time attribute label of the selected node s.

[0066] Furthermore, the step 6 is specifically as follows: construct a logic library of data flow and control flow operations, repeat steps 4-5 for different control flow operations, add the label propagation rules abstracted from the gate-level circuit diagram to the basic logic library, and continuously update the logic library so that the logic library can cover the most common RTL statements.

[0067] Furthermore, the step 13 is specifically as follows: evaluating and analyzing the RTL information flow composite model, selecting different test benchmarks for verification, repeating steps 7-12, completing composite attribute modeling, and verifying the validity of the model through simulation and formal verification:

[0068] When the assertion result can be proven, it can be inferred that the hardware design is secure and there are no time side channels or hardware Trojans that may cause sensitive information leakage;

[0069] When only the security property assertion cannot be satisfied, it indicates that there is a security vulnerability in the design that causes sensitive information to be leaked;

[0070] When only the assertion of the time domain attribute cannot be satisfied, it indicates that sensitive information is leaked due to the existence of a hardware time side channel during the design process.

[0071] The advantages of the present invention are:

[0072] (1) The present invention targets the time domain properties of the RTL information flow tracing model, models and designs security behaviors from the perspective of information flow using security properties and time domain properties, and uses additional time domain property tracking logic circuits to capture the data flow and the update time of the signal during the process, and performs dual modeling of the security properties and time domain properties of RTLIFT, wherein the addition of time tags further increases the sensitivity to time side channels. The tags allow each data unit to be associated with a time value, which is used to track the time characteristics of data flowing in the hardware system; by analyzing the propagation of time tags, it is possible to determine how input changes affect the time changes of outputs, so that the model can capture and analyze the time differences caused by the imbalance of execution paths, thereby effectively identifying hardware time side channels that may lead to sensitive information leakage. Compared with the prior art, the present invention can effectively identify time side channel vulnerabilities and improve the accuracy of RTLIFT modeling.

[0073] (2) The present invention defines a multi-bit binary-coded time domain attribute tag in RTLIFT to describe the temporal characteristics of information flow. The tag is measured by the clock cycle in which the data is updated, and can reflect the temporal impact of the input signal on the output signal. By introducing the concept of time domain attribute tags, it is possible to more accurately detect potential security risks when designing and processing new attacks such as timing channel attacks.

[0074] (3) This paper proposes a novel RTLIFT composite attribute label propagation strategy, which explicitly stipulates that labels are only propagated when input updates affect outputs. This fine-grained propagation mechanism is more accurate than traditional methods, can effectively reduce false positives and false negatives, and ensure that the real information flow dynamics are captured in security verification.

[0075] (4) The present invention defines the propagation rules of the composite attribute labels of basic logical operations based on mathematical formulas. By constructing truth tables and Karnaugh maps, specific logical expressions of different basic logical operations are obtained. These expressions can not only capture the security characteristics of RTL information flows, but also effectively characterize time dynamics, providing a basis for accurate modeling of security attribute labels and time domain attribute labels in complex circuits.

[0076] (5) The present invention integrates the security attribute labels and time domain attribute labels of RTLIFT to construct a composite attribute model, and completes the innovative introduction of time domain attribute labels for data flow, control flow and always block operations. The composite model can not only analyze circuit design from the dual perspectives of security and timing, but also provide effective defense strategies for new attacks (such as timing attacks), so that designers can comprehensively evaluate the security and timing behavior of the circuit when performing RTL information flow tracking, thereby achieving more in-depth and effective security verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Figure 1 It is a technical schematic diagram of information flow tracking under the existing technology;

[0078] Figure 2 It is a flow chart of a method for joint modeling of time domain and security attributes based on RTL information flow according to a first embodiment of the present invention;

[0079] Figure 3 It is a schematic diagram of an RTL design program segment of an if statement according to the first embodiment of the present invention;

[0080] Figure 4 is a schematic diagram of a gate-level netlist obtained through DC synthesis according to the first embodiment of the present invention;

[0081] Figure 5 It is a gate-level circuit diagram drawn based on a gate-level netlist according to the first embodiment of the present invention. DETAILED DESCRIPTION

[0082] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described in combination with the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0083] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and specific embodiments:

[0084] Embodiment 1

[0085] like Figure 2 Specifically, a time domain and security attribute joint modeling method based on RTL information flow is disclosed, comprising the following steps:

[0086] Step 1: Establish the definition of RTLIFT composite attribute tag, wherein the composite attribute tag includes a security attribute tag and a time domain attribute tag;

[0087] The security attribute label uses a single-bit binary code to characterize the security attribute of the data object, identify the security of the circuit information flow, and ensure that there is no information leakage and other security issues during the transmission of sensitive signals. The security attribute of data object A is denoted as a x Security attributes cover dimensions such as confidentiality and integrity. This embodiment takes integrity as an example. If data object A is judged to be untrustworthy and data object B is trustworthy, data cannot flow from A to B. At this time, the security attribute label a of data object A is set to x Marked as "1", the security attribute label b of data object B x Marked as "0".

[0088] The time domain attribute label uses multi-bit binary coding to characterize the time domain attribute of the data object, describes the time when information flows from input to output, and reflects the time dynamic characteristics of the input signal affecting the output signal. The time domain attribute label can be accurately measured by the clock cycle when the data is updated. The time attribute label of data object A is denoted as a t .

[0089] The composite attribute label is encoded in N bits binary format. The composite attribute label of data object A is denoted as a n , where a n The highest bit of is the security attribute label, denoted as a x =a n [N-1], a n The 0th to N-2th bits are time domain attribute labels, denoted as a t =a n [N-2:0]. In this embodiment, the number of bits of the time domain attribute label can be dynamically adjusted according to the circuit scale and time cycle. For example, for complex circuits and longer clock cycles, more bits of time attribute labels can be used, where N represents the number of bits of the composite attribute label.

[0090] Step 2: Formulate a composite attribute label propagation strategy;

[0091] Furthermore, the composite attribute propagation strategy is specifically: the label is propagated only when the input update can affect the output.

[0092] Since the RTLIFT technology is a fine-grained information flow analysis method that can track information flow more accurately, unlike previous conservative strategies, the composite attribute label propagation strategy proposed in this embodiment stipulates that labels are propagated only when input updates can affect outputs.

[0093] This embodiment uses integrity as an example to illustrate the security attribute label. When the untrusted information of the input data object A can affect the output O, the output security attribute label is marked as untrusted, that is, a x =1,o x =1; Conversely, when the untrusted information of the input data object A cannot affect the output O, the output security attribute label will not be marked as untrusted, that is, a x =1,o x =0.

[0094] As for the time domain attribute label, the input time domain attribute label is passed to the output only when the update of the input affects the update of the output.

[0095] Step 3: Define label formulas for basic logical operations;

[0096] Furthermore, the label formula for defining the basic logic operation is specifically as follows: defining the propagation rules of the composite attribute labels of the basic logic operation by mathematical formulas, constructing the truth table and Karnaugh map of each logic operation, and obtaining the logical expression of the composite attribute label of each logic operation, wherein the basic logic operation includes a logical AND operation, a logical OR operation, and a logical NOT operation;

[0097] In this embodiment, the logic and operation is taken as an example to illustrate how to define the label formula of the basic operation. The original logic of the logic and operation is known to be O=A·B. x ,b x ,O,o x The truth table is shown in Table 1 below:

[0098] Table 1A,B,a x ,b x ,O,o x The truth table of

[0099]

[0100] The logical expression of the security attribute of the logical AND operation is obtained by using the Karnaugh map simplification method (not shown in the figure):

[0101] o x =a x b x +B·a x +A·b x

[0102] Denoted as:

[0103] o x =and x {A,a x ,B,b x}

[0104] Considering the output time attribute label o t Depends on A, B, a t ,b t , when A=0, B=0, o t =min{a t ,b t}, because if the first input to the AND operation is 0, the output must depend on the first input to arrive; if the first input to the AND gate is 1, the output must depend on the second input to arrive. Similarly, when A=1, B=0, o t =b t ; When A=0, B=1, o t =a t ; When A=1, B=1, ot =max{a t ,b t Combining all the above situations, the logical expression of the time domain attribute of the logical AND operation is:

[0105]

[0106] Denoted as:

[0107] o t =and t {A,a t ,B,b t}

[0108] Repeat the above steps to get the logical expression of the security attribute of the logical OR operation:

[0109]

[0110] Denoted as:

[0111] o x =or x {A,a x ,B,b x}

[0112] The logical expression for the time domain attribute of the logical OR operation is:

[0113]

[0114] Denoted as:

[0115] o t =or t {A,a t ,B,b t}

[0116] The logical expression for the safety property of the logical NOT operation is:

[0117] o x =a x

[0118] The logical expression for the time domain property of the logical NOT operation is:

[0119] o t =a t

[0120] Furthermore, the input data objects A and B and output O of the above logic expression are all single bits, and the above logic expression can be expanded to multiple bits, and the logic expression of the composite label can be calculated bit by bit.

[0121] In this embodiment, the above logical expressions can capture the security characteristics and time characteristics of basic logical operations, and arbitrary logical operations are constructed by the above basic logical operations, which provides a basis for constructing security attribute labels and time domain attribute labels for subsequent complex operations.

[0122] Step 4: synthesize the RTL design of the control flow operation into a gate-level netlist and draw a gate-level circuit diagram;

[0123] In this embodiment, the RTL code is converted into a gate-level netlist through the DC synthesis tool. The gate-level netlist can accurately reflect the layout of the RTL design in the physical circuit. The gate-level netlist can be used to analyze the propagation rules of complex attribute labels on different paths from a more detailed level, providing an accurate description for the specific implementation of the logic circuit.

[0124] Step 5: Abstract the propagation rules of the composite attribute labels based on the gate-level circuit diagram;

[0125] When constructing the RTLIFT model, the RTL design needs to be divided into data flow operation statements and control flow operation statements, and RTLIFT labels are added to them respectively. In this embodiment, the propagation rules of data flow operations and control flow operations can be better defined through the information path of the gate-level circuit.

[0126] Furthermore, the step 5 includes the following specific steps:

[0127] Step 51, defining propagation rules for data flow operations, wherein the data flow operations include logical operations and unconditional assignment statements, and using the label formula defined in step 3 to propagate the security attributes and time domain attributes of the input signal;

[0128] In this embodiment, since the information is displayed and flows, this embodiment directly uses the defined label formula to propagate the security attribute and the time domain attribute of the input signal, as shown in the following Table 2:

[0129] Table 2 Data stream operation security attribute labels and time domain attribute labels

[0130]

[0131] This embodiment takes sequence number 1 as an example for explanation. The data flow operation is OUT=A[N:0]·B[N:0]. This operation is performed bit by bit and the operation for each bit is OUT[i]=A[i]·B[i]. For the output security attribute label O of OUT[i], x [i] and output time domain attribute label O t [i], use the label formula defined in step 3 to solve. Similarly, the basic data flow operations of sequence numbers 2-5 can all construct their security attribute labels and time domain attribute labels according to the label formula defined in step 3, specifically:

[0132] When OUT = A[N:0]·B[N:0], OUT[i] = A[i]·B[i], the i-th bit outputs the security attribute label o x [i]=and x {A[i],a x [i],B[i],b x [i]}, the i-th output time attribute label o t [i]=and t {A[i],a t [i],B[i],b t [i]}, where OUT represents output, OUT[i] represents the output of the i-th bit, A[i] represents the i-th bit of data object A, B[i] represents the i-th bit of data object B, and a x [i] represents the i-th bit of the security attribute label of data object A, b x [i] represents the i-th bit of the security attribute label of data object B;

[0133] When OUT=A[N:0]+B[N:0], OUT[i]=A[i]+B[i], the i-th bit outputs the security attribute label o x [i]=or x {A[i],a x [i],B[i],b x [i]}, the i-th output time attribute label o t [i]=or t {A[i],a t [i],B[i],b t [i]};

[0134] When OUT={A[N:0],B[N:0]}, OUT[i]=A[i] / B[iN], and the i-th bit outputs the security attribute label o x [i] = a x [i] / b x [iN], the i-th output time attribute label o t [i] = a t [i] / b t [iN];

[0135] When OUT=A[N:0], OUT[i]=A[i], the i-th bit outputs the security attribute label o x [i] = a x [i], the i-th output time attribute label o t [i] = a t [i];

[0136] When OUT = ~A[N:0], OUT[i] = ~A[i], the i-th bit outputs the security attribute label o x [i] = a x [i], the i-th output time attribute label o t [i] = a t [i];

[0137] When OUT = {n{A[i]}}, OUT[i] = A[i], and the i-th bit outputs the security attribute label o x [i] = a x [i], the i-th output time attribute label o t [i] = a t [i].

[0138] Step 52: define propagation rules for control flow operations, where the control flow operations include conditional assignment statements and continuous assignment statements, determine the composite attribute label of each node based on the gate-level circuit diagram drawn in step 4 and the label formula defined in step 3, and consider the impact of different paths on the final output label;

[0139] In this embodiment, since information has the characteristics of explicit flow and implicit flow, this embodiment defines the propagation rules of the control flow operation based on the gate-level circuit diagram drawn in step 4 and the label formula defined in step 3, and takes the conditional assignment statement guided by the if statement as an example for explanation, as shown in FIG. Figure 3 The following is the RTL program code of the if conditional statement. Figure 4 To perform DC synthesis on the RTL design, we get the gate-level netlist. Figure 5 This is a gate-level circuit diagram drawn based on the gate-level netlist. From the gate-level circuit diagram of the if statement, we can see that the input data objects A[2:0] and B[2:0], the selection signal sel[1:0], and the output OUT[2:0]. In the figure, n1 represents OUT[0], n2 represents OUT[1], and n3 represents OUT[2]. sel[1:0] controls the input A[2:0] and B[2:0] to flow to the output OUT[2:0], realizing the following functions:

[0140] When sel[1:0]=0, OUT[2:0]=B[2:0];

[0141] When sel[1:0]≠0, OUT[2:0]=A[2:0].

[0142] The logical relationship between nodes can be obtained according to the gate-level circuit diagram. Suppose the selected node s = sel[0] + sel[1], the logical expressions of the security attribute label and the time domain attribute label of s are as follows:

[0143] s x =or x{sel[0],sel x [0],sel[1],sel x [1]}

[0144] s t =or t {sel[0],sel t [0],sel[1],sel t [1]}

[0145] The logical expressions of n1, n2, and n3 are expressed as follows using s:

[0146]

[0147] After sorting, the logical expression of any output of the gate-level circuit is as follows:

[0148]

[0149] Take OUT[0] as an example to explain the operation. This operation is a bitwise operation, transferring the lowest bit of A or B, A[0], B[0], to the lowest bit of OUT[0]. For the security attribute label o of OUT[0] x [0] Solve according to the label formula defined in step 3. The derivation process is as follows:

[0150] o x [0]=or x {n10,n10 x ,n11,n11 x}

[0151] n10=A[0]·s

[0152]

[0153] n10 x =and x {A[0],a x [0],s,s x}

[0154]

[0155] For the time domain attribute label o of OUT[0] t [0] Also solve according to the label formula defined in step 3. The derivation process is as follows:

[0156] o t [0]=or t {n10,n10 t ,n11,n11 t}

[0157] n10=A[0]·s

[0158]

[0159] n10 t =and t {A[0],a t [0],s,s t}

[0160]

[0161] Similarly, the security attribute labels and time domain attribute labels of all bits OUT[2:0] of output OUT can be obtained. After sorting, the security attribute label of output OUT[i] is represented by the following logic:

[0162]

[0163] The following logic represents the time domain attribute label of output OUT[i]:

[0164]

[0165] The security attribute labels and time domain attribute labels of other basic control flow operations can be constructed similarly.

[0166] Step 53: define the propagation rules of the Always block, wherein the Always block includes the Always statement, the security attribute label a of the Always statement x_always =a x , the time domain attribute label a of the Always statement t_always =max{a t ,clk}.

[0167] In this embodiment, it is necessary to perform timing label analysis on all possible paths in the always statement. The time domain attribute label of the operation object is not only related to the propagation rules of the data flow or control flow, but also to the clock clk. The operation is performed only when the clock changes. Therefore, the time domain attribute label of the always statement in this embodiment takes the maximum value of the label and clk obtained by the above data flow and control flow propagation rules, that is, a t_always =max{a t ,clk}; the security attribute label of the always statement is still consistent with the label obtained by the above data flow control flow propagation rules, that is, a x_always =a x .

[0168] Step 6: Build and update the logic library of data flow and control flow operations;

[0169] In this embodiment, a logic library of data flow and control flow operations is first constructed. For different control flow operations, steps 4-5 are repeated, and the label propagation rules abstracted from the gate-level circuit diagram are added to the basic logic library. By continuously updating the logic library, the logic library can cover the most common RTL statements, such as addition, logical operations, conditional assignments, etc., to provide standardized security attribute labels and time attribute label propagation formulas for each operation.

[0170] Step 7: Single variable label definition and bit width processing;

[0171] In this embodiment, a label is defined for each variable according to the bit width of the circuit signal to be tested. Each variable may be composed of several bits. In this embodiment, a 1-bit security attribute label and an (N-1)-bit time domain attribute label are assigned to each bit, which are combined into an N-bit composite attribute label for each bit, where N is dynamically adjusted according to the circuit scale and the clock cycle. For example, for complex circuits and longer clock cycles, time attribute labels with more bits can be used.

[0172] Step 8: Use Verilog to design an abstract syntax tree to distinguish between data flow and control flow;

[0173] In this embodiment, Yosys is used to convert the Verilog code of the circuit to be tested into an abstract syntax tree (AST) and divide the data flow and control flow. This process automatically analyzes the code structure, extracts the types of different statements, and provides semantic information for the subsequent modeling process, ensuring that the data flow and control flow operations can be labeled and modeled using the corresponding logic libraries respectively.

[0174] Yosys is an open source logic synthesis and verification tool based on Verilog RTL. It can handle any synthesizable Verilog design. Its Verilog front end converts Verilog code into an abstract syntax tree (AST) to generate a data flow graph. The RTL syntax tree (AST) is a tree structure formed after parsing the RTL source code. It clearly represents the logical structure and grammatical relationship of the code. AST contains all the information of the circuit, including data nodes, operation nodes, and instance nodes. It can distinguish between data flow operation statements and control flow operation statements, and add information flow tracking logic to them according to the operation rules of the logic library. In addition, AST plays an important role in extracting circuit features, especially in hardware Trojan detection.

[0175] Step 9: Map the RTL code of the circuit to be tested to the logic library and add RTLIFT logic;

[0176] In this embodiment, each operation is mapped to a label formula defined in a basic logic library by parsing the RTL code, and time tracking logic is automatically added according to different operation types to ensure that the time changes of the signal during transmission are accurately captured.

[0177] Step 10: Combine the composite attribute labels and the original variables to complete the modeling;

[0178] In this embodiment, the time information flow model of the entire RTL design is completed by combining the composite label with the original variable, and each variable is assigned a composite attribute label that reflects its security attribute and time dynamic behavior (time attribute).

[0179] Step 11: Generate composite attribute assertion;

[0180] In this embodiment, based on the propagation strategy of composite attribute labels, the security attributes and time domain attributes of the model are extracted, and the composite attributes are described using an assertion specification language (such as SystemVerilog Assertions, SVA) in the assertion automatic generator to automatically generate composite attribute assertions. The assertions verify the constancy of the time domain attribute labels based on the system execution time invariance, thereby detecting time side channel vulnerabilities.

[0181] Step 12: Execute assertion verification;

[0182] In this embodiment, based on the aforementioned assertion description, the model is verified, and formal verification tools such as Mentor GraphicsQuesta Formal are used to verify whether the timing domain properties and security properties meet expectations. Assertion verification can capture potential timing errors or security vulnerabilities in the design and ensure that the design meets all predefined property requirements.

[0183] After building the RTLIFT model for the RTL design, the validity of the test benchmark (such as AES-T100) can be verified through simulation testing and formal verification. Specifically, this model verification method combines the advantages of simulation testing and formal verification, abstracts the system behavior into a finite state model, and uses formal specifications to describe the system properties to check whether there are any violations of the specifications. The logical model of information flow tracing combined with formal verification tools can achieve qualitative detection of hardware design security vulnerabilities. During the verification process, the SystemVerilog language is used to describe the label attributes to be verified, and the attribute assertions in the SystemVerilog Assertions (SVA) format are generated through the automatic assertion generator; then, the RTLIFT model and assertions are verified using formal verification tools such as Mentor Graphics Questa Formal; finally, the verification results are observed to determine whether the assertions are established, thereby evaluating whether the design has security vulnerabilities, and the RTLIFT model is evaluated based on the accuracy and coverage of formal verification.

[0184] Step 13: Select different test benchmarks for model evaluation and analysis;

[0185] In this embodiment, the RTL information flow composite model is evaluated and analyzed, different test benchmarks are selected for verification, and steps 7-12 are repeated to complete the composite attribute modeling and verify the validity of the model through simulation and formal verification.

[0186] When the assertion result can be proven, it can be inferred that the hardware design is secure and there are no time side channels or hardware Trojans that may cause sensitive information leakage;

[0187] When only the security property assertion cannot be satisfied, it indicates that there is a security vulnerability in the design that causes sensitive information to be leaked;

[0188] When only the assertion of the time domain attribute cannot be satisfied, it indicates that sensitive information is leaked due to the existence of a hardware time side channel during the design process.

[0189] This embodiment targets the time domain properties of the RTL information flow tracing model, models and designs security behaviors from the perspective of information flow using security properties and time domain properties respectively, and uses additional time domain property tracking logic circuits to capture the data flow and the update time of the signal during the process, and performs dual modeling of the security properties and time domain properties of RTLIFT, wherein the addition of time tags further increases the sensitivity to time side channels. Tags allow each data unit to be associated with a time value, which is used to track the time characteristics of data flowing in the hardware system; by analyzing the propagation of time tags, it is possible to determine how input changes affect the time changes of outputs, so that the model can capture and analyze the time differences caused by the imbalance of execution paths, thereby effectively identifying hardware time side channels that may lead to sensitive information leakage. Compared with the prior art, this embodiment can effectively identify time side channel vulnerabilities and improve the accuracy of RTLIFT modeling.

[0190] This embodiment defines a multi-bit binary-coded time domain attribute label in RTLIFT, which is used to describe the time characteristics of information flow. The label is measured by the clock cycle in which the data is updated, and can reflect the time impact of the input signal on the output signal. By introducing the concept of time domain attribute labels, it is possible to more accurately detect potential security risks when designing and processing new attacks such as timing channel attacks.

[0191] This embodiment proposes a novel RTLIFT composite attribute label propagation strategy, which explicitly stipulates that labels are only propagated when input updates affect outputs. This fine-grained propagation mechanism is more accurate than traditional methods, can effectively reduce false positives and false negatives, and ensure that the real information flow dynamics are captured in security verification.

[0192] This embodiment defines the propagation rules of composite attribute labels of basic logical operations based on mathematical formulas. By constructing truth tables and Karnaugh maps, specific logical expressions of different basic logical operations are obtained. These expressions can not only capture the security characteristics of RTL information flows, but also effectively characterize time dynamics, providing a basis for accurate modeling of security attribute labels and time domain attribute labels in complex circuits.

[0193] This embodiment integrates the security attribute labels and time domain attribute labels of RTLIFT to construct a composite attribute model, and completes the innovative introduction of time domain attribute labels for data flow, control flow and always block operations. This composite model can not only analyze circuit design from the dual perspectives of security and timing, but also provide effective defense strategies for new attacks (such as timing attacks), allowing designers to comprehensively evaluate the security and timing behavior of the circuit when performing RTL information flow tracking, thereby achieving more in-depth and effective security verification.

[0194] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A joint modeling method of time domain and security attributes based on RTL information flow, characterized in that: The following steps are involved: Step 1: Establish the definition of RTLIFT composite attribute tag, wherein the composite attribute tag includes a security attribute tag and a time domain attribute tag; Step 2: Formulate a composite attribute label propagation strategy; Step 3: Define label formulas for basic logical operations; Step 4: synthesize the RTL design of the control flow operation into a gate-level netlist and draw a gate-level circuit diagram; Step 5: Abstract the propagation rules of the composite attribute labels based on the gate-level circuit diagram; Step 6: Build and update the logic library of data flow and control flow operations; Step 7: Single variable label definition and bit width processing; Step 8: Use Verilog to design an abstract syntax tree to distinguish between data flow and control flow; Step 9: Map the RTL code of the circuit to be tested to the logic library and add RTLIFT logic; Step 10: Combine the composite attribute labels and the original variables to complete the modeling; Step 11: Generate composite attribute assertion; Step 12: Execute assertion verification; Step 13: Select different test benchmarks for model evaluation and analysis.

2. The time domain and security attribute joint modeling method based on RTL information flow according to claim 1 is characterized in that: The security attribute label described in step 1 adopts single-bit binary encoding, the time domain attribute label adopts multi-bit binary encoding, and the composite attribute label adopts N-bit binary encoding, where the highest bit of the composite attribute label is the security attribute label, and the 0th to N-2th bits of the composite attribute label are the time domain attribute label, where N represents the number of bits of the composite attribute label.

3. The time domain and security attribute joint modeling method based on RTL information flow according to claim 1 is characterized in that: The step 2 is specifically: label propagation is performed only when the input update can affect the output.

4. The time domain and security attribute joint modeling method based on RTL information flow according to claim 1 is characterized in that: The step 3 is specifically as follows: defining the propagation rules of the composite attribute labels of basic logical operations through mathematical formulas, constructing the truth table and Karnaugh map of each logical operation, and obtaining the logical expression of the composite attribute labels of each logical operation, wherein the basic logical operations include logical AND operation, logical OR operation and logical NOT operation.

5. The time domain and security attribute joint modeling method based on RTL information flow according to claim 4 is characterized in that: The logical expression of the security attribute of the logical AND operation is: o x =a x ·b x +B·a x +A·b x Denoted as: o x =and x {A,a x ,B,b x } In the formula, O x Indicates the output security attribute label, a x Indicates the security attribute label of data object A, b x Represents the security attribute label of data object B, A represents the input data object A, and B represents the input data object B; The logical expression of the time attribute of the logical AND operation is: Denoted as: o t =and t {A,a t ,B,b t } In the formula, O t Represents the output time domain attribute label, a t Indicates the time domain attribute label of data object A, b t Represents the time domain attribute label of data object B; The logical expression of the security attribute of the logical OR operation is: Denoted as: o x =or x {A,a x ,B,b x } The logical expression of the time domain attribute of the logical OR operation is: Denoted as: o t =or t {A,a t ,B,b t } The logical expression of the safety attribute of the logical NOT operation is: the x =a x The logical expression of the time domain attribute of the logical NOT operation is: the t =a t 。 6. The time domain and security attribute joint modeling method based on RTL information flow according to claim 1 is characterized in that: The step 5 comprises the following steps: Step 51, defining propagation rules for data flow operations, wherein the data flow operations include logical operations and unconditional assignment statements, and using the label formula defined in step 3 to propagate the security attributes and time domain attributes of the input signal; Step 52: define propagation rules for control flow operations, wherein the control flow operations include conditional assignment statements and continuous assignment statements, determine the composite attribute label of each node according to the gate-level circuit diagram drawn in step 4 and the label formula defined in step 3, and consider the impact of different paths on the final output label; Step 53: define the propagation rules of the Always block, wherein the Always block includes the Always statement, the security attribute label a of the Always statement x_always =a x , the time domain attribute label a of the Always statement t_always =max{a t ,clk}.

7. The time domain and security attribute joint modeling method based on RTL information flow according to claim 6 is characterized in that: The step 51 is specifically as follows: When OUT = A[N:0]·B[N:0], OUT[i] = A[i]·B[i], the i-th bit outputs the security attribute label o x [i]=and x {A[i],a x [i],B[i],b x [i]}, the i-th output time attribute label o t [i]=and t {A[i],a t [i],B[i],b t [i]}, where OUT represents output, OUT[i] represents the output of the i-th bit, A[i] represents the i-th bit of data object A, B[i] represents the i-th bit of data object B, and a x [i] represents the i-th bit of the security attribute label of data object A, b x [i] represents the i-th bit of the security attribute label of data object B; When OUT=A[N:0]+B[N:0], OUT[i]=A[i]+B[i], the i-th bit outputs the security attribute label o x [i]=or x {A[i],a x [i],B[i],b x [i]}, the i-th output time attribute label o t [i]=or t {A[i],a t [i],B[i],b t [i]}; When OUT={A[N:0],B[N:0]}, OUT[i]=A[i] / B[iN], and the i-th bit outputs the security attribute label o x [i] = a x [i] / b x [iN], the i-th output time attribute label o t [i] = a t [i] / b t [iN]; When OUT=A[N:0], OUT[i]=A[i], the i-th bit outputs the security attribute label o x [i] = a x [i], the i-th output time attribute label o t [i] = a t [i]; When OUT = ~A[N:0], OUT[i] = ~A[i], the i-th bit outputs the security attribute label o x [i] = a x [i], the i-th output time attribute label o t [i] = a t [i]; When OUT = {n{A[i]}}, OUT[i] = A[i], and the i-th bit outputs the security attribute label o x [i] = a x [i], the i-th output time attribute label o t [i] = a t [i].

8. The time domain and security attribute joint modeling method based on RTL information flow according to claim 6 is characterized in that: The step 52 is specifically as follows: The security attribute label of output OUT[i] is represented by the following logic: The time domain attribute label of output OUT[i] is represented by the following logic: In the formula, s represents the selected node, s = sel[0] + sel[1], s x Indicates the security attribute label of the selected node s, s t Indicates the time attribute label of the selected node s.

9. The time domain and security attribute joint modeling method based on RTL information flow according to claim 1 is characterized in that: The step 6 is specifically as follows: construct a logic library for data flow and control flow operations, repeat steps 4-5 for different control flow operations, add the label propagation rules abstracted from the gate-level circuit diagram to the basic logic library, and continuously update the logic library so that the logic library can cover the most common RTL statements.

10. The time domain and security attribute joint modeling method based on RTL information flow according to claim 1 is characterized in that: The step 13 is specifically: evaluating and analyzing the RTL information flow composite model, selecting different test benchmarks for verification, repeating steps 7-12, completing composite attribute modeling, and verifying the validity of the model through simulation and formal verification. When the assertion result can be proven, it can be inferred that the hardware design is secure and there are no time side channels or hardware Trojans that may cause sensitive information leakage; When only the security property assertion cannot be satisfied, it indicates that there is a security vulnerability in the design that causes sensitive information to be leaked; When only the assertion of the time domain attribute cannot be satisfied, it indicates that sensitive information is leaked due to the existence of a hardware time side channel during the design process.

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