A method for predicting wire length and wire delay of digital integrated circuit layout in cooperation

Abstract

The application discloses a kind of digital integrated circuit layout post wire length and line delay collaborative prediction method, comprising: constructing preliminary version heterogeneous graph based on the connection information of circuit netlist;From netlist file and process file, the features used for prediction are extracted;The features extracted are added to the corresponding node and edge of preliminary version heterogeneous graph, to obtain final version heterogeneous graph;Construct prediction model;The constructed prediction model is trained;Final version heterogeneous graph is input into the prediction model that training is completed, and finally the prediction result of wire length and the prediction result of line delay are obtained.The model used in the application introduces multi-task learning framework, considers the collaborative relationship of wire length and line delay, in this case, by the model, wire length and line delay are predicted, not only can reduce the time cost of training and reasoning, improve the prediction efficiency, but also can ensure the deep integration and full use of wire length and line delay related information, overcome the problem that the two indicators are relatively independent in the prior art.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital integrated circuit electronic design automation, and particularly relates to a method for predicting wire length and wire delay after layout of a digital integrated circuit. BACKGROUND

[0002] The design process of a digital integrated circuit includes multiple links, and each link has an important influence on the performance of the final design. Among them, logic synthesis and layout are important stages that are indispensable in the design process. Logic synthesis is to convert a hardware description language (such as Verilog or VHDL) into a gate-level netlist, laying a foundation for subsequent physical design. Layout focuses on placing circuit elements reasonably on a chip to ensure that wiring can be carried out smoothly.

[0003] In these two stages, timing analysis is an important step, and its purpose is to verify whether the design meets the established timing requirements. The core task of timing analysis is to calculate the propagation time of signals in the circuit, i.e., the delay. Delay refers to the time required for a signal to pass from one point to another, which directly affects the working frequency and response speed of the circuit. In the calculation of delay, the influence of wire length cannot be ignored. Wire length refers to the length of the wire connecting two or more circuit elements. Since the transmission of signals on the wire is not instantaneous, but requires a certain time to cross these distances, this produces additional delay caused by the wire. Longer wires will increase the resistance and capacitance effect, resulting in greater delay, which will destroy the original expected timing characteristics.

[0004] In the logic synthesis stage, due to the lack of detailed physical location information, timing analysis usually predicts wire length based on idealized assumptions or some estimation models, but such an approach is difficult to accurately estimate the additional delay caused by the actual wire length. When the design enters the layout stage, with the specific location of the circuit elements being determined, the influence of wire length becomes clear, which will change the originally estimated delay value, and thus affect the overall timing performance. This deviation often leads to multiple rounds of iteration to adjust design constraints and re-layout to meet strict timing requirements, which not only prolongs the design cycle, but also increases resource consumption, greatly affecting design efficiency. Therefore, how to accurately predict the wire length and even the delay in the subsequent stage (such as layout) in the early stage of design (such as logic synthesis) has become the key to improving design efficiency and quality.

[0005] (Xie Z, Liang R, Xu X, et al. Preplacement net length and timing estimation by customized graph neural network[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, 41(11): 4667-4680.) is the most similar prior art to the present invention. The research innovatively proposes a two-step prediction process: first, the net length is predicted by a graph neural network, and then the prediction results are input into a random forest model as features to realize the prediction of cell delay and net delay. Specifically, the research models each net in the design as a node in the graph, combines pre-defined node features and uses a graph neural network to complete the net length prediction task, and then builds two independent prediction models based on random forest to predict cell delay and net delay. The prediction model uses the net length prediction value as the input feature. The experimental results show that this method can significantly improve the accuracy of delay prediction. Although the literature has some innovations in the method and has improved the prediction accuracy, it still has some limitations and shortcomings:

[0006] Single-task model limitation: The literature uses a single-task model to handle the net length and delay prediction problems separately. The single-task model is limited in capturing the correlation between tasks and cannot effectively share features and information. Although the two-step method in the literature attempts to consider the correlation between net length and delay by first predicting net length and then predicting delay, it partially considers the influence of net length on delay. However, this approach is slightly insufficient because the models used for the two tasks are still handled independently, and the complex interaction between net length and delay is not fully captured. This separate processing approach limits the comprehensive use of related features by the model, which may miss some important information and affect the accuracy of the final prediction.

[0007] Speed problem: The two-step prediction process in the literature may result in longer training and inference time, requiring the training of two independent models - one for net length prediction and the other for delay prediction. Moreover, whether it is training or inference, the corresponding net length prediction value needs to be added to each feature used for delay prediction before the next step of delay prediction. This two-step method is not only cumbersome but also may cause significant time overhead in practical applications, especially when dealing with large-scale circuit designs, where efficiency is particularly important. SUMMARY

[0008] The present application aims to overcome the deficiencies of the prior art, and provide a digital integrated circuit layout post-line length and line delay collaborative prediction method.

[0009] To achieve the above-mentioned purpose, the technical scheme provided by the present application is:

[0010] A digital integrated circuit layout post-line length and line delay collaborative prediction method, comprising:

[0011] Constructing a preliminary heterogeneous graph based on the connection information of the circuit netlist;

[0012] Extracting features for line length and line delay prediction of the line edge from the netlist file and the process file;

[0013] Adding the extracted features to the corresponding nodes and edges of the preliminary heterogeneous graph to obtain a final heterogeneous graph with connection relationships and features;

[0014] Constructing a line length and line delay collaborative prediction model based on graph neural network and multi-task learning;

[0015] Training the constructed line length and line delay collaborative prediction model based on graph neural network and multi-task learning;

[0016] Inputting the final heterogeneous graph into the trained line length and line delay collaborative prediction model based on graph neural network and multi-task learning, and finally obtaining the prediction results of line length and line delay.

[0017] Further, the features extracted from the netlist file and the process file include node features and edge features;

[0018] Among them, the edge features for line length prediction include the driving strength of the source pin unit, the source pin fan-out number, the source pin unit area, the source pin unit pin number, the target pin unit area, and the target pin unit fan-out number;

[0019] The node features for line delay prediction include the conversion time, the margin, the capacitance of the input pin, and the maximum capacitance of the output pin;

[0020] The edge features for line delay prediction include the line network capacitance and the line network resistance.

[0021] Further, the constructed line length and line delay collaborative prediction model based on graph neural network and multi-task learning includes three TransformerConv layers, each of which is provided with a cross-stitch unit after the layer, and the last cross-stitch unit is connected to two task branches, both of which include a line edge embedding generation module and a fully connected layer.

[0022] Further, the working mechanism of the TransformerConv layer includes:

[0023] For each node i in the graph, its input feature is represented as where d is the feature dimension, and l represents the index of the current network layer; first, the input feature is linearly transformed by a learnable weight matrix to obtain the query vector , the key vector , and the value vector

[0024]

[0025] where the query vector is used to measure the attention degree of node i to other nodes; the key vector is used to match the query vectors of other nodes to calculate the attention weight; and the value vector contains the actual information of the node and is used for weighted summation to update the node feature;

[0026] To utilize the information of the edge features in the graph, the TransformerConv layer linearly transforms the edge feature by a learnable weight matrix to map it to the same dimension space as the node feature:

[0027]

[0028] Subsequently, the attention weight coefficient ij between node i and its neighbor node j is calculated according to the above transformation results:

[0029]

[0030] where the dot product operation T k measures the similarity between the query vector and the key vector, while the normalization in the denominator ensures that the sum of the attention weights is 1, and the introduction of the edge feature enhances the model's ability to utilize edge feature information;

[0031] Based on the attention weight coefficient ij , the new feature of the node is obtained by weighted summation of the value vectors of the neighbor nodes:

[0032]

[0033] where is a learnable weight matrix used to transform the feature of the node itself; Retain the feature information of the node itself Fuse the information of the neighbor nodes, and realize weighted aggregation through attention weights Edge features Join the aggregation process to enhance the model's expression ability for the relationship between nodes.

[0034] Further, a cross-stitch unit is arranged after each layer of the TransformerConv layer to dynamically interact the node features in the feature extraction process of the line length prediction task T1 and the line delay prediction task T2. In the lth layer of the TransformerConv, the node feature representations of the two tasks T1 and T2 are and where i represents the node index, and d is the feature dimension; the cross-stitch unit fuses the feature representations of different tasks by learning the linear combination weight to generate a new feature representation and

[0035]

[0036] wherein, α 11 , α 12 , α 21 , α 22 are attention weight coefficients.

[0037] Further, in the line edge embedding generation module of each task branch, the embedding representations of the source node and the target node are fused into a new embedding representation, i.e., the line edge embedding, through a concatenation operation. The concatenation operation retains the complete information of the source node and the target node and captures the relationship between them.

[0038] Each task branch processes the embedding representation through a fully connected layer, which is composed of three consecutive hidden layers. Each layer uses a nonlinear activation function ReLU to enhance the expression ability of the model and finally outputs the prediction result.

[0039] Further, for the constructed line length and line delay collaborative prediction model based on the graph neural network and multi-task learning, the line length prediction task T1 and the line delay prediction task T2 use the mean square error as the single-task loss function, which are defined as follows:

[0040]

[0041] wherein, N represents the total number of line edges, y wirelength,i and represent the real line length value and the predicted value of the ith line edge, respectively, y netdelay,i and represent the real line delay value and the predicted value of the ith line edge, respectively.

[0042] In order to effectively balance the optimization objectives of the two tasks in the multi-task learning framework, a geometric mean loss is used as a joint loss function The definition is as follows:

[0043]

[0044] Compared with the prior art, the technical scheme principle and advantages are as follows:

[0045] The technical scheme creates a line length and line delay collaborative prediction model based on a graph neural network and multi-task learning. The model introduces a multi-task learning framework and considers the collaborative relationship between line length and line delay. In this case, the model can not only reduce the time cost of training and inference and improve the prediction efficiency, but also ensure the deep fusion and full use of line length and line delay related information, overcoming the problem that the two indicators are relatively independent in the prior art. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical scheme in the embodiments of the present application or the prior art, the services required in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0047] Figure 1 A principle flowchart of a digital integrated circuit layout post-line length and line delay collaborative prediction method according to an embodiment of the present application;

[0048] Figure 2 A multi-task learning framework diagram;

[0049] Figure 3 An example diagram of converting a circuit diagram into a heterogeneous graph;

[0050] Figure 4 An architecture diagram of a line length and line delay collaborative prediction model based on a graph neural network and multi-task learning created in a digital integrated circuit layout post-line length and line delay collaborative prediction method according to an embodiment of the present application. DETAILED DESCRIPTION

[0051] The present application will be further described below in conjunction with specific embodiments:

[0052] The digital integrated circuit layout post-line length and line delay collaborative prediction method described in this embodiment defines the collaborative prediction problem to be solved as a multi-task learning problem, as follows:

[0053] Given two supervised learning tasks TI , I = 1, 2, where task T1 is a graph edge-level regression task for wire length prediction of different cell pin-to-pin connections. The wire length prediction target of this embodiment is the length of the wire between two pins belonging to different cells, as it is directly related to the signal propagation path inside the chip, can finely model the signal propagation characteristics, and can more accurately locate potential problematic connections to provide guidance for subsequent optimization. What is particularly important is that this fine-grained selection maintains consistent granularity with the pin-to-pin wire delay, thereby providing a natural fit for feature sharing in the multi-task learning framework. Task T2 is a graph edge-level regression task for wire delay prediction. For these two tasks, the input is a heterogeneous graph with logic synthesis stage feature information, and the construction of the heterogeneous graph will be described in detail in the data representation. There is a significant correlation between task T1 and task T2, because longer connection wires will usually result in higher resistance and capacitance effects, thereby increasing the signal propagation time. In addition, the relationship between wire length and wire delay is not a simple linear relationship, but is jointly influenced by multiple factors such as load capacitance and driving capability. Therefore, the multi-task learning framework (as shown in Figure 2 ) helps to capture this complex non-linear relationship and helps to improve the prediction accuracy of wire length and wire delay at the same time.

[0054] For each task T I , suppose the training data set D I contains n I training samples (i.e. n I graphs), then:

[0055]

[0056] where G I,J is a heterogeneous graph constructed for task T I , containing node and edge feature information; Y I,J is a vector containing the true values of the wire length or wire delay of all wire-related edges in the graph.

[0057] Let φ mtl be a wire length and wire delay collaborative prediction model based on graph neural networks and multi-task learning, and θ mtl be the total trainable parameters of the model, then the multi-task regression task is expressed as follows:

[0058] Y = φ mtl (G, θ mtl )

[0059] where Y = (Y 1 , Y 2 ), I = 1, 2 represents the true value set, G = (G 1 , G 2 ), I = 1,2 denotes the set of graphs. Further, let φ1 and φ2 be the task-specific branches of φ mtl , θ1 and θ2 be the trainable parameters for the corresponding tasks, then the above formula expands to:

[0060]

[0061] where θ mtl = θ1∪θ2. Let the loss function of multi-task regression be L mtl , which is calculated as follows:

[0062]

[0063] where and represent the predicted values of tasks T1 and T2 respectively, L1 and L2 represent the loss functions of the two tasks, represents the joint function, which is used to balance the loss weights of the two tasks. By minimizing the total loss function L mtl , the method described in the embodiment can simultaneously learn efficiently and accurately predict the line length and line delay.

[0064] As shown in Figure 1 , the digital integrated circuit layout post-line length and line delay co-prediction method described in the embodiment comprises the following steps:

[0065] S1, constructing a preliminary heterogeneous graph based on the connection information of the circuit netlist;

[0066] A heterogeneous graph is a special graph structure, and its significant feature is to contain multiple types of nodes and edges, which enables it to model the diversified relationships in complex systems more finely. Therefore, a heterogeneous directed graph G = (V, E c , E n ) is selected to realize the effective representation of circuit design. Wherein, V represents a node set composed of all pins; E c represents a unit edge set, which is used to describe the connection relationship between the pins inside the same unit; E n represents a line edge set, which is used to describe the connection relationship between the pins of different units. As Figure 3 shown, the pins in the circuit are modeled as nodes in the graph (the terms "node" and "pin" are interchangeable in this invention), and according to the types of connections between the pins, different types of edges are used to represent their relationships: unit edges (dashed arrows) represent the connections between pins inside the same component, and line edges (solid arrows) represent the connections between pins of different components.

[0067] Figure 3In the (a) part, the circuit composed of three units U1, U2 and U3 and a wire net Net1 is shown, each unit contains input and output pins, taking unit U1 as an example, U1 / A1 and U1 / A2 are input pins, and U1 / ZN is an output pin, thus the total number of pins of unit U1 is 3. Figure 3 In the (b) part, for the wire edge U1 / ZN-U2 / A2, U1 / ZN is the source pin, i.e. the starting point of the signal, and U2 / A2 is the target pin, which receives the signal from the source pin, and U1, as the unit where the source pin U1 / ZN is located, is called the driving unit. Another wire edge U1 / ZN-U3 / A shares the same source pin U1 / ZN with the wire edge U1 / ZN-U2 / A2, but the target pin is different. In this case, the fan-out number of the source pin U1 / ZN is 2, i.e. it is connected to two pins subsequently, and the two wire edges belong to the same wire net Net1.

[0068] S2, extracting features for wire length and wire delay prediction of the wire edge from the netlist file and the process file;

[0069] In this embodiment, the features for wire length and wire delay prediction of the wire edge include node features and edge features;

[0070] Among them, the edge features for wire length prediction include the driving strength of the source pin unit, the fan-out number of the source pin, the area of the source pin unit, the number of pins of the source pin unit, the area of the target pin unit, and the fan-out number of the target pin unit; the node features for wire delay prediction include the conversion time, the margin, the capacitance of the input pin, and the maximum capacitance of the output pin; and the edge features for wire delay prediction include the wire net capacitance and the wire net resistance.

[0071] The features will be described in detail as follows:

[0072] Driving strength of source pin unit: driving strength is an important indicator to measure the ability of a unit to effectively drive subsequent loads. In digital circuit design, driving strength directly affects the transmission speed and stability of signals. For high fan-out or long wire net cases, it is particularly important to choose a unit with high driving strength, because high driving strength can reduce the time delay caused by excessive load during signal transmission, thereby ensuring that the signal can be reliably transmitted to multiple target pins without affecting performance.

[0073] Fan-out number of source pin: fan-out number directly reflects the number of pins connected to other pins, which is an important parameter for evaluating circuit complexity and load capacity. In actual circuits, a pin with a high fan-out number often means that it needs to drive more loads, which not only increases the length of the wire, but also introduces additional wire delay.

[0074] Source pin cell area, source pin cell pin count, target pin cell area, target pin cell pin count: The larger the area or the more pins a cell has, the more physical space it may need to be allocated when laying out the design. This increased space requirement not only affects the placement of the cell, but can also indirectly cause changes in the length of the wires connected to it.

[0075] Target pin cell fanout count: Similar to the fanout count of a source pin, the fanout count of a target pin's cell also affects the length of the subsequent wire net it drives. When it has a large fanout count, the subsequent wire net it drives can be more complex, and this complexity can affect the length of the current predicted wire net by providing information about neighboring wire nets that the model can capture the interactions and potential impacts from.

[0076] Transition time: Represents the time required for a signal to transition from one logic state (e.g., low) to another (e.g., high). A longer transition time means that the signal changes more slowly, which can result in a larger delay on the rising or falling edge of the signal, directly increasing the total delay of signal propagation.

[0077] Margin: Margin is a key metric in timing analysis, used to measure the time slack of a signal under the design constraints. Margin represents the difference between the actual arrival time of a signal and the expected arrival time. If the margin is positive, it means that the signal can arrive on time within the specified time, meeting the design requirements. If the margin is negative, it indicates a risk of timing violation, which requires further optimization. This feature can reflect the timing pressure of a path and provide global timing information for the model.

[0078] Capacitance (input pin): The capacitance of an input pin significantly increases the load of the cell driving it, which has a significant impact on signal propagation delay. A larger input capacitance can cause a longer charging and discharging time, making the signal change slower and resulting in higher wire delay.

[0079] Maximum capacitance (output pin): The maximum capacitance of an output pin limits the maximum load capacitance it can drive, which is an important parameter for evaluating the driving capability of a cell. In the design process, if a cell is expected to have a large fanout or need to drive a long wire net, it is generally preferred to choose a cell with a higher maximum output pin capacitance to ensure that the signal can be reliably transmitted to all target pins.

[0080] Wire net capacitance, wire net resistance: Wire net capacitance and wire net resistance are the main factors affecting wire delay. Wire net capacitance is mainly derived from the parasitic effects of metal interconnections and the input capacitance of pins, while wire net resistance is determined by the material properties and geometric dimensions of the metal wires. Higher wire net capacitance and resistance will cause the signal to decay faster during transmission, significantly increasing the wire delay.

[0081] S3, construct a line length and line delay collaborative prediction model based on graph neural network and multi-task learning;

[0082] As shown in Figure 4 , the constructed line length and line delay collaborative prediction model based on graph neural network and multi-task learning includes three TransformerConv layers, each of which is provided with a cross-stitch unit, and the last cross-stitch unit is connected to two task branches, each of which includes a line edge embedding generation module and a fully connected layer.

[0083] Among them, the working mechanism of TransformerConv layer includes:

[0084] For each node i in the graph, its input feature representation is where d is the feature dimension, and l represents the index of the current network layer; first, the input feature is linearly transformed by a learnable weight matrix to obtain the query vector key vector and value vector

[0085]

[0086] Among them, the query vector is used to measure the attention degree of node i to other nodes; the key vector is used to match the query vectors of other nodes to calculate the attention weight; the value vector contains the actual information of the node, which is used for weighted summation to update the node feature;

[0087] In order to utilize the information of edge features in the graph, the TransformerConv layer linearly transforms the edge feature by a learnable weight matrix to map it to the same dimension space as the node feature:

[0088]

[0089] Subsequently, the attention weight coefficient α ij between node i and its neighbor node j is calculated according to the above transformation results:

[0090]

[0091] Among them dot product operation q Tk measures the similarity between the query vector and the key vector, while the normalization in the denominator ensures that the sum of the attention weights is 1, and the edge feature The introduction of the edge feature enhances the model's ability to utilize edge feature information.

[0092] Based on the attention weight coefficient α ij , the new feature of the node is obtained by weighted summation of the value vectors of the neighbor nodes:

[0093]

[0094] wherein is a learnable weight matrix used to transform the node's own features; retaining the node's own feature information, and fusing the information of neighbor nodes, and realizing weighted aggregation through attention weights ; the edge feature is added to the aggregation process to enhance the model's ability to express the relationship between nodes.

[0095] A cross-stitch unit is provided after each TransformerConv layer to dynamically interact node features during feature extraction in the line length prediction task T1 and the line delay prediction task T2. In the lth TransformerConv layer, the node feature representations of the two tasks T1 and T2 are and wherein i represents the node index and d is the feature dimension; the cross-stitch unit learns the linear combination weights between tasks to weight and fuse the feature representations of different tasks, thereby generating new feature representations and

[0096]

[0097] wherein α 11 , α 12 , α 21 , and α 22 are attention weight coefficients.

[0098] In the line edge embedding generation module of each task branch, the embedding representations of the source node and the target node are fused into a new embedding representation, i.e., the line edge embedding, through concatenation operation; through this kind of concatenation operation, the complete information of the source node and the target node is retained, and the relationship between the two is captured.

[0099] Each task branch processes the embedding representation through a fully connected layer, which consists of three consecutive hidden layers. Each layer uses a nonlinear activation function ReLU to enhance the model's expression ability, and finally outputs the prediction result.

[0100] For the constructed line length and line delay collaborative prediction model based on graph neural network and multi-task learning, the line length prediction task T1 and the line delay prediction task T2 adopt mean square error as a single task loss function, and are defined as follows:

[0101]

[0102] Wherein, N represents the total number of line edges, y wirelength,i and respectively represent the real line length value and the predicted value of the i-th line edge, y netdelay,i and respectively represent the real line delay value and the predicted value of the i-th line edge.

[0103] In order to effectively balance the optimization objectives of the two tasks in the multi-task learning framework, the geometric mean loss is used as the joint loss function The definition is as follows:

[0104] S4, the constructed line length and line delay collaborative prediction model based on graph neural network and multi-task learning is trained.

[0105] S5, the extracted feature data is input into the trained line length and line delay collaborative prediction model based on graph neural network and multi-task learning, and finally the prediction results of line length and line delay are obtained.

[0106] In order to fully verify the effectiveness of the method proposed in the present application, a plurality of benchmark data sets are selected as experimental data sources, and these data sets include ISCAS'89, ITC'99, ANUBIS and IWLS'05. On this basis, the original data is screened, and the small-scale design is removed, and only those more representative and challenging circuit designs are retained. The purpose of this strategy is to ensure that the experimental data can better reflect the real characteristics of complex circuits, so as to improve the practical significance and reference value of the experimental results. After screening, 20 circuit designs of different scales are finally obtained for experimental analysis, and the detailed information of these designs is shown in Table 1, wherein the 20 designs are randomly divided into 12 for training and 8 for testing. All designs are based on 45nm NanGate library, and the logic synthesis and layout process are completed through EDA tools. After layout, the line length and line delay between pins in each design are extracted as training labels through EDA tools. Among them, the line delay is the maximum value of the rise delay and the fall delay. The features and labels are normalized to accelerate the model convergence.

[0107] Table 1 Detailed information of data set division and design

[0108]

[0109] In the model parameter setting, the hidden channel number of the TransformerConv layer is set to 64. The design of the fully connected layer is as follows: the input dimension of the first fully connected layer is 64x2 (i.e. the splicing result of the source node and target node embedding), and the output dimension is 64; the input dimension of the second fully connected layer is 64, and the output dimension is 32; the input dimension of the third fully connected layer is 32, and the output dimension is 1, which is finally used for predicting the regression value of the edge. Considering the large difference in the scale of the graph data, only one graph is included in each batch during the training process, and the training data is randomly shuffled during the training process to avoid the model from overfitting to the specific order of the data. In addition, an early stopping mechanism is introduced during the training process. Since multi-task learning needs to repeatedly weigh the accuracy between different tasks, the model may need more training rounds to reach full convergence. Therefore, the patience value is set to 30, that is, when the performance of the validation set does not appear to improve for 30 consecutive rounds, the training process will be terminated in advance. In the selection of the optimizer, the Adam optimizer is adopted, and the initial learning rate is set to 0.005 and the weight decay is set to 0.0001. This configuration aims to balance the convergence speed and regularization effect of the model, so as to effectively prevent overfitting and improve the generalization ability.

[0110] In the experiment, the methods proposed in two papers (Xie Z, Liang R, Xu X, et al. Preplacement netlength and timing estimation by customized graph neural network [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, 41(11): 4667-4680.) and (Guo Z, Liu M, Gu J, et al. A timing engine inspired graph neural network model for pre-routing slack prediction [C] / / Proceedings of the 59th ACM / IEEE Design Automation Conference. 2022: 1207-1212.) are used as baseline models for performance comparison with the model proposed in the present application.

[0111] Xie et al. proposed two models Net 2f and Time fRespectively used for predicting line length and line latency. Net 2f is a model based on Graph Attention Network (GAT). The core idea is to construct an undirected graph by regarding lines as nodes, and use GAT to extract high-level features of nodes to achieve line length prediction. In the specific implementation, Net 2f uses 3 layers of GAT for feature extraction, each layer contains 2 attention heads, and the hidden layer dimension is 64. In addition, Batch Normalization is used after each layer of GAT to stabilize the training process. Finally, the node features of all GAT layers are concatenated to form the final node embedding representation, and a 2-layer fully connected layer is used to output the line length prediction value. The input dimension of the first fully connected layer is 3x64x2, corresponding to the dimension of the node embedding, and the output dimension is 64. The input dimension of the second fully connected layer is 64, and the output dimension is 1. The optimizer uses Stochastic Gradient Descent (SGD) with a learning rate of 0.005, a momentum factor of 0.9, and a weight decay of 0.0001. Time f is a model based on random forest, whose input features include not only the line length predicted by Net 2f , but also the predicted line length features and other line latency related features. The specific configuration of the random forest model is that the number of trees is 80 and the maximum tree depth is 12.

[0112] On the other hand, the model implementation of Guo et al. is based on their open source code, the most core part of which is their custom graph convolution layer (NetConv). The NetConv layer captures complex relationships in line network structure through two custom operations (graph broadcasting and graph reduction). Graph broadcasting allows information to flow from source nodes to target nodes, which operates by concatenating the features of source nodes, target nodes and edges, and generating new features of target nodes through a fully connected layer; graph reduction makes information flow from target nodes back to source nodes, which is implemented through two channels, sum channel (summing the features of all target nodes) and max channel (taking the maximum value of all target nodes' features). In the experiment, a multi-task learning model for line length prediction and line latency prediction is implemented based on NetConv, each task stacks three layers of NetConv, and a cross-stitch unit is inserted between each layer to realize multi-task learning. Finally, each task outputs the line length prediction result and the line latency prediction result through a fully connected layer respectively. The model is trained using the Adam optimizer with a learning rate of 0.005 and a weight decay of 0.0001.

[0113] The experimental environment is a high-performance workstation, and the hardware configuration includes Intel(R) Xeon(R) Platinum 8368 CPU @ 2.40 GHz processor and NVIDIA A100 80GB PCIe GPU. The software environment is based on Ubuntu 20.04 LTS operating system, and Python 3.9.21 is used as the programming language. In the experiment, the construction of the deep learning model uses the PyTorchGeometric 2.6.1 framework, and the implementation of the traditional machine learning algorithm is based on Scikit-learn 1.6.1.

[0114] 1. Evaluation index

[0115] The Pearson correlation coefficient R and the determination coefficient R 2 , commonly used in many research works, are selected to evaluate the performance of the model.

[0116] The Pearson correlation coefficient R is used to measure the linear correlation between the predicted value and the true value, and its value range is [-1, 1]. When R is close to 1, it indicates that the predicted value and the true value have a high positive correlation; when R is close to -1, it indicates that the two have a high negative correlation; when R is close to 0, it indicates that there is almost no linear relationship between the two. The formula is defined as:

[0117]

[0118] where y i and represent the true value and the predicted value of the i-th sample, respectively, and are the mean values of the true value and the predicted value, respectively.

[0119] The determination coefficient R 2 is used to measure the explanatory power of the model to the change of the target variable, and its value range is (-∞, 1]. When R 2 is close to 1, it indicates that the model can well capture the trend of the change of the target variable; when R 2 is close to 0 or negative, it indicates that the fitting effect of the model is poor. The formula is defined as:

[0120] where the numerator represents the sum of squared errors between the predicted value and the true value of the model, reflecting the part that the model fails to explain; the denominator represents the sum of squared deviations between the true value and its mean value, reflecting the overall fluctuation degree of the target variable.

[0121] 2. Experimental results

[0122] Table 2 and Table 3 respectively show the prediction performance comparison of different methods, in which STL-Ours represents the method proposed in the present application independently performing two prediction tasks, i.e., removing the shared strategy of multi-task learning, except for two baseline models (MTL-Guo and Net 2f -Time f ).

[0123] In the comparison between single-task learning (STL-Ours) and multi-task learning (MTL-Ours), it can be found that the performances of the two methods on the online length prediction are almost the same. However, in terms of online time delay prediction, the multi-task learning model (MTL-Ours) exhibits higher correlation coefficient R and determination coefficient R 2 . This result shows that the multi-task learning framework can significantly improve the prediction ability of the online time delay without affecting the accuracy of the online length prediction, fully embodying the effectiveness and advantages of multi-task learning.

[0124] Table 2 Comparison of prediction performance of different methods on the test set (R)

[0125]

[0126]

[0127] Table 3 Comparison of prediction performance of different methods on the test set (R 2 )

[0128]

[0129] When comparing the method proposed in the present application (MTL-Ours) with the baseline models (MTL-Guo and Net 2f -Time f ), it can be found that the overall performance of the present application method on all test designs is significantly better than the two baseline models, which shows that the method has stronger generalization ability and better adaptability. In the online length prediction task, the correlation coefficient R of MTL-Ours is 12% and 1% higher than that of the baseline models Net 2f and MTL-Guo, respectively, and the determination coefficient R 2 is 26.3% and 21.2% higher, respectively. In the online time delay prediction task, the correlation coefficient R of MTL-Ours is 4.7% and 4.8% higher than that of the baseline models Time f and MTL-Guo, respectively, and the determination coefficient R 2 is 10.4% and 15.1% higher, respectively. In addition, it needs to be pointed out that the baseline model Time fThe performance on the training set is significantly better than that on the test set, showing a significant overfitting phenomenon, which limits its generalization ability. In contrast, the stability and superiority of the method of the present application on the test set further highlights its potential in practical applications.

[0130] In addition, Table 4 also records the time used for training and inference of each method, and the results show that by introducing a multi-task learning framework to integrate the line length and line delay prediction process, the training and inference time cost can be reduced, and the prediction efficiency can be improved.

[0131] Table 4 Training time and inference time of different methods

[0132]

[0133] The above-described embodiments are only the preferred embodiments of the present application, and do not limit the scope of the present application. Any changes made in shape or principle according to the present application should be covered within the scope of protection of the present application.

Claims

1. A method for wire length and wire delay co-prediction of digital integrated circuit layout, characterized in that, The method comprises the following steps: constructing a preliminary heterogeneous graph based on connection information of a circuit netlist; extracting features for wire length and wire delay prediction from a netlist file and a process file; adding the extracted features to corresponding nodes and edges of the preliminary heterogeneous graph to obtain a final heterogeneous graph with connection relationships and features; constructing a wire length and wire delay collaborative prediction model based on a graph neural network and multi-task learning; training the constructed wire length and wire delay collaborative prediction model based on the graph neural network and multi-task learning; inputting the final heterogeneous graph into the trained wire length and wire delay collaborative prediction model based on the graph neural network and multi-task learning to finally obtain prediction results of wire length and wire delay; the constructed wire length and wire delay collaborative prediction model based on the graph neural network and multi-task learning comprises three TransformerConv layers, each of which is provided with a cross-stitch unit, and the last cross-stitch unit is connected to two task branches, each of which comprises a wire edge embedding generation module and a fully connected layer; the working mechanism of the TransformerConv layer comprises: For each node i in the figure, its input feature representation is denoted as where d is the feature dimension, and l represents the index of the current network layer; first, the input feature is linearly transformed by a learnable weight matrix to obtain the query vector the key vector and the value vector wherein the query vector is used to measure the degree of attention of node i to other nodes; the key vector is used to match the query vector of other nodes to calculate the attention weight; the value vector contains the actual information of the node, which is used for weighted summation to update the node features; To utilize the information of edge features in the graph, the TransformerConv layer applies a linear transformation to the edge features by a learnable weight matrix The edge features are linearly transformed to be mapped into the same dimensional space as the node features: Subsequently, the attention weight coefficient a of the node i and its neighbor node j is calculated according to the above transformation result ij : wherein Dot product operation q T k measures the similarity between the query vector and the key vector, while the normalization in the denominator ensures that the sum of the attention weights is 1, edge feature The introduction of the edge feature enhances the model's ability to utilize edge feature information; Based on the attention weight coefficient α ij , the new features of the nodes By weighted sum of the value vectors of the neighbor nodes: wherein is a learnable weight matrix for transforming the node's own features; retaining the node's own feature information, while fusing the information of neighbor nodes through attention weights to achieve weighted aggregation; edge features are added to the aggregation process to enhance the model's ability to express the relationship between nodes.

2. The method of claim 1, wherein the method is characterized by: the extracted features from the netlist file and the process file include node features and edge features; the edge features for wire length prediction include driving strength of a source pin unit, source pin fan-out number, source pin unit area, source pin unit pin number, target pin unit area, and target pin unit fan-out number; the node features for wire delay prediction include conversion time, margin, input pin capacitance, and output pin maximum capacitance; the edge features for wire delay prediction include wire net capacitance and wire net resistance.

3. The method of claim 1, wherein the method further comprises: determining a delay of each of the plurality of wires; and determining a delay of each of the plurality of wires based on the delay of each of the plurality of wires and the length of each of the plurality of wires. Each layer of the TransformerConv is followed by a cross-stitch unit to dynamically interact node features in the feature extraction process of the line length prediction task T1 and the line delay prediction task T2. In the l-th layer of the TransformerConv, the node feature representations of the two tasks T1 and T2 are and where i represents the node index, and d is the feature dimension; the cross-stitch unit generates a new feature representation by learning the linear combination weight between tasks to weight and fuse the feature representations of different tasks and wherein α 11 , α 12 , α 21 , α 22 are attention weight coefficients.

4. The method of claim 1 or 3, wherein the method is characterized by: In the wire edge embedding generation module of each task branch, the embedding representations of the source node and the target node are fused into a new embedding representation, i.e., a wire edge embedding, through a splicing operation; the splicing operation retains the complete information of the source node and the target node and captures the relationship between them; each task branch processes the embedding representation through a fully connected layer, which comprises three consecutive hidden layers; each layer adopts a nonlinear activation function ReLU to enhance the expression ability of the model and finally outputs a prediction result.

5. The method of claim 4, wherein the method further comprises: determining a delay of each of the plurality of wires; and determining a delay of each of the plurality of wires based on the delay of each of the plurality of wires and the length of each of the plurality of wires. For the constructed wire length and wire delay collaborative prediction model based on the graph neural network and multi-task learning, the mean square error is used as the single-task loss function for the wire length prediction task T1 and the wire delay prediction task T2, and is defined as follows: wherein N represents the total number of line edges, y wirelength,i and respectively represent the real line length value and the predicted value of the i-th line edge, y netdelay,i and respectively represent the real line delay value and the predicted value of the i-th line edge; In order to effectively balance the optimization objectives of the two tasks in the multi-task learning framework, a geometric mean loss is adopted as a joint loss function It is defined as follows:

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