Gate signal masking circuit, gate driver, display device, and electronic device

Abstract

A gate signal masking circuit, a gate driver, a display device, and an electronic device are provided. The gate signal masking circuit includes a first switching element, a second switching element, a third switching element, a fourth switching element, and a fifth switching element, the first switching element including a control electrode connected to a masking node, a first electrode connected to a first node, and a second electrode connected to a third node, the second switching element includes a control electrode connected to a second node, a first electrode receiving a masking signal, and a second electrode connected to a fourth node, and the third switching element includes a control electrode receiving a first signal, a first electrode connected to the fourth node, and a second electrode connected to a masking node, the fourth switching element includes a control electrode receiving a second signal, a first electrode connected to the mask node, and a second electrode connected to a fifth node. The fifth switching element includes a control electrode connected to the second node, an electrode connected to the fifth node, and another electrode receiving power.

Description

Technical Field

[0001] Embodiments of the present invention relate to a gate signal masking circuit, a gate driver including the gate signal masking circuit, a display device including the gate driver, and an electronic device including the gate driver. More specifically, embodiments of the present invention relate to a gate signal masking circuit with reduced power consumption, a gate driver including the gate signal masking circuit, a display device including the gate driver, and an electronic device including the gate driver. Background Art

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel may include a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver may include a gate driver, a data driver, an emission driver, and a drive controller. The gate driver outputs a gate signal to the gate line. The data driver outputs a data voltage to the data line. The emission driver outputs an emission signal to the emission line. The drive controller controls the gate driver, the data driver, and the emission driver.

[0003] When the image displayed on the display panel is a static image or the display panel operates in a screen-off mode, the driving frequency of the display panel may be reduced to reduce power consumption. Summary of the invention

[0004] When part of the image displayed on the display panel is a static image and part of the image displayed on the display panel is a moving image, it may be desirable to reduce the driving frequency of the portion of the display panel corresponding to the static image to further reduce power consumption.

[0005] However, a stage of a gate driver generally receives an output of a previous stage as a carry signal to output a gate signal, so that it is not possible to reduce the driving frequency of only a portion of the display panel corresponding to a static image.

[0006] Embodiments of the present invention provide a gate signal masking circuit that enables multiplexing of a driving frequency to reduce power consumption of a display device.

[0007] An embodiment of the present invention also provides a gate driver including a gate signal masking circuit.

[0008] An embodiment of the present invention also provides a display device including a gate driver.

[0009] An embodiment of the present invention also provides an electronic device including a gate driver.

[0010] In an embodiment of the gate signal masking circuit of the present invention, the gate signal masking circuit includes a first switching element, a second switching element, a third switching element, a fourth switching element and a fifth switching element. In such an embodiment, the first switching element includes a control electrode connected to a masking control node, a first electrode connected to a first control node and a second electrode connected to a third control node. In such an embodiment, the second switching element includes a control electrode connected to a second control node, a first electrode receiving a masking power signal and a second electrode connected to a first intermediate node. In such an embodiment, the third switching element includes a control electrode receiving a first enable signal, a first electrode connected to a first intermediate node and a second electrode connected to a masking control node. In such an embodiment, the fourth switching element includes a control electrode receiving a second enable signal, a first electrode connected to a masking control node and a second electrode connected to a second intermediate node. In such an embodiment, the fifth switching element includes a control electrode connected to a second control node, a first electrode connected to a second intermediate node and a second electrode receiving a second low power voltage.

[0011] In an embodiment, the gate signal masking circuit may further include a sixth switching element, a seventh switching element and an eighth switching element, the sixth switching element including a control electrode connected to the third control node, a first electrode receiving a first clock signal and a second electrode connected to the gate output node, the seventh switching element including a control electrode connected to the second control node, a first electrode connected to the gate output node and a second electrode receiving a low power voltage, and the eighth switching element including a control electrode connected to the second control node, a first electrode receiving the first clock signal and a second electrode connected to the third control node.

[0012] In an embodiment, the second low power voltage may be less than the low power voltage.

[0013] In an embodiment, the gate signal masking circuit may also include a first masking capacitor and a second masking capacitor, the first masking capacitor including a first electrode receiving the first clock signal and a second electrode connected to a third control node, and the second masking capacitor including a first electrode connected to a masking control node and a second electrode receiving a low power voltage.

[0014] In an embodiment, the masking power signal may be a high power voltage that is a direct current (DC) voltage.

[0015] In an embodiment, a high level of the first enable signal may be substantially the same as a high level of the second enable signal. A low level of the first enable signal may be different from a low level of the second enable signal.

[0016] In an embodiment, the high level of the first enable signal may be a high power voltage, and the low level of the first enable signal may be a low power voltage greater than the second low power voltage. In such an embodiment, the high level of the second enable signal may be a high power voltage, and the low level of the second enable signal may be a second low power voltage.

[0017] In an embodiment, the high level of the first enable signal may be a high power voltage, and the low level of the first enable signal may be a low power voltage greater than the second low power voltage. In such an embodiment, the high level of the second enable signal may be a high power voltage, and the low level of the second enable signal may be a third low power voltage different from the low power voltage and the second low power voltage.

[0018] In an embodiment, the high level of the first enable signal may be a high power voltage, and the low level of the first enable signal may be a second low power voltage. The high level of the second enable signal may be a high power voltage, and the low level of the second enable signal may be a second low power voltage.

[0019] In an embodiment, the high level of the first enable signal may be a high power voltage, and the low level of the first enable signal may be a third low power voltage different from the second low power voltage. In such an embodiment, the high level of the second enable signal may be a high power voltage, and the low level of the second enable signal may be a third low power voltage.

[0020] In an embodiment, the first switching element may further comprise an additional control electrode connected to the masking control node.

[0021] In an embodiment, the fifth switching element may further include an additional control electrode connected to the second control node.

[0022] In an embodiment, the mask power signal may be a clock signal having a high level when the first enable signal changes from an active level to an inactive level and when the first enable signal changes from an inactive level to an active level.

[0023] In an embodiment, when the first enable signal has a non-active level in all periods in which the signal at the second control node has an active level, the gate signal masking circuit may output the gate pulse.

[0024] In an embodiment, when the first enable signal has a valid level in all periods in which the signal at the second control node has a valid level, the gate signal masking circuit may not output the gate pulse.

[0025] In an embodiment, when the first enable signal changes from an inactive level to an active level during a period in which a signal at the second control node has an active level, the gate signal masking circuit may output a gate pulse.

[0026] In an embodiment, when the first enable signal changes from the active level to the inactive level during a period in which the signal at the second control node has the active level, the gate signal masking circuit may not output the gate pulse.

[0027] In an embodiment of the gate driver according to the present invention, the gate driver includes a carry generator and a gate signal masking circuit. In such an embodiment, the carry generator generates a carry signal based on a previous carry signal, a first clock signal, a second clock signal and a low power voltage. In such an embodiment, the gate signal masking circuit is connected to the carry generator. In such an embodiment, the carry generator includes a pull-up switch element and a pull-down switch element, the pull-up switch element pulls up the carry signal in response to a signal of a first control node, and the pull-down switch element pulls down the carry signal in response to a signal of a second control node. In such an embodiment, the gate signal masking circuit outputs a gate pulse or does not output a gate pulse based on a signal of a second control node, a first enable signal and a second enable signal.

[0028] In an embodiment, the gate signal masking circuit may include a first switching element, a second switching element, a third switching element, a fourth switching element and a fifth switching element, the first switching element including a control electrode connected to a masking control node, a first electrode connected to the first control node and a second electrode connected to the third control node, the second switching element including a control electrode connected to the second control node, a first electrode receiving a masking power signal and a second electrode connected to the first intermediate node, the third switching element including a control electrode receiving a first enable signal, a first electrode connected to the first intermediate node and a second electrode connected to the masking control node, the fourth switching element including a control electrode receiving a second enable signal, a first electrode connected to the masking control node and a second electrode connected to the second intermediate node, and the fifth switching element including a control electrode connected to the second control node, a first electrode connected to the second intermediate node and a second electrode receiving a second low power voltage.

[0029] In an embodiment, the carry generator may include a first gate switching element, a second gate switching element, a third gate switching element, a fourth gate switching element, a fifth gate switching element, a sixth gate switching element, a seventh gate switching element, an eighth gate switching element, a ninth gate switching element, a tenth gate switching element, an eleventh gate switching element, and a fourteenth gate switching element, the first gate switching element including a control electrode receiving a first clock signal, a first electrode receiving a previous carry signal, and a second electrode connected to a first node, the second gate switching element including a control electrode connected to a second control node, a first electrode receiving a second clock signal, and a second electrode connected to a fifth node, the third gate switching element including a control electrode receiving the first clock signal, a first electrode connected to the second node, and a second electrode receiving a low power voltage, the fourth gate switching element including a control electrode receiving a low power voltage, a first electrode connected to the second node, and a second electrode connected to the third node, and the fifth gate switching element including a control electrode connected to the second control node, a first electrode receiving the first clock signal, and a second electrode connected to the second node. The second electrode, the sixth gate switching element includes a control electrode connected to the third node, a first electrode receiving the second clock signal, and a second electrode connected to the third intermediate node, the seventh gate switching element includes a control electrode connected to the third node, a first electrode connected to the fourth node, and a second electrode connected to the third intermediate node, the eighth gate switching element includes a control electrode receiving the second clock signal, a first electrode connected to the fourth node, and a second electrode connected to the first control node, the ninth gate switching element includes a control electrode connected to the first control node, a first electrode receiving the first clock signal, and a second electrode connected to the carry output node, the tenth gate switching element includes a control electrode connected to the second control node, a first electrode connected to the carry output node, and a second electrode receiving a low power voltage, the eleventh gate switching element includes a control electrode receiving a low power voltage, a first electrode connected to the first node, and a second electrode connected to the second control node, the fourteenth gate switching element includes a control electrode connected to the second control node, a first electrode receiving the first clock signal, and a second electrode connected to the first control node. In such an embodiment, the ninth gate switching element may be a pull-up switching element, and the tenth gate switching element may be a pull-down switching element.

[0030] In an embodiment, the carry generator may further include a twelfth gate switching element and a thirteenth gate switching element, the twelfth gate switching element including a control electrode receiving a reset signal, a first electrode receiving a first clock signal, and a second electrode connected to the first node, and the thirteenth gate switching element including a control electrode receiving a reset signal, a first electrode connected to the first control node, and a second electrode receiving a low power voltage.

[0031] In an embodiment, the carry generator may further include a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, the first capacitor including a first electrode receiving the first clock signal and a second electrode connected to the first control node, the second capacitor including a first electrode connected to the third node and a second electrode connected to the fourth node, the third capacitor including a first electrode connected to the fifth node and a second electrode connected to the second control node, and the fourth capacitor including a first electrode connected to the carry output node and a second electrode receiving a low power voltage.

[0032] In an embodiment, the control electrode of the tenth gate switching element and the control electrode of the fourteenth gate switching element may be connected to the control electrode of the seventh switching element and the control electrode of the eighth switching element.

[0033] In an embodiment, the control electrode of the ninth gate switching element may be connected to the first electrode of the first switching element.

[0034] In an embodiment of a display device according to the present invention, the display device includes a display panel, a gate driver and a data driver. The display panel includes pixels. In such an embodiment, the gate driver outputs a gate signal to the pixel. In such an embodiment, the data driver outputs a data voltage to the pixel. In such an embodiment, the gate driver includes a carry generator and a gate signal masking circuit, the carry generator generates a carry signal based on a previous carry signal, a first clock signal, a second clock signal and a low power voltage, and the gate signal masking circuit is connected to the carry generator. In such an embodiment, the carry generator includes a pull-up switch element and a pull-down switch element, the pull-up switch element pulls up the carry signal in response to a signal of a first control node, and the pull-down switch element pulls down the carry signal in response to a signal of a second control node. In such an embodiment, the gate signal masking circuit outputs a gate pulse or does not output a gate pulse based on a signal of a second control node, a first enable signal and a second enable signal.

[0035] In an embodiment of an electronic device according to the present invention, the electronic device includes a display panel, a gate driver, a data driver, a drive controller and a processor. The display panel includes pixels. In such an embodiment, the gate driver outputs a gate signal to the pixel. In such an embodiment, the data driver outputs a data voltage to the pixel. In such an embodiment, the drive controller controls the gate driver and the data driver. In such an embodiment, the processor outputs input image data and an input control signal to the drive controller. In such an embodiment, the gate driver includes a carry generator and a gate signal masking circuit, the carry generator generates a carry signal based on a previous carry signal, a first clock signal, a second clock signal and a low power voltage, and the gate signal masking circuit is connected to the carry generator. In such an embodiment, the carry generator includes a pull-up switch element and a pull-down switch element, the pull-up switch element pulls up the carry signal in response to a signal of a first control node, and the pull-down switch element pulls down the carry signal in response to a signal of a second control node. In such an embodiment, the gate signal masking circuit outputs a gate pulse or does not output a gate pulse based on a signal of a second control node, a first enable signal and a second enable signal.

[0036] According to embodiments of the gate signal masking circuit, the gate driver, the display device, and the electronic device, the output of the gate signal can be controlled based on a signal of a second control node of a pull-down switching element applied to a pull-down carry signal, a first enable signal, and a second enable signal, so that multi-way frequency division of a driving frequency can be effectively performed.

[0037] In such an embodiment, the power consumption of the display device can be effectively reduced by multi-way frequency division of the driving frequency.

[0038] In such an embodiment, the signal of the masking control node may be determined based on the signal of the second control node, so that the reliability of the gate signal masking circuit is improved by reducing the low level of the signal of the masking control node.

[0039] In such an embodiment, a second low power voltage lower than the low power voltage is applied to the second electrode of the fifth switching element so that the reliability of the gate signal masking circuit is improved by reducing the low level of the signal of the masking control node.

[0040] In such an embodiment, the first switching element may further include an additional control electrode connected to the masking control node, so that the reliability of the gate signal masking circuit is improved by reducing the low level of the signal of the third control node.

[0041] In such an embodiment, the fifth switching element may further include an additional control electrode connected to the second control node, so that the reliability of the gate signal masking circuit is improved by reducing the low level of the signal of the masking control node. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and other features of the embodiments of the present disclosure will become more apparent by describing in detail the embodiments of the present invention with reference to the accompanying drawings, in which:

[0043] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention;

[0044] Figure 2 It is shown Figure 1 A circuit diagram of an example of a pixel of a display panel;

[0045] Figure 3 It is shown Figure 1 A circuit diagram of an example of a pixel of a display panel;

[0046] Figure 4 It is shown Figure 1 A circuit diagram of an example of a pixel of a display panel;

[0047] Figure 5 It is shown Figure 1 A schematic diagram of an embodiment of a gate driver;

[0048] Figure 6 It shows that according to Figure 1 The driving frequency of the display panel is applied to the Figure 1 A schematic diagram of a first enable signal and a second enable signal of a gate driver;

[0049] Figure 7 It is shown Figure 1 A circuit diagram of an embodiment of a carry generator and a gate signal masking circuit of a gate driver;

[0050] Figure 8 It is shown Figure 7 A signal timing diagram of an input signal, a node signal and an output signal of a carry generator;

[0051] Fig. 9 It is shown Figure 7 The carry generator is Figure 8 A circuit diagram of the operation at a first point in time;

[0052] Fig.10 It is shown Figure 7 The carry generator is Figure 8 A circuit diagram of the operation at a second point in time;

[0053] Fig.11 It is shown Figure 7 The carry generator is Figure 8 A circuit diagram of the operation at a third time point of FIG.

[0054] Fig.12 It is shown Figure 7 The carry generator is Figure 8 A circuit diagram of the operation at a fourth time point of FIG.

[0055] Fig.13 It is shown Figure 7 The carry generator is Figure 8 A circuit diagram of the operation at a fifth time point of FIG.

[0056] Fig.14 It is shown Figure 7 A signal timing diagram of a signal of a masked control node and a signal of a second control node of a gate signal masking circuit;

[0057] Fig.15 It shows that according to Figure 7 a table of states of signals of a masking control node of an input signal of a gate signal masking circuit;

[0058] Fig.16 It shows that according to Figure 7 A signal timing diagram of an input signal of a gate signal masking circuit and an output signal of a gate signal masking circuit;

[0059] Fig.17 is shown in the first case Figure 7 A signal timing diagram of input signals, node signals and output signals of a carry generator and a gate signal masking circuit;

[0060] Fig.18 is shown in the second case Figure 7 A signal timing diagram of input signals, node signals and output signals of a carry generator and a gate signal masking circuit;

[0061] Fig.19 It is shown that in the third case Figure 7 A signal timing diagram of input signals, node signals and output signals of a carry generator and a gate signal masking circuit;

[0062] Fig. 20 It is shown that in the fourth case Figure 7 A signal timing diagram of input signals, node signals and output signals of a carry generator and a gate signal masking circuit;

[0063] Fig.21A is shown applied to Figure 7 A signal timing diagram showing an example of a waveform of a first enable signal and a waveform of a second enable signal of a gate signal masking circuit;

[0064] Fig.21B is shown applied to Figure 7A signal timing diagram showing an example of a waveform of a first enable signal and a waveform of a second enable signal of a gate signal masking circuit;

[0065] Fig. 21C is shown applied to Figure 7 A signal timing diagram showing an example of a waveform of a first enable signal and a waveform of a second enable signal of a gate signal masking circuit;

[0066] Fig.21D is shown applied to Figure 7 A signal timing diagram showing an example of a waveform of a first enable signal and a waveform of a second enable signal of a gate signal masking circuit;

[0067] Fig. 22 It is shown Figure 7 A signal timing diagram of a carry signal of a carry generator and a signal of a second control node;

[0068] Fig.23 is a signal timing diagram showing a signal of a mask control node of a gate signal masking circuit according to a comparative embodiment and an embodiment of the present invention;

[0069] Fig.24 is a circuit diagram showing a carry generator and a gate signal masking circuit of a gate driver according to an embodiment of the present invention;

[0070] Fig.25 is a circuit diagram showing a carry generator and a gate signal masking circuit of a gate driver according to an embodiment of the present invention;

[0071] Fig.26 is a circuit diagram showing a carry generator and a gate signal masking circuit of a gate driver according to an embodiment of the present invention;

[0072] Fig. 27 is a circuit diagram showing a carry generator and a gate signal masking circuit of a gate driver according to an embodiment of the present invention;

[0073] Fig.28 It is shown Fig. 27 A signal timing diagram of a signal of a masked control node and a signal of a second control node of a gate signal masking circuit;

[0074] Fig.29 is a block diagram showing an electronic device according to an embodiment of the present invention; and

[0075] Fig.30 It shows that Fig.29 FIG. 1 is a diagram of an embodiment in which the electronic device is implemented as a smart phone. DETAILED DESCRIPTION

[0076] The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the specification, similar reference numerals refer to similar elements.

[0077] It will be understood that when an element is referred to as being “on” another element, the element can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0078] It will be understood that, although the terms "first", "second", "third", etc., may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the "first element", "first component", "first region", "first layer" or "first part" discussed below can be referred to as the second element, second component, second region, second layer or second part without departing from the teachings herein.

[0079] The terms used herein are only for the purpose of describing a specific embodiment, and are not intended to be limited. Unless the context clearly indicates otherwise, "a", "an", "the" and "at least one" as used herein do not represent the limitation of quantity, and are intended to include both the singular and the plural. Therefore, the element mentioned in a claim that subsequently mentions "the" element includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one (at least one)" will not be interpreted as limiting "a" or "an". "Or (or)" means "and / or (and / or)". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms “comprise” and / or “comprising” or “include” and / or “including” are used in the present specification, it specifies the presence of stated features, regions, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or clusters thereof.

[0080] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, relative terms are intended to also cover different orientations of the device. For example, if the device in one of the multiple figures is turned over, the element described as being on the "lower" side of the other elements will then be oriented on the "upper" side of the other elements. Therefore, the term "lower" can cover both the "lower" and "upper" orientations depending on the specific orientation of the figure. Similarly, if the device in one of the multiple figures is turned over, the element described as being "below" or "below" the other elements will then be oriented "above" the other elements. Therefore, the term "below" or "below" can cover both the orientations of the upper and lower sides.

[0081] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0082] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0083] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present invention.

[0084] Reference Figure 1 , an embodiment of a display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0085] The display panel 100 has a display area displaying an image and a peripheral area adjacent to the display area.

[0086] The display panel 100 includes a plurality of gate lines GWL, GCL, GIL, and GBL, a plurality of data lines DL, a plurality of emission lines EML, and a plurality of pixels electrically connected to the gate lines GWL, GCL, GIL, and GBL, the data lines DL, and the emission lines EML. The gate lines GWL, GCL, GIL, and GBL may extend in a first direction D1, the data lines DL may extend in a second direction D2 crossing the first direction D1, and the emission lines EML may extend in the first direction D1.

[0087] The driving controller 200 receives input image data IMG and input control signal CONT from an external device (e.g., a processor). In an embodiment, for example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. In another embodiment, for example, the input image data IMG may include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0088] The driving controller 200 generates a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0089] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0090] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0091] The driving controller 200 generates a data signal DATA based on the input image data IMG. The driving controller 200 outputs the data signal DATA to the data driver 500.

[0092] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400 .

[0093] The driving controller 200 generates a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and outputs the fourth control signal CONT4 to the emission driver 600 .

[0094] The gate driver 300 generates gate signals driving the gate lines GWL, GCL, GIL, and GBL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may sequentially output the gate signals to the gate lines GWL, GCL, GIL, and GBL.

[0095] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA.

[0096] In an embodiment, the gamma reference voltage generator 400 may be disposed in the driving controller 200 or in the data driver 500 .

[0097] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200 and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into an analog type data voltage using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage to the data line DL.

[0098] The emission driver 600 generates an emission signal to drive the emission lines EML in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signal to the emission lines EML.

[0099] Despite Figure 1 100 is arranged at a first side of the display panel 100 and the emission driver 600 is arranged at a second side of the display panel 100 opposite to the first side, but the present invention may not be limited thereto. In another embodiment, for example, both the gate driver 300 and the emission driver 600 may be arranged at the first side of the display panel 100. In another embodiment, for example, the gate driver 300 and the emission driver 600 may be arranged at both sides of the display panel 100. In another embodiment, for example, the gate driver 300 and the emission driver 600 may be formed integrally.

[0100] Figure 2 It is shown Figure 1 FIG. 1 is a circuit diagram of an example of a pixel of the display panel 100 .

[0101] Reference Figure 1 and Figure 2 , an embodiment of the display panel 100 includes a plurality of pixels. Each of the pixels includes a light emitting element EE.

[0102] The pixel receives a data write gate signal (e.g., a data write gate signal GW[n]), a compensation gate signal (e.g., a compensation gate signal GC[n]), a data initialization gate signal (e.g., a data initialization gate signal GI[n]), a light emitting element initialization gate signal (e.g., a light emitting element initialization gate signal GB[n]), a data voltage VDATA, and an emission signal (e.g., an emission signal EM[n]), and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0103] In an embodiment, a pixel may include a first type of pixel switching element and a second type of pixel switching element different from the first type. In an embodiment, for example, the first type of pixel switching element may be a polysilicon thin film transistor. In an embodiment, for example, the first type of pixel switching element may be a low temperature polysilicon (LTPS) thin film transistor. In an embodiment, for example, the second type of pixel switching element may be an oxide thin film transistor. In an embodiment, for example, the first type of pixel switching element may be a P-type transistor, and the second type of pixel switching element may be an N-type transistor.

[0104] In an embodiment, some of the pixel switching elements may be oxide thin film transistors, and other pixel switching elements may be polysilicon thin film transistors, but the present invention may not be limited thereto. Features of the embodiments of the present invention described herein may be applied to pixels including only oxide thin film transistors. In an embodiment, some of the pixel switching elements may be N-type transistors, and other pixel switching elements may be P-type transistors, but the present invention may not be limited thereto. Features of the embodiments of the present invention described herein may be applied to pixels including only N-type transistors.

[0105] In an embodiment, Figure 2 As shown in , at least one of the pixels may include first to seventh pixel switching elements PT1 to PT7 and a light emitting element EE.

[0106] The first pixel switching element PT1 may include a control electrode connected to the first pixel node PN1, a first electrode connected to the second pixel node PN2, and a second electrode connected to the third pixel node PN3. The second pixel switching element PT2 may include a control electrode receiving a data write gate signal GW[n], a first electrode receiving a data voltage VDATA, and a second electrode connected to the second pixel node PN2. The third pixel switching element PT3 may include a control electrode receiving a compensation gate signal GC[n], a first electrode connected to the first pixel node PN1, and a second electrode connected to the third pixel node PN3. The fourth pixel switching element PT4 may include a control electrode receiving a data initialization gate signal GI[n], a first electrode receiving an initialization voltage VINIT, and a second electrode connected to the first pixel node PN1. The fifth pixel switching element PT5 may include a control electrode receiving an emission signal EM[n], a first electrode receiving a pixel high power voltage ELVDD, and a second electrode connected to the second pixel node PN2. The sixth pixel switching element PT6 may include a control electrode receiving an emission signal EM[n], a first electrode connected to the third pixel node PN3, and a second electrode connected to the anode electrode of the light emitting element EE. The seventh pixel switching element PT7 may include a control electrode receiving a light emitting element initialization gate signal GB[n], a first electrode receiving a light emitting element initialization voltage VAINIT, and a second electrode connected to an anode electrode of the light emitting element EE. The light emitting element EE may include an anode electrode and a cathode electrode receiving a pixel low power voltage ELVSS.

[0107] The pixel may further include a storage capacitor CST including a first electrode receiving a pixel high power voltage ELVDD and a second electrode connected to the first pixel node PN1 and a boosting capacitor CBOOST including a first electrode receiving a data write gate signal GW[n] and a second electrode connected to the first pixel node PN1.

[0108] The signal output from the gate signal masking circuit of the gate driver 300 may be the compensation gate signal GC[n].

[0109] The driving current may flow through the fifth pixel switching element PT5, the first pixel switching element PT1 and the sixth pixel switching element PT6 to drive the light emitting element EE. The intensity of the driving current may be determined by the level of the data voltage VDATA. The brightness of the light emitting element EE may be determined by the intensity of the driving current.

[0110] In an embodiment, when the image displayed on the display panel 100 is a static image or the display panel is operated in a screen-off mode, the driving frequency of the display panel 100 may be reduced to reduce power consumption. In the case where all of the switching elements of the pixels of the display panel 100 are polysilicon thin film transistors, flickering may occur due to leakage current of the pixel switching elements in a low-frequency driving mode. Therefore, some of the pixel switching elements may be designed using oxide thin film transistors. In an embodiment, the third pixel switching element PT3 and the fourth pixel switching element PT4 may be oxide thin film transistors. In such an embodiment, the first pixel switching element PT1, the second pixel switching element PT2, the fifth pixel switching element PT5, the sixth pixel switching element PT6, and the seventh pixel switching element PT7 may be polysilicon thin film transistors.

[0111] Figure 3 It is shown Figure 1 FIG. 1 is a circuit diagram of an example of a pixel of the display panel 100 .

[0112] Reference Figure 1 and Figure 3 , an embodiment of the display panel 100 includes a plurality of pixels. Each of the pixels includes a light emitting element EE.

[0113] The pixel receives a data write gate signal (e.g., data write gate signals GW[n] and GW[n-1]), a compensation gate signal (e.g., compensation gate signal GC[n]), a data initialization gate signal (e.g., data initialization gate signal GI[n]), a data voltage VDATA, and an emission signal (e.g., emission signal EM[n]), and the light-emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0114] In an embodiment, a pixel may include a first type of pixel switching element and a second type of pixel switching element different from the first type. In an embodiment, for example, the first type of pixel switching element may be a polysilicon thin film transistor. In an embodiment, for example, the first type of pixel switching element may be a low temperature polysilicon (LTPS) thin film transistor. In an embodiment, for example, the second type of pixel switching element may be an oxide thin film transistor. In an embodiment, for example, the first type of pixel switching element may be a P-type transistor, and the second type of pixel switching element may be an N-type transistor.

[0115] In an embodiment, Figure 3 As shown in , at least one of the pixels may include first to seventh pixel switching elements PT1 to PT7 and a light emitting element EE.

[0116] The first pixel switching element PT1 may include a control electrode connected to the first pixel node PN1, a first electrode connected to the second pixel node PN2, and a second electrode connected to the third pixel node PN3. The second pixel switching element PT2 may include a control electrode receiving a data write gate signal GW[n], a first electrode receiving a data voltage VDATA, and a second electrode connected to the second pixel node PN2. The third pixel switching element PT3 may include a control electrode receiving a compensation gate signal GC[n], a first electrode connected to the first pixel node PN1, and a second electrode connected to the third pixel node PN3. The fourth pixel switching element PT4 may include a control electrode receiving a data initialization gate signal GI[n], a first electrode receiving an initialization voltage VINIT, and a second electrode connected to the first pixel node PN1. The fifth pixel switching element PT5 may include a control electrode receiving an emission signal EM[n], a first electrode receiving a pixel high power voltage ELVDD, and a second electrode connected to the second pixel node PN2. The sixth pixel switching element PT6 may include a control electrode receiving an emission signal EM[n], a first electrode connected to the third pixel node PN3, and a second electrode connected to the anode electrode of the light emitting element EE. The seventh pixel switching element PT7 may include a control electrode receiving a data write gate signal GW[n-1], a first electrode receiving a light emitting element initialization voltage VAINIT, and a second electrode connected to an anode electrode of the light emitting element EE. The light emitting element EE may include an anode electrode and a cathode electrode receiving a pixel low power voltage ELVSS.

[0117] The pixel may further include a storage capacitor CST including a first electrode receiving a pixel high power voltage ELVDD and a second electrode connected to the first pixel node PN1 and a boosting capacitor CBOOST including a first electrode receiving a data write gate signal GW[n] and a second electrode connected to the first pixel node PN1.

[0118] The signal output from the gate signal masking circuit of the gate driver 300 may be the compensation gate signal GC[n].

[0119] In an embodiment, Figure 3 As shown in Figure 2 The light emitting element initialization gate signal GB[n] shown in the figure may be the data write gate signal GW[n-1] of the previous stage. In such an embodiment in which the data write gate signal GW[n-1] of the previous stage is used as the light emitting element initialization gate signal GB[n] of the current stage, part of the gate signal generation circuit of the gate driver 300 may be omitted. Therefore, the manufacturing cost of the display device may be reduced, and the dead zone of the display device may be reduced.

[0120] In an embodiment, the third pixel switching element PT3 and the fourth pixel switching element PT4 may be oxide thin film transistors. In such an embodiment, the first pixel switching element PT1, the second pixel switching element PT2, the fifth pixel switching element PT5, the sixth pixel switching element PT6 and the seventh pixel switching element PT7 may be polysilicon thin film transistors.

[0121] Figure 4 It is shown Figure 1 FIG. 1 is a circuit diagram of an example of a pixel of the display panel 100 .

[0122] Reference Figure 1 and Figure 4 , an embodiment of the display panel 100 includes a plurality of pixels. Each of the pixels includes a light emitting element EE.

[0123] The pixel receives a data write gate signal (e.g., a data write gate signal GW[n]), a compensation gate signal (e.g., a compensation gate signal GC[n]), a data initialization gate signal (e.g., a data initialization gate signal GI[n]), a light emitting element initialization gate signal (e.g., a light emitting element initialization gate signal GB[n]), a bias gate signal (e.g., a bias gate signal GBI[n]), a data voltage VDATA, and an emission signal (e.g., an emission signal EM[n]), and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0124] In an embodiment, Figure 4 As shown in , a pixel may include a first type of pixel switch element and a second type of pixel switch element different from the first type. In an embodiment, for example, the first type of pixel switch element may be a polysilicon thin film transistor. In an embodiment, for example, the first type of pixel switch element may be a low temperature polysilicon (LTPS) thin film transistor. In an embodiment, for example, the second type of pixel switch element may be an oxide thin film transistor. In an embodiment, for example, the first type of pixel switch element may be a P-type transistor, and the second type of pixel switch element may be an N-type transistor.

[0125] At least one of the pixels may include first to eighth pixel switching elements PT1 to PT8 and a light emitting element EE.

[0126] The first pixel switching element PT1 may include a control electrode connected to the first pixel node PN1, a first electrode connected to the second pixel node PN2, and a second electrode connected to the third pixel node PN3. The second pixel switching element PT2 may include a control electrode receiving a data write gate signal GW[n], a first electrode receiving a data voltage VDATA, and a second electrode connected to the second pixel node PN2. The third pixel switching element PT3 may include a control electrode receiving a compensation gate signal GC[n], a first electrode connected to the first pixel node PN1, and a second electrode connected to the third pixel node PN3. The fourth pixel switching element PT4 may include a control electrode receiving a data initialization gate signal GI[n], a first electrode receiving an initialization voltage VINIT, and a second electrode connected to the first pixel node PN1. The fifth pixel switching element PT5 may include a control electrode receiving an emission signal EM[n], a first electrode receiving a pixel high power voltage ELVDD, and a second electrode connected to the second pixel node PN2. The sixth pixel switching element PT6 may include a control electrode receiving an emission signal EM[n], a first electrode connected to the third pixel node PN3, and a second electrode connected to the anode electrode of the light emitting element EE. The seventh pixel switch element PT7 may include a control electrode receiving a light emitting element initialization gate signal GB[n], a first electrode receiving a light emitting element initialization voltage VAINIT, and a second electrode connected to an anode electrode of the light emitting element EE. The eighth pixel switch element PT8 may include a control electrode receiving a bias gate signal GBI[n], a first electrode receiving a bias voltage VBIAS, and a second electrode connected to a second pixel node PN2. The light emitting element EE may include an anode electrode and a cathode electrode receiving a pixel low power voltage ELVSS.

[0127] The pixel may further include a storage capacitor CST including a first electrode receiving a pixel high power voltage ELVDD and a second electrode connected to the first pixel node PN1 and a boosting capacitor CBOOST including a first electrode receiving a data write gate signal GW[n] and a second electrode connected to the first pixel node PN1.

[0128] The signal output from the gate signal masking circuit of the gate driver 300 may be the compensation gate signal GC[n].

[0129] In an embodiment, the third pixel switching element PT3 and the fourth pixel switching element PT4 may be oxide thin film transistors. In such an embodiment, the first pixel switching element PT1, the second pixel switching element PT2, the fifth pixel switching element PT5, the sixth pixel switching element PT6, the seventh pixel switching element PT7 and the eighth pixel switching element PT8 may be polysilicon thin film transistors.

[0130] Figure 5It is shown Figure 1 Schematic diagram of an embodiment of a gate driver 300 . Figure 6 It shows that according to Figure 1 The driving frequency of the portion of the display panel 100 is applied to Figure 1 Schematic diagram of a first enable signal EN and a second enable signal ENB of a gate driver 300. Figure 7 It is shown Figure 1 2 is a circuit diagram of an embodiment of a carry generator ST and a gate signal masking circuit MC of a gate driver 300.

[0131] Reference Figures 1 to 7 , an embodiment of the gate driver 300 may include a carry generator ST that generates a carry signal GC_CR(n) based on a previous carry signal GC_CR(n-1), a first clock signal NCLK1, a second clock signal NCLK2, and a low power voltage VGL, and a gate signal masking circuit MC connected to the carry generator ST.

[0132] The gate signal masking circuit MC may output or not output a gate pulse based on a signal of a second control node Q of the carry generator ST, a first enable signal EN, and a second enable signal ENB.

[0133] In an embodiment, for example, when the first enable signal EN has a high level H1 and the second enable signal ENB has a low level L2 , the gate signal masking circuit MC may output a gate pulse.

[0134] In an embodiment, for example, when the first enable signal EN has a low level L1 and the second enable signal ENB has a high level H2 , the gate signal masking circuit MC may not output a gate pulse.

[0135] In an embodiment, Figure 6 As shown in , based on the first enable signal EN and the second enable signal ENB, the gate driver 300 can output gate pulses at a high frequency (e.g., 120 Hz) for a portion of the display panel 100 that performs high-frequency driving, and can output gate pulses at a low frequency (e.g., 1 Hz) for a portion of the display panel 100 that performs low-frequency driving.

[0136] The gate signal masking circuit MC can mask the output of the gate pulse so as to output the gate pulse at a low frequency (e.g., 1 Hz). The carry generator ST transmits the carry signal to the next stage regardless of the operation of the gate signal masking circuit MC that masks the output of the gate pulse, so that the gate driver 300 can effectively perform multiplexing of the driving frequency.

[0137] In an embodiment, Figure 7As shown in, the gate signal masking circuit MC may include a first switch element S1 to a fifth switch element S5. The first switch element S1 may include a control electrode connected to a masking control node S-node, a first electrode connected to a first control node QB, and a second electrode connected to a third control node QM. The second switch element S2 may include a control electrode connected to a second control node Q, a first electrode receiving a masking power signal, and a second electrode connected to a first intermediate node. The third switch element S3 may include a control electrode receiving a first enable signal EN, a first electrode connected to a first intermediate node, and a second electrode connected to the masking control node S-node. The fourth switch element S4 may include a control electrode receiving a second enable signal ENB, a first electrode connected to a masking control node S-node, and a second electrode connected to a second intermediate node. The fifth switch element S5 may include a control electrode connected to a second control node Q, a first electrode connected to a second intermediate node, and a second electrode receiving a second low power voltage VGL2.

[0138] In such an embodiment, the gate signal masking circuit MC may further include a sixth switch element S6 to an eighth switch element S8. The sixth switch element S6 may include a control electrode connected to the third control node QM, a first electrode receiving the first clock signal NCLK1, and a second electrode connected to the gate output node. The seventh switch element S7 may include a control electrode connected to the second control node Q, a first electrode connected to the gate output node, and a second electrode receiving the low power voltage VGL. The eighth switch element S8 may include a control electrode connected to the second control node Q, a first electrode receiving the first clock signal NCLK1, and a second electrode connected to the third control node QM.

[0139] In an embodiment, the second low power voltage VGL2 may be lower than the low power voltage VGL. The second low power voltage VGL2 may be a direct current (DC) voltage. The low power voltage VGL may be a DC voltage.

[0140] The gate signal masking circuit MC may further include a first masking capacitor CM1 including a first electrode receiving the first clock signal NCLK1 and a second electrode connected to the third control node QM, and a second masking capacitor CM2 including a first electrode connected to the masking control node S-node and a second electrode receiving the low power voltage VGL.

[0141] In an embodiment, the masking power signal may be a high power voltage VGH. The high power voltage VGH may be a DC voltage.

[0142] The carry generator ST may include first to eleventh gate switching elements T11 and a fourteenth gate switching element T14 .

[0143] The first gate switching element T1 may include a control electrode receiving the first clock signal NCLK1, a first electrode receiving the previous carry signal GC_CR(n-1), and a second electrode connected to the first node ND1. The second gate switching element T2 may include a control electrode connected to the second control node Q, a first electrode receiving the second clock signal NCLK2, and a second electrode connected to the fifth node ND5. The third gate switching element T3 may include a control electrode receiving the first clock signal NCLK1, a first electrode connected to the second node ND2, and a second electrode receiving the low power voltage VGL. The fourth gate switching element T4 may include a control electrode receiving the low power voltage VGL, a first electrode connected to the second node ND2, and a second electrode connected to the third node ND3. The fifth gate switching element T5 may include a control electrode connected to the second control node Q, a first electrode receiving the first clock signal NCLK1, and a second electrode connected to the second node ND2. The sixth gate switching element T6 may include a control electrode connected to the third node ND3, a first electrode receiving the second clock signal NCLK2, and a second electrode connected to the third intermediate node. The seventh gate switching element T7 may include a control electrode connected to the third node ND3, a first electrode connected to the fourth node ND4, and a second electrode connected to the third intermediate node. The eighth gate switch element T8 may include a control electrode receiving the second clock signal NCLK2, a first electrode connected to the fourth node ND4, and a second electrode connected to the first control node QB. The ninth gate switch element T9 may include a control electrode connected to the first control node QB, a first electrode receiving the first clock signal NCLK1, and a second electrode connected to the carry output node. The tenth gate switch element T10 may include a control electrode connected to the second control node Q, a first electrode connected to the carry output node, and a second electrode receiving the low power voltage VGL. The eleventh gate switch element T11 may include a control electrode receiving the low power voltage VGL, a first electrode connected to the first node ND1, and a second electrode connected to the second control node Q. The fourteenth gate switch element T14 may include a control electrode connected to the second control node Q, a first electrode receiving the first clock signal NCLK1, and a second electrode connected to the first control node QB.

[0144] The ninth gate switching element T9 may be a pull-up switching element that pulls up the carry signal GC_CR(n) in response to the signal of the first control node QB. The tenth gate switching element T10 may be a pull-down switching element that pulls down the carry signal GC_CR(n) in response to the signal of the second control node QB.

[0145] The carry generator ST may further include a twelfth gate switching element T12 including a control electrode receiving a reset signal SESR, a first electrode receiving the first clock signal NCLK1, and a second electrode connected to the first node ND1, and a thirteenth gate switching element T13 including a control electrode receiving the reset signal SESR, a first electrode connected to the first control node QB, and a second electrode receiving the low power voltage VGL.

[0146] The carry generator ST may further include a first capacitor C1 including a first electrode receiving the first clock signal NCLK1 and a second electrode connected to the first control node QB, a second capacitor C2 including a first electrode connected to the third node ND3 and a second electrode connected to the fourth node ND4, and a third capacitor C3 including a first electrode connected to the fifth node ND5 and a second electrode connected to the second control node Q. The carry generator ST may further include a fourth capacitor C4 including a first electrode connected to the carry output node and a second electrode receiving the low power voltage VGL.

[0147] In an embodiment, for example, the control electrode of the tenth gate switching element T10 of the carry generator ST and the control electrode of the fourteenth gate switching element T14 of the carry generator ST may be connected to the control electrode of the seventh switching element S7 of the gate signal masking circuit MC and the control electrode of the eighth switching element S8 of the gate signal masking circuit MC.

[0148] In an embodiment, for example, the control electrode of the ninth gate switching element T9 of the carry generator ST may be connected to the first electrode of the first switching element S1 of the gate signal masking circuit MC.

[0149] In an embodiment, the previous carry signal GC_CR(n-1) may be a carry signal of the immediately previous stage of the current stage. However, the present invention may not be limited thereto. Alternatively, the previous carry signal GC_CR(n-1) may be a carry signal of one of the multiple previous stages of the current stage.

[0150] Figure 8 It is shown Figure 7 : Signal timing diagram of the input signal, node signal and output signal of the carry generator ST. Fig. 9 It is shown Figure 7 The carry generator ST is in Figure 8 Circuit diagram of the operation at the first time point t1. Fig.10 It is shown Figure 7 The carry generator ST in Figure 8 Circuit diagram of the operation at the second time point t2. Fig.11 It is shown Figure 7 The carry generator ST is in Figure 8 Circuit diagram of the operation at the third time point t3. Fig.12 It is shown Figure 7 The carry generator ST is in Figure 8 Circuit diagram of the operation at the fourth time point t4. Fig.13 It is shown Figure 7 The carry generator ST is in Figure 8 Circuit diagram of the operation at the fifth time point t5.

[0151] In the following, reference will be made to Figures 8 to 13 The operation of the carry generator ST is described in detail. Figure 8 The waveform of the signal of the second control node Q is briefly shown in FIG. Figures 17 to 20 and Fig. 22 The waveform of the signal at the second control node Q is shown in detail.

[0152] like Figure 8 and Fig. 9 As shown in FIG. 1 , at the first time point t1 , the vertical start signal FLM or the previous carry signal GC_CR(n−1) may have a valid level (eg, a high level), and the first clock signal NCLK1 may drop from a high level to a low level.

[0153] At the first time point t1, the voltage of the second control node Q may have a high level. At the first time point t1, the first clock signal NCLK1 is coupled through the first capacitor C1 so that the voltage of the first control node QB may change to a first low level.

[0154] At the first time point t1 , the third gate switching element T3 and the fourth gate switching element T4 are turned on, and the second capacitor C2 may be charged.

[0155] like Figure 8 and Fig.10 As shown in FIG. 1 , at the second time point t2 , the second clock signal NCLK2 drops from a high level to a low level.

[0156] At the second time point t2, the voltage of the first control node QB may be changed to a second low level by the boosting of the second capacitor C2.

[0157] At the second time point t2 , the ninth gate switching element T9 has a turned-on state and the first clock signal NCLK1 has a low level, so that the low level is output as the carry signal GC_CR(n).

[0158] At the second time point t2 , the low power voltage VGL is charged at the first capacitor C1 .

[0159] like Figure 8 and Fig.11 As shown in FIG. 1 , at the third time point t3 , the first clock signal NCLK1 rises from a low level to a high level.

[0160] When the first clock signal NCLK1 rises from a low level to a high level in the on state of the ninth gate switch element T9 at the third time point t3 , the high level is output as the carry signal GC_CR(n).

[0161] like Figure 8 and Fig.12 As shown in FIG. 4 , at the fourth time point t4 , the first clock signal NCLK1 drops from a high level to a low level.

[0162] When the first clock signal NCLK1 drops to a low level at the fourth time point t4, the vertical start signal FLM or the previous carry signal GC_CR(n-1) has a low state at the fourth time point t4, so that the voltage of the second control node Q can become a low level. In addition, at the fourth time point t4, the voltage of the first control node QB can drop to a third low level.

[0163] When the second control node Q is at a low level at the fourth time point t4 , the tenth gate switching element T10 is turned on, so that the low level of the low power voltage VGL is output as the carry signal GC_CR(n) due to the tenth gate switching element T10 .

[0164] In addition, at the fourth time point t4, the fourteenth gate switching element T14 is turned on by the voltage of the second control node Q, and the ninth gate switching element T9 is turned on by the first clock signal NCLK1, so that the falling edge of the first clock signal NCLK1 is output as the carry signal GC_CR(n).

[0165] like Figure 8 and Fig.13 As shown in FIG. 5 , at the fifth time point t5 , the first clock signal NCLK1 rises from a low level to a high level.

[0166] When the first clock signal NCLK1 rises from a low level to a high level at the fifth time point t5, the voltage of the second control node Q maintains a low level. At the fifth time point t5, the tenth gate switch element T10 is turned on by the low level of the voltage of the second control node Q, and the low level of the low power voltage VGL is output as a carry signal GC_CR(n) due to the tenth gate switch element T10.

[0167] In addition, the fourteenth gate switching element T14 is turned on by the low level of the voltage of the second control node Q in the fifth time point t5 , and the voltage of the first control node QB becomes a high state due to the fourteenth gate switching element T14 at the rising edge of the first clock signal NCLK1 .

[0168] In an embodiment, when the signal of the second control node Q has a low level at (or before) the fifth time point t5, the signal of the second control node Q may drop to a second low level at (or before) the fifth time point t5 at a position where the second clock signal NCLK2 drops.

[0169] When the reset signal SESR is applied to the twelfth gate switching element T12 and the thirteenth gate switching element T13, the twelfth gate switching element T12 and the thirteenth gate switching element T13 are turned on, so that the voltage of the second control node Q can be initialized by the twelfth gate switching element T12, and the voltage of the first control node QB can be initialized by the thirteenth gate switching element T13. When the reset signal SESR is applied, the gate driver 300 can output the gate signal GC(n) having a high level.

[0170] Fig.14 It is shown Figure 7 A signal timing diagram of a signal of a masked control node S-node and a signal of a second control node Q(n) of a gate signal masking circuit MC (in this article, Figure 7 The second control node Q in the example may be the abbreviation of the second control node Q(n)). Fig.15 It shows that according to Figure 7 A table showing the state of the signal of the masking control node S-node of the input signal of the gate signal masking circuit MC. Fig.16 It shows that according to Figure 7 FIG. 5 is a signal timing diagram of an input signal of the gate signal masking circuit MC and an output signal of the gate signal masking circuit MC. Fig.17 is shown in the first case Figure 7 Signal timing diagram of input signals, node signals and output signals of the carry generator ST and the gate signal masking circuit MC. Fig.18 is shown in the second case Figure 7 Signal timing diagram of input signals, node signals and output signals of the carry generator ST and the gate signal masking circuit MC. Fig.19 It is shown that in the third case Figure 7 Signal timing diagram of input signals, node signals and output signals of the carry generator ST and the gate signal masking circuit MC. Fig. 20 It is shown that in the fourth case Figure 7 Signal timing diagram of input signals, node signals and output signals of the carry generator ST and the gate signal masking circuit MC.

[0171] In the following, reference will be made to Figures 14 to 20 The operation of the gate signal masking circuit MC is described in detail. Fig.14 and Fig.16 The waveform of the signal of the second control node Q(n) is briefly shown in FIG. Figures 17 to 20 and Fig. 22 The waveform of the signal of the second control node Q(n) is shown in detail in FIG.

[0172] In an embodiment, Figure 7 As shown in , the gate signal masking circuit MC may include eight transistors S1 to S8 and two capacitors CM1 and CM2.

[0173] For the multiplexing of the driving frequency, the gate driver 300 may use the output of the carry generator ST as the carry signal GC_CR(n) and use the output of the gate signal masking circuit MC as the gate signal GC(n).

[0174] The first control node QB and the second control node Q of the carry generator ST may be connected to the gate signal masking circuit MC.

[0175] As the state of the masking control node S-node and the state of the first switching element S1 change based on the first enable signal EN, the second enable signal ENB, and the frequency control signal, the gate signal masking circuit MC operates.

[0176] Fig.14 A case is shown in which the gate signal GC(n) is not output from the ninth gate line #9 to the twelfth gate line #12 among the twenty gate lines #1 to #20 due to the gate signal masking operation.

[0177] The first to eighth gate lines #1 to #8 and the thirteenth to twentieth gate lines #13 to #20 may output gate pulses, while the ninth to twelfth gate lines #9 to #12 may not output gate pulses.

[0178] like Fig.14 As shown in , on the line where the gate pulse is not output, the masking control node S-node can maintain a high level. When the masking control node S-node maintains a high level, the first switch element S1 can be turned off, and the sixth switch element S6 can be turned off, so that the gate output node can not output a gate pulse.

[0179] The sixth switching element S6 operates similarly to the ninth gate switching element T9 of the carry generator ST. The ninth gate switching element T9 outputs the first clock signal NCLK1 as the carry signal GC_CR(n) in response to the first control node QB. The sixth gate switching element T6 outputs the first clock signal NCLK1 as the gate signal GC(n) in response to the third control node QM.

[0180] The seventh switching element S7 operates similarly to the tenth gate switching element T10 of the carry generator ST. The tenth gate switching element T10 outputs the low power voltage VGL as the low level of the carry signal GC_CR(n) in response to the voltage of the second control node Q. The seventh switching element S7 outputs the low power voltage VGL as the low level of the gate signal GC(n) in response to the voltage of the second control node Q.

[0181] The eighth switching element S8 operates similarly to the fourteenth gate switching element T14 of the carry generator ST. The fourteenth gate switching element T14 outputs the first clock signal NCLK1 to the first control node QB in response to the voltage of the second control node Q. The eighth gate switching element T8 outputs the first clock signal NCLK1 to the third control node QM in response to the voltage of the second control node Q.

[0182] The signal of the masking control node S-node may be determined by operations of the second to fifth switching elements S2 to S5 .

[0183] In an embodiment, for example, when the signal of the second control node Q(n) has a low level and the first enable signal EN has a low level, the second and third switching elements S2 and S3 are turned on so that the high power voltage VGH can be applied to the masking control node S-node.

[0184] In an embodiment, Figure 6 As shown in , the second enable signal ENB may have an inverted waveform of the waveform of the first enable signal EN. Therefore, when the third switch element S3 is turned on in response to the first enable signal EN, the fourth switch element S4 may be turned off in response to the second enable signal ENB.

[0185] In an embodiment, for example, when the signal of the second control node Q(n) has a low level and the second enable signal ENB has a low level, the fourth switching element S4 and the fifth switching element S5 are turned on so that the second low power voltage VGL2 can be applied to the masking control node S-node.

[0186] The second enable signal ENB may have an inverted waveform of the waveform of the first enable signal EN. Therefore, when the fourth switch element S4 is turned on in response to the second enable signal ENB, the third switch element S3 may be turned off in response to the first enable signal EN.

[0187] When the signal of the second control node Q(n) is at a high level, the second switch element S2 and the fifth switch element S5 are turned off so that the masking control node S-node can maintain a previous state regardless of the states of the first enable signal EN and the second enable signal ENB.

[0188] exist Fig.15In FIG. 1 , the signal of the masking control node S-node in the embodiment is shown as a table according to the states of the first enable signal EN and the signal of the second control node Q(n) of the gate signal masking circuit MC.

[0189] Reference Fig.15 When the first enable signal EN has a high level and the signal of the second control node Q(n) has a low level, the signal of the masking control node S-node may have a low level. This condition may be defined as a first condition CN1.

[0190] When the first enable signal EN has a low level and the signal of the second control node Q(n) has a low level, the signal of the masking control node S-node may have a high level. Such a condition may be defined as a second condition CN2.

[0191] When the first enable signal EN has a high level and the signal of the second control node Q(n) has a high level, the previous state of the signal of the mask control node S-node may be maintained. This condition may be defined as a third condition CN3.

[0192] When the first enable signal EN has a low level and the signal of the second control node Q(n) has a high level, the previous state of the signal of the masking control node S-node may be maintained. This condition may be defined as a fourth condition CN4.

[0193] In an embodiment, Fig.16 As shown in , for example, the signal of the second control node Q( 1 ) of the first line may sequentially have the first condition CN1 and the third condition CN3 , and the gate signal GC( 1 ) of the first line may be output normally.

[0194] In an embodiment, Fig.16 As shown in , for example, the signal of the second control node Q( 2 ) of the second line may sequentially have the first condition CN1 , the third condition CN3 , and the fourth condition CN4 , and the gate signal GC( 2 ) of the second line may be output normally.

[0195] In such an embodiment, the signal of the second control node Q( 3 ) of the third line may sequentially have the second condition CN2 and the fourth condition CN4 , and the gate signal GC( 3 ) of the third line may be masked and not output accordingly.

[0196] In such an embodiment, the signal of the second control node Q(4) of the fourth line may sequentially have the second condition CN2, the fourth condition CN4, and the third condition CN3, and the gate signal GC(4) of the fourth line may be masked and not output accordingly.

[0197] In such an embodiment, the signal of the second control node Q(5) of the fifth line may sequentially have the first condition CN1 and the third condition CN3, and the gate signal GC(5) of the fifth line may be normally output.

[0198] Fig.17 A case where the first enable signal EN has a non-active level (eg, a high level) in all periods in which the signal at the second control node Q has an active level (eg, a high level) is shown.

[0199] When the first enable signal EN has a non-active level in all periods in which the signal of the second control node Q has an active level, the gate signal masking circuit MC may output a gate pulse.

[0200] Fig.18 A case where the first enable signal EN has an active level (eg, a low level) in all periods in which the signal at the second control node Q has an active level (eg, a high level) is shown.

[0201] When the first enable signal EN has the active level in all periods in which the signal of the second control node Q has the active level, the gate signal masking circuit MC may not output the gate pulse.

[0202] Fig.19 A case is shown in which the first enable signal EN changes from an inactive level (eg, a high level) to an active level (eg, a low level) during a period in which the signal at the second control node Q has an active level (eg, a high level).

[0203] When the first enable signal EN changes from the inactive level to the active level during a period in which the signal of the second control node Q has the active level, the gate signal masking circuit MC may output the gate pulse.

[0204] Fig. 20 A case is shown in which the first enable signal EN changes from an active level (eg, a low level) to an inactive level (eg, a high level) during a period in which the signal of the second control node Q has an active level (eg, a high level).

[0205] When the first enable signal EN changes from the active level to the inactive level during a period in which the signal of the second control node Q has the active level, the gate signal masking circuit MC may not output the gate pulse.

[0206] As mentioned above Figures 17 to 20As described above, in an embodiment, when the first enable signal EN has a non-valid level (e.g., a high level) at the rising edge of the signal at the second control node Q, the gate signal masking circuit MC may output a gate pulse. In such an embodiment, when the first enable signal EN has a valid level (e.g., a low level) at the rising edge of the signal at the second control node Q, the gate signal masking circuit MC may not output a gate pulse.

[0207] Fig.21A is shown applied to Figure 7 2 is a signal timing diagram of an example of a waveform of a first enable signal EN and a waveform of a second enable signal ENB of a gate signal masking circuit MC.

[0208] Reference Fig.21A , the first enable signal EN may have an inverted waveform of a waveform of the second enable signal ENB.

[0209] In an embodiment, for example, a high level of the first enable signal EN may be the same as a high level of the second enable signal ENB, but a low level of the first enable signal EN may be different from a low level of the second enable signal ENB.

[0210] A high level of the first enable signal EN may be a high power voltage VGH, and a low level of the first enable signal EN may be a low power voltage VGL.

[0211] A high level of the second enable signal ENB may be the high power voltage VGH, and a low level of the second enable signal ENB may be the second low power voltage VGL2.

[0212] In an embodiment, the second low power voltage VGL2 is applied to the second electrode of the fifth switching element S5 so that the low level of the second enable signal ENB applied to the fourth switching element S4 may be the second low power voltage VGL2. Therefore, the voltage drop may be improved at the fourth switching element S4.

[0213] Fig.21B is shown applied to Figure 7 2 is a signal timing diagram of an example of a waveform of a first enable signal EN and a waveform of a second enable signal ENB of a gate signal masking circuit MC.

[0214] Reference Fig.21B , the first enable signal EN may have an inverted waveform of a waveform of the second enable signal ENB.

[0215] In an embodiment, for example, a high level of the first enable signal EN may be the same as a high level of the second enable signal ENB, but a low level of the first enable signal EN may be different from a low level of the second enable signal ENB.

[0216] A high level of the first enable signal EN may be a high power voltage VGH, and a low level of the first enable signal EN may be a low power voltage VGL.

[0217] The high level of the second enable signal ENB may be the high power voltage VGH. The low level of the second enable signal ENB may be the third low power voltage VGL3 different from the second low power voltage VGL2. In an embodiment, for example, the third low power voltage VGL3 may be lower than the second low power voltage VGL2.

[0218] In an embodiment, the second low power voltage VGL2 is applied to the second electrode of the fifth switching element S5 so that the low level of the second enable signal ENB applied to the fourth switching element S4 may be the third low power voltage VGL3. Therefore, the voltage drop may be improved at the fourth switching element S4.

[0219] Fig. 21C is shown applied to Figure 7 2 is a signal timing diagram of an example of a waveform of a first enable signal EN and a waveform of a second enable signal ENB of a gate signal masking circuit MC.

[0220] Reference Fig. 21C , the first enable signal EN may have an inverted waveform of a waveform of the second enable signal ENB.

[0221] In an embodiment, for example, a high level of the first enable signal EN may be the same as a high level of the second enable signal ENB, and a low level of the first enable signal EN may be the same as a low level of the second enable signal ENB.

[0222] A high level of the first enable signal EN may be the high power voltage VGH, and a low level of the first enable signal EN may be the second low power voltage VGL2.

[0223] A high level of the second enable signal ENB may be the high power voltage VGH, and a low level of the second enable signal ENB may be the second low power voltage VGL2.

[0224] In an embodiment, the second low power voltage VGL2 is applied to the second electrode of the fifth switching element S5 so that the low level of the second enable signal ENB applied to the fourth switching element S4 may be the second low power voltage VGL2. Therefore, the voltage drop may be improved at the fourth switching element S4.

[0225] Fig.21D is shown applied to Figure 7 2 is a signal timing diagram of an example of a waveform of a first enable signal EN and a waveform of a second enable signal ENB of a gate signal masking circuit MC.

[0226] Reference Fig.21D, the first enable signal EN may have an inverted waveform of a waveform of the second enable signal ENB.

[0227] In an embodiment, for example, a high level of the first enable signal EN may be the same as a high level of the second enable signal ENB, and a low level of the first enable signal EN may be the same as a low level of the second enable signal ENB.

[0228] The high level of the first enable signal EN may be the high power voltage VGH. The low level of the first enable signal EN may be a third low power voltage VGL3 different from the low power voltage VGL and the second low power voltage VGL2. In an embodiment, for example, the third low power voltage VGL3 may be lower than the second low power voltage VGL2.

[0229] The high level of the second enable signal ENB may be the high power voltage VGH, and the low level of the second enable signal ENB may be the third low power voltage VGL3.

[0230] In an embodiment, the second low power voltage VGL2 is applied to the second electrode of the fifth switching element S5 so that the low level of the second enable signal ENB applied to the fourth switching element S4 may be the third low power voltage VGL3. Therefore, the voltage drop may be improved at the fourth switching element S4.

[0231] Fig. 22 It is shown Figure 7 0047 is a signal timing diagram of the carry signal GC_CR(n) of the carry generator ST and the signal of the second control node Q(n). Fig.23 : is a signal timing chart showing a signal of a masking control node S-node of a gate signal masking circuit MC according to a comparative embodiment and an embodiment of the present invention (hereinafter will be referred to as “the present embodiment”).

[0232] Reference Fig. 22 , the low level of the carry signal GC_CR(n) may be the low power voltage VGL, and the low level of the signal of the second control node Q(n) may decrease to a level less than the low power voltage VGL in response to the falling of the second clock signal NCLK2.

[0233] exist Fig.23 In the comparative embodiment of , the signal of the masking control node S-node may be determined by applying the carry signal GC_CR(n) to the control electrode of the second switching element S2 and the control electrode of the fifth switching element S5. Fig.23 In the comparative embodiment of , the signal of the mask control node S-node is determined based on the carry signal GC_CR(n), so that the low level of the mask control node S-node can be relatively high.

[0234] exist Fig.23In the embodiment of the present invention, the signal of the masking control node S-node can be determined by applying the signal of the second control node Q(n) to the control electrode of the second switching element S2 and the control electrode of the fifth switching element S5. Fig.23 In the embodiment, the signal of the masking control node S-node is determined based on the signal of the second control node Q(n), so that the low level of the masking control node S-node can be reduced, and the reliability of the gate signal masking circuit MC can be improved accordingly.

[0235] According to an embodiment, the output of the gate signal GC(n) may be controlled based on the signal of the second control node Q of the pull-down switching element T10 applied to the pull-down carry signal GC_CR(n), the first enable signal EN and the second enable signal ENB so that multiplexing of the driving frequency may be effectively performed.

[0236] The power consumption of the display device can be effectively reduced by multi-way division of the driving frequency.

[0237] The signal of the masking control node S-node may be determined based on the signal of the second control node Q, so that the reliability of the gate signal masking circuit MC is improved by reducing the low level of the signal of the masking control node S-node.

[0238] In addition, a second low power voltage VGL2 lower than the low power voltage VGL is applied to the second electrode of the fifth switching element S5 so that the reliability of the gate signal masking circuit MC is improved by reducing the low level of the signal of the masking control node S-node.

[0239] Fig.24 is a circuit diagram illustrating a carry generator ST and a gate signal masking circuit MCA of a gate driver 300 according to an embodiment of the present invention.

[0240] In addition to the first switching element of the gate signal masking circuit, according to Fig.24 The gate signal masking circuit, gate driver and display device of the embodiment are similar to those described above with reference to Figures 1 to 23 The gate signal masking circuit, gate driver and display device of the described embodiments are substantially the same. Therefore, the same reference numerals will be used to refer to the same as those in the referenced Figures 1 to 23 Parts that are described are the same or similar, and any repeated detailed description thereof will be omitted or simplified.

[0241] Reference Figures 1 to 6 and Figures 8 to 24 , an embodiment of a display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0242] The gate driver 300 may include a carry generator ST generating a carry signal GC_CR(n) based on a previous carry signal GC_CR(n-1), the first clock signal NCLK1, the second clock signal NCLK2, and the low power voltage VGL, and a gate signal masking circuit MCA connected to the carry generator ST.

[0243] The gate signal masking circuit MCA may include a first switching element S1 to a fifth switching element S5. The first switching element S1 may include a control electrode connected to a masking control node S-node, a first electrode connected to a first control node QB, and a second electrode connected to a third control node QM. The second switching element S2 may include a control electrode connected to a second control node Q, a first electrode receiving a masking power signal, and a second electrode connected to a first intermediate node. The third switching element S3 may include a control electrode receiving a first enable signal EN, a first electrode connected to a first intermediate node, and a second electrode connected to the masking control node S-node. The fourth switching element S4 may include a control electrode receiving a second enable signal ENB, a first electrode connected to a masking control node S-node, and a second electrode connected to a second intermediate node. The fifth switching element S5 may include a control electrode connected to a second control node Q, a first electrode connected to a second intermediate node, and a second electrode receiving a second low power voltage VGL2.

[0244] In an embodiment, the first switch element S1 may further include an additional control electrode (hereinafter referred to as a "second control electrode") connected to the masking control node S-node. The first switch element S1 may be a dual-gate switch element including two control electrodes. Accordingly, the voltage drop at the first switch element S1 may be improved so that the low level of the signal of the third control node QM may be further reduced, and the reliability of the gate signal masking circuit MCA may be improved.

[0245] According to an embodiment, the output of the gate signal GC(n) may be controlled based on the signal of the second control node Q of the pull-down switching element T10 applied to the pull-down carry signal GC_CR(n), the first enable signal EN and the second enable signal ENB so that multiplexing of the driving frequency may be effectively performed.

[0246] The power consumption of the display device can be effectively reduced by multi-way division of the driving frequency.

[0247] The signal of the masking control node S-node may be determined based on the signal of the second control node Q, so that the reliability of the gate signal masking circuit MCA is improved by reducing the low level of the signal of the masking control node S-node.

[0248] In addition, a second low power voltage VGL2 lower than the low power voltage VGL is applied to the second electrode of the fifth switching element S5 so that the reliability of the gate signal masking circuit MCA is improved by reducing the low level of the signal of the masking control node S-node.

[0249] In addition, the first switch element S1 may further include a second control electrode connected to the masking control node S-node, so that the reliability of the gate signal masking circuit MCA is improved by reducing the low level of the signal of the third control node QM.

[0250] Fig.25 is a circuit diagram illustrating a carry generator ST and a gate signal masking circuit MCB of a gate driver 300 according to an embodiment of the present invention.

[0251] In addition to the fifth switch element of the gate signal masking circuit, according to Fig.25 The gate signal masking circuit, gate driver and display device of the embodiment are similar to those described above with reference to Figures 1 to 23 The gate signal masking circuit, gate driver and display device of the described embodiments are substantially the same. Therefore, the same reference numerals will be used to refer to the same as those in the above reference. Figures 1 to 23 Parts that are described are the same or similar, and any repeated detailed description thereof will be omitted or simplified.

[0252] Reference Figures 1 to 6 and Figures 8 to 23 and Fig.25 , an embodiment of a display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0253] The gate driver 300 may include a carry generator ST generating a carry signal GC_CR(n) based on a previous carry signal GC_CR(n-1), a first clock signal NCLK1, a second clock signal NCLK2, and a low power voltage VGL, and a gate signal masking circuit MCB connected to the carry generator ST.

[0254] The gate signal masking circuit MCB may include a first switching element S1 to a fifth switching element S5. The first switching element S1 may include a control electrode connected to a masking control node S-node, a first electrode connected to a first control node QB, and a second electrode connected to a third control node QM. The second switching element S2 may include a control electrode connected to a second control node Q, a first electrode receiving a masking power signal, and a second electrode connected to a first intermediate node. The third switching element S3 may include a control electrode receiving a first enable signal EN, a first electrode connected to a first intermediate node, and a second electrode connected to the masking control node S-node. The fourth switching element S4 may include a control electrode receiving a second enable signal ENB, a first electrode connected to a masking control node S-node, and a second electrode connected to a second intermediate node. The fifth switching element S5 may include a control electrode connected to a second control node Q, a first electrode connected to a second intermediate node, and a second electrode receiving a second low power voltage VGL2.

[0255] In an embodiment, the fifth switch element S5 may further include an additional control electrode (hereinafter referred to as "second control electrode") connected to the second control node Q. The fifth switch element S5 may be a dual-gate switch element including two control electrodes. Accordingly, the voltage drop at the fifth switch element S5 may be improved so that the low level of the signal of the masking control node S-node may be further reduced, and the reliability of the gate signal masking circuit MCB may be improved.

[0256] According to an embodiment, the output of the gate signal GC(n) may be controlled based on the signal of the second control node Q of the pull-down switching element T10 applied to the pull-down carry signal GC_CR(n), the first enable signal EN and the second enable signal ENB so that multiplexing of the driving frequency may be effectively performed.

[0257] The power consumption of the display device can be effectively reduced by multi-way division of the driving frequency.

[0258] The signal of the masking control node S-node may be determined based on the signal of the second control node Q, so that the reliability of the gate signal masking circuit MCB is improved by reducing the low level of the signal of the masking control node S-node.

[0259] In addition, a second low power voltage VGL2 lower than the low power voltage VGL is applied to the second electrode of the fifth switching element S5 so that the reliability of the gate signal masking circuit MCB is improved by reducing the low level of the signal of the masking control node S-node.

[0260] In addition, the fifth switching element S5 may further include a second control electrode connected to the second control node Q, so that the reliability of the gate signal masking circuit MCB is improved by reducing the low level of the signal of the masking control node S-node.

[0261] Fig.26 is a circuit diagram illustrating a carry generator ST and a gate signal masking circuit MCC of a gate driver 300 according to an embodiment of the present invention.

[0262] In addition to the first switch element and the fifth switch element of the gate signal masking circuit, according to Fig.26 The gate signal masking circuit, gate driver and display device of the embodiment are similar to those described above with reference to Figures 1 to 23 The gate signal masking circuit, gate driver and display device of the described embodiments are substantially the same. Therefore, the same reference numerals will be used to refer to the same as those in the above reference. Figures 1 to 23 Parts that are described are the same or similar, and any repeated detailed description thereof will be omitted or simplified.

[0263] Reference Figures 1 to 6 and Figures 8 to 23 and Fig.26 , an embodiment of a display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0264] The gate driver 300 may include a carry generator ST generating a carry signal GC_CR(n) based on a previous carry signal GC_CR(n-1), the first clock signal NCLK1, the second clock signal NCLK2, and the low power voltage VGL, and a gate signal masking circuit MCC connected to the carry generator ST.

[0265] The gate signal masking circuit MCC may include a first switching element S1 to a fifth switching element S5. The first switching element S1 may include a control electrode connected to a masking control node S-node, a first electrode connected to a first control node QB, and a second electrode connected to a third control node QM. The second switching element S2 may include a control electrode connected to a second control node Q, a first electrode receiving a masking power signal, and a second electrode connected to a first intermediate node. The third switching element S3 may include a control electrode receiving a first enable signal EN, a first electrode connected to a first intermediate node, and a second electrode connected to the masking control node S-node. The fourth switching element S4 may include a control electrode receiving a second enable signal ENB, a first electrode connected to a masking control node S-node, and a second electrode connected to a second intermediate node. The fifth switching element S5 may include a control electrode connected to a second control node Q, a first electrode connected to a second intermediate node, and a second electrode receiving a second low power voltage VGL2.

[0266] In an embodiment, the first switch element S1 may further include a second control electrode connected to the masking control node S-node. The first switch element S1 may be a dual-gate switch element including two control electrodes. Accordingly, the voltage drop at the first switch element S1 may be improved so that the low level of the signal of the third control node QM may be further reduced, and the reliability of the gate signal masking circuit MCC may be improved.

[0267] In an embodiment, the fifth switch element S5 may further include a second control electrode connected to the second control node Q. The fifth switch element S5 may be a dual-gate switch element including two control electrodes. Accordingly, the voltage drop at the fifth switch element S5 may be improved so that the low level of the signal of the masking control node S-node may be further reduced, and the reliability of the gate signal masking circuit MCC may be improved.

[0268] According to an embodiment, the output of the gate signal GC(n) may be controlled based on the signal of the second control node Q of the pull-down switching element T10 applied to the pull-down carry signal GC_CR(n), the first enable signal EN and the second enable signal ENB so that multiplexing of the driving frequency may be effectively performed.

[0269] The power consumption of the display device can be effectively reduced by multi-way division of the driving frequency.

[0270] The signal of the masking control node S-node may be determined based on the signal of the second control node Q, so that the reliability of the gate signal masking circuit MCC is improved by reducing the low level of the signal of the masking control node S-node.

[0271] In addition, a second low power voltage VGL2 lower than the low power voltage VGL is applied to the second electrode of the fifth switching element S5 so that the reliability of the gate signal masking circuit MCC is improved by reducing the low level of the signal of the masking control node S-node.

[0272] In addition, the first switch element S1 may further include a second control electrode connected to the masking control node S-node, so that the reliability of the gate signal masking circuit MCC is improved by reducing the low level of the signal of the third control node QM.

[0273] In addition, the fifth switching element S5 may further include a second control electrode connected to the second control node Q, so that the reliability of the gate signal masking circuit MCC is improved by reducing the low level of the signal of the masking control node S-node.

[0274] Fig. 27 is a circuit diagram illustrating a carry generator ST and a gate signal masking circuit MCD of a gate driver 300 according to an embodiment of the present invention. Fig.28 It is shown Fig. 27 1. Signal timing diagram of the signal of the masked control node S-node and the signal of the second control node Q(n) of the gate signal masking circuit MCD.

[0275] In addition to the masking power signal of the gate signal masking circuit, according to Fig. 27 The gate signal masking circuit, gate driver and display device of the embodiment are similar to those described above with reference to Figures 1 to 23 The gate signal masking circuit, gate driver and display device of the described embodiments are substantially the same. Therefore, the same reference numerals will be used to refer to the same as those in the above reference. Figures 1 to 23 Parts that are described are the same or similar, and any repeated detailed description thereof will be omitted or simplified.

[0276] Reference Figures 1 to 6 , Figures 8 to 13 , Figures 15 to 23 , Fig. 27 and Fig.28 , an embodiment of a display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0277] The gate driver 300 may include a carry generator ST generating a carry signal GC_CR(n) based on a previous carry signal GC_CR(n-1), the first clock signal NCLK1, the second clock signal NCLK2, and the low power voltage VGL, and a gate signal masking circuit MCD connected to the carry generator ST.

[0278] The gate signal masking circuit MCD may include a first switching element S1 to a fifth switching element S5. The first switching element S1 may include a control electrode connected to a masking control node S-node, a first electrode connected to a first control node QB, and a second electrode connected to a third control node QM. The second switching element S2 may include a control electrode connected to a second control node Q, a first electrode receiving a masking power signal, and a second electrode connected to a first intermediate node. The third switching element S3 may include a control electrode receiving a first enable signal EN, a first electrode connected to a first intermediate node, and a second electrode connected to the masking control node S-node. The fourth switching element S4 may include a control electrode receiving a second enable signal ENB, a first electrode connected to a masking control node S-node, and a second electrode connected to a second intermediate node. The fifth switching element S5 may include a control electrode connected to a second control node Q, a first electrode connected to a second intermediate node, and a second electrode receiving a second low power voltage VGL2.

[0279] In an embodiment, the masked power signal may be a clock signal NCLK4. When the first enable signal EN changes from an active level (e.g., a low level) to an inactive level (e.g., a high level) and when the first enable signal EN changes from an inactive level (e.g., a high level) to an active level (e.g., a low level), the clock signal NCLK4 may have a high level.

[0280] A signal having a high level in transition of the first enable signal EN and the second enable signal ENB may be used as a mask power signal.

[0281] When Fig. 27 When one of the clock signals (eg, the clock signal NCLK4) is used as the mask power signal as shown in FIG, the carry generator ST and the gate signal mask circuit MCD can be operated without adding a high power voltage ( Figure 7 The device operates under the condition of high power voltage VGH).

[0282] In the following, reference will be made to Fig.28 Detailed Description Fig. 27 The gate signal masking circuit MCD operates.

[0283] Fig.28 It is shown Fig. 27 The signal timing diagram of the gate signal masking circuit MCD of the masking control node S-node and the signal of the second control node Q(n). Fig.28 The waveform of the signal of the second control node Q(n) is briefly shown in FIG. Figures 17 to 20 and Fig. 22 The waveform of the signal of the second control node Q(n) is shown in detail in FIG.

[0284] In an embodiment, as described above, the gate signal masking circuit MCD may include eight transistors S1 to S8 and two capacitors CM1 and CM2 .

[0285] For the multiplexing of the driving frequency, the gate driver 300 may use the output of the carry generator ST as the carry signal GC_CR(n) and the output of the gate signal masking circuit MCD as the gate signal GC(n).

[0286] Fig.28 A case is shown in which the gate signal GC(n) is not output from the ninth gate line #9 to the twelfth gate line #12 among the twenty gate lines #1 to #20 due to the gate signal masking operation.

[0287] The first to eighth gate lines #1 to #8 and the thirteenth to twentieth gate lines #13 to #20 may output gate pulses, while the ninth to twelfth gate lines #9 to #12 may not output gate pulses.

[0288] like Fig.28 As shown in , on the line where the gate pulse is not output, the masking control node S-node may maintain a high level. When the masking control node S-node maintains a high level, the first switch element S1 may be turned off, and the sixth switch element S6 may be turned off, so that the gate output node may not output a gate pulse. However, in the embodiment, the masking power signal is the fourth clock signal NCLK4, so that the voltage of the masking control node S-node does not constantly maintain a high level, but may have a period with a low level according to the pulse of the fourth clock signal NCLK4.

[0289] According to an embodiment, the output of the gate signal GC(n) may be controlled based on the signal of the second control node Q of the pull-down switching element T10 applied to the pull-down carry signal GC_CR(n), the first enable signal EN and the second enable signal ENB so that multiplexing of the driving frequency may be effectively performed.

[0290] The power consumption of the display device can be effectively reduced by multi-way division of the driving frequency.

[0291] The signal of the masking control node S-node may be determined based on the signal of the second control node Q, so that the reliability of the gate signal masking circuit MCD is improved by reducing the low level of the signal of the masking control node S-node.

[0292] In addition, a second low power voltage VGL2 lower than the low power voltage VGL is applied to the second electrode of the fifth switching element S5 so that the reliability of the gate signal masking circuit MCD is improved by reducing the low level of the signal of the masking control node S-node.

[0293] Fig.29 is a block diagram showing an electronic device 1000 according to an embodiment of the present invention. Fig.30 It shows that Fig.29 The electronic device 1000 is implemented as an example of a smart phone.

[0294] Reference Fig.29 and Fig.30 , an embodiment of the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be Figure 1 In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0295] In an embodiment, Fig.30 As shown in , the electronic device 1000 may be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. For example, the electronic device 1000 may be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet computer, a car navigation system, a computer display screen, a laptop computer, a head mounted display (HMD) device, or the like.

[0296] The processor 1010 may perform various computing functions or various tasks. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), or the like. The processor 1010 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 may be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0297] The processor 1010 may Figure 1 The input image data IMG and the input control signal CONT are output to the driving controller 200.

[0298] The memory device 1020 may store data used for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one nonvolatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, or the like and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, or the like.

[0299] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, or the like. The I / O device 1040 may include an input device such as a keyboard, a keypad, a mouse device, a touch pad, a touch screen, or the like, and an output device such as a printer, a speaker, or the like. In some embodiments, a display device 1060 may be included in the I / O device 1040. The power supply 1050 may provide power for the operation of the electronic device 1000. The display device 1060 may be coupled to other components via a bus or other communication link.

[0300] According to embodiments of the gate signal masking circuit, the gate driver, the display device, and the electronic device, the power consumption of the display device can be reduced.

[0301] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0302] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope or spirit of the invention as defined in the following claims.

Claims

1. A gate signal masking circuit, comprising: a first switch element including a control electrode connected to a masked control node, a first electrode connected to a first control node, and a second electrode connected to a third control node; a second switch element including a control electrode connected to the second control node, a first electrode receiving the masking power signal, and a second electrode connected to the first intermediate node; a third switch element, the third switch element comprising a control electrode receiving a first enable signal, a first electrode connected to the first intermediate node, and a second electrode connected to the masking control node; a fourth switch element, the fourth switch element comprising a control electrode receiving a second enable signal, a first electrode connected to the masking control node, and a second electrode connected to a second intermediate node; as well as A fifth switching element includes a control electrode connected to the second control node, a first electrode connected to the second intermediate node, and a second electrode receiving a second low power voltage.

2. The gate signal masking circuit according to claim 1, further comprising: a sixth switch element, the sixth switch element comprising a control electrode connected to the third control node, a first electrode receiving the first clock signal, and a second electrode connected to the gate output node; a seventh switching element including a control electrode connected to the second control node, a first electrode connected to the gate output node, and a second electrode receiving a low power voltage; as well as An eighth switch element includes a control electrode connected to the second control node, a first electrode receiving the first clock signal, and a second electrode connected to the third control node.

3. The gate signal masking circuit according to claim 2, wherein: The second low power voltage is lower than the low power voltage.

4. The gate signal masking circuit according to claim 2, further comprising: a first masked capacitor including a first electrode receiving the first clock signal and a second electrode connected to the third control node; as well as A second masking capacitor includes a first electrode connected to the masking control node and a second electrode receiving the low power voltage.

5. The gate signal masking circuit according to claim 1, wherein: The masking power signal is a high power voltage which is a direct current voltage.

6. The gate signal masking circuit according to claim 5, wherein: The high level of the first enable signal is the same as the high level of the second enable signal, and The low level of the first enable signal is different from the low level of the second enable signal.

7. The gate signal masking circuit according to claim 6, wherein: The high level of the first enable signal is the high power voltage, and the low level of the first enable signal is a low power voltage greater than the second low power voltage, and The high level of the second enable signal is the high power voltage, and the low level of the second enable signal is the second low power voltage.

8. The gate signal masking circuit according to claim 6, wherein: The high level of the first enable signal is the high power voltage, and the low level of the first enable signal is a low power voltage greater than the second low power voltage, and The high level of the second enable signal is the high power voltage, and the low level of the second enable signal is a third low power voltage different from the low power voltage and the second low power voltage.

9. The gate signal masking circuit according to claim 5, wherein: The high level of the first enable signal is the high power voltage, and the low level of the first enable signal is the second low power voltage, and The high level of the second enable signal is the high power voltage, and the low level of the second enable signal is the second low power voltage.

10. The gate signal masking circuit according to claim 5, wherein: The high level of the first enable signal is the high power voltage, and the low level of the first enable signal is a third low power voltage different from the second low power voltage, and The high level of the second enable signal is the high power voltage, and the low level of the second enable signal is the third low power voltage.

11. The gate signal masking circuit according to claim 1, wherein: The first switching element further comprises an additional control electrode connected to the masked control node.

12. The gate signal masking circuit according to claim 1, wherein: The fifth switching element further comprises an additional control electrode connected to the second control node.

13. The gate signal masking circuit according to claim 1, wherein: The mask power signal is a clock signal having a high level when the first enable signal changes from an active level to an inactive level and when the first enable signal changes from the inactive level to the active level.

14. The gate signal masking circuit according to claim 1, wherein: The gate signal masking circuit outputs a gate pulse when the first enable signal has a non-active level in all periods in which the signal of the second control node has an active level.

15. The gate signal masking circuit according to claim 1, wherein: When the first enable signal has an active level in all periods in which the signal of the second control node has an active level, the gate signal masking circuit does not output a gate pulse.

16. The gate signal masking circuit according to claim 1, wherein: The gate signal masking circuit outputs a gate pulse when the first enable signal changes from an inactive level to an active level during a period in which a signal of the second control node has an active level.

17. The gate signal masking circuit according to claim 1, wherein: When the first enable signal changes from the active level to the inactive level during a period in which the signal of the second control node has the active level, the gate signal masking circuit does not output a gate pulse.

18. A gate driver comprising: a carry generator that generates a carry signal based on a previous carry signal, a first clock signal, a second clock signal, and a low power voltage; as well as a gate signal masking circuit connected to the carry generator, Wherein, the carry generator comprises: a pull-up switch element, the pull-up switch element pulling up the carry signal in response to a signal of a first control node; and a pull-down switch element, the pull-down switch element pulling down the carry signal in response to a signal of a second control node, and The gate signal masking circuit outputs a gate pulse or does not output the gate pulse based on the signal of the second control node, the first enable signal and the second enable signal.

19. The gate driver according to claim 18, wherein: The gate signal masking circuit comprises: a first switch element, the first switch element comprising a control electrode connected to a masked control node, a first electrode connected to the first control node, and a second electrode connected to a third control node; a second switch element, the second switch element comprising a control electrode connected to the second control node, a first electrode receiving a masking power signal, and a second electrode connected to the first intermediate node; a third switch element, the third switch element comprising a control electrode receiving the first enable signal, a first electrode connected to the first intermediate node, and a second electrode connected to the masking control node; a fourth switch element, the fourth switch element comprising a control electrode receiving the second enable signal, a first electrode connected to the masking control node, and a second electrode connected to a second intermediate node; and A fifth switching element includes a control electrode connected to the second control node, a first electrode connected to the second intermediate node, and a second electrode receiving a second low power voltage.

20. The gate driver according to claim 19, wherein: The carry generator comprises: a first gate switching element, the first gate switching element comprising a control electrode receiving the first clock signal, a first electrode receiving the previous carry signal, and a second electrode connected to a first node; a second gate switching element, the second gate switching element comprising a control electrode connected to the second control node, a first electrode receiving the second clock signal, and a second electrode connected to a fifth node; a third gate switching element, the third gate switching element including a control electrode receiving the first clock signal, a first electrode connected to a second node, and a second electrode receiving the low power voltage; a fourth gate switching element including a control electrode receiving the low power voltage, a first electrode connected to the second node, and a second electrode connected to a third node; a fifth gate switching element, the fifth gate switching element comprising a control electrode connected to the second control node, a first electrode receiving the first clock signal, and a second electrode connected to the second node; a sixth gate switching element, the sixth gate switching element comprising a control electrode connected to the third node, a first electrode receiving the second clock signal, and a second electrode connected to a third intermediate node; a seventh gate switching element, the seventh gate switching element comprising a control electrode connected to the third node, a first electrode connected to a fourth node, and a second electrode connected to the third intermediate node; an eighth gate switching element, the eighth gate switching element comprising a control electrode receiving the second clock signal, a first electrode connected to the fourth node, and a second electrode connected to the first control node; a ninth gate switching element, the ninth gate switching element comprising a control electrode connected to the first control node, a first electrode receiving the first clock signal, and a second electrode connected to a carry output node; a tenth gate switching element, the tenth gate switching element comprising a control electrode connected to the second control node, a first electrode connected to the carry output node, and a second electrode receiving the low power voltage; an eleventh gate switching element including a control electrode receiving the low power voltage, a first electrode connected to the first node, and a second electrode connected to the second control node; and a fourteenth gate switching element, the fourteenth gate switching element comprising a control electrode connected to the second control node, a first electrode receiving the first clock signal, and a second electrode connected to the first control node, Wherein, the ninth gate switch element is the pull-up switch element, and Wherein, the tenth gate switch element is the pull-down switch element.

21. The gate driver according to claim 20, wherein: The carry generator also includes: a twelfth gate switching element, the twelfth gate switching element including a control electrode receiving a reset signal, a first electrode receiving the first clock signal, and a second electrode connected to the first node; and A thirteenth gate switching element includes a control electrode receiving the reset signal, a first electrode connected to the first control node, and a second electrode receiving the low power voltage.

22. The gate driver according to claim 20, wherein: The carry generator also includes: a first capacitor including a first electrode receiving the first clock signal and a second electrode connected to the first control node; a second capacitor including a first electrode connected to the third node and a second electrode connected to the fourth node; a third capacitor including a first electrode connected to the fifth node and a second electrode connected to the second control node; and A fourth capacitor includes a first electrode connected to the carry output node and a second electrode receiving the low power voltage.

23. The gate driver according to claim 20, wherein: The gate signal masking circuit as claimed in claim 2, and The control electrode of the tenth gate switching element and the control electrode of the fourteenth gate switching element are connected to the control electrode of the seventh switching element and the control electrode of the eighth switching element.

24. The gate driver according to claim 20, wherein: The control electrode of the ninth gate switching element is connected to the first electrode of the first switching element.

25. A display device comprising: A display panel, the display panel comprising pixels; a gate driver, the gate driver outputting a gate signal to the pixel; as well as a data driver that outputs a data voltage to the pixel, Wherein, the gate driver comprises: a carry generator that generates a carry signal based on a previous carry signal, a first clock signal, a second clock signal, and a low power voltage; and a gate signal masking circuit connected to the carry generator, Wherein, the carry generator comprises: a pull-up switch element, the pull-up switch element pulling up the carry signal in response to a signal of a first control node; and a pull-down switch element, the pull-down switch element pulling down the carry signal in response to a signal of a second control node, and The gate signal masking circuit outputs a gate pulse or does not output the gate pulse based on the signal of the second control node, the first enable signal and the second enable signal.

26. An electronic device comprising: A display panel, the display panel comprising pixels; a gate driver, the gate driver outputting a gate signal to the pixel; a data driver that outputs a data voltage to the pixel, A driving controller, the driving controller controlling the gate driver and the data driver; as well as a processor, the processor outputting input image data and input control signals to the drive controller; Wherein, the gate driver comprises: a carry generator that generates a carry signal based on a previous carry signal, a first clock signal, a second clock signal, and a low power voltage; and a gate signal masking circuit connected to the carry generator, Wherein, the carry generator comprises: a pull-up switch element, the pull-up switch element pulling up the carry signal in response to a signal of a first control node; and a pull-down switch element, the pull-down switch element pulling down the carry signal in response to a signal of a second control node, and The gate signal masking circuit outputs a gate pulse or does not output the gate pulse based on the signal of the second control node, the first enable signal and the second enable signal.

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