A panel gate driving circuit based on LTPS CMOS

Abstract

The present invention discloses a panel gate driving circuit based on LTPS CMOS, which includes n cascaded units. Each cascaded unit receives a control signal and provides a scan driving signal G to the panel gate. Among them, the STVU terminal of the Nth cascaded unit is connected to the NEXT terminal of the (N-1)th cascaded unit, and the STVD terminal of the Nth cascaded unit is connected to the NEXT terminal of the (N+1)th cascaded unit. The present invention is based on the basic logic gates of LTPS CMOS and realizes bidirectional scanning.

Description

Technical Field

[0001] The present invention relates to a panel gate driving circuit, in particular to a panel gate driving circuit based on LTPS CMOS, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] The panel gate driving circuit sequentially turns on the TFT gate lines of the panel display, and then writes the display information into the pixels through the TFT source lines. When the Nth row gate driving pulse is completed, the (N + 1)th row gate driving pulse output can be controlled by a clock and transmitted in this way. For high-resolution and high-refresh-rate panels, since the proportion of circuit delay becomes larger, a gate driving circuit with bidirectional scanning needs to be provided.

[0003] LTPS CMOS (Low Temperature Poly-Silicon, CMOS, low-temperature polysilicon CMOS) is commonly used to integrate the gate driving circuit of the panel display and fabricate it on a glass substrate or a flexible panel by using the Array process. This technology also has the advantages of low power consumption, high hole mobility, high electron mobility, and noise tolerance of CMOS circuits, and is also used to fabricate other integrated circuit chips.

[0004] Therefore, it is necessary to design a panel gate driving circuit based on the basic logic gates of LTPS CMOS and adopting bidirectional scanning. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a panel gate driving circuit based on LTPS CMOS, which is based on the basic logic gates of LTPS CMOS and realizes bidirectional scanning.

[0006] To solve the above technical problem, the technical solution adopted by the present invention is:

[0007] A panel gate driving circuit based on LTPS CMOS includes n cascaded units. Each cascaded unit receives a control signal and provides a scanning driving signal G to the panel gate. The STVU terminal of the Nth cascaded unit is connected to the NEXT terminal of the (N - 1)th cascaded unit, and the STVD terminal of the Nth cascaded unit is connected to the NEXT terminal of the (N + 1)th cascaded unit.

[0008] Further, the control signals include a global clock signal CLK1, a global clock signal CLK2, a global top-down scan control signal U2D, a global bottom-up scan control signal D2U, and a global reset signal GRESET. The CKV1 terminal of the Nth cascaded unit is connected to the global clock signal CLK1, the CKV2 terminal of the Nth cascaded unit is connected to the global clock signal CLK2, the UD terminal of the Nth cascaded unit is connected to the global top-down scan control signal U2D, the DU terminal of the Nth cascaded unit is connected to the global bottom-up scan control signal D2U, the RESET terminal of the Nth cascaded unit is connected to the global reset signal GRESET. The CKV1 terminals of the (N + 1)th and (N - 1)th cascaded units are connected to the global clock signal CLK2, and the CKV2 terminals of the (N + 1)th and (N - 1)th cascaded units are connected to the global clock signal CLK1.

[0009] Further, the NEXT terminal of the cascaded unit outputs a control signal for the output of the lower-level signal.

[0010] Further, the cascaded unit includes a video control switch, an inverter INV1, a latch, a reset transistor T1, an enable NAND gate N1, and an inverter INV4. The first input terminal of the video control switch serves as the UD terminal of the cascaded unit, the second input terminal of the video control switch serves as the DU terminal of the cascaded unit, the third input terminal of the video control switch serves as the STVU terminal of the cascaded unit, the fourth input terminal of the video control switch serves as the STVD terminal of the cascaded unit. The output terminal of the video control switch is connected to the input terminal of the inverter INV1. The output terminal of the inverter INV1 is connected to the first input terminal of the latch. The second input terminal of the latch serves as the CKV1 terminal of the cascaded unit. The third input terminal of the latch serves as the CKV2 terminal of the cascaded unit and is connected to the first input terminal of the enable NAND gate N1. The fourth input terminal of the latch is connected to the drain of the reset transistor T1. The source of the reset transistor T1 is connected to the global high potential VGH. The gate of the reset transistor T1 serves as the RESET terminal of the cascaded unit. The output terminal of the latch is connected to the second input terminal of the enable NAND gate N1 and serves as the NEXT terminal of the cascaded unit. The output terminal of the enable NAND gate N1 is connected to the input terminal of the inverter INV4. The output terminal of the inverter INV4 serves as the output terminal of the cascaded unit and generates a scan driving signal G.

[0011] Further, the video control switch includes a CMOS transmission gate TG1 and a CMOS transmission gate TG2. The IN terminal of the CMOS transmission gate TG1 serves as the third input terminal of the video control switch, and the IN terminal of the CMOS transmission gate TG2 serves as the fourth input terminal of the video control switch. The OUT terminal of the CMOS transmission gate TG1 is connected to the OUT terminal of the CMOS transmission gate TG2 and serves as the output terminal of the video control switch. The CN terminal of the CMOS transmission gate TG1 is connected to the CP terminal of the CMOS transmission gate TG2 and serves as the first input terminal of the video control switch. The CP terminal of the CMOS transmission gate TG1 is connected to the CN terminal of the CMOS transmission gate TG2 and serves as the second input terminal of the video control switch.

[0012] Further, the latch includes a CMOS transmission gate TG3, a CMOS transmission gate TG4, an inverter INV2, and an inverter INV3. The IN terminal of the CMOS transmission gate TG3 serves as the first input terminal of the latch. The OUT terminal of the CMOS transmission gate TG3 is connected to the OUT terminal of the CMOS transmission gate TG4 and the input terminal of the inverter INV2 and serves as the fourth input terminal of the latch. The CN terminal of the CMOS transmission gate TG3 is connected to the CP terminal of the CMOS transmission gate TG4 and serves as the second input terminal of the latch. The CP terminal of the CMOS transmission gate TG3 is connected to the CN terminal of the CMOS transmission gate TG4 and serves as the third input terminal of the latch. The output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3 and serves as the output terminal of the latch. The output terminal of the inverter INV3 is connected to the IN terminal of the CMOS transmission gate TG4.

[0013] Further, the inverter includes a transistor T2 and a transistor T3. The gates of the transistor T2 and the transistor T3 are connected and serve as the input terminal of the inverter. The source of the transistor T2 is connected to the global high potential VGH. The source of the transistor T3 is connected to the global low potential VGL. The drains of the transistor T2 and the transistor T3 are connected and serve as the output terminal of the inverter.

[0014] Further, the CMOS transmission gate includes a transistor T4 and a transistor T5. The drains of the transistor T4 and the transistor T5 are connected and serve as the IN terminal of the CMOS transmission gate. The sources of the transistor T4 and the transistor T5 are connected and serve as the OUT terminal of the CMOS transmission gate. The gate of the transistor T4 serves as the CP terminal of the CMOS transmission gate. The gate of the transistor T5 serves as the CN terminal of the CMOS transmission gate.

[0015] Further, the enable NAND gate includes transistors T6, T7, T8, and T9. The source of transistor T6 is connected to the source of transistor T7 and connected to the global high potential VGH. The gate of transistor T6 is connected to the gate of transistor T8 and serves as the first input terminal of the enable NAND gate. The drain of transistor T6 is connected to the drain of transistor T7 and the drain of transistor T8 and serves as the output terminal of the enable NAND gate. The gate of transistor T7 is connected to the gate of transistor T9 and serves as the second input terminal of the enable NAND gate. The source of transistor T8 is connected to the drain of transistor T9, and the source of transistor T9 is connected to the global low potential VGL.

[0016] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a panel gate driving circuit based on LTPS CMOS, which can integrate the Array process, achieving the purposes of fewer peripheral circuits, low manufacturing cost, narrow border, high resolution, high freedom, flexible screen, and customizable design; The present invention adopts bidirectional GOA scanning, improving the panel refresh rate. Brief Description of the Drawings

[0017] Figure 1 is a schematic diagram of a panel gate driving circuit based on LTPS CMOS of the present invention.

[0018] Figure 2 is a circuit diagram of a cascade unit of the present invention.

[0019] Figure 3 is a schematic diagram of an inverter of the present invention.

[0020] Figure 4 is a schematic diagram of a CMOS transmission gate of the present invention.

[0021] Figure 5 is a schematic diagram of an enable NAND gate of the present invention.

[0022] Figure 6 is a simulation waveform diagram of a panel gate driving circuit based on LTPS CMOS of the present invention. Detailed Embodiments

[0023] In order to elaborate in detail the technical solutions adopted by the present invention to achieve the predetermined technical purposes, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. And, without creative efforts, the technical means or technical features in the embodiments of the present invention can be replaced. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0024] Such as Figure 1As shown in the figure, a panel gate driving circuit based on LTPS CMOS of the present invention includes n cascaded units. Each cascaded unit receives a control signal and provides a scanning driving signal G to the panel gate. The STVU terminal of the Nth cascaded unit is connected to the NEXT terminal of the (N - 1)th cascaded unit, and the STVD terminal of the Nth cascaded unit is connected to the NEXT terminal of the (N + 1)th cascaded unit.

[0025] The control signal includes a global clock signal CLK1, a global clock signal CLK2, a global top - down scanning control signal U2D, a global bottom - up scanning control signal D2U, and a global reset signal GRESET. The CKV1 terminal of the Nth cascaded unit is connected to the global clock signal CLK1, the CKV2 terminal of the Nth cascaded unit is connected to the global clock signal CLK2, the UD terminal of the Nth cascaded unit is connected to the global top - down scanning control signal U2D, the DU terminal of the Nth cascaded unit is connected to the global bottom - up scanning control signal D2U, the RESET terminal of the Nth cascaded unit is connected to the global reset signal GRESET. The CKV1 terminals of the (N + 1)th and (N - 1)th cascaded units are connected to the global clock signal CLK2, and the CKV2 terminals of the (N + 1)th and (N - 1)th cascaded units are connected to the global clock signal CLK1.

[0026] The NEXT terminal of the cascaded unit outputs a control signal for the next - stage signal output.

[0027] As Figure 2 shown, the cascaded unit includes a video control switch 121, an inverter INV1, a latch 122, a reset transistor T1, an enable NAND gate N1, and an inverter INV4. The first input terminal of the video control switch 121 serves as the UD terminal of the cascaded unit, the second input terminal of the video control switch 121 serves as the DU terminal of the cascaded unit, the third input terminal of the video control switch 121 serves as the STVU terminal of the cascaded unit, the fourth input terminal of the video control switch 121 serves as the STVD terminal of the cascaded unit. The output terminal of the video control switch 121 is connected to the input terminal of the inverter INV1. The output terminal of the inverter INV1 is connected to the first input terminal of the latch 122. The second input terminal of the latch 122 serves as the CKV1 terminal of the cascaded unit. The third input terminal of the latch 122 serves as the CKV2 terminal of the cascaded unit and is connected to the first input terminal of the enable NAND gate N1. The fourth input terminal of the latch 122 is connected to the drain of the reset transistor T1. The source of the reset transistor T1 is connected to the global high potential VGH. The gate of the reset transistor T1 serves as the RESET terminal of the cascaded unit. The output terminal of the latch 122 is connected to the second input terminal of the enable NAND gate N1 and serves as the NEXT terminal of the cascaded unit. The output terminal of the enable NAND gate N1 is connected to the input terminal of the inverter INV4. The output terminal of the inverter INV4 serves as the output terminal of the cascaded unit and generates the scanning driving signal G.

[0028] As Figure 2 shown, the video control switch 121 includes a CMOS transmission gate TG1 and a CMOS transmission gate TG2. The IN terminal of the CMOS transmission gate TG1 serves as the third input terminal of the video control switch, the IN terminal of the CMOS transmission gate TG2 serves as the fourth input terminal of the video control switch, the OUT terminals of the CMOS transmission gate TG1 and the CMOS transmission gate TG2 are connected and serve as the output terminal of the video control switch, the CN terminal of the CMOS transmission gate TG1 and the CP terminal of the CMOS transmission gate TG2 are connected and serve as the first input terminal of the video control switch, and the CP terminal of the CMOS transmission gate TG1 and the CN terminal of the CMOS transmission gate TG2 are connected and serve as the second input terminal of the video control switch.

[0029] As Figure 2 shown, the latch 122 includes a CMOS transmission gate TG3, a CMOS transmission gate TG4, an inverter INV2, and an inverter INV3. The IN terminal of the CMOS transmission gate TG3 serves as the first input terminal of the latch, the OUT terminals of the CMOS transmission gate TG3 and the CMOS transmission gate TG4 and the input terminal of the inverter INV2 are connected and serve as the fourth input terminal of the latch, the CN terminal of the CMOS transmission gate TG3 and the CP terminal of the CMOS transmission gate TG4 are connected and serve as the second input terminal of the latch, the CP terminal of the CMOS transmission gate TG3 and the CN terminal of the CMOS transmission gate TG4 are connected and serve as the third input terminal of the latch, the output terminal of the inverter INV2 and the input terminal of the inverter INV3 are connected and serve as the output terminal of the latch, and the output terminal of the inverter INV3 is connected to the IN terminal of the CMOS transmission gate TG4.

[0030] As Figure 3 shown, the inverter includes a transistor T2 and a transistor T3. The gates of the transistor T2 and the transistor T3 are connected and serve as the input terminal of the inverter, the source of the transistor T2 is connected to the global high potential VGH, the source of the transistor T3 is connected to the global low potential VGL, and the drains of the transistor T2 and the transistor T3 are connected and serve as the output terminal of the inverter.

[0031] As Figure 4 shown, the CMOS transmission gate includes a transistor T4 and a transistor T5. The drains of the transistor T4 and the transistor T5 are connected and serve as the IN terminal of the CMOS transmission gate, the sources of the transistor T4 and the transistor T5 are connected and serve as the OUT terminal of the CMOS transmission gate, the gate of the transistor T4 serves as the CP terminal of the CMOS transmission gate, and the gate of the transistor T5 serves as the CN terminal of the CMOS transmission gate.

[0032] As Figure 5As shown, the enabled NAND gate includes transistors T6, T7, T8, and T9. The source of transistor T6 is connected to the source of transistor T7 and connected to the global high potential VGH. The gate of transistor T6 is connected to the gate of transistor T8 and serves as the first input terminal of the enabled NAND gate. The drain of transistor T6 is connected to the drains of transistor T7 and transistor T8 and serves as the output terminal of the enabled NAND gate. The gate of transistor T7 is connected to the gate of transistor T9 and serves as the second input terminal of the enabled NAND gate. The source of transistor T8 is connected to the drain of transistor T9, and the source of transistor T9 is connected to the global low potential VGL.

[0033] The CMOS transmission gates TG1 - TG4, the inverters INV1 - INV4, and the enabled NAND gate N1 are all composed of complementary ntft and ptft transistors, and the transistors T1 - T9 are all LTPS CMOS transistors.

[0034] As Figure 6 shown, the working principle of the present invention is as follows:

[0035] The video control switch is a bidirectional selection switch composed of the CMOS transmission gate TG1 and the CMOS transmission gate TG2. The global top - down scan control signal U2D and the global bottom - up scan control signal D2U are opposite signals. When the global top - down scan control signal U2D is the global high potential VGH and the global bottom - up scan control signal D2U is the global low potential VGL, the video control signal STV enters the inverter INV1 from the STVU terminal through the CMOS transmission gate TG1, and a reversed STV signal NSTV is obtained.

[0036] The global clock signal CLK1 and the global clock signal CLK2 are opposite clock signals, and the pulse width of the video control signal STV covers the width of the global clock signal CLK1.

[0037] When the first rising edge of the global clock signal CLK1 arrives, the working state of the N - th cascaded unit: The CKV1 terminal of the N - th cascaded unit is at the global high potential VGH, the CKV2 terminal is at the global low potential VGL, the video control signal STV is at the global high potential VGH. The video control signal STV enters the inverter INV1 from the STVU terminal through the CMOS transmission gate TG1. The output signal NSTV of the inverter INV1 is at the global low potential VGL. At this time, the CMOS transmission gate TG3 is opened to enable the signal NSTV to enter the latch 122 of the N - th cascaded unit and a global high potential VGH is obtained at the NEXT terminal of the N - th cascaded unit. The NEXT terminal and the CKV2 terminal pass through the enabled NAND gate N1, and the output of the enabled NAND gate N1 is at the global high potential VGH. Then, through the inverter INV4, the output terminal of the inverter INV4 is at the global low potential VGL.

[0038] Working state of the (N + 1)-th stage cascade unit at this time: Since the CKV1 terminal of the (N + 1)-th stage cascade unit is at the global low potential VGL and the CKV2 terminal is at the global high potential VGH at this time, the CMOS transmission gate TG3 of the latch of the (N + 1)-th stage cascade unit is in the off state. The NEXT terminal of the (N + 1)-th stage cascade unit is not affected by the N-th stage cascade unit at this time and remains at the global low potential VGL. The NEXT terminal and the CKV2 terminal pass through the enable NAND gate N1, and the output of the enable NAND gate N1 is at the global high potential VGH. Then, through the inverter INV4, the output terminal of the inverter INV4 is at the global low potential VGL.

[0039] Working state of the N-th stage cascade unit when the first falling edge of the global clock signal CLK1 arrives: When the CKV1 terminal of the N-th stage cascade unit is at the global low potential VGL and the CKV2 terminal is at the global high potential VGH, the CMOS transmission gate TG3 is closed and the CMOS transmission gate TG4 is opened. The latch locks the current state at the global high potential VGH at the NEXT terminal. The NEXT terminal and the CKV2 terminal of the N-th stage cascade unit pass through the enable NAND gate N1, and the output of the enable NAND gate N1 is at the global low potential VGL. Then, through the inverter INV4, the output of the inverter INV4 is at the global high potential VGH.

[0040] Working state of the (N + 1)-th stage cascade unit at this time: Since the CKV1 terminal of the (N + 1)-th stage cascade unit is at the global high potential VGH and the CKV2 terminal is at the global low potential VGL at this time, the CMOS transmission gate TG3 is opened and the CMOS transmission gate TG4 is closed. The NEXT terminal of the N-th stage cascade unit is at the global high potential VGH, so the global high potential VGH is obtained at the NEXT terminal of the (N + 1)-th stage cascade unit. The NEXT terminal and the CKV2 terminal of the (N + 1)-th stage cascade unit pass through the enable NAND gate N1, and the output of the enable NAND gate N1 is at the global high potential VGH. Then, through the inverter INV4, the output is still at the global low potential VGL.

[0041] Working state of the N-th stage cascade unit when the second rising edge of the global clock signal CLK1 arrives: The CKV1 terminal of the N-th stage cascade unit is at the global high potential VGH, the CKV2 terminal is at the global low potential VGL, and the video control signal STV is at the global low potential VGL. The video control signal STV enters the inverter INV1 through the CMOS transmission gate TG1 from the STVU terminal, and the output signal NSTV of the inverter INV1 is at the global high potential VGH. At this time, the CMOS transmission gate TG3 is opened to allow the signal NSTV to enter the latch 122 of the N-th stage cascade unit and the global low potential VGL is obtained at the NEXT terminal of the N-th stage cascade unit. The NEXT terminal and the CKV2 terminal pass through the enable NAND gate N1, and the output of the enable NAND gate N1 is at the global high potential VGH. Then, through the inverter INV4, the output terminal of the inverter INV4 is at the global low potential VGL.

[0042] Operating state of the (N + 1)-th cascaded unit at this time: Since the CKV1 terminal of the (N + 1)-th cascaded unit is at the global low potential VGL and the CKV2 terminal is at the global high potential VGH at this time, the CMOS transmission gate TG3 is closed and the CMOS transmission gate TG4 is open. The NEXT terminal of the (N + 1)-th cascaded unit locks the global high potential VGH. The NEXT terminal and the CKV2 terminal of the (N + 1)-th cascaded unit pass through the enable NAND gate N1, and the output of the enable NAND gate N1 is the global low potential VGL, and then passes through the inverter INV4 to output the global high potential VGH. The line-by-line scanning from the output terminal of the N-th cascaded unit to the output terminal of the (N + 1)-th cascaded unit is realized.

[0043] When the global reset signal GRESET is low, the reset transistor T1 is turned on. After the global high potential VGH passes through the inverter INV2, the signal output at the NEXT terminal of the N-th cascaded unit is the global low potential VGL, the output terminal of the enable NAND gate N1 is the global high potential VGH, and the output terminal of the inverter INV4 outputs the global low potential VGL.

[0044] The present invention provides a panel gate driving circuit based on LTPS CMOS. This circuit can integrate the Array process, achieving the purposes of fewer peripheral circuits, low manufacturing cost, narrow border, high resolution, high freedom, flexible screen and customizable design; the present invention adopts bidirectional GOA scanning, which improves the panel refresh rate.

[0045] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the equivalent embodiments with equivalent changes within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, based on the technical essence of the present invention, any simple modification, equivalent replacement and improvement of the above embodiments within the spirit and principle of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. A panel gate driving circuit based on LTPS CMOS, characterized in that: It includes n - stage cascaded units. Each stage of cascaded unit receives a control signal and provides a scan driving signal G to the panel gate. Among them, the STVU terminal of the N - th stage cascaded unit is connected to the NEXT terminal of the (N - 1) - th stage cascaded unit, and the STVD terminal of the N - th stage cascaded unit is connected to the NEXT terminal of the (N + 1) - th stage cascaded unit; The control signal includes a global clock signal CLK1, a global clock signal CLK2, a global top - to - bottom scan control signal U2D, a global bottom - to - top scan control signal D2U, and a global reset signal GRESET. The CKV1 terminal of the N - th stage cascaded unit is connected to the global clock signal CLK1, the CKV2 terminal of the N - th stage cascaded unit is connected to the global clock signal CLK2, the UD terminal of the N - th stage cascaded unit is connected to the global top - to - bottom scan control signal U2D, the DU terminal of the N - th stage cascaded unit is connected to the global bottom - to - top scan control signal D2U, the RESET terminal of the N - th stage cascaded unit is connected to the global reset signal GRESET, the CKV1 terminals of the (N + 1) - th stage cascaded unit and the (N - 1) - th stage cascaded unit are connected to the global clock signal CLK2, and the CKV2 terminals of the (N + 1) - th stage cascaded unit and the (N - 1) - th stage cascaded unit are connected to the global clock signal CLK1; The cascaded unit includes a video control switch, an inverter INV1, a latch, a reset transistor T1, an enable NAND gate N1, and an inverter INV4. The first input terminal of the video control switch is used as the UD terminal of the cascaded unit, the second input terminal of the video control switch is used as the DU terminal of the cascaded unit, the third input terminal of the video control switch is used as the STVU terminal of the cascaded unit, the fourth input terminal of the video control switch is used as the STVD terminal of the cascaded unit. The output terminal of the video control switch is connected to the input terminal of the inverter INV1. The output terminal of the inverter INV1 is connected to the first input terminal of the latch. The second input terminal of the latch is used as the CKV1 terminal of the cascaded unit. The third input terminal of the latch is used as the CKV2 terminal of the cascaded unit and is connected to the first input terminal of the enable NAND gate N1. The fourth input terminal of the latch is connected to the drain of the reset transistor T1. The source of the reset transistor T1 is connected to the global high potential VGH. The gate of the reset transistor T1 is used as the RESET terminal of the cascaded unit. The output terminal of the latch is connected to the second input terminal of the enable NAND gate N1 and is used as the NEXT terminal of the cascaded unit. The output terminal of the enable NAND gate N1 is connected to the input terminal of the inverter INV4. The output terminal of the inverter INV4 is used as the output terminal of the cascaded unit and generates the scan driving signal G; The video control switch includes a CMOS transmission gate TG1 and a CMOS transmission gate TG2. The IN terminal of the CMOS transmission gate TG1 serves as the third input terminal of the video control switch, and the IN terminal of the CMOS transmission gate TG2 serves as the fourth input terminal of the video control switch. The OUT terminals of the CMOS transmission gate TG1 and the CMOS transmission gate TG2 are connected and serve as the output terminal of the video control switch. The CN terminal of the CMOS transmission gate TG1 and the CP terminal of the CMOS transmission gate TG2 are connected and serve as the first input terminal of the video control switch. The CP terminal of the CMOS transmission gate TG1 and the CN terminal of the CMOS transmission gate TG2 are connected and serve as the second input terminal of the video control switch. The latch includes a CMOS transmission gate TG3, a CMOS transmission gate TG4, an inverter INV2, and an inverter INV3. The IN terminal of the CMOS transmission gate TG3 serves as the first input terminal of the latch. The OUT terminal of the CMOS transmission gate TG3 is connected to the OUT terminal of the CMOS transmission gate TG4 and the input terminal of the inverter INV2 and serves as the fourth input terminal of the latch. The CN terminal of the CMOS transmission gate TG3 and the CP terminal of the CMOS transmission gate TG4 are connected and serve as the second input terminal of the latch. The CP terminal of the CMOS transmission gate TG3 and the CN terminal of the CMOS transmission gate TG4 are connected and serve as the third input terminal of the latch. The output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3 and serves as the output terminal of the latch. The output terminal of the inverter INV3 is connected to the IN terminal of the CMOS transmission gate TG4.

2. The panel gate driving circuit based on LTPS CMOS according to claim 1, wherein: The NEXT terminal of the cascading unit outputs a control signal for the output of the next-stage signal.

3. The panel gate driving circuit based on LTPS CMOS according to claim 1, wherein: The inverter includes a transistor T2 and a transistor T3. The gates of the transistor T2 and the transistor T3 are connected and serve as the input terminal of the inverter. The source of the transistor T2 is connected to the global high potential VGH, and the source of the transistor T3 is connected to the global low potential VGL. The drains of the transistor T2 and the transistor T3 are connected and serve as the output terminal of the inverter.

4. The panel gate driving circuit based on LTPS CMOS according to claim 1, wherein: The CMOS transmission gate includes a transistor T4 and a transistor T5. The drains of the transistor T4 and the transistor T5 are connected and serve as the IN terminal of the CMOS transmission gate. The sources of the transistor T4 and the transistor T5 are connected and serve as the OUT terminal of the CMOS transmission gate. The gate of the transistor T4 serves as the CP terminal of the CMOS transmission gate, and the gate of the transistor T5 serves as the CN terminal of the CMOS transmission gate.

5. The panel gate driving circuit based on LTPS CMOS according to claim 1, wherein: The enabling NAND gate includes a transistor T6, a transistor T7, a transistor T8, and a transistor T9. The source of the transistor T6 is connected to the source of the transistor T7 and connected to the global high potential VGH. The gate of the transistor T6 is connected to the gate of the transistor T8 and serves as the first input terminal of the enabling NAND gate. The drain of the transistor T6 is connected to the drain of the transistor T7 and the drain of the transistor T8 and serves as the output terminal of the enabling NAND gate. The gate of the transistor T7 is connected to the gate of the transistor T9 and serves as the second input terminal of the enabling NAND gate. The source of the transistor T8 is connected to the drain of the transistor T9, and the source of the transistor T9 is connected to the global low potential VGL.

Images