Display device

Abstract

The invention relates to a display device. The display device includes: a bottom metal layer; the semiconductor layer is arranged on the bottom metal layer; a first electrode layer disposed on the semiconductor layer; a second electrode layer disposed on the first electrode layer and overlapping the first electrode layer; a power line disposed on the second electrode layer and electrically connected to the bottom metal layer and the second electrode layer; and a light emitting device including a pixel electrode, a common electrode facing the pixel electrode, and an emission layer between the pixel electrode and the common electrode.

Description

[0001] This application is a divisional application of the invention patent application with application date of June 28, 2019, application number 201910572327.9, and invention name “Display Device”. Technical Field

[0002] Exemplary embodiments of the present invention generally relate to a display device, and more particularly, to a display device having a pixel structure capable of compensating for hysteresis. Background Art

[0003] A display device such as an organic light emitting display device or a liquid crystal display device includes an array substrate including a thin film transistor (TFT), a capacitor, and a plurality of wirings. The array substrate is formed of fine patterns such as TFT, capacitor, and wiring, and the display device operates through complex connections between TFT, capacitor, and wiring.

[0004] Recently, as the demand for small and high-resolution display devices increases, there is an increasing demand for efficient spatial arrangement, connection structure, and driving method of TFTs, capacitors, and wirings included in such display devices, and improvement in the quality of images achieved.

[0005] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore the above information may contain information that does not constitute the prior art. Summary of the invention

[0006] Applicants have discovered that brightness problems such as color streaking in small and high-resolution display devices may be caused by hysteresis. A display device constructed according to an exemplary embodiment of the present invention can reduce or prevent the color streaking phenomenon by compensating for hysteresis. For example, a compensation capacitor in a pixel driving circuit of a display device can compensate for hysteresis by stabilizing voltage.

[0007] More specifically, a display device constructed according to an exemplary embodiment of the present invention may include a compensation capacitor so that the on-bias voltage of the driving transistor can be increased, the compensation capacitor having a first electrode as at least a portion of a source region or a drain region of the driving transistor and a second electrode connected to a power line receiving a first power supply voltage. The on-bias voltage of the driving transistor can be further increased by further providing a pair of compensation capacitors connected in parallel.

[0008] In addition, the display device constructed according to the exemplary embodiment of the present invention can distinguish the conduction bias voltage for each color pixel by controlling the capacitance capacity by controlling the area (width) of the counter electrode of the compensation capacitor. Therefore, the conduction bias voltage can be controlled for each color pixel to adjust the luminous amount and luminous time point of each color pixel. Therefore, the display device according to the exemplary embodiment can reduce the deviation of the luminous delay between color pixels, thereby improving color tailing and / or color blur.

[0009] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the provided exemplary embodiments.

[0010] According to one or more exemplary embodiments, a display device includes: a first electrode layer; a semiconductor layer, the semiconductor layer including a source region, a drain region and a channel region, wherein at least a portion of the source region or the drain region overlaps with the first electrode layer; a second electrode layer, the second electrode layer is adjacent to the channel region; a third electrode layer, the third electrode layer overlaps with the second electrode layer and at least a portion of the source region or the drain region; and a power line, the power line electrically connected to the first electrode layer and the third electrode layer.

[0011] The first electrode layer may overlap the channel region.

[0012] The first electrode layer may be disposed on a lower layer of the semiconductor layer, and the third electrode layer may be disposed on an upper layer of the semiconductor layer.

[0013] The power line may receive a substantially constant voltage.

[0014] The channel region of the semiconductor layer may be curved.

[0015] The display device may also include: a first insulating layer, which is arranged between the first electrode layer and the semiconductor layer; a second insulating layer, which is arranged between the semiconductor layer and the second electrode layer; a third insulating layer, which is arranged between the second electrode layer and the third electrode layer; and a fourth insulating layer, which is arranged between the third electrode layer and the power line.

[0016] According to one or more exemplary embodiments, a display device includes: a first driving transistor, which is in a first pixel region of a substrate and has a first semiconductor layer and a first gate electrode, wherein the first semiconductor layer includes a first source region, a first drain region, and a first channel region; a second driving transistor, which is in a second pixel region of the substrate adjacent to the first pixel region and has a second semiconductor layer and a second gate electrode, wherein the second semiconductor layer includes a second source region, a second drain region, and a second channel region; a first electrode layer, wherein the first electrode layer faces at least a portion of the first source region or the first drain region; a second electrode layer, wherein the second electrode layer faces the first gate electrode and at least a portion of the first source region or the first drain region; a third electrode layer, wherein the third electrode layer faces at least a portion of the second source region or the second drain region; a fourth electrode layer, wherein the fourth electrode layer faces the second gate electrode and at least a portion of the second source region or the second drain region; and a power line, wherein the power line is electrically connected to the first electrode layer, the second electrode layer, the third electrode layer, and the fourth electrode layer.

[0017] An area of ​​the third electrode layer overlapping with the second source region or the second drain region may be greater than an area of ​​the first electrode layer overlapping with the first source region or the first drain region.

[0018] An area of ​​the second source region or the second drain region overlapping with the third electrode layer may be greater than an area of ​​the first source region or the first drain region overlapping with the first electrode layer.

[0019] An area of ​​the fourth electrode layer overlapping with the second source region or the second drain region may be greater than an area of ​​the second electrode layer overlapping with the first source region or the first drain region.

[0020] An area of ​​the fourth electrode layer overlapping with the second source region or the second drain region may be greater than an area of ​​the second electrode layer overlapping with the first source region or the first drain region.

[0021] An area of ​​the fourth electrode layer may be greater than an area of ​​the second electrode layer.

[0022] The display device may also include: a third driving transistor, which may be in a third pixel region of the substrate adjacent to the second pixel region and has a third semiconductor layer and a third gate electrode, wherein the third semiconductor layer may include a third source region, a third drain region and a third channel region; a fifth electrode layer, the fifth electrode layer facing at least a portion of the third source region or the third drain region; and a sixth electrode layer facing the third gate electrode and at least a portion of the third source region or the third drain region, wherein the fifth electrode layer and the sixth electrode layer may be electrically connected to the power line.

[0023] An area of ​​the fifth electrode layer overlapping with the third source region or the third drain region may be equal to an area of ​​the first electrode layer overlapping with the first source region or the first drain region.

[0024] An area of ​​the fifth electrode layer overlapping with the third source region or the third drain region may be equal to an area of ​​the third electrode layer overlapping with the second source region or the second drain region.

[0025] According to one or more exemplary embodiments, a display device includes: a first pixel circuit, the first pixel circuit is in the first pixel region of the substrate, and includes a first driving transistor, a first capacitor and a second capacitor, the first driving transistor having a first semiconductor layer and a first gate electrode, wherein the first semiconductor layer includes a first source region and a first drain region, the first capacitor includes a first lower electrode and a first upper electrode and the second capacitor includes a second lower electrode and a second upper electrode; and a power line, the power line is electrically connected to the first upper electrode and the second lower electrode, wherein the first lower electrode and the second upper electrode are part of the first source region or part of the first drain region, the first upper electrode is arranged on an upper layer of the first semiconductor layer, and the second lower electrode is arranged on a lower layer of the first semiconductor layer.

[0026] The second lower electrode may overlap a channel region of the first semiconductor layer.

[0027] The first pixel circuit may further include a third capacitor having a third lower electrode and a third upper electrode, wherein the third upper electrode may be electrically connected to the power line, and the third lower electrode may be a portion of the first gate electrode.

[0028] The display device may further include: a second pixel circuit, the second pixel circuit is in a second pixel area of ​​the substrate adjacent to the first pixel area, and includes a second driving transistor, a fourth capacitor and a fifth capacitor, the second driving transistor includes a second semiconductor layer and a second gate electrode, wherein the second semiconductor layer includes a second source area and a second drain area, the fourth capacitor includes a fourth lower electrode and a fourth upper electrode, and the fifth capacitor includes a fifth lower electrode and a fifth upper electrode, wherein the fourth upper electrode and the fifth lower electrode can be electrically connected to the power line, the fourth lower electrode and the fifth upper electrode can be part of the second source area or part of the second drain area, the fourth upper electrode can be arranged on the upper layer of the second semiconductor layer, and the fifth lower electrode can be arranged on the lower layer of the second semiconductor layer.

[0029] An area of ​​the fourth lower electrode may be greater than an area of ​​the first lower electrode.

[0030] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept.

[0032] Figure 1 is a plan view of a display device constructed according to an exemplary embodiment of the present invention;

[0033] Figure 2 is constructed according to an exemplary embodiment Figure 1 An equivalent circuit diagram of a representative pixel of a display device;

[0034] Figure 3 is a diagram showing a method according to an exemplary embodiment Figure 2 The timing diagram of the pixel drive;

[0035] Figure 4 is a diagram showing a comparative example Figure 2 The timing diagram of the pixel drive;

[0036] Figure 5 is a graph showing hysteresis characteristics of a thin film transistor;

[0037] Figure 6 is a graph showing a brightness problem of a display device due to hysteresis characteristics of a thin film transistor;

[0038] Figure 7is constructed according to an exemplary embodiment Figure 2 A plan view of a pixel circuit of a pixel shown in ;

[0039] Figure 8 yes Figure 7 an enlarged plan view of a first transistor, a storage capacitor, and a compensation capacitor;

[0040] Fig. 9 It is along Figure 8 A cross-sectional view taken along line AA';

[0041] Fig.10 is a plan view of pixel circuits of different color pixels constructed according to an exemplary embodiment;

[0042] Fig.11 yes Fig.10 an enlarged plan view of a first transistor, a storage capacitor, and a compensation capacitor;

[0043] Fig.12 It is along Fig.11 A cross-sectional view taken along line BB' and line CC';

[0044] Fig.13 is an enlarged plan view of a first transistor, a storage capacitor, and a compensation capacitor constructed according to another exemplary embodiment;

[0045] Fig.14 It is along Fig.13 A cross-sectional view taken along line D-D' and line EE';

[0046] Fig.15 According to another exemplary embodiment Figure 2 A plan view of a pixel circuit of a pixel shown in ;

[0047] Fig.16 yes Fig.15 an enlarged plan view of a first transistor, a storage capacitor, and a compensation capacitor;

[0048] Fig.17 It is along Fig.16 A cross-sectional view taken along line F-F';

[0049] Fig.18 is a plan view of a pixel circuit of a different color pixel constructed according to another exemplary embodiment;

[0050] Fig.19 yes Fig.18 an enlarged plan view of a first transistor, a storage capacitor, and a compensation capacitor;

[0051] Fig. 20 It is along Fig.19A cross-sectional view taken along line G-G' and line H-H';

[0052] Fig.21 is an enlarged plan view of a first transistor, a storage capacitor, and a compensation capacitor constructed according to another exemplary embodiment; and

[0053] Fig. 22 It is along Fig.21 A cross-sectional view taken along line II' and line JJ'. DETAILED DESCRIPTION

[0054] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of various exemplary embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words as non-limiting examples of devices or methods using one or more inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other cases, known structures and devices are shown in block diagram form to avoid making various exemplary embodiments unnecessarily obscure. In addition, various exemplary embodiments may be different, but need not be exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0055] Unless otherwise specified, the illustrated exemplary embodiments will be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0056] The use of cross hatching and / or shading in the drawings is generally provided to make the boundaries between adjacent elements clear. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, or performance of the elements. In addition, in the drawings, the size and relative size of the elements can be magnified for the purpose of clarity and / or description. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0057] When an element or layer is described as being "on" another element or another layer, "connected to" another element or another layer, or "bonded to" another element or another layer, the element or layer may be directly on the other element or another layer, directly connected to the other element or another layer, or directly bonded to the other element or another layer, or there may be an intermediate element or intermediate layer. However, when an element or layer is described as being "directly on" another element or another layer, "directly connected to" another element or another layer, or "directly bonded to" another element or another layer, there is no intermediate element or intermediate layer. For this reason, the term "connection" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without an intermediate element. In addition, the D1 axis, the D2 axis, and the D3 axis are not limited to the three axes of a rectangular coordinate system such as an x-axis, a y-axis, and a z-axis, and may be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0058] Although the terms "first" and "second" etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0059] For descriptive purposes, spatially relative terms such as "under," "below," "below," "down," "above," "up," "above," "higher," or "side" (e.g., as in "sidewall") may be used herein to describe the relationship of one element(s) to another element(s) as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, the spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "beneath" other elements or features would subsequently be positioned as "above" the other elements or features. Thus, the exemplary term "under" may include both above and below orientations. In addition, the device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein are interpreted accordingly.

[0060] The term used in the text is to describe the purpose of specific embodiments, rather than being intended to limit. As used in the text, unless the context clearly indicates otherwise, the singular "one", "a kind of" and "described" are also intended to include plural forms. In addition, when the term "comprising" is used in this specification, the term description has stated features, integral bodies, steps, operations, elements, assemblies and / or their groups, but does not exclude the existence or addition of one or more other features, other integral bodies, other steps, other operations, other elements, other assemblies and / or their groups. It should also be noted that, as used in the text, the term "substantially", "approximately" and other similar terms are used as approximate terms rather than degree terms, so that the term "substantially", "approximately" and other similar terms are used to explain the measured values, calculated values ​​and / or the inherent deviation of the provided value that a person of ordinary skill in the art can recognize.

[0061] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the exemplary embodiments disclosed herein should not necessarily be interpreted as being limited to the specific illustrated shapes of the regions, but will include deviations in shapes due to, for example, manufacturing. In this manner, the regions illustrated in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and as such, the regions illustrated in the drawings are not necessarily intended to be restrictive.

[0062] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure is a part. Unless explicitly defined as such herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense.

[0063] Figure 1 is a plan view of a display device 1 constructed according to an exemplary embodiment of the present invention.

[0064] Reference Figure 1 , the display device 1 according to the exemplary embodiment includes a substrate 10. The substrate 10 includes a display area DA and a peripheral area PA outside the display area DA.

[0065] A plurality of pixels PX may be arranged in the display area DA of the substrate 10. Various wirings for transmitting electrical signals to be applied to the display area DA may be in the peripheral area PA of the substrate 10.

[0066] The pixel PX may include a first sub-pixel emitting light of a first color, a second sub-pixel emitting light of a second color, and a third sub-pixel emitting light of a third color. In the text, the sub-pixels may also be referred to as "color pixels". The first pixel may be a red pixel, the second pixel may be a green pixel, and the third pixel may be a blue pixel. However, exemplary embodiments are not limited thereto, and the display device 1 may include one or more pixels having sub-pixels emitting light of different colors.

[0067] Figure 2 is constructed according to an exemplary embodiment Figure 1 1 is an equivalent circuit diagram of a representative pixel of the display device 1.

[0068] The pixel PX includes a light emitting device that emits light and a pixel circuit that receives signals from a plurality of wirings and drives the light emitting device. Hereinafter, a pixel PX having an organic light emitting device OLED as a light emitting device is described as an example, but the principles of the present invention may be applied to other types of light emitting devices as will be recognized by those skilled in the art.

[0069] The wiring may include a first scan line GIL for transmitting a first scan signal GI, a second scan line GWL for transmitting a second scan signal GW, a third scan line GBL for transmitting a third scan signal GB, a data line DL for transmitting a data signal DATA, and a power line PL for transmitting a first power supply voltage ELVDD. The present disclosure may also include, but is not limited to, an initialization line VL for transmitting an initialization voltage Vint and a light emitting control line EML for transmitting a light emitting control signal EM.

[0070] The pixel circuit of the pixel PX may include a plurality of transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 , and capacitors Cst and Cse1 , Cse2 . Figure 2 The first electrodes E11, E21, E31, E41, E51, E61 and E71 and the second electrodes E12, E22, E32, E42, E52, E62 and E72 may be source electrodes (source regions) or drain electrodes (drain regions) depending on the type (p-type or n-type) of the transistor and / or operating conditions.

[0071] The first transistor T1 includes a gate electrode G1 connected to a first electrode Cst1 of a storage capacitor Cst, a first electrode E11 connected to a power line PL via a fifth transistor T5, and a second electrode E12 electrically connected to a pixel electrode of the organic light emitting device OLED via a sixth transistor T6. The first transistor T1 functions as a driving transistor and receives a data signal DATA to supply current to the organic light emitting device OLED according to a switching operation of the second transistor T2.

[0072] The second transistor T2 includes a gate electrode G2 connected to the second scan line GWL, a first electrode E21 connected to the data line DL, and a second electrode E22 connected to the first electrode E11 of the first transistor T1. The second transistor T2 is turned on in response to a second scan signal GW received through the second scan line GWL, and performs a switching operation to transmit a data signal DATA transmitted to the data line DL to the first electrode E11 of the first transistor T1.

[0073] The third transistor T3 includes a gate electrode G3 connected to the second scan line GWL, a first electrode E31 connected to the second electrode E12 of the first transistor T1, and a second electrode E42 connected to the fourth transistor T4, the first electrode Cst1 of the storage capacitor Cst, and the second electrode E32 of the gate electrode G1 of the first transistor T1. The third transistor T3 is turned on in response to the second scan signal GW received through the second scan line GWL to diode-connect the first transistor T1.

[0074] The fourth transistor T4 includes a gate electrode G4 connected to the first scan line GIL, a first electrode E41 connected to the initialization line VL, and a second electrode E42 connected to the second electrode E32 of the third transistor T3, the first electrode Cst1 of the storage capacitor Cst, and the gate electrode G1 of the first transistor T1. The fourth transistor T4 is turned on in response to the first scan signal GI received through the first scan line GIL to transfer the initialization voltage Vint to the gate electrode G1 of the first transistor T1 and initialize the gate voltage of the first transistor T1.

[0075] The fifth transistor T5 includes a gate electrode G5 connected to the emission control line EML, a first electrode E51 connected to the power line PL, and a second electrode E52 connected to the first electrode E11 of the first transistor T1 and the second electrode E22 of the second transistor T2.

[0076] The sixth transistor T6 includes a gate electrode G6 connected to the emission control line EML, a first electrode E61 connected to the second electrode E12 of the first transistor T1 and the first electrode E31 of the third transistor T3 , and a second electrode E62 connected to a pixel electrode of the organic light emitting device OLED.

[0077] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on in response to the light emission control signal EM received through the light emission control line EML, so that current flows to the organic light emitting device OLED.

[0078] The seventh transistor T7 includes a gate electrode G7 connected to the third scan line GBL, a first electrode E71 connected to the second electrode E62 of the sixth transistor T6 and the pixel electrode of the organic light emitting device OLED, and a second electrode E72 connected to the initialization line VL. The seventh transistor T7 is turned on in response to the third scan signal GB received through the third scan line GBL to transmit the initialization voltage Vint to the pixel electrode of the organic light emitting device OLED and initialize the voltage of the pixel electrode of the organic light emitting device OLED.

[0079] The third scan line GBL connected to the gate electrode G7 of the seventh transistor T7 may be the first scan line GIL or the second scan line GWL of the next or previous row, and the third scan signal GB may be the first scan signal GI or the second scan signal GW of the next or previous row. The seventh transistor T7 may be omitted.

[0080] The storage capacitor Cst includes a first electrode Cst1 connected to the gate electrode G1 of the first transistor T1 and a second electrode Cst2 connected to the power line PL. The first electrode Cst1 of the storage capacitor Cst is also connected to the second electrode E32 of the third transistor T3 and the second electrode E42 of the fourth transistor T4.

[0081] The first compensation capacitor Cse1 includes a first electrode Cse11 connected to the first electrode E11 of the first transistor T1 and a second electrode Cse12 connected to the power line PL. The first electrode Cse11 of the first compensation capacitor Cse1 is also connected to the second electrode E22 of the second transistor T2 and the second electrode E52 of the fifth transistor T5.

[0082] The second compensation capacitor Cse2 is connected in parallel with the first compensation capacitor Cse1. The second compensation capacitor Cse2 includes a first electrode Cse21 connected to the first electrode E11 of the first transistor T1 and a second electrode Cse22 connected to the power line PL. The first electrode Cse21 of the second compensation capacitor Cse2 is also connected to the second electrode E22 of the second transistor T2 and the second electrode E52 of the fifth transistor T5.

[0083] The organic light emitting device OLED includes a pixel electrode and a common electrode facing the pixel electrode, and the common electrode may receive a second power voltage ELVSS.

[0084] The intermediate layer is between the pixel electrode and the common electrode of the organic light emitting device OLED. The intermediate layer includes a light-emitting organic emission layer, and may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). However, the illustrated embodiment is not limited thereto, and various functional layers may be between the pixel electrode and the common electrode.

[0085] The organic emission layer may emit red light, green light, or blue light. However, the present disclosure is not limited thereto, and the organic emission layer may emit white light. In this case, the organic emission layer may include a structure in which a light-emitting material emitting red light, a light-emitting material emitting green light, and a light-emitting material emitting blue light are stacked, or may include a structure in which a light-emitting material emitting red light, a light-emitting material emitting green light, and a light-emitting material emitting blue light are mixed.

[0086] The organic light emitting device OLED receives the driving current Ioled from the first transistor T1 and emits light of a predetermined color to display an image.

[0087] Figure 3 is a diagram showing a method according to an exemplary embodiment Figure 2 Timing diagram of pixel driving.

[0088] Reference Figure 3 , the pixel PX performs hysteresis compensation from the first period t1 to the fourth period t4, initialization in the fifth period t5, threshold voltage compensation and data writing in the sixth period t6, and light emission in the eighth period t8 within one frame. Before the eighth period t8 for light emission, initialization of the light emitting device in the seventh period t7 may also be performed.

[0089] During the hysteresis compensation from the first period t1 to the fourth period t4 , initialization and threshold voltage compensation are repeatedly performed on the pixel PX.

[0090] In the first period t1 and the third period t3, the first scan signal GI is supplied to the first scan line GIL, and the initialization voltage Vint is supplied to the gate electrode G1 of the first transistor T1 through the fourth transistor T4 turned on in response to the first scan signal GI.

[0091] Furthermore, in the second period t2 and the fourth period t4 , the second scan signal GW is supplied to the second scan line GWL, and the first transistor T1 is diode-connected through the third transistor T3 turned on in response to the second scan signal GW to compensate for the threshold voltage of the first transistor T1 .

[0092] During the first period t1 to the fourth period t4 , before the data signal is applied to the pixel PX, a turn-on bias voltage is applied to the gate electrode G1 of the first transistor T1 , and hysteresis compensation of the first transistor T1 is performed.

[0093] Thereafter, in a fifth period t5, a first scan signal GI is supplied to the first scan line GIL, and an initialization voltage Vint is supplied to the gate electrode G1 of the first transistor T1 through the fourth transistor T4 turned on in response to the first scan signal GI. The first compensation capacitor Cse1 prevents a voltage drop of the first electrode E11 of the first transistor T1.

[0094] Then, in the sixth period t6, the second scan signal GW is supplied to the second scan line GWL, and the second transistor T2 and the third transistor T3 are turned on. When the third transistor T3 is turned on, the first transistor T1 is connected in a diode manner. When the first transistor T1 is connected in a diode manner, a compensation voltage corresponding to the data signal DATA and a threshold voltage of the first transistor T1 are applied to the gate electrode G1 of the first transistor T1. Here, a charge corresponding to the difference between the first power supply voltage ELVDD and the compensation voltage is stored in the storage capacitor Cst.

[0095] In the seventh period t7, the third scan signal GB is supplied to the third scan line GBL, and the seventh transistor T7 is turned on. The initialization voltage Vint is supplied to the pixel electrode of the organic light emitting device OLED through the seventh transistor T7.

[0096] In the eighth period t8, the fifth transistor T5 and the sixth transistor T6 are turned on by the light emission control signal EM supplied from the light emission control line EML. Therefore, a driving current Ioled according to a voltage difference between a voltage of a gate electrode G1 of the first transistor T1 and the first power supply voltage ELVDD is generated in the first transistor T1, and the driving current Ioled is supplied to the organic light emitting device OLED through the sixth transistor T6.

[0097] exist Figure 3 In the exemplary embodiment, in the seventh period t7, the third scan signal GB is supplied to the third scan line GBL, but the present disclosure is not limited thereto. The seventh period t7 overlaps at least one of the second period t2, the fourth period t4, and the sixth period t6, and the second scan signal GW may be supplied to the third scan line GBL.

[0098] Figure 4 is a diagram showing a comparative example Figure 2 Timing diagram of pixel driving. Figure 5 is a graph showing hysteresis characteristics of a thin film transistor, and Figure 6 is a graph showing a brightness problem of a display device due to hysteresis characteristics of a thin film transistor.

[0099] When the display device displays an image, color streaking (afterimage) of a predetermined color occurs due to a difference between time points in which pixels emitting light of different colors (hereinafter, referred to as 'color pixels') emit light and hysteresis characteristics of thin film transistors.

[0100] according to Figure 4 The pixel driving method of the comparative example performs initialization of the first transistor T1 (t5'), threshold voltage compensation and data writing (t6'), initialization of the light emitting device (t7'), and light emission (t8'), without Figure 3 Hysteresis compensation (t1 to t4) of the pixel driving method of the exemplary embodiment.

[0101] Reference Figure 5 and Figure 6 When the second scan signal GW is supplied to the second scan line GWL, the data signal is applied and the threshold voltage of the first transistor T1 is compensated. Here, due to the hysteresis characteristics of the thin film transistor, the threshold voltage changes depending on whether the previous light emitting state is the on state or the off state.

[0102] Therefore, when the pixel changes from black display to white display, a brightness difference occurs between white brightness of a first frame in which the first transistor T1 receives a data signal in an off state and white brightness of a second frame in which the first transistor T1 receives a data signal in an on state.

[0103] In order to solve the problem caused by the hysteresis characteristic of the thin film transistor, the exemplary embodiment applies an arbitrary on-bias voltage to the first transistor T1 at a predetermined number of times before the threshold voltage compensation for shifting the threshold voltage of the first transistor T1 in the same direction and compensating for the hysteresis. The bias voltage Vgs represents the difference between the voltage Vgate of the gate electrode G1 of the first transistor T1 and the voltage Vsource of the first electrode E11 (Vsource-Vgate=Vgs). The on-bias voltage is a bias voltage greater than the threshold voltage Vth.

[0104] Go to Figure 3 , when the initialization voltage Vint is applied to the gate electrode G1 of the first transistor T1 in the fifth period t5, the voltage Vgate of the gate electrode G1 of the first transistor T1 is the difference between the voltage before the initialization voltage is applied and the initialization voltage Vint. Through the parasitic capacitance of the first transistor T1, the voltage of the gate electrode G1 of the first transistor T1 drops, and the voltage of the first electrode E11 of the first transistor T1 also drops. Here, the bias voltage of the first transistor T1 drops. Therefore, the output current of the first transistor T1 can be reduced.

[0105] Therefore, for voltage stability between the power line PL of the pixel PX and the first electrode E11 of the first transistor T1, the exemplary embodiment adds the first compensation capacitor Cse1 and the second compensation capacitor Cse2. The first compensation capacitor Cse1 and the second compensation capacitor Cse2 can reduce the voltage fluctuation in the first electrode E11 of the first transistor T1, so that the on-bias voltage can be ensured. The higher the on-bias voltage, the greater the amount of light emitted by the pixel, and the deviation between the brightness of the first frame displaying white after displaying black and the brightness of the second frame can be reduced.

[0106] The illustrated embodiment discloses the parallel connection of the first compensation capacitor Cse1 and the second compensation capacitor Cse2, but is not limited thereto. The exemplary embodiment may include only one of the first compensation capacitor Cse1 and the second compensation capacitor Cse2. Compared to the exemplary embodiment including only one compensation capacitor, the illustrated embodiment in which the first compensation capacitor Cse1 and the second compensation capacitor Cse2 are connected in parallel to each other can increase the capacitance of the compensation capacitor to further enhance the afterimage improvement effect.

[0107] Figure 7 is constructed according to an exemplary embodiment Figure 2 0 is a plan view of a pixel circuit of a pixel shown in . Figure 8 yes Figure 7 FIG. 1 is an enlarged plan view of a first transistor T1, a storage capacitor Cst, and compensation capacitors Cse1 and Cse2. Fig. 9 It is along Figure 8 A cross-sectional view taken along line AA'.

[0108] The pixels PX are arranged at points where a plurality of wirings extending in a first direction and a plurality of wirings extending in a second direction intersecting the first direction intersect each other. The first scan line GIL, the second scan line GWL, the third scan line GBL, the initialization line VL, and the emission control line EML extend in the second direction. The data line DL and the power line PL extend in the first direction.

[0109] Each of the first to seventh transistors T1 to T7 includes: a semiconductor layer including a source region, a drain region, and a channel region between the source region and the drain region; and a gate electrode arranged to be insulated from the semiconductor layer at a position corresponding to the channel region. The source region may be Figure 2 The source region and the drain region are one of the first electrode and the second electrode shown in , and the drain region may be the other of the first electrode and the second electrode. Hereinafter, for convenience of description, the source region and the drain region are referred to as the first electrode and the second electrode.

[0110] On the substrate 10 , a semiconductor layer may be formed on the first insulating layer 12 .

[0111] The substrate 10 may be a flexible substrate. The substrate 10 may be a plastic substrate. The substrate 10 may be formed into a stacked structure of an organic layer and an inorganic layer. For example, the substrate 10 may be a stacked structure of an organic layer / inorganic layer / organic layer / inorganic layer. The inorganic layer as the uppermost layer of the substrate 10 may be a barrier layer.

[0112] The semiconductor layer is made of, for example, polysilicon and includes a channel region not doped with impurities and a first electrode and a second electrode doped with impurities. The impurities may vary depending on the type of transistor and may include n-type impurities or p-type impurities. The semiconductor layers of the first transistor T1 to the seventh transistor T7 may be arranged on the same layer and may be bent into various shapes when connected to each other.

[0113] The conductive layer 110 used as the second electrode Cse22 of the second compensation capacitor Cse2 may be disposed between the substrate 10 and the semiconductor layer. The conductive layer 110 may be disposed on the buffer layer 11 (see Fig. 9 The buffer layer 11 may be omitted.

[0114] A second insulating layer 13 is arranged between the semiconductor layer and the gate electrode (see Fig. 9 ).

[0115] The first scan line GIL, the second scan line GWL, the third scan line GBL, and the light emission control line EML extend in the second direction over the same layer as the gate electrodes G1 to G7 of the first to seventh transistors T1 to T7. Fig. 9 ) on the gate electrodes G1 to G7 of the first to seventh transistors T1 to T7.

[0116] The first transistor T1 includes a semiconductor layer and a gate electrode G1, the semiconductor layer including a first electrode E11, a second electrode E12, and a channel region C1. In a plan view, the gate electrode G1 of the first transistor T1 overlaps the channel region C1. The semiconductor layer of the first transistor T1 has a curve between the first electrode E11 and the second electrode E12, so that the channel region C1 can be formed long and the driving range of the gate voltage applied to the gate electrode G1 can be widened. The shape of the semiconductor layer of the first transistor T1 can have various shapes, such as a curve shape 'C', 'S', 'M' or 'W' etc.

[0117] The second transistor T2 includes a semiconductor layer and a gate electrode G2, wherein the semiconductor layer includes a first electrode E21, a second electrode E22, and a channel region C2. In a plan view, the gate electrode G2 of the second transistor T2 overlaps the channel region C2. The first electrode E21 of the second transistor T2 is connected to the fourth insulating layer 15 through the second insulating layer 13 (see FIG. Fig. 9) is electrically connected to the data line DL. The second electrode E22 of the second transistor T2 is connected to the first electrode E11 of the first transistor T1.

[0118] The third transistor T3 includes a semiconductor layer and a gate electrode G3, the semiconductor layer including a first electrode E31, a second electrode E32 and a channel region C3. In a plan view, the gate electrode G3 of the third transistor T3 overlaps the channel region C3 and is formed by a portion of the second scan line GWL. The first electrode E31 of the third transistor T3 is connected to the second electrode E12 of the first transistor T1, and the second electrode E32 is electrically connected to the gate electrode G1 of the first transistor T1 through a connecting electrode. The connecting electrode connects the second electrode E32 of the third transistor T3 to the gate electrode G1 of the first transistor T1 through a contact hole of the second insulating layer 13 to the fourth insulating layer 15 exposing the second electrode E32 of the third transistor T3 and a contact hole of the third insulating layer 14 and the fourth insulating layer 15 exposing the gate electrode G1 of the first transistor T1.

[0119] The fourth transistor T4 includes a semiconductor layer and a gate electrode G4, the semiconductor layer including a first electrode E41, a second electrode E42 and a channel region C4. In a plan view, the gate electrode G4 of the fourth transistor T4 overlaps the channel region C4 and is formed by a portion of the first scan line GIL. The first electrode E41 of the fourth transistor T4 is electrically connected to the initialization line VL through a connecting electrode, and the second electrode E42 is electrically connected to the second electrode E32 of the third transistor T3 and the gate electrode G1 of the first transistor T1. The connecting electrode connects the initialization line VL to the first electrode E41 of the fourth transistor T4 through a contact hole of the second insulating layer 13 to the fourth insulating layer 15 exposing the first electrode E41 of the fourth transistor T4 and a contact hole of the fourth insulating layer 15 exposing the initialization line VL. The initialization line VL is arranged above the same layer as the layer of the second electrode Cst2 of the storage capacitor Cst.

[0120] The fifth transistor T5 includes a semiconductor layer and a gate electrode G5, the semiconductor layer including a first electrode E51, a second electrode E52 and a channel region C5. In a plan view, the gate electrode G5 of the fifth transistor T5 overlaps the channel region C5 and is formed by a portion of the light emission control line EML. The first electrode E51 of the fifth transistor T5 is electrically connected to the power line PL through a contact hole of the second insulating layer 13 to the fourth insulating layer 15 that exposes a portion of the first electrode E51, and the second electrode E52 is connected to the first electrode E11 of the first transistor T1.

[0121] The sixth transistor T6 includes a semiconductor layer and a gate electrode G6, the semiconductor layer including a first electrode E61, a second electrode E62 and a channel region C6. In a plan view, the gate electrode G6 of the sixth transistor T6 overlaps the channel region C6 and is formed by a portion of the light emitting control line EML. The first electrode E61 of the sixth transistor T6 is connected to the second electrode E12 of the first transistor T1, and the second electrode E62 is electrically connected to the pixel electrode of the organic light emitting device OLED. The second electrode E62 of the sixth transistor T6 is electrically connected to the connection electrode above the fourth insulating layer 15 through a contact hole of the second insulating layer 13 to the fourth insulating layer 15 that exposes a portion of the second electrode E62. The pixel electrode is electrically connected to the second electrode E62 of the sixth transistor T6 by being electrically connected to the connection electrode via a via hole of the fifth insulating layer above the connection electrode connected to the second electrode E62 of the sixth transistor T6.

[0122] The seventh transistor T7 includes a semiconductor layer and a gate electrode G7, the semiconductor layer includes a first electrode E71, a second electrode E72 and a channel region C7. In a plan view, the gate electrode G7 of the seventh transistor T7 overlaps the channel region C7 and is formed by a portion of the third scan line GBL. The second electrode E72 of the seventh transistor T7 is connected to the first electrode E41 of the fourth transistor T4, and the first electrode E71 is connected to the second electrode E62 of the sixth transistor T6.

[0123] The first electrode Cst1 of the storage capacitor Cst is the gate electrode G1 of the first transistor T1. That is, it can be understood that the first electrode Cst1 of the storage capacitor Cst and the gate electrode G1 of the first transistor T1 are integrated. The first electrode Cst1 of the storage capacitor Cst is formed in a square shape separated from the adjacent pixel, and is formed on the same layer as the first scan line GIL, the second scan line GWL, the third scan line GBL, and the light emission control line EML, and is formed of the same material as the first scan line GIL, the second scan line GWL, the third scan line GBL, and the light emission control line EML.

[0124] The second electrode Cst2 of the storage capacitor Cst is connected to the second electrodes Cst2 of the pixels adjacent to each other in the second direction, i.e., the pixels on the same row. The second electrode Cst2 of the storage capacitor Cst overlaps the first electrode Cst1 so as to cover the entire first electrode Cst1, and vertically overlaps the first transistor T1 according to the plan view and the cross-sectional view. The third insulating layer 14 between the first electrode Cst1 and the second electrode Cst2 of the storage capacitor Cst serves as a dielectric layer. The second electrode Cst2 of the storage capacitor Cst has an opening at a position corresponding to the contact hole exposing a portion of the first electrode Cst1.

[0125] The fourth insulating layer 15 is over the second electrode Cst2 of the storage capacitor Cst. The data line DL and the power line PL extend in the first direction over the fourth insulating layer 15. The power line PL partially overlaps the second electrode Cst2 of the storage capacitor Cst.

[0126] The second electrode Cst2 of the storage capacitor Cst is electrically connected to the power line PL through the contact hole CH1 of the fourth insulating layer 15 exposing a portion of the second electrode Cst2. Therefore, the power line PL serves as a power line in the first direction, and the second electrode Cst2 of the storage capacitor Cst serves as a power line in the second direction. Therefore, the power line PL as a whole may have a mesh structure. The power line PL is electrically connected to the first electrode E51 of the fifth transistor T5.

[0127] The first electrode Cse11 of the first compensation capacitor Cse1 is at least a portion of the first electrode E11 of the first transistor T1. That is, it can be understood that the first electrode Cse11 of the first compensation capacitor Cse1 and the first electrode E11 of the first transistor T1 are integrated.

[0128] The second electrode Cse12 of the first compensation capacitor Cse1 is an electrode layer extending from the second electrode Cst2 of the storage capacitor Cst and covering at least a portion of the first electrode E11 of the first transistor T1. That is, it can be understood that the second electrode Cse12 of the first compensation capacitor Cse1 and the second electrode Cst2 of the storage capacitor Cst are integrated. Therefore, the second electrode Cse12 of the first compensation capacitor Cse1 is electrically connected to the power line PL.

[0129] The first electrode Cse21 of the second compensation capacitor Cse2 is at least a portion of the first electrode E11 of the first transistor T1. That is, it can be understood that the first electrode Cse21 of the second compensation capacitor Cse2 and the first electrode E11 of the first transistor T1 are integrated.

[0130] The second electrode Cse22 of the second compensation capacitor Cse2 is an electrode layer 110 arranged below the first electrode E11 of the first transistor T1 so as to overlap with the first electrode E11 of the first transistor T1. The second electrode Cse22 of the second compensation capacitor Cse2 does not overlap with the channel region C1 of the first transistor T1. The second electrode Cse22 of the second compensation capacitor Cse2 is electrically connected to the second electrode Cse12 of the first compensation capacitor Cse1 through the contact hole CH2 of the first insulating layer 12 to the third insulating layer 14. Therefore, the second electrode Cse22 of the second compensation capacitor Cse2 is electrically connected to the power line PL.

[0131] The initialization line VL extends in the second direction over the same layer as the second electrode Cst2 of the storage capacitor Cst. Fig. 9 ), the data line DL and the power line PL extend in the first direction.

[0132] The pixel PX may include a light shielding member 120 that covers a portion of at least one of the first electrode E21 and the second electrode E22 of the second transistor T2, and / or a portion of at least one of the first electrode E31 and the second electrode E32 of the third transistor T3, and / or a portion of at least one of the first electrode E41 and the second electrode E42 of the fourth transistor T4.

[0133] The light shielding member 120 may be above the same layer as the layer of the initialization line VL. The light shielding member 120 may include the same material as the material of the initialization line VL. The light shielding member 120 may be electrically connected to the power line PL or the initialization line VL. The light shielding member 120 is connected to the power line PL or the initialization line VL and receives a constant voltage, so that the second transistor T2, the third transistor T3, and the fourth transistor T4 can be prevented from being affected by other peripheral electrical signals. That is, the light shielding member 120 can improve the operating characteristics of the circuit of the pixel PX.

[0134] Reference Figure 8 and Fig. 9 , the first transistor T1 of the pixel PX includes: a semiconductor layer including a first electrode E11, a second electrode E12, and a channel region C1; and a gate electrode G1, the gate electrode G1 corresponding to the channel region C1. In the plan view and the cross-sectional view, the storage capacitor Cst, the first compensation capacitor Cse1, and the second compensation capacitor Cse2 vertically overlap the first transistor T1. The storage capacitor Cst includes a first electrode Cst1 as a lower electrode and a second electrode Cst2 as an upper electrode. The first compensation capacitor Cse1 includes a first electrode Cse11 as a lower electrode and a second electrode Cse12 as an upper electrode. The second compensation capacitor Cse2 includes a second electrode Cse22 as a lower electrode and a first electrode Cse21 as an upper electrode.

[0135] The electrode layer 110 overlaps at least the first electrode E11 of the first transistor T1. The electrode layer 111 includes at least a first region 111-1 overlapping at least the gate electrode G1 of the first transistor T1 and a second region 111-2 overlapping at least the first electrode E11 of the first transistor T1. A portion of the electrode layer 110 and the second region 111-2 of the electrode layer 111 overlap the data line DL.

[0136] The first region 111-1 of the electrode layer 111 functions as a second electrode Cst2 of the storage capacitor Cst. The second region 111-2 of the electrode layer 111 functions as a second electrode Cse12 of the first compensation capacitor Cse1. The electrode layer 111 is electrically connected to the power line PL through the contact hole CH1.

[0137] The storage capacitor Cst is formed by a first electrode Cst1 as a gate electrode G1 of the first transistor T1 and a second electrode Cst2 opposite to the first electrode Cst1. The first compensation capacitor Cse1 is formed by a first electrode Cse11 as a first electrode E11 of the first transistor T1 and a second electrode Cse12 opposite to the first electrode Cse11. The second electrode Cst2 of the storage capacitor Cst and the second electrode Cse12 of the first compensation capacitor Cse1 are electrically connected to the power line PL through a contact hole CH1 of the fourth insulating layer 15.

[0138] The electrode layer 110 serves as a second electrode Cse22 of the second compensation capacitor Cse2. The electrode layer 110 is electrically connected to the power line PL through the contact hole CH2. The second compensation capacitor Cse2 is formed by a first electrode Cse21 as the first electrode E11 of the first transistor T1 and a second electrode Cse22 opposite to the first electrode Cse21.

[0139] In an exemplary embodiment, the capacitance of the first compensation capacitor Cse1 and the second compensation capacitor Cse2 is designed differently for each color pixel, and the on-bias voltage for each color pixel can be set differently, so that the amount of light emission for each color pixel can be adjusted. Therefore, the difference between the time points of light emission caused by the deviation of the output current of each color pixel can be reduced. By changing the amount of the facing area (overlapping area) of the electrodes, the capacitance of the first compensation capacitor Cse1 and the second compensation capacitor Cse2 for each color pixel can be achieved.

[0140] Fig.10 is a plan view of pixel circuits of different color pixels constructed according to an exemplary embodiment. Fig.11 yes Fig.10 FIG. 1 is an enlarged plan view of a first transistor T1, a storage capacitor Cst, and compensation capacitors Cse1 and Cse2. Fig.12 It is along Fig.11 The sectional view taken along the line BB' and the line CC' of FIG. Figures 7 to 9 Description of the content A detailed description of the duplicate content.

[0141] Fig.10An example is shown in which a first pixel PX1 is arranged in a first pixel region of a substrate 10 and a second pixel PX2 is arranged in a second pixel region adjacent to the first pixel region. A third pixel PX3 may be arranged in a third pixel region adjacent to the second pixel region. The first to third pixel regions may be arranged sequentially along the second direction. Figure 2 As shown in FIG. 1 , each of the first to third pixels PX1 to PX3 includes a light emitting device and a pixel circuit connected to the light emitting device. Fig.10 In the figure, for convenience of explanation, the pixel circuit of the first pixel PX1 is arranged in the first pixel area, and the pixel circuit of the second pixel PX2 is arranged in the second pixel area.

[0142] exist Fig.11 and Fig.12 In the drawings, for convenience of explanation, different reference numerals are used to distinguish between the pixel circuit of the first pixel PX1 and the pixel circuit of the second pixel PX2.

[0143] The length and width (or area) of the electrode layer 110a of the first pixel PX1 are substantially the same as the length and width (or area) of the electrode layer 110b of the second pixel PX2. The length and width (or area) of the electrode layer 111a of the first pixel PX1 are substantially the same as the length and width (or area) of the electrode layer 111b of the second pixel PX2. Here, the length is in the first direction and the width is in the second direction.

[0144] The width W2 or area of ​​the first electrode E11_2 of the first transistor T1 of the second pixel PX2 is greater than the width W1 or area of ​​the first electrode E11_1 of the first transistor T1 of the first pixel PX1. Therefore, the facing area of ​​the first electrode E11_2 of the first transistor T1 of the second pixel PX2 and each of the electrode layers 110b and 111b is greater than the facing area of ​​the first electrode E11_1 of the first transistor T1 of the first pixel PX1 and each of the electrode layers 110a and 111a. Therefore, the capacitance capacity of the first compensation capacitor Cse1 of the second pixel PX2 is greater than the capacitance capacity of the first compensation capacitor Cse1 of the first pixel PX1, and the capacitance capacity of the second compensation capacitor Cse2 of the second pixel PX2 is greater than the capacitance capacity of the second compensation capacitor Cse2 of the first pixel PX1.

[0145] By adjusting the width or area of ​​the first electrode E11 of the first transistor T1 of the first pixel PX1 and the second pixel PX2, the illustrated embodiment can derive the conduction bias voltage deviation between the first pixel PX1 and the second pixel PX2 by using the capacitance difference between the first compensation capacitor Cse1 and the second compensation capacitor Cse2 of the first pixel PX1 and the second pixel PX2. Therefore, a strong conduction bias voltage is applied to the second pixel PX2 instead of the first pixel PX1 to speed up the response rate, thereby reducing the difference in light emission delay between pixels.

[0146] The capacitance of the first compensation capacitor Cse1 and the second compensation capacitor Cse2 of the third pixel PX3 in the third pixel area may be substantially the same as or different from the capacitance of the first compensation capacitor Cse1 and the second compensation capacitor Cse2 of the first pixel PX1 or the capacitance of the first compensation capacitor Cse1 and the second compensation capacitor Cse2 of the second pixel PX2. That is, the width or area of ​​the first electrode E11 of the first transistor T1 of the third pixel PX3 may be substantially the same as or different from the width or area of ​​the first electrode E11 of the first transistor T1 of the first pixel PX1 or the second pixel PX2. The facing area of ​​the first electrode E11_1 of the first transistor T1 of the first pixel PX1 and each of the electrode layer (first electrode layer) 110a and the electrode layer (second electrode layer) 111a may be substantially the same as or different from the facing area of ​​the first electrode of the first transistor of the third pixel PX3 and each of the first electrode layer and the second electrode layer of the third pixel PX3. A facing area between the first electrode E11_2 of the first transistor T1 of the second pixel PX2 and each of the electrode layers 110 b and 111 b may be substantially the same as or different from a facing area between the first electrode of the first transistor T1 of the third pixel PX3 and each of the first and second electrode layers of the third pixel PX3 .

[0147] Fig.13 is an enlarged plan view of a first transistor T1 , a storage capacitor Cst, and compensation capacitors Cse1 and Cse2 configured according to another exemplary embodiment. Fig.14 It is along Fig.13 Hereinafter, contents different from the above-described exemplary embodiment will be mainly described to avoid redundancy.

[0148] Fig.13 and Fig.14 The exemplary embodiment shown in Fig.11 and Fig.12 The exemplary embodiment shown in FIG. 1 is different in that the size (area) of the electrode layer 111 a of the first pixel PX1 is different from the electrode layer 111 b of the second pixel PX2 .

[0149] The width W4 or area of ​​the electrode layer 111b of the second pixel PX2 is greater than the width W3 or area of ​​the electrode layer 111a of the first pixel PX1. The electrode layer 111b of the second pixel PX2 covers both the gate electrode G1_2 and the first electrode E11_2 of the first transistor T1, while the electrode layer 111a of the first pixel PX1 covers the gate electrode G1_1 of the first transistor T1 and a portion of the first electrode E11_1 of the first transistor T1. The width of the first electrode E11_2 of the first transistor T1 of the second pixel PX2 is greater than the width of the first electrode E11_1 of the first transistor T1 of the first pixel PX1. In another exemplary embodiment, the width of the first electrode E11_1 of the first transistor T1 of the first pixel PX1 is substantially the same as the width of the first electrode E11_2 of the first transistor T1 of the second pixel PX2.

[0150] Therefore, the facing area between the first electrode E11_2 of the first transistor T1 of the second pixel PX2 and the electrode layer 111b is larger than the facing area between the first electrode E11_1 of the first transistor T1 of the first pixel PX1 and the electrode layer 111a. Therefore, the capacitance of the first compensation capacitor Cse1 of the second pixel PX2 is larger than the capacitance of the first compensation capacitor Cse1 of the first pixel PX1.

[0151] By adjusting the width or area of ​​the second electrode Cse12 of the first compensation capacitor Cse1 of the first pixel PX1 and the second pixel PX2, the illustrated embodiment can derive the conduction bias voltage deviation between the first pixel PX1 and the second pixel PX2 by using the capacitance difference between the first compensation capacitor Cse1 and the second compensation capacitor Cse2 of the first pixel PX1 and the second pixel PX2. Therefore, a strong conduction bias voltage is applied to the second pixel PX2 instead of the first pixel PX1 to speed up the response rate, thereby reducing the difference in light emission delay between pixels.

[0152] The capacitance of the first compensation capacitor Cse1 of the third pixel PX3 in the third pixel area may be substantially the same as or different from the capacitance of the first compensation capacitor Cse1 of the first pixel PX1 or the capacitance of the first compensation capacitor Cse1 of the second pixel PX2. That is, the width or area of ​​the second electrode Cse12 of the first compensation capacitor Cse1 of the third pixel PX3 may be substantially the same as or different from the width or area of ​​the second electrode Cse12 of the first compensation capacitor Cse1 of the first pixel PX1 or the second pixel PX2. The facing area of ​​the first electrode E11_2 of the first transistor T1 of the second pixel PX2 and the electrode layer (second electrode layer) 111b may be substantially the same as or different from the facing area of ​​the first electrode of the first transistor of the third pixel PX3 and the second electrode layer of the third pixel PX3.

[0153] Fig.15 According to another exemplary embodiment Figure 2 0 is a plan view of a pixel circuit of a pixel shown in . Fig.16 yes Fig.15 FIG. 1 is an enlarged plan view of a first transistor T1, a storage capacitor Cst, and compensation capacitors Cse1 and Cse2. Fig.17 It is along Fig.16 The following mainly describes the cross-sectional view taken along the line F-F'. Figures 7 to 9 The exemplary embodiments differ in content to avoid redundancy.

[0154] Figures 15 to 17 An exemplary embodiment of Figures 7 to 9 The exemplary embodiment of FIG. 1 is different in that the electrode layer 110 of the pixel PX overlaps the first electrode E11 and the channel region C1 of the first transistor T1.

[0155] The electrode layer 110 includes a first region 110 - 1 overlapping at least the first electrode E11 of the first transistor T1 and a second region 110 - 2 extending from the first region 110 - 1 and overlapping the channel region C1 of the first transistor T1 .

[0156] The first region 110-1 of the electrode layer 110 is used as the second electrode Cse22 of the second compensation capacitor Cse2. The second region 110-2 of the electrode layer 110 is used as a bottom gate electrode for controlling the carrier movement of the channel region C1 together with the gate electrode G1 of the first transistor T1. Since the electrode layer 110 receives the first power supply voltage ELVDD, the on-bias voltage of the first transistor T1 can be further ensured.

[0157] Fig.18 is a plan view of a pixel circuit of a different color pixel constructed according to another exemplary embodiment. Fig.19 yes Fig.18 FIG. 1 is an enlarged plan view of a first transistor T1, a storage capacitor Cst, and compensation capacitors Cse1 and Cse2. Fig. 20 It is along Fig.19 A cross-sectional view taken along line G-G' and line H-H'.

[0158] Figures 18 to 20 Examples and Figures 10 to 12 The embodiment of FIG. 1 is different in that the electrode layer 110 of the pixel PX overlaps the first electrode E11 and the channel region C1 of the first transistor T1.

[0159] exist Figures 18 to 20In the illustrated embodiment, the width W2 or area of ​​the first electrode E11_2 of the first transistor T1 of the second pixel PX2 is greater than the width W1 or area of ​​the first electrode E11_1 of the first transistor T1 of the first pixel PX1. That is, by adjusting the width or area of ​​the first electrode E11 of the first transistor T1 of the first pixel PX1 and the second pixel PX2, the illustrated embodiment can derive the conduction bias voltage deviation between the first pixel PX1 and the second pixel PX2 by using the capacitance difference between the first compensation capacitor Cse1 and the second compensation capacitor Cse2 of the first pixel PX1 and the second pixel PX2. Therefore, a strong conduction bias voltage is applied to the second pixel PX2 instead of the first pixel PX1 to speed up the response rate, thereby reducing the difference in light emission delay between pixels.

[0160] In addition, in the illustrated embodiment, the electrode layer 110 overlaps the first electrode E11 and the channel region C1 of the first transistor T1, so that a portion of the electrode layer 110 is used as the second electrode Cse22 of the second compensation capacitor Cse2, and the other portion is used as a bottom gate electrode for controlling the movement of carriers in the channel region C1. Therefore, since the electrode layer 110 receives the first power supply voltage ELVDD, the turn-on bias voltage of the first transistor T1 can be further ensured.

[0161] Fig.21 is an enlarged plan view of a first transistor T1, a storage capacitor Cst, and compensation capacitors Cse1 and Cse2 according to another exemplary embodiment. Fig. 22 It is along Fig.21 Hereinafter, contents different from the above-described exemplary embodiment will be mainly described to avoid redundancy.

[0162] Fig.21 and Fig. 22 The embodiments shown in Fig.19 and Fig. 20 The embodiment shown in FIG. 1 is different in that the size (area) of the electrode layer 111 a of the first pixel PX1 is different from the electrode layer 111 b of the second pixel PX2 .

[0163] The width W4 or area of ​​the electrode layer 111b of the second pixel PX2 is greater than the width W3 or area of ​​the electrode layer 111a of the first pixel PX1. That is, by adjusting the width or area of ​​the second electrode Cse12 of the first compensation capacitor Cse1 of the first pixel PX1 and the second pixel PX2, the illustrated embodiment can derive the conduction bias voltage deviation between the first pixel PX1 and the second pixel PX2 by using the capacitance difference between the first compensation capacitor Cse1 of the first pixel PX1 and the second pixel PX2. Therefore, a strong conduction bias voltage is applied to the second pixel PX2 instead of the first pixel PX1 to speed up the response rate, thereby reducing the difference in light emission delay between pixels.

[0164] Moreover, the capacitance of the first compensation capacitor Cse1 and the second compensation capacitor Cse2 of the third pixel PX3 in the third pixel area may be substantially the same as or different from the capacitance of the first compensation capacitor Cse1 and the second compensation capacitor Cse2 of the first pixel PX1 or the capacitance of the first compensation capacitor Cse1 and the second compensation capacitor Cse2 of the second pixel PX2. That is, the width or area of ​​the first electrode E11 of the first transistor T1 of the third pixel PX3 may be substantially the same as or different from the width or area of ​​the first electrode E11 of the first transistor T1 of the first pixel PX1 or the second pixel PX2. Alternatively, the width or area of ​​the second electrode Cse12 of the first compensation capacitor Cse1 of the third pixel PX3 may be substantially the same as or different from the width or area of ​​the second electrode Cse12 of the first compensation capacitor Cse1 of the first pixel PX1 or the second pixel PX2.

[0165] In addition, in the illustrated embodiment, the electrode layer 110 overlaps the first electrode E11 and the channel region C1 of the first transistor T1, so that a portion of the electrode layer 110 is used as the second electrode Cse22 of the second compensation capacitor Cse2, and the other portion is used as a bottom gate electrode for controlling the movement of carriers in the channel region C1. Therefore, since the electrode layer 110 receives the first power supply voltage ELVDD, the turn-on bias voltage of the first transistor T1 can be further ensured.

[0166] A display device according to an exemplary embodiment includes a compensation capacitor, the compensation capacitor including a first electrode as at least a portion of a source region or a drain region of a driving transistor and a second electrode connected to a power line receiving a first power supply voltage, so that a turn-on bias voltage of the driving transistor can be increased. The turn-on bias voltage of the driving transistor can be further increased by further providing a pair of compensation capacitors connected in parallel.

[0167] In addition, the display device according to the exemplary embodiment can distinguish the conduction bias voltage for each color pixel by controlling the capacitance capacity by controlling the area (width) of the counter electrode of the compensation capacitor. Therefore, the conduction bias voltage can be controlled for each color pixel to adjust the light emission amount and light emission time point for each color pixel. Therefore, the display device according to the exemplary embodiment can reduce the deviation of the light emission delay between the color pixels, thereby improving color tailing and / or color blur.

[0168] The display device according to the exemplary embodiments may reduce or prevent a color tailing phenomenon and provide a high-quality image.

[0169] Although specific exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, as will be apparent to one of ordinary skill in the art, the inventive concept is not limited to these embodiments, but to a wider range of various obvious modifications and equivalent arrangements.

Claims

1. A display device, wherein: The display device comprises: Bottom metal layer; A semiconductor layer, disposed on the bottom metal layer; A first electrode layer, disposed on the semiconductor layer; a second electrode layer, disposed on the first electrode layer and overlapping the first electrode layer; a power supply line disposed on the second electrode layer and electrically connected to the bottom metal layer and the second electrode layer; and A light emitting device comprising a pixel electrode, a common electrode facing the pixel electrode, and an emission layer between the pixel electrode and the common electrode, wherein a first end of the semiconductor layer is electrically connected to the power line, and a second end of the semiconductor layer is electrically connected to the pixel electrode, The semiconductor layer includes a source region, a drain region, and a channel region between the source region and the drain region. wherein each of the bottom metal layer, the first electrode layer, the second electrode layer and the power line overlaps with the channel region of the semiconductor layer, and The channel region of the semiconductor layer is positioned between a connection portion between the power line and the first end of the semiconductor layer and a connection portion between the second end of the semiconductor layer and the pixel electrode.

2. The display device according to claim 1, wherein: The second electrode layer is between the first electrode layer and the power line and is electrically insulated from the first electrode layer.

3. The display device according to claim 1, wherein: The semiconductor layer includes polycrystalline silicon.

4. The display device according to claim 1, wherein: The power line is configured to receive a constant voltage.

5. The display device according to claim 1, wherein: The channel region of the semiconductor layer is curved.

6. The display device according to claim 1, wherein: The display device further includes: A first insulating layer, disposed between the bottom metal layer and the semiconductor layer; a second insulating layer, disposed between the semiconductor layer and the first electrode layer; a third insulating layer, disposed between the first electrode layer and the second electrode layer; and A fourth insulating layer is provided between the second electrode layer and the power line.

7. A display device, wherein: The display device comprises: substrate; A driving transistor, disposed on the substrate, the driving transistor comprising a semiconductor layer and a gate electrode; a power supply line disposed on the driving transistor and electrically connected to the driving transistor; a bottom metal layer disposed between the substrate and the semiconductor layer; an electrode layer overlapping the gate electrode of the driving transistor and electrically connected to the power line; and A light emitting device comprising a pixel electrode, a common electrode facing the pixel electrode, and an emission layer between the pixel electrode and the common electrode, wherein the semiconductor layer overlaps with the bottom metal layer, wherein the power line and the bottom metal layer are configured to receive the same voltage, wherein a first end of the semiconductor layer is electrically connected to the power line, and a second end of the semiconductor layer is electrically connected to the pixel electrode, The semiconductor layer includes a source region, a drain region, and a channel region between the source region and the drain region. wherein each of the bottom metal layer, the gate electrode of the driving transistor, the electrode layer and the power supply line overlaps with the channel region of the semiconductor layer, and The channel region of the semiconductor layer is positioned between a connection portion between the power line and the first end of the semiconductor layer and a connection portion between the second end of the semiconductor layer and the pixel electrode.

8. The display device according to claim 7, wherein: The semiconductor layer includes polycrystalline silicon.

9. The display device according to claim 7, wherein: The display device further includes: A first insulating layer, disposed between the bottom metal layer and the semiconductor layer; A second insulating layer, disposed between the semiconductor layer and the first electrode layer; a third insulating layer, disposed between the first electrode layer and the second electrode layer; and A fourth insulating layer is provided between the second electrode layer and the power line.

10. The display device according to claim 7, wherein: The display device further includes: A buffer layer is disposed between the substrate and the bottom metal layer.

11. The display device according to claim 7, wherein: The substrate includes an organic layer and an inorganic layer.

12. A display device, wherein: The display device comprises: substrate; a bottom metal layer on the substrate; a first transistor overlapping the bottom metal layer and comprising a first semiconductor layer and a first gate electrode; an electrode layer overlapping the first gate electrode of the first transistor; a power supply line, disposed on the first transistor and electrically connected to the electrode layer; a second transistor comprising a second semiconductor layer and a second gate electrode; a connecting electrode electrically connecting the first gate electrode of the first transistor and the first end of the second semiconductor layer; and A light emitting device comprising a pixel electrode, a common electrode facing the pixel electrode, and an emission layer between the pixel electrode and the common electrode, wherein a first end of the first semiconductor layer is electrically connected to the power line, and a second end of the first semiconductor layer is electrically connected to the pixel electrode, and The second end of the second semiconductor layer is electrically connected to the second end of the first semiconductor layer.

13. The display device according to claim 12, in, The first semiconductor layer includes a source region, a drain region, and a channel region between the source region and the drain region, and Wherein, each of the bottom metal layer, the first gate electrode, the electrode layer and the power line overlaps with the channel region of the first semiconductor layer.

14. The display device according to claim 12, wherein: The electrode layer is electrically insulated from the first gate electrode of the first transistor.

15. The display device according to claim 12, wherein: The first semiconductor layer includes polycrystalline silicon.

16. The display device according to claim 13, wherein: The channel region of the first semiconductor layer is curved.

17. The display device according to claim 12, further comprising: A buffer layer is disposed between the substrate and the bottom metal layer.

18. The display device according to claim 12, wherein: The substrate includes an organic layer and an inorganic layer.

19. The display device according to claim 12, further comprising: The data line is arranged on the same layer as the power line.

20. The display device according to claim 19, wherein: A portion of the power line and a portion of the data line overlap the electrode layer.

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