Display panel, driving method thereof, and display device

Abstract

The display panel and the driving method thereof and the display device are disclosed.The display panel of an embodiment comprises a display area and a non-display area, a first area of the non-display area comprises a binding area, the display area comprises at least two sub-display areas arranged in sequence in a direction away from the binding area, a third area comprises at least one group of first shift register circuits arranged in sequence in a first direction, a sub-display area close to the second area in the sub-display areas is a second sub-display area, and other sub-display areas constitute first sub-display areas, and a rising edge of a clock signal received by a first shift register circuit away from the first area in the first shift register circuits corresponding to the first sub-display areas approximates a rising edge of a clock signal received by a first shift register circuit close to the first area, and a falling edge approximates a falling edge of the clock signal received by the first shift register circuit close to the first area.The embodiment of the present disclosure improves the charging time of the near-end and far-end clock signals and improves the display uniformity.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel and a driving method thereof, and a display device. BACKGROUND

[0002] An AMOLED (Active-matrix organic light-emitting diode) display relies on organic light-emitting diodes to emit light independently, and has excellent display effect. In order to improve the screen competitiveness, the shift register (GOA) prepared by the array process in the frame provides driving for the lighting of the AMOLED, however, the timing of the GOA is provided by the display driving chip, and the timing signals are different when the distance from the display driving chip is different, resulting in uneven screen display. SUMMARY

[0003] In order to solve at least one of the above problems, a first aspect of the present disclosure provides a display panel, comprising: a display area and a non-display area, the non-display area comprising a first area and a second area arranged oppositely, and a third area arranged between the first area and the second area, the first area comprising a binding area, the display area comprising at least two sub-display areas arranged in sequence along a first direction,

[0004] The third area comprises at least one group of first shift register circuits arranged in sequence along the first direction in cascade, each first shift register circuit providing a scanning signal to corresponding at least one row of pixel units in the display area,

[0005] The display area comprises a first sub-display area and a second sub-display area, wherein the sub-display area close to the second area is the second sub-display area, and the other sub-display areas constitute the first sub-display area, and the rising edge of the clock signal received by the first shift register circuit far from the first area in the first shift register circuit corresponding to the first sub-display area approaches the rising edge of the clock signal received by the first shift register circuit close to the first area, and the falling edge approaches the falling edge of the clock signal received by the first shift register circuit close to the first area.

[0006] Optionally, the sub-display areas are bending areas,

[0007] For each group of cascaded first shift register circuits, the non-display area further comprises: a first clock signal line and a second clock signal line arranged in the third area and extending along the first direction, and a first compensation signal line and a second compensation signal line extending along the first direction,

[0008] One of the first clock signal terminal and the second clock signal terminal of each first shift register circuit is electrically connected to the first clock signal line, and the other is electrically connected to the second clock signal line, the first clock signal line is connected to the first clock signal, and the second clock signal line is connected to the second clock signal,

[0009] The first compensation signal line is electrically connected to the first outer bending end of the first clock signal line and connected to the first compensation signal, and the second compensation signal line is electrically connected to the second outer bending end of the second clock signal line and connected to the second compensation signal, the first outer bending end and the second outer bending end are located in the extension area of the third area away from the bending area,

[0010] The first compensation signal is at an invalid level in the scanning time period of the corresponding row of pixel units in the second sub-display area, and the signal of the first clock signal provided in the scanning time period of the corresponding row of pixel units in the first sub-display area is the same,

[0011] The second compensation signal is at an invalid level in the scanning time period of the corresponding row of pixel units in the second sub-display area, and the signal of the second clock signal provided in the scanning time period of the corresponding row of pixel units in the first sub-display area is the same.

[0012] Optionally, the bending area is between the first sub-display area and the second sub-display area,

[0013] For each group of cascaded first shift register circuits, the non-display area further comprises: a first clock signal line, a second clock signal line and a first initial compensation signal line arranged in the third area and extending in the first direction,

[0014] The display area comprises: a first display mode in which the first sub-display area displays a picture and the second sub-display area does not display a picture,

[0015] One of the first clock signal terminal and the second clock signal terminal of each first shift register circuit is electrically connected to the first clock signal line, and the other is electrically connected to the second clock signal line, the first initial compensation signal line is electrically connected to the first shift register circuit farthest from the first area in the first shift register circuit corresponding to the first sub-display area,

[0016] In the first display mode, the first clock signal line is at an invalid level in the scanning time period of the corresponding row of pixel units in the second sub-display area, the first clock signal is provided in the scanning time period of the corresponding row of pixel units in the first sub-display area, the second clock signal line is at an invalid level in the scanning time period of the corresponding row of pixel units in the second sub-display area, the second clock signal is provided in the scanning time period of the corresponding row of pixel units in the first sub-display area, and the first initial compensation signal line provides an initial signal to the first shift register circuit farthest from the first area in the first shift register circuit of the first sub-display area.

[0017] Optionally, for each group of cascaded first shift register circuits, the non-display region further comprises: at least two groups of clock signal lines arranged in the third region and extending along the first direction, the groups of clock signal lines are arranged one-to-one corresponding to the sub-display regions, each group of clock signal lines comprises a first clock signal line and a second clock signal line,

[0018] One of the first clock signal end and the second clock signal end of each first shift register circuit in each sub-display region is electrically connected to the first clock signal line of the corresponding group of clock signal lines, and the other is electrically connected to the second clock signal line of the group of clock signal lines, and

[0019] In the group of clock signal lines, the first clock signal line provides the first clock signal in the scanning time period of the corresponding row of pixel units of the corresponding sub-display region, and is at an invalid level in other time periods, and the second clock signal line provides the second clock signal in the scanning time period of the corresponding row of pixel units of the corresponding sub-display region, and is at an invalid level in other time periods.

[0020] Optionally, the first clock signal and the second clock signal are both periodic signals with high and low levels arranged alternately,

[0021] In the time period when the first clock signal is at a valid level, the second clock signal is at least partially at an invalid level, and in the time period when the second clock signal is at a valid level, the first clock signal line is at least partially at an invalid level.

[0022] Optionally, the first clock signal and the second clock signal are mutually inverse signals.

[0023] Optionally, the first clock signal end and the second clock signal end of the first shift register circuit generate a scanning signal of the corresponding row of pixel units based on the received clock signal.

[0024] Optionally, the display region comprises three sub-display regions.

[0025] The second aspect of the present disclosure provides a display device comprising the display panel described above.

[0026] The third aspect of the present disclosure provides a display driving method applied to the display panel described above, the method comprising:

[0027] The rising edge of the clock signal received by the first shift register circuit far from the first region in the first shift register circuit corresponding to the first sub-display region approaches the rising edge of the clock signal received by the first shift register circuit close to the first region, and the falling edge approaches the falling edge of the clock signal received by the first shift register circuit close to the first region. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0029] Figure 1 Schematic diagram of the structure of a display panel driven by GOA;

[0030] Figure 2 A timing diagram of shift register clock signals corresponding to the far end and the near end of the display area in the related art;

[0031] Figure 3 A timing superposition comparison diagram of shift register clock signals corresponding to the far end and the near end of the display area in the related art;

[0032] Figure 4 is a schematic diagram of a display panel according to an embodiment of the present disclosure;

[0033] Figure 5 Based on Figure 4 A timing diagram of clock signals of a first shift register circuit of a display panel according to the embodiment shown;

[0034] Figure 6 is a schematic diagram of a display panel according to another embodiment of the present disclosure;

[0035] Figure 7 Based on Figure 6 A timing diagram of clock signals of a first shift register circuit of a display panel according to the embodiment shown;

[0036] Figure 8 is a schematic diagram of a display panel according to another embodiment of the present disclosure;

[0037] Figure 9 is a schematic diagram of a display panel according to another embodiment of the present disclosure;

[0038] Figure 10 Based on Figure 9 The clock signal timing diagram of the first shift register circuit of the display panel of the embodiment shown is shown.

[0039] The beneficial effects of the present disclosure are as follows:

[0040] In response to the current existing problems, the present disclosure develops a display panel, a driving method thereof, and a display device. By setting the rising edge of the clock signal received by the first shift register circuit close to the first area in the first shift register circuit corresponding to the first sub-display area to approach the rising edge of the clock signal received by the first shift register circuit away from the first area and the falling edge to approach the falling edge of the clock signal received by the first shift register circuit away from the first area, the charging time consistency of the clock signals received by the near-end and far-end first shift register circuits is improved, thereby improving display uniformity, and having broad application prospects. DETAILED DESCRIPTION

[0041] To more clearly illustrate the present disclosure, the present disclosure is further described below in conjunction with preferred embodiments and accompanying drawings. Similar components in the accompanying drawings are represented by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be used to limit the scope of protection of the present disclosure.

[0042] It should be noted that ordinal numbers such as "first," "second," "third," etc. herein are not intended to limit the order of the units, nodes, elements, or components, but are merely intended to distinguish the units, nodes, elements, or components. The meanings of "include," "comprising," and "having" herein are open-ended. For example, when describing the inclusion of units, nodes, elements, or components, in addition to the included units, nodes, elements, or components, other units, nodes, elements, or components may also be included.

[0043] Reference Figure 1 As shown, a display panel that uses GOA to provide scanning signals for pixel units in the display area requires a display driver chip to provide signals for driving each shift register circuit in the GOA. The display driver chip is located on the display panel or on a flexible circuit board bound to the display panel. In this example, the display driver chip is located in the non-display area below the display panel. Figure 1 The enlarged partial view in the figure shows that multiple signal lines are arranged in the non-display area to the left of the display area. One end of these signal lines is electrically connected to the display driver chip, which is used to provide signals provided by the display driver chip to the various shift register circuits. The trace lengths near the display driver chip and those far from the driver chip vary, resulting in different RC loading near and far ends of the display area.

[0044] Reference Figure 2 and Figure 3 As shown, Figure 2The three signals on the top represent the signals inputted into the input terminal STV of the shift register circuit located at the proximal end of the display area, the first clock signal terminal CK and the second clock signal terminal CB, and the three signals on the bottom represent the signals inputted into the input terminal STV of the shift register circuit located at the distal end of the display area, the first clock signal terminal CK and the second clock signal terminal CB, Figure 3 The superimposed contrast diagram of the two groups of signals in Figure 2 The superimposed contrast diagram of the two groups of signals in However, the first clock signal terminals CK and the second clock signal terminals CB of all the cascade shift register circuits are respectively connected to the same first clock signal line CK and the second clock signal line, and due to the different lengths of the lines, the RC load difference is caused, and then the charging time at the proximal end and the distal end is significantly different because the closer to the display driving chip, the stronger the signal driving ability, and the farther to the display driving chip, the greater the RC value caused by the resistance of the signal line itself, and the longer the charging time, the rising edge time Tr and the falling edge time Tf of the clock signal terminal of the shift register circuit at the proximal end are shorter, and the rising edge time Tr and the falling edge time Tf of the clock signal terminal of the shift register circuit at the distal end are longer, which causes the display unevenness of the display product at the distal end and the proximal end. Especially, for the folding display product with multiple display areas, the display screen is larger, and the display area far away from the display driving chip is farther away from the proximal end, thereby causing the display unevenness more significantly, and the visual display uniformity difference is more obvious.

[0045] Therefore, the display panel of the embodiment of the present disclosure comprises a display area and a non-display area, the non-display area comprises a first area and a second area arranged oppositely, and a third area arranged between the first area and the second area, the first area comprises a binding area, the display area comprises at least two sub-display areas arranged in sequence along a first direction, the first direction is a direction away from the binding area,

[0046] The third area comprises at least one group of first shift register circuits arranged in sequence along the first direction, each first shift register circuit provides a scanning signal to corresponding at least one row of pixel units in the display area,

[0047] The display area comprises a first sub-display area and a second sub-display area, the sub-display area close to the second area is the second sub-display area, and the other sub-display areas constitute the first sub-display area, the rising edge of the clock signal received by the first shift register circuit far away from the first area in the first shift register circuit corresponding to the first sub-display area approaches the rising edge of the clock signal received by the first shift register circuit close to the first area, and the falling edge approaches the falling edge of the clock signal received by the first shift register circuit close to the first area.

[0048] In the embodiment, the rising edge of the clock signal received by the first shift register circuit far away from the first area approaches the rising edge of the clock signal received by the first shift register circuit close to the first area and the falling edge approaches the falling edge of the clock signal received by the first shift register circuit close to the first area, so that the consistency of the charging time of the clock signals received by the first shift register circuits at the near end and the far end is improved, thereby improving the display uniformity.

[0049] In a specific embodiment, referring to Figure 4 , the display panel includes a display area AA and a non-display area NA surrounding the display area AA. The non-display area NA includes oppositely arranged first areas NA1 and NA2, and a third area NA3 arranged between the first area NA1 and the second area NA2. In this example, the third area NA3 refers to the area of the non-display area on the left and right sides of the display area AA between the first area NA1 at the upper part and the second area NA2 at the lower part.

[0050] The first area NA1 includes a binding area 11. If the display driving chip is located on the display panel, the binding area 11 can be a binding area for binding the display driving chip, and if the display driving chip is not located on the display panel but on a flexible circuit board or on another circuit board, the binding area 11 can be a binding area for binding the flexible circuit board. In other words, the signal source for driving the first shift register circuit in the GOA is derived from the first area NA1, i.e. for the display area AA, the end close to the first area NA1 is the near end and the end far away from the first area NA1 is the far end.

[0051] Continuing to refer to Figure 4 , the display area AA includes three sub-display areas AA-1, AA-2 and AA2 arranged in sequence along a first direction, which is the direction away from the first area NA1, i.e. the Y direction in the figure. The sub-display area far away from the first area NA1 among the three sub-display areas AA-1, AA-2 and AA2 is the second sub-display area, denoted by the reference numeral "AA2", and the other sub-display areas AA-1 and AA-2 constitute the first sub-display area, denoted by the reference numeral "AA1".

[0052] As shown in Figure 4 , in this example, the sub-display areas are bend areas, the bend area between the sub-display area AA-1 and the sub-display area AA-2 is the bend area 121, and the bend area between the first sub-display area AA1 and the second sub-display area AA2 is the bend area 122. The bend area 122 is arranged away from the first area NA1 relative to the bend area 121, for example: the bend area 122 can be referred to as an "outer folding area" and the bend area 121 can be referred to as an "inner folding area".

[0053] Figure 4 The third area NA3 shown on the left side of the display area AA includes a group of first shift register circuits arranged in cascade in the first direction in sequence, each of which provides a scanning signal to a corresponding row of pixel units in the display area AA.

[0054] Specifically, the cascaded first shift register circuits scan the pixel units in sequence starting from the first row of pixel units away from the first area NA1, so as to drive the display area AA to display a picture. Thus, the first shift register circuit G_1 away from the end of the first area NA1 is the first-stage first shift register circuit.

[0055] Referring to Figure 4 As shown, the first-stage first shift register circuit G_1 to the A-th stage first shift register circuit G_A in the group of cascaded first shift register circuits correspond to A rows of pixel units in the second sub-display area AA2; the A+1-th stage first shift register circuit G_A+1 to the B-th stage first shift register circuit G_B correspond to B-(A) rows of pixel units in the sub-display area AA-2 away from the first area NA1 in the second sub-display area AA2; and the B+1-th stage first shift register circuit G_B+1 to the N-th stage first shift register circuit G_N correspond to N-(B) rows of pixel units in the sub-display area AA-1 close to the first area NA1 in the second sub-display area AA2, each stage of first shift register circuit provides a scanning signal to a corresponding row of pixel units, A, B and N are positive integers greater than 1. When no distinction is needed, the first shift register circuits are collectively referred to as first shift register circuits G.

[0056] It should be noted that in the present disclosure, the cascaded first shift register circuits output scanning signals in sequence, but this does not mean that the cascaded first shift register circuits scan adjacent rows of pixel units in the display area in sequence, in other words, for example, each stage of first shift register circuit in a group of first shift register circuits can only correspond to odd rows of pixel units in the display area AA, and scan these rows in sequence, of course, each stage of first shift register circuit in a group of first shift register circuits can also only scan even rows of pixel units or other interval rows of pixel units. In addition, one first shift register circuit can also scan multiple rows of pixel units at the same time, which is not described herein.

[0057] It should also be noted that although Figure 4The example of FIG shows a circuit structure of a group of cascaded first shift register circuits, but the present disclosure is not intended to limit the number of groups of cascaded first shift register circuits in the third area NA3 and the position of each group of first shift register circuits. For example, the third area NA3 may include multiple groups of first shift register circuits, with one or more groups arranged in the third area NA3 on the left and one or more groups arranged in the third area NA3 on the right. This is not described in detail herein.

[0058] Continue to refer to Figure 4 As shown, the non-display area NA further includes: first clock signal lines CK and second clock signal lines CB, which are arranged in the third area NA3 and extend along the first direction Y, and first compensation signal lines CK1 and second compensation signal lines CB1, which extend along the first direction Y. The first shift register circuit G is capable of outputting scan signals and shifting them step by step in response to signals from the first clock signal lines CK and the second clock signal lines CB. The first clock signal line CK is electrically connected to the first clock signal terminal of each first shift register circuit G and receives the first clock signal. The second clock signal line CB is electrically connected to the second clock signal terminal of each first shift register circuit G and receives the second clock signal.

[0059] One of the first clock signal terminal ck and the second clock signal terminal cb of each first shift register circuit G is electrically connected to the first clock signal line CK, and the other is electrically connected to the second clock signal line CB. Figure 5 As shown, the first clock signal line CK is connected to the first clock signal, and the second clock signal line CB is connected to the second clock signal.

[0060] Of course, in order to simplify the view, the figure does not reflect the initial signal line STV that provides the initial signal, and the input end of the first shift register circuit at each level. It should be understood that the input end of the first shift register circuit of the first level is connected to the initial signal line, and the first shift register circuits of each level are cascaded with the cascade end of the previous level through the input end.

[0061] Combine Figure 4 and Figure 5 As shown, the first compensation signal line CK1 is electrically connected to the first outer fold end N1 of the first clock signal line CK and receives the first compensation signal, and the second compensation signal line CB1 is electrically connected to the second outer fold end N2 of the second clock signal line CB and receives the second compensation signal. The first outer fold end N1 and the second outer fold end N2 are located in the extension area of ​​the third area NA3 of the bending area 122 away from the binding area 11 (the area defined by the dotted extension line of the bending area boundary in the figure). For clarity, the symbols of the corresponding clock signal lines are used in the figure to represent the signals received by the clock signal lines.

[0062] Optionally, the length of the first compensation signal line CK1 is less than the length of the first clock signal line CK, and the length of the second compensation signal line CB1 is less than the length of the second clock signal line CB.

[0063] Through the arrangement, the signal line resistance of the first compensation signal line CK1 is smaller than that of the first clock signal line CK, and the signal line resistance of the second compensation signal line CB1 is smaller than that of the second clock signal line CB at the compensation position.

[0064] In addition, the first compensation signal line CK1 can be arranged on the side of the first clock signal line CK away from the display area AA, and the second compensation signal line CB1 can be arranged on the side of the second clock signal line CB away from the display area AA.

[0065] Referring to Figure 5 As shown in the figure, the first compensation signal is at an invalid level in the scanning time period of each row of pixel units in the second sub-display area AA2, and the signal of the first clock signal provided in the scanning time period of each row of pixel units in the first sub-display area AA1 is the same; the second compensation signal is at an invalid level in the scanning time period of each row of pixel units in the second sub-display area AA2, and the signal of the second clock signal provided in the scanning time period of each row of pixel units in the first sub-display area AA1 is the same.

[0066] Through the arrangement, considering that the farther the signal line is from the first area NA1, the greater the signal line load RC is, and the more significant the charging time of the rising and falling edges of the signals loaded on the first signal end ck and the second signal end cb is, and the first clock signal of the first clock signal line CK and the second clock signal of the second clock signal line CB are scanned from the farthest end of the display area as the first row to the near end, in order to supplement the first compensation signal and the second compensation signal at the first outer folding end N1 and the second outer folding end N2 as the starting point to strengthen the driving ability of the far end, the actual arrival time at the compensation end needs to be considered, that is, the first compensation signal and the second compensation signal are both at an invalid level (the invalid level is high in this example) in the corresponding time period of the second sub-display area AA2, and the scanning time period of each row of pixel units in the first sub-display area AA1 is the same as the first clock signal and the second clock signal respectively, so as to ensure that the rising edge of the clock signal accessed by the shift register circuit far away from the first area NA1 is consistent with the rising edge of the clock signal accessed by the shift register circuit closer to the first area NA1, and at the same time, the falling edge of the clock signal accessed by the shift register circuit far away from the first area NA1 is consistent with the falling edge of the clock signal accessed by the shift register circuit in the first area NA1, thereby improving the display uniformity.

[0067] It should be noted that for the corresponding period of the shift register circuit G_1 to G_A, the first compensation signal CK1 and the second compensation signal CB2 input invalid level signals, so as to correspond to the position of the period without compensation, and the compensation position is at the position of the shift register circuit G_A+1. In addition, although the invalid level is high in this example, it is not limited thereto, and the invalid level can also be low according to the structure and driving principle of the shift register circuit, which will not be described herein.

[0068] Optionally, the first clock signal and the second clock signal are both periodic signals with high and low levels arranged alternately. The period ② of the first clock signal is the effective level, and the period ① of the second clock signal is at least partially invalid level, and the period of the second clock signal is the effective level, and the period of the first clock signal line is at least partially invalid level.

[0069] Referring to Figure 5 In this example, the high level is the invalid level, and the low level is the effective level. In the period ② of the first clock signal being low, the period ① of the second clock signal is high, and in the period ③ of the second clock signal being low, the period ④ of the first clock signal is high.

[0070] Of course, those skilled in the art should understand that the first clock signal and the second clock signal are not limited thereto, and the first clock signal and the second clock signal can be mutually inverted signals.

[0071] In other optional embodiments, referring to Figure 6 and Figure 7 Another structure of the display panel is shown in the figure, which is different from the display panel shown in Figure 4 In this embodiment, the first clock signal line and the second clock signal line are not electrically connected to the compensation signal line, but in the first display mode in which the first sub-display area AA1 displays the picture and the second sub-display area AA2 does not display the picture, the first clock signal line CK is invalid level in the scanning period of the corresponding row of pixel units in the second sub-display area AA2, and provides the first clock signal in the scanning period of the corresponding row of pixel units in the first sub-display area AA1. The second clock signal line CB is invalid level in the scanning period of the corresponding row of pixel units in the second sub-display area AA2, and provides the second clock signal in the scanning period of the corresponding row of pixel units in the first sub-display area AA1.

[0072] Exemplarily, in the first display mode, the first clock signal end ck and the second clock signal end cb of the first shift register circuit corresponding to the second sub-display area AA2 do not generate the scanning signal due to receiving invalid level, so that the scanning and refreshing of the pixel units are not performed, and the first shift register circuit corresponding to the first sub-display area AA1 normally outputs the scanning signal under the driving of the first clock signal and the second clock signal, so that the second sub-display area AA2 performs picture display.

[0073] In addition, because the first stage of the first shift register circuit is located at the far end, and the initial signal should be input to the first shift register circuit located at the first stage via the initial signal line STV in the normal display, in order that the initial signal can be normally transmitted to the first shift register circuit corresponding to the first sub-display area AA1 in the case that the second sub-display area AA2 does not generate normal output, referring to Figure 7 As shown in the figure, the non-display area NA further includes a first initial compensation signal line STV1, and the first initial compensation signal line STV1 is electrically connected to the first shift register circuit G_A+1 farthest from the first area NA1 in the first shift register circuits G_A+1-G_N corresponding to the first sub-display area AA1. In the first display mode, the first initial compensation signal line STV1 provides the initial signal to the first shift register circuit G_A+1 farthest from the first area NA1 in the first shift register circuits corresponding to the first sub-display area AA1. Specifically, if the input end of the first shift register circuit G_A+1 is stv, the first initial compensation signal line STV1 is electrically connected to the input end stv.

[0074] The connection relationship of the first shift register circuit G and the first clock signal line CK and CB is similar to the example shown in the figure, which is not described herein. The first clock signal end ck and the second clock signal end cb of the first shift register circuit G generate the scanning signal corresponding to the row pixel units based on the received clock signal. Figure 4

[0075] ​Through the above setting, when the second sub-display area AA2 does not need to display a picture, for example, if the bending area 122 is the outer bending area and the second sub-display area AA2 is folded to the back of the first sub-display area AA1 so that the second sub-display area AA2 is not a display screen facing the user, by setting the first clock signal line CK and the second clock signal line CB to be simultaneously high in the scanning period of each row of display units of the second sub-display area AA2, that is, the period in which the first shift register G_1 to G_A needs to be driven to work, so that there is no charging and discharging period of clock high-low conversion in this period, which is equivalent to the start of the first clock signal and the second clock signal being at the end of the first sub-display area AA1 away from the first area NA1, thereby eliminating the load effect of the first clock signal line and the second clock signal line on the second sub-display area AA2, and further improving the consistency of the rising edge and falling edge of the signals received by the first clock signal end ck and the second clock signal end cb of the first shift register circuit G in the near end and the far end of the first sub-display area AA1, and improving the display uniformity. At the same time, through the above setting, the display driving power consumption of the display driving chip in the first display mode can also be reduced.

[0076] In some other optional embodiments, referring to FIG. 1, based on the display panel shown in FIG. 1, the display area can also be set to include a first display mode in which the first sub-display area AA1 displays a picture and the second sub-display area AA2 does not display a picture. Figure 8 Figure 4 In some other optional embodiments, referring to FIG. 1, based on the display panel shown in FIG. 1, the display area can also be set to include a first display mode in which the first sub-display area AA1 displays a picture and the second sub-display area AA2 does not display a picture. Figure 6 The area filled with the pattern in the first display mode indicates a black screen that does not display a picture.

[0077] In the first display mode, the first clock signal line CK is an invalid level in the scanning period of each row of pixel units in the second sub-display area AA2, and provides the first clock signal in the scanning period of each row of pixel units in the first sub-display area AA1. The second clock signal line CB is an invalid level in the scanning period of each row of pixel units in the second sub-display area AA2, and provides the second clock signal in the scanning period of each row of pixel units in the first sub-display area AA1. At the same time, the first compensation signal line CK1 and the second clock signal line CK2 do not input valid signals. In the present disclosure, the first compensation signal line CK1 and the second clock signal line CK2 not inputting valid signals means that neither of them inputs a signal or only inputs an invalid level signal.

[0078] In some other optional embodiments, referring to FIG. 1, based on the display panel shown in FIG. 1, the display area can also be set to include a first display mode in which the first sub-display area AA1 displays a picture and the second sub-display area AA2 does not display a picture. Figure 8 ​As shown, the non-display area NA further includes a first initial compensation signal line STV1, which is electrically connected to the first shift register circuit G_A+1 farthest from the first area NA1 in the first shift register circuit G_A+1-G_N corresponding to the first sub-display area AA1. In the first display mode, the first initial compensation signal line STV1 provides an initial signal to the first shift register circuit G_A+1 farthest from the first area NA1 in the first shift register circuit of the first sub-display area AA1. Specifically, if the input end of the first shift register circuit G_A+1 is stv, the first initial compensation signal line STV1 is electrically connected to the input end stv.

[0079] Through the above arrangement, when the second sub-display area AA2 does not need to display a picture, the end of the first sub-display area AA1 farthest from the first area NA1 is equivalent to the starting end of the first clock signal and the second clock signal, thereby eliminating the load effect of the first clock signal line and the second clock signal line on the second sub-display area AA2, and further improving the consistency of the rising edge and the falling edge of the signals received by the first clock signal end ck and the second clock signal end cb of the first shift register circuit G at the near end and the far end in the first sub-display area AA1, and improving the display uniformity.

[0080] Meanwhile, the above arrangement can fully utilize the display characteristics, ensure that when the first sub-display area AA1 and the second sub-display area AA2 both need to display, the timing consistency of the clock signal ends at the near end and the far end is improved, the display uniformity is improved, and the display uniformity can also be realized in the first display mode. In addition, in the first display mode, the driving difficulty of the display driving chip can be reduced, and when neither the first compensation signal line nor the second compensation signal line is connected to a signal, the driving power consumption of the display driving signal can be reduced.

[0081] In another embodiment, the display panel has another structure, which is different from the above display panel in that, for a group of cascaded first shift register circuits G, the non-display area NA includes: at least two clock signal line groups arranged in the third area NA3 and extending along the first direction Y, and the clock signal line groups are arranged one by one corresponding to the sub-display areas, and each of the clock signal line groups includes a first clock signal line and a second clock signal line.

[0082] Specifically, the first clock signal line and the second clock signal line in each clock signal line group are arranged in the third area NA3 and extend along the first direction Y, and the first clock signal line and the second clock signal line in each clock signal line group are arranged one by one corresponding to the sub-display areas. Figure 9In the shown example, the display area AA includes three sub-display areas AA-1, AA-2 and AA2, for the first shift register circuit G of the group, the sub-display area AA2 corresponds to the clock signal line group composed of the first clock signal line CK1 and the second clock signal line CB1, the sub-display area AA-2 corresponds to the clock signal line group composed of the first clock signal line CK2 and the second clock signal line CB2, and the sub-display area AA-1 corresponds to the clock signal line group composed of the first clock signal line CK3 and the first clock signal line CB3.

[0083] One of the first clock signal end and the second clock signal end of each first shift register circuit in each sub-display area is electrically connected to the first clock signal line of the corresponding clock signal line group, and the other is electrically connected to the second clock signal line of the clock signal line group.

[0084] Specifically, Figure 9 As shown, one of the first clock signal end ck and the second clock signal end cb of the first shift register circuits G_1 to G_A corresponding to the sub-display area AA2 is electrically connected to the first clock signal line CK1, and the other is electrically connected to the second clock signal line CB1. One of the first clock signal end ck and the second clock signal end cb of the first shift register circuits G_A+1 to G_B corresponding to the sub-display area AA-2 is electrically connected to the first clock signal line CK2, and the other is electrically connected to the second clock signal line CB2. One of the first clock signal end ck and the second clock signal end cb of the first shift register circuits G_B+1 to G_N corresponding to the sub-display area AA-2 is electrically connected to the first clock signal line CK3, and the other is electrically connected to the second clock signal line CB3.

[0085] In the clock signal line group, the first clock signal line provides the first clock signal in the scanning time period of the corresponding row of pixel units of the corresponding sub-display area, and is at an invalid level in other time periods. The first clock signal line provides the second clock signal in the scanning time period of the corresponding row of pixel units of the corresponding sub-display area, and is at an invalid level in other time periods.

[0086] In combination with Figure 9 And Figure 10As shown, the first stage of the first shift register circuit G away from the first area NA1 is the first stage, and the first clock signal end ck and the second clock signal end cb of each stage of the first shift register circuit G are sequentially connected to the corresponding clock signal to sequentially generate the scanning signal. Then, the first clock signal line CK1 and the second clock signal line CB1 electrically connected to the first shift register circuit G_1 to G_A corresponding to the sub-display area AA2 are only connected to the first clock signal and the second clock signal in the scanning time period of each row of pixel units corresponding to these stages of the first shift register circuit, and are invalid in other periods. Correspondingly, the first clock signal line CK2 and the second clock signal line CB2 electrically connected to the first shift register circuit G_A+1 to G_B corresponding to the sub-display area AA-2 are only connected to the first clock signal and the second clock signal in the scanning time period of each row of pixel units corresponding to these stages of the first shift register circuit, and are invalid in other periods. The first clock signal line CK3 and the second clock signal line CB3 electrically connected to the first shift register circuit G_B+1 to G_N corresponding to the sub-display area AA-1 are only connected to the first clock signal and the second clock signal in the scanning time period of each row of pixel units corresponding to these stages of the first shift register circuit, and are invalid in other periods.

[0087] Through the above arrangement, the first clock signal line and the second clock signal line of the first shift register circuit corresponding to each sub-display area are driven from the corresponding sub-display area as the starting point, so that the signal line length actually affecting the RC load is cut into multiple segments, which is equivalent to greatly shortening the signal line length, thereby reducing the attenuation caused by the signal line RC load corresponding to each sub-display area. Therefore, the rising edge of the clock signal of the first shift register circuit close to one end of the first area NA1 of the first sub-display area AA1 is consistent with the rising edge of the clock signal of the first shift register circuit away from the one end of the first area NA1, and the falling edge of the clock signal of the first shift register circuit close to one end of the first area NA1 of the first sub-display area AA1 is consistent with the falling edge of the clock signal of the first shift register circuit away from the one end of the first area NA1, thereby improving the display uniformity.

[0088] Optionally, the length of the first clock signal line CK1 is greater than the length of the first clock signal line CK2, the length of the first clock signal line CK2 is greater than the length of the first clock signal line CK3, and the length of the second clock signal line CB1 is greater than the length of the second clock signal line CB2, the length of the second clock signal line CB2 is greater than the length of the second clock signal line CB3.

[0089] Through the arrangement, the signal line length corresponding to the sub-display area close to the first area NA1 is adjusted according to the area corresponding to the driving of each group of first clock signal lines and second clock signal lines, so that the influence of the signal line coupling capacitance and signal line resistance on the RC load is reduced as much as possible.

[0090] It should be noted that other structural features of the display panel of this embodiment are similar to those of the above Figure 4 embodiment, and will not be described here.

[0091] Based on the same inventive concept, the display panel driving method provided by the embodiments of the present disclosure comprises: the rising edge of the clock signal received by the first shift register circuit far away from the first area in the first shift register circuit corresponding to the first sub-display area approaches the rising edge of the clock signal received by the first shift register circuit close to the first area, and the falling edge approaches the falling edge of the clock signal received by the first shift register circuit close to the first area.

[0092] Optionally, referring to Figure 5 , for the structure shown in Figure 4 , when display driving, the first clock signal line CK inputs the first clock signal, the second clock signal line CB inputs the second clock signal, the first compensation signal CK1 is at an invalid level in the scanning time period of each row of pixel units corresponding to the second sub-display area AA2, and the signal of the first clock signal provided in the scanning time period of each row of pixel units corresponding to the first sub-display area AA1 is the same, and the second compensation signal CB1 is at an invalid level in the scanning time period of each row of pixel units corresponding to the second sub-display area AA2, and the signal of the second clock signal provided in the scanning time period of each row of pixel units corresponding to the first sub-display area AA1 is the same.

[0093] Optionally, referring to Figure 7 , for the structure shown in Figure 6 , when display driving, in the first display mode, the first clock signal line CK is at an invalid level in the scanning time period of each row of pixel units corresponding to the second sub-display area AA2, and provides the first clock signal in the scanning time period of each row of pixel units corresponding to the first sub-display area AA1, and the second clock signal line CB is at an invalid level in the scanning time period of each row of pixel units corresponding to the second sub-display area AA2, and provides the second clock signal in the scanning time period of each row of pixel units corresponding to the first sub-display area AA1.

[0094] Additionally optionally, for the structure shown in Figure 8 , in the first display mode, in addition to the first clock signal line CK and the second clock signal line CB inputting Figure 6In addition to the timing shown, the first compensation signal line CK1 and the second compensation signal line CB1 are not connected to a signal or to an invalid level.

[0095] Optionally, referring to Figure 10 As shown, for Figure 9 As shown in the structure, when the display is driven, in each clock signal line group, the first clock signal line provides the first clock signal in the scanning time period of the corresponding row of pixel units of the corresponding sub-display area, and provides the invalid level in other time periods; and the first clock signal line provides the second clock signal in the scanning time period of the corresponding row of pixel units of the corresponding sub-display area, and provides the invalid level in other time periods.

[0096] Through the above setting, the consistency of the charging time of the clock signals received by the first shift register circuits at the near end and the far end can be improved, thereby improving the display uniformity.

[0097] Based on the same inventive concept, the embodiments of the present disclosure also provide a display device comprising the display panel described in the above embodiments.

[0098] Since the display panel included in the display device provided by the embodiments of the present disclosure corresponds to the display panel provided by the above embodiments, the previous embodiments are also applicable to the present embodiment, and will not be described in detail in the present embodiment.

[0099] In the present embodiment, the display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a vehicle-mounted display, a digital photo frame, a navigator, etc., especially a large folding product with multiple folding ends. By loading the above display panel, the display device can have uniform display effect and has wide application prospect.

[0100] The present disclosure is clear that the above embodiments of the present disclosure are only examples for clearly illustrating the present disclosure, and are not limitations on the embodiments of the present disclosure. For those skilled in the art, on the basis of the above description, other different forms of changes or modifications can also be made, and it is impossible to enumerate all the embodiments here. Any changes or modifications that fall within the scope of the technical solutions of the present disclosure are still within the protection scope of the present disclosure.

Claims

1. A display panel, characterized in that: include: A display area and a non-display area, the non-display area including a first area and a second area arranged opposite to each other, and a third area arranged between the first area and the second area, the first area including a binding area, the display area including at least two sub-display areas arranged in sequence along a first direction, the first direction being a direction away from the binding area, The third area includes at least one group of first shift register circuits sequentially cascaded along the first direction, each of the first shift register circuits provides a scanning signal to at least one corresponding row of pixel units in the display area. The display area includes a first sub-display area and a second sub-display area, wherein the sub-display area close to the second area is the second sub-display area, and the other sub-display areas constitute the first sub-display area. In the first shift register circuit corresponding to the first sub-display area, the rising edge of the clock signal received by the first shift register circuit far away from the first area approaches the rising edge of the clock signal received by the first shift register circuit close to the first area, and the falling edge approaches the falling edge of the clock signal received by the first shift register circuit close to the first area.

2. The display panel according to claim 1, wherein: The bending area is between the sub-display areas. For each group of cascaded first shift register circuits, the non-display area further includes: a first clock signal line and a second clock signal line arranged in the third area and extending along the first direction, and a first compensation signal line and a second compensation signal line extending along the first direction. One of the first clock signal terminal and the second clock signal terminal of each first shift register circuit is electrically connected to the first clock signal line, and the other is electrically connected to the second clock signal line, the first clock signal line receives a first clock signal, and the second clock signal line receives a second clock signal. The first compensation signal line is electrically connected to a first outer folded end of the first clock signal line and receives a first compensation signal. The second compensation signal line is electrically connected to a second outer folded end of the second clock signal line and receives a second compensation signal. The first outer folded end and the second outer folded end are located in an extension area of ​​the bending area away from the binding area in the third area. The first compensation signal is at an invalid level during a scanning period of each row of pixel units corresponding to the second sub-display area, and the first clock signal provided during a scanning period of each row of pixel units corresponding to the first sub-display area is the same. The second compensation signal is at an invalid level during a scanning period corresponding to each row of pixel units in the second sub-display area, and the second clock signal provided during a scanning period corresponding to each row of pixel units in the first sub-display area is the same.

3. The display panel according to claim 1, wherein: There is a bending area between the first sub-display area and the second sub-display area. For each group of cascaded first shift register circuits, the non-display area further includes: a first clock signal line, a second clock signal line, and a first initial compensation signal line arranged in the third area and extending along the first direction; The display area includes a first display mode in which the first sub-display area displays a picture and the second sub-display area does not display a picture, One of the first clock signal terminal and the second clock signal terminal of each first shift register circuit is electrically connected to the first clock signal line, and the other is electrically connected to the second clock signal line. The first initial compensation signal line is electrically connected to the first shift register circuit farthest from the first sub-display area among the first shift register circuits corresponding to the first sub-display area. In the first display mode, the first clock signal line is at an invalid level during a scanning period of each row of pixel units corresponding to the second sub-display area, and provides a first clock signal during a scanning period of each row of pixel units corresponding to the first sub-display area. The second clock signal line is at an invalid level during a scanning period of each row of pixel units corresponding to the second sub-display area, and provides a second clock signal during a scanning period of each row of pixel units corresponding to the first sub-display area. The first initial compensation signal line provides an initial signal to the first shift register circuit in the first sub-display area that is farthest from the first area.

4. The display panel according to claim 1, wherein: For each group of cascaded first shift register circuits, the non-display area further includes: at least two clock signal line groups arranged in the third area and extending along the first direction, the clock signal line groups being arranged in a one-to-one correspondence with the sub-display areas, and each of the clock signal line groups including a first clock signal line and a second clock signal line. One of the first clock signal terminal and the second clock signal terminal of each first shift register circuit in each sub-display area is electrically connected to the first clock signal line of a corresponding group of clock signal line groups, and the other is electrically connected to the second clock signal line of the group of clock signal line groups, and In the clock signal line group, the first clock signal line provides a first clock signal during the scanning time period of each row of pixel units corresponding to the corresponding sub-display area, and is an invalid level in other time periods. The first clock signal line provides a second clock signal during the scanning time period of each row of pixel units corresponding to the corresponding sub-display area, and is an invalid level in other time periods.

5. The display panel according to any one of claims 2 to 4, characterized in that: The first clock signal and the second clock signal are both periodic signals with high level and low level alternately arranged. During the period when the first clock signal is at a valid level, the second clock signal is at an invalid level for at least part of the period; during the period when the second clock signal is at a valid level, the first clock signal line is at an invalid level for at least part of the period.

6. The display panel according to claim 5, wherein: The first clock signal and the second clock signal are inverted signals of each other.

7. The display panel according to any one of claims 2 to 4, characterized in that: The first clock signal terminal and the second clock signal terminal of the first shift register circuit generate a scanning signal for the corresponding row of pixel units based on the received clock signal.

8. The display panel according to any one of claims 2 to 4, characterized in that: The display area includes three sub-display areas.

9. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 8.

10. A display driving method applied to the display panel according to any one of claims 1 to 8, characterized in that: include: In the first shift register circuit corresponding to the first sub-display area, the rising edge of the clock signal received by the first shift register circuit away from the first area approaches the rising edge of the clock signal received by the first shift register circuit close to the first area, and the falling edge approaches the falling edge of the clock signal received by the first shift register circuit close to the first area.

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