Fabricating semiconductor structures for semiconductor packages

Abstract

Systems, devices, and methods for fabricating semiconductor structures for semiconductor packages are provided. An exemplary method includes forming a stack of conductive layers interleaved with isolation layers in a redistribution layer (RDL) structure of a semiconductor device. First contact structures and second contact structures are formed in the RDL structure, where each of the first contact structures extends through portions of the conductive layer and the isolation layer and is connected to a pad on a first interface of the RDL structure, each of the second contact structures is connected to a respective one of the first contact structures through one of the conductive layers, and each of the second contact structures is connected to a pad on a second interface of the RDL structure opposite the first interface.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a manufacturing method for the semiconductor device. Background Art

[0002] Semiconductor devices can have various structures to facilitate the semiconductor packaging process. A redistribution layer (RDL) on a semiconductor chip can reorganize the electrical connections to the semiconductor chip. When manufacturing an integrated circuit, it is common to have a set of I / O pads that are wire-bonded to the pins of the package. RDL is an additional wiring layer on the chip that can enable bonding outward from different locations on the chip, making chip-to-chip bonding simpler. RDL can also be used to distribute contact points around the die so that solder balls can be applied, and the thermal stress of the installation can be dispersed.

[0003] In highly integrated semiconductor packages such as heterogeneous integration, a large number of chips are stacked both horizontally and vertically. The horizontal and vertical stacking of chips often uses RDL interconnect layers to redistribute chip signal lead-out locations. Therefore, it is usually necessary to reduce RDL manufacturing costs and improve efficiency. Summary of the invention

[0004] The present disclosure describes methods, apparatus, systems, and techniques for fabricating semiconductor structures for use in semiconductor packaging.

[0005] Certain aspects of the subject matter described herein can be implemented as a semiconductor device. The semiconductor device includes a chip and an RDL structure disposed on the chip. The RDL structure includes: a stack of conductive layers interlaced with isolation layers; a first pad located on a first interface of the RDL structure; a second pad located on a second interface of the RDL structure opposite to the first interface; a first connection region including a first contact structure, wherein each of the first contact structures extends through a portion of the conductive layer and the isolation layer, and each of the first contact structures is connected to one of the first pads; and a second connection region including a second contact structure, wherein each of the second contact structures is connected to a corresponding one of the first contact structures through one of the conductive layers, and each of the second contact structures is connected to one of the second pads.

[0006] The semiconductor device may include one or more of the following features.

[0007] In some embodiments, the contact structure in the second contact structure includes a first end and a second end opposite to the first end, the second end is connected to one of the second pads, and a size of the first end is larger than a size of the second end.

[0008] In some embodiments, the contact structure in the first contact structure includes a first end and a second end opposite to the first end, the first end is connected to one of the first pads, and a size of the first end is the same as a size of the second end.

[0009] In some embodiments, each of the first contact structures includes a first conductive material, and each of the second contact structures includes a second conductive material.

[0010] In some embodiments, the RDL structure includes a gap separating a pair of adjacent contact structures in the first contact structure and separating a pair of adjacent contact structures in the second contact structure, and the contact structures in the first contact structure and the contact structures in the second contact structure are located on the same side of the gap and are connected by one of the conductive layers.

[0011] In some embodiments, a pair of adjacent contact structures in the first contact structure connected to the same conductive layer in the conductive layer are isolated by a first gap in the RDL structure, and a pair of adjacent contact structures in the second contact structure connected to the same conductive layer in the conductive layer are isolated by a second gap in the RDL structure.

[0012] In some embodiments, the first gap is the same as the second gap.

[0013] Certain aspects of the subject matter described herein can be implemented as a semiconductor package structure. The semiconductor package structure includes a first chip, a second chip, and an RDL structure disposed on the second chip and connected to the first chip, wherein the first chip and the second chip are located on opposite sides of the RDL structure, and the RDL structure includes: a stack of conductive layers interlaced with isolation layers; a first pad located on a first interface of the RDL structure; a second pad located on a second interface of the RDL structure opposite to the first interface, and the RDL structure is connected to the first chip through the first pad and to the second chip through the second pad; a first connection region including a first contact structure, wherein each of the first contact structures extends through a portion of the conductive layer and the isolation layer, and each of the first contact structures is connected to one of the first pads; and a second connection region including a second contact structure, wherein each of the second contact structures is connected to a corresponding one of the first contact structures through one of the conductive layers, and each of the second contact structures is connected to one of the second pads.

[0014] The semiconductor package structure may include one or more of the following features.

[0015] In some embodiments, each of the first pads is connected to the first chip through a micro bump or a hybrid bonding structure.

[0016] In some embodiments, the contact structure in the second contact structure includes a first end and a second end opposite to the first end, the second end is connected to one of the second pads, and a size of the first end is larger than a size of the second end.

[0017] In some embodiments, the contact structure in the first contact structure includes a first end and a second end opposite to the first end, the first end is connected to one of the first pads, and a size of the first end is the same as a size of the second end.

[0018] In some embodiments, each of the first contact structures includes a first conductive material, and each of the second contact structures includes a second conductive material.

[0019] In some embodiments, the RDL structure includes a gap separating a pair of adjacent contact structures of a first contact structure, the gap separating a pair of adjacent contact structures of a second contact structure, and the contact structures in the first contact structure and the contact structures in the second contact structure are located on the same side of the gap and are connected by one of the conductive layers.

[0020] In some embodiments, a pair of adjacent contact structures in the first contact structure connected to the same conductive layer in the conductive layer are isolated by a first gap in the RDL structure, and a pair of adjacent contact structures in the second contact structure connected to the same conductive layer in the conductive layer are isolated by a second gap in the RDL structure.

[0021] In some embodiments, the first gap is the same as the second gap.

[0022] Certain aspects of the subject matter described herein can be implemented as a method. The method includes forming a stack of conductive layers interleaved with isolation layers in an RDL structure of a semiconductor device. First contact structures and second contact structures are formed in the RDL structure, wherein each of the first contact structures extends through portions of the conductive layers and the isolation layers and is connected to a pad on a first interface of the RDL structure, each of the second contact structures is connected to a corresponding one of the first contact structures through one of the conductive layers, and each of the second contact structures is connected to a pad on a second interface of the RDL structure opposite the first interface.

[0023] The method may include one or more of the following features.

[0024] In some embodiments, the method also includes forming a gap in the RDL structure to separate a pair of adjacent contact structures in the first contact structure and to separate a pair of adjacent contact structures in the second contact structure, wherein the contact structures in the first contact structure and the contact structures in the second contact structure are located on the same side of the gap and are connected by one of the conductive layers.

[0025] In some embodiments, the method also includes filling a first isolation material into the gap, filling a second isolation material into each of the first contact structures to form an isolation layer on an inner surface of each of the first contact structures, and filling a first conductive material in the first contact structure and filling a second conductive material in the second contact structure.

[0026] In some embodiments, the method further includes forming a third isolation material over the second conductive material in the second contact structure after filling the second conductive material in the second contact structure.

[0027] In some embodiments, each of the first contact structures includes a first trench, and each of the second contact structures includes a second trench.

[0028] The details of one or more implementations of the subject matter of the present disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings, which are incorporated herein and form a part of the present disclosure, illustrate various aspects of the present disclosure and, together with the written description, further serve to explain the principles of the present disclosure and enable one of ordinary skill in the relevant art to make and use the present disclosure.

[0030] Figure 1 A cross-sectional view of an exemplary semiconductor device having an RDL structure disposed on a chip is shown.

[0031] Figure 2A A cross-sectional view of an exemplary semiconductor package structure is shown.

[0032] Figure 2B A top view of an exemplary semiconductor package structure is shown.

[0033] Figure 2C Another cross-sectional view of an exemplary semiconductor package structure is shown.

[0034] Figures 3A-3E Shown for manufacturing Figure 1 An exemplary process for RDL structure in FIG.

[0035] Figure 4 A cross-sectional view of an exemplary semiconductor package structure including a micro-bump structure for connecting an RDL structure to a chip is shown.

[0036] Figure 5 is a flow chart of an exemplary process for forming a semiconductor structure.

[0037] Figure 6A block diagram of an example tier system with storage is shown.

[0038] Like reference numerals and designations in the various drawings indicate like elements.It should also be understood that the various exemplary embodiments shown in the drawings are merely illustrative representations and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0039] The present specification relates to methods, apparatus, systems and techniques for manufacturing semiconductor structures for semiconductor packaging. A redistribution layer (RDL) is a layer added to an integrated circuit or semiconductor chip to redistribute electrical connections, which allows multiple dies to be integrated into a single package. In some cases, manufacturing an RDL structure may involve multiple thin film depositions, as well as multiple etching and material filling steps. In order to simplify RDL manufacturing, a stack of conductive layers interlaced with isolation layers can be deposited at one time to form the body of the RDL structure. Multiple contact structures (e.g., trenches) can then be formed in the stack, and the multiple contact structures are connected to each other in a specific pattern and through the conductive layers in the stack. Therefore, these interconnected contact structures can be electrically connected to I / O pads, which can redistribute electrical connections to the dies in the semiconductor package.

[0040] Embodiments of the present disclosure may provide one or more of the following technical advantages. For example, the disclosed RDL manufacturing process may reduce the complexity and cost associated with manufacturing RDL and semiconductor packaging processes, because the disclosed RDL manufacturing process may avoid multiple thin film deposition processes during RDL manufacturing, and the processes associated with etching and filling materials during RDL manufacturing may also be simplified. In addition, as the number of interlaced conductive layers and isolation layers in the disclosed RDL structure increases, the cost associated with manufacturing RDL may be reduced. Furthermore, the disclosed RDL manufacturing process may increase the flexibility of adjusting the number of pads available for electrical connection to the die.

[0041] Figure 1A cross-sectional view of an exemplary semiconductor device 100 having an RDL structure 180 disposed on a chip 130 is shown. The RDL structure 180 includes a stack 120 of conductive layers 120A interlaced with isolation layers 120B. A first group of pads 150 (e.g., first pads) are located on a first interface of the RDL structure 180. A second group of pads 160 (e.g., second pads) are located on a second interface of the RDL structure opposite to the first interface and are connected to the chip 130. A first connection region 191 includes a first group of contact structures 140 (e.g., first contact structures). Each contact structure in the first group of contact structures 140 extends through portions of the conductive layer 120A and the isolation layer 120B, and each of the first group of contact structures 140 is connected to a corresponding pad in the first group of pads 150. In some cases, the conductive layer 120A may include a conductive material, such as copper (Cu). The isolation layer 120B may include a dielectric material, such as silicon oxide. The first group of pads 150 may include a conductive material, such as aluminum. The second group of pads 160 may include a conductive material, such as aluminum. In some cases, the number of conductive layers 120A may be the same as the number of isolation layers 120B, for example, each of 120A and 120B may have three layers. In some cases, the number of conductive layers 120A and the number of isolation layers 120B may also differ by one layer.

[0042] The second connection region 192 includes a second group of contact structures 170 (e.g., second contact structures). Each of the contact structures in the second group of contact structures 170 is connected to a corresponding contact structure in the first group of contact structures 140 through one of the conductive layers 120A, and each of the contact structures in the second group of contact structures 170 is connected to a corresponding pad in the second group of pads 160.

[0043] In some embodiments, the contact structure in the second group of contact structures 170 includes a first end and a second end opposite to the first end. The second end is electrically connected to a corresponding pad in the second group of pads 160, and the size of the first end is larger than the size of the second end. In some cases, the second group of contact structures 170 can be formed by etching in a direction from a side of the RDL structure 180 having the second group of pads 160 to an opposite side of the RDL structure 180 having the first group of pads 150.

[0044] In some embodiments, the contact structure in the first group of contact structures 140 includes a first end and a second end opposite to the first end. The first end is electrically connected to a corresponding pad in the first group of pads 150, and the size of the first end can be larger than the size of the second end. In some cases, the first group of contact structures 140 can be formed by etching in a direction from a side of the RDL structure 180 having the first group of pads 150 to an opposite side of the RDL structure 180 having the second group of pads 160.

[0045] In some embodiments, each contact structure in the first set of contact structures 140 includes a first conductive material, and each contact structure in the second set of contact structures 170 includes a second conductive material.

[0046] Figure 2A The exemplary semiconductor package structure 200 is shown along Figure 2B Cross-sectional view along cutting line AB in FIG. Figure 2B A top view of an exemplary semiconductor package structure 200 is shown. Figure 2C The exemplary semiconductor package structure 200 is shown along Figure 2B Cross-sectional view along cutting line CD.

[0047] like Figure 2A As shown, the exemplary semiconductor package structure 200 includes an RDL structure (eg, Figure 1 The RDL structure 180 shown in FIG. 1 and two chips, namely, die 1 130 (eg, a first chip) and die 2 132 (eg, a second chip). Die 1 130 and die 2 132 are connected via the RDL structure 180. Figure 2A In the example shown, the pad 250 used to connect the RDL structure 180 to the die 2 132 is a hybrid bonding structure. Figure 4 In some other examples shown, pads 250 may be micro-bump pads.

[0048] exist Figure 2B In the RDL structure 180, multiple contact structures having the same label (e.g., 1, 2, or 3) and in the same connection region (e.g., 191 or 192) can be electrically connected to the same conductive layer of the conductive layer 120A. However, if any pair of contact structures in the multiple contact structures having the same label and located in the same connection region are separated by a gap (e.g., gap 210, 212, 214, or 216), the pair of contact structures are electrically isolated by the gap. In some cases, each gap in the RDL structure 180 can extend through all conductive layers 120A to electrically isolate each pair of conductive structures separated by the gap in the RDL structure 180.

[0049] In some embodiments, RDL structure 180 includes a gap 210 that separates a pair of adjacent contact structures (e.g., contact structures 242 and 244) in first group of contact structures 140. Gap 210 may also separate a pair of adjacent contact structures (e.g., contact structures 272 and 274) in second group of contact structures 170. In some cases, contact structures in first group of contact structures 140 (e.g., contact structure 244) and contact structures in second group of contact structures 170 (e.g., contact structure 272) are located on the same side of gap 210 and are connected through one of conductive layers 120A because contact structures 244 and 272 are both connected to the same conductive layer in conductive layer 120A.

[0050] In some embodiments, RDL structure 180 includes more than one slot, such as slots 210, 212, 214, and 216. Two contact structures (e.g., 242 and 274) between two adjacent slots (e.g., slots 210 and 212) can be connected through one of conductive layers 120A because contact structures 242 and 274 are both connected to the same conductive layer in conductive layers 120A.

[0051] In some embodiments, a pair of adjacent contact structures (e.g., 242 and 246) in the first group of contact structures 140 that are electrically connected to the same conductive layer in the conductive layer 120A are electrically isolated by a first gap (e.g., 212) in the RDL structure 180. A pair of adjacent contact structures (e.g., 272 and 274) in the second group of contact structures 170 that are electrically connected to the same conductive layer in the conductive layer 120A are electrically isolated by a second gap (e.g., 210) in the RDL structure 180. In some cases, the first gap can be the same as the second gap. For example, the gap 210 can electrically isolate the contact structures 242 and 244 in the first group of contact structures 140. The gap 210 can also electrically isolate the contact structures 272 and 274 in the second group of contact structures 170.

[0052] In some embodiments, the contact structures in the RDL structure 180 and the gaps separating the contact structures may be Figure 2B The patterns shown in FIG. 1 and FIG. 2 may be arranged in different patterns depending on the arrangement of the positions of the die pads on die 1 130 and die 2 132 to be connected to pads 160 and 250, respectively. In some cases, in first connection region 191, Figure 2B Each group of three contact structures (eg, contact structures 246, 247, and 248) arranged perpendicular to the cutting line AB may be arranged parallel to the cutting line AB. Thus, in the first connection region 191, Figure 2BEach slit segment in the arrangement perpendicular to the cut line AB (eg, the segment of the slit 212 separating the contact structures 242 and 246) may be arranged parallel to the cut line AB. In some cases, Figure 2B Each group of three contact structures (eg, contact structures 246 , 247 , and 248 ) arranged along one side of the slit may be arranged in a reverse order.

[0053] exist Figure 2C In the figure, it is shown that Figure 2B In some cases, the three contact structures may be Figure 1 The three contact structures 140 in the first connection region 191 in FIG. Figure 2C As shown, each of the three contact structures is connected to a corresponding pad 250 that connects the RDL structure 180 to the die 2 132. Each of the three contact structures is connected to only one corresponding conductive layer, e.g. Figure 1 The conductive layer 120A in the second connection region 192 is formed so that each of the three contact structures can connect the corresponding pad 250 to another contact structure in the second connection region 192 through the corresponding conductive layer, thereby connecting its corresponding pad 250 to another pad 160 in the second connection region 192. In this way, Figure 2B Each pad 250 in the first connection region 191 can be connected to Figure 2B The pads in the second connection region 192 are, for example, Figure 1 The pad 160 in the embodiment of the present invention.

[0054] FIG. 3A to FIG. 3E Shown for manufacturing Figure 1 An exemplary process of the RDL structure in FIG. Figure 3A As shown, an exemplary process includes forming a stack of conductive layers 120A interleaved with isolation layers 120B in an RDL structure 180 of a semiconductor device. In some cases, conductive layers 120A may include a conductive material, such as copper (Cu). Isolation layers 120B may include a dielectric material, such as silicon oxide. The interleaved conductive layers 120A and isolation layers 120B may be formed by depositing one layer over another so as to be interleaved in other structures (e.g., Figure 1Before the contact structures 140 and 170 in the embodiment are formed inside the stack of interlaced conductive layers 120A and isolation layers 120B, a complete stack of conductive layers 120A interlaced with isolation layers 120B is formed. The number of conductive layers 120A can be the same as the number of isolation layers 120B, for example, each of 120A and 120B can have three layers. The number of conductive layers 120A and the number of isolation layers 120B can also differ by one layer. In some cases, the exemplary process can also include forming a hard mask 310 above the stack. The hard mask 310 can be used to help form Figure 1 The contact structures 140 and 170 in FIG.

[0055] like Figure 3B As shown, the exemplary process includes forming a first group of contact structures 140 and a second group of contact structures 170 in an RDL structure 180. Each contact structure in the first group of contact structures 140 extends through the conductive layer 120A and a portion of the conductive layer 120A, and each contact structure in the first group of contact structures 140 is connected to a corresponding pad on a first interface of the RDL structure 180. Each contact structure in the second group of contact structures 170 is connected to a corresponding contact structure in the first group of contact structures 140 through one of the conductive layers 120A, and each contact structure in the second group of contact structures 170 is connected to a corresponding pad on a second interface of the RDL structure opposite to the first interface.

[0056] In some embodiments, each contact structure in the first set of contact structures 140 includes a corresponding first trench, and each contact structure in the second set of contact structures 170 includes a corresponding second trench.

[0057] In some embodiments, an exemplary process may include forming a gap, such as gap 210, in the RDL structure 180 to separate a pair of adjacent contact structures (e.g., contact structures 242 and 244) in the first group of contact structures 140. The gap 210 also separates a pair of adjacent contact structures (e.g., contact structures 272 and 274) in the second group of contact structures 170. The contact structures (e.g., contact structure 244) in the first group of contact structures 140 and the contact structures (e.g., contact structure 272) in the second group of contact structures 170 are located on the same side of the gap 210 and are connected through a common conductive layer in the conductive layer 120A.

[0058] In some implementations, the exemplary process may include forming more than one slit, for example, slits 210, 212, 214, and 216. Two contact structures (for example, contact structures 242 and 274) located between two adjacent slits (for example, slits 210 and 212) may be connected through a common conductive layer in conductive layer 120A.

[0059] In some embodiments, the contact structures in the RDL structure 180 and the gaps separating the contact structures may be Figure 3B The patterns shown in FIG. 1 and FIG. 2 may be arranged in different patterns, depending on the arrangement of the locations of the die pads on die 1 130 and die 2 132 to be connected to the contact structures in RDL structure 180. Figure 2B Additional details can be found in the description.

[0060] like Figure 3C As shown, the exemplary process includes filling the first isolation material into each of the gaps 210, 212, 214, and 216, filling the second isolation material in each of the first group of contact structures 140 to form an isolation layer on the inner surface of each of the first group of contact structures 140, and filling the second isolation material in each of the second group of contact structures 170 to form an isolation layer on the inner surface of each of the second group of contact structures 170. As a result, when each of the first group of contact structures 140 or each of the second group of contact structures 170 extends through one or more conductive layers 120A in the RDL structure 180, the isolation layer formed on the inner surface of each of the contact structures in 140 and 170 using the second isolation material can isolate each contact structure from the conductive layer 120A through which it extends.

[0061] In some embodiments, a pair of adjacent contact structures (e.g., contact structures 242 and 246) in the first group of contact structures 140 that are electrically connected to the same conductive layer in the conductive layer 120A are electrically isolated by a first gap (e.g., gap 212) in the RDL structure 180. A pair of adjacent contact structures (e.g., contact structures 272 and 274) in the second group of contact structures 170 that are electrically connected to the same conductive layer in the conductive layer 120A are electrically isolated by a second gap (e.g., gap 210) in the RDL structure 180. In some cases, the first gap can be the same as the second gap. For example, gap 210 can electrically isolate contact structures 242 and 244 in the first group of contact structures 140. Gap 210 can also electrically isolate contact structures 272 and 274 in the second group of contact structures 170.

[0062] like Figure 3D As shown, the exemplary process includes: filling the second conductive material in the second group of contact structures 170 so that the second conductive material in each of the second group of contact structures 170 can be connected to a corresponding pad, for example Figure 2A The pads 160 in the second group of contact structures 170 may be connected to the die 1130; and in the second group of contact structures 170, a third isolation material is formed over the second conductive material.

[0063] like Figure 3EAs shown, the exemplary process includes: filling the first conductive material in the first group of contact structures 140 so that the first conductive material in each of the first group of contact structures 140 can be connected to a corresponding pad, for example Figure 2A 250 connected to die 2 132; removing hard mask 310; and obtaining the resulting RDL structure 180. In some cases, chemical mechanical polishing (CMP) can be used to remove hard mask 310. The resulting RDL structure 180 also includes Figure 3E The second side is opposite to the side shown, and the second side exposes the first conductive material in the first set of contact structures 140. The second side exposes the second conductive material in the second set of contact structures 170, which can be connected to the pad 160, which can be connected to the pad 160. Figure 2A The die 1 130 in.

[0064] Figure 4 A cross-sectional view of an exemplary semiconductor package structure including a microbump structure for connecting an RDL structure to a chip is shown. In some embodiments, Figure 4 The RDL structure 480 can be used with Figure 1 The RDL structure 180 is the same or similar. Figure 4 As shown, the pad 450 for connecting the RDL structure to the die 2 has a micro-bump structure.

[0065] In some embodiments, to make Figure 4 In the exemplary semiconductor package structure of FIG. 1 , a die 1 130 may be manufactured first. Then, an RDL structure 480 may be formed on the die 1 130, wherein the RDL structure 480 may be formed using Figure 2A Any hybrid bonding structure shown in the pad 250 or Figure 4 The micro bump structure shown in the pad 450 in FIG. 1 is connected to the tube core 1 130. After the RDL structure 480 is formed on the tube core 1 130, the tube core 2 132 can be connected to the RDL structure 480 to form Figure 4 The exemplary semiconductor package structure in FIG. can then be used Figure 2A Any hybrid bonding structure shown in the pad 250 or Figure 4 The micro-bump structure shown in pad 450 in FIG. 4 connects RDL structure 480 to die 2 132 .

[0066] In some embodiments, to make Figure 4 In the exemplary semiconductor package structure of FIG. 1 , the die 2 132 may be manufactured first. Then, an RDL structure 480 may be formed on the die 2 132, wherein the RDL structure 480 may be formed using Figure 2A Any hybrid bonding structure shown in the pad 250 or Figure 4The micro bump structure shown in the pad 450 in FIG. 1 is connected to the die 2 132. After forming the RDL structure 480 over the die 2 132, the die 1 130 can be connected to the RDL structure 480 to form Figure 4 The exemplary semiconductor package structure in FIG. can then be used Figure 2A Any hybrid bonding structure shown in the pad 250 or Figure 4 The micro bump structure shown in pad 450 in FIG. 4 connects RDL structure 480 to die 1 130 .

[0067] In some embodiments, Figure 4 The RDL structure 480 in the embodiment may be a stack 120 of conductive layers 120A interlaced with isolation layers 120B. A first group of pads 150 (e.g., first pads) are located on a first interface of the RDL structure 480, and each of the first group of pads 150 is connected to a corresponding pad 450, which in turn is connected to the die 2 132. A second group of pads 160 (e.g., second pads) are located on a second interface of the RDL structure opposite to the first interface and are connected to the die 1130. The first connection region 191 includes a first group of contact structures 140 (e.g., first contact structures). Each of the first group of contact structures 140 extends through portions of the conductive layer 120A and the isolation layer 120B, and each of the first group of contact structures 140 is connected to a corresponding pad in the first group of pads 150. In some cases, the conductive layer 120A may include a conductive material, such as copper (Cu). The isolation layer 120B may include a dielectric material, such as silicon oxide. The first group of pads 150 may include a conductive material, such as aluminum. The second group of pads 160 may include a conductive material, such as aluminum. In some cases, the number of conductive layers 120A may be the same as the number of isolation layers 120B, for example, each of 120A and 120B may have three layers. In some cases, the number of conductive layers 120A and the number of isolation layers 120B may also differ by one layer.

[0068] The second connection region 192 includes a second group of contact structures 170 (e.g., second contact structures). Each of the contact structures in the second group of contact structures 170 is connected to a corresponding contact structure in the first group of contact structures 140 through one of the conductive layers 120A, and each of the contact structures in the second group of contact structures 170 is connected to a corresponding pad in the second group of pads 160.

[0069] In some embodiments, the contact structure in the second group of contact structures 170 includes a first end and a second end opposite to the first end. The second end is electrically connected to a corresponding pad in the second group of pads 160, and the size of the first end is larger than the size of the second end. In some cases, the second group of contact structures 170 can be formed by etching in a direction from the side of the RDL structure 480 having the second group of pads 160 to the opposite side of the RDL structure 480 having the first group of pads 150.

[0070] In some embodiments, the contact structure in the first group of contact structures 140 includes a first end and a second end opposite to the first end. The first end is electrically connected to a corresponding pad in the first group of pads 150, and the size of the first end can be larger than the size of the second end. In some cases, the first group of contact structures 140 can be formed by etching in a direction from a side of the RDL structure 480 having the first group of pads 150 to an opposite side of the RDL structure 480 having the second group of pads 160.

[0071] In some embodiments, each contact structure in the first set of contact structures 140 includes a first conductive material, and each contact structure in the second set of contact structures 170 includes a second conductive material.

[0072] Figure 5 is a flow chart of an exemplary process for forming a semiconductor structure. The semiconductor structure may be Figure 1 The process can be similar to or the same as the RDL structure 180, or is part of the RDL structure 180. Figure 1 The process may include forming Figure 2A-2B or Figures 3A-3E A process for manufacturing a semiconductor structure in a semiconductor device. The process includes steps that can be performed in any suitable order and / or in any combination.

[0073] At 502 , the exemplary process includes forming a stack of conductive layers interleaved with isolation layers in an RDL structure of a semiconductor device.

[0074] At 504, the exemplary process includes forming first contact structures and second contact structures in the RDL structure. In some embodiments, each of the first contact structures extends through portions of the conductive layer and the isolation layer and is connected to a pad on a first interface of the RDL structure. Each of the second contact structures is connected to a corresponding one of the first contact structures through one of the conductive layers. Each of the second contact structures is connected to a pad on a second interface of the RDL structure opposite the first interface.

[0075] Figure 6600 is a block diagram of an exemplary system 600 having a storage device. The system 600 may be a mobile phone, a desktop computer, a notebook computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 6 As shown, system 600 may include a host 608 and a memory system 602 having one or more storage devices 604 and a memory controller 606. Host 608 may be a processor such as a central processing unit (CPU) of an electronic device, or a system on chip (SoC) such as an application processor (AP). Host 608 may be configured to send data to storage device 604 or receive data from storage device 604.

[0076] The storage device 604 may be any storage device disclosed in the present disclosure. According to some embodiments, the memory controller 606 is coupled to the storage device 604 and the host 608 and is configured to control the storage device 604. The memory controller 606 may manage the data stored in the storage device 604 and communicate with the host 608. In some embodiments, the memory controller 606 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 606 is designed to operate in a high duty cycle environment SSD, or in an embedded multimedia card (eMMC) used as a data storage device for mobile devices such as smart phones, tablet computers, notebook computers, and enterprise storage arrays. The memory controller 606 may be configured to control the operation of the storage device 604, such as read, erase, and program operations. The memory controller 606 may also be configured to manage various functions regarding data stored or to be stored in the storage device 604, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 606 is also configured to process error correction codes (ECC) regarding data read from or written to the storage device 604. The memory controller 606 may also perform any other suitable functions, such as formatting the storage device 604.

[0077] The memory controller 606 may communicate with an external device (e.g., the host 608) according to a specific communication protocol. For example, the memory controller 606 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, an express PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0078] The memory controller 606 and one or more storage devices 604 can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 602 can be implemented and packaged into different types of terminal electronic products. In some embodiments, the memory system 602 can be implemented and packaged into an SSD, such as a client SSD or an enterprise SSD. The client SSD can be used in electronic devices such as personal computers, digital cameras, smart phones, mobile devices, etc. The enterprise SSD can be used in enterprise environments such as data centers or servers.

[0079] The subject matter described in the present disclosure and the implementation of actions and operations can be implemented in digital electronic circuit systems, in tangibly embodied computer software or firmware, in computer hardware, including the structures disclosed in the present disclosure and their structural equivalents, or a combination of one or more thereof. The implementation of the subject matter described in the present disclosure can be implemented as one or more computer programs, such as one or more modules of computer program instructions encoded on a computer program carrier, which are executed by a data processing device or control the operation of the data processing device. The carrier can be a tangible non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagation signal, such as a machine-generated electrical, optical or electromagnetic signal, which is generated to encode information for transmission to a suitable receiver device for execution by a data processing device. The computer storage medium can be the following or a part thereof: a machine-readable storage device, a machine-readable storage substrate, a random or serial access storage device, or a combination of one or more thereof. The computer storage medium is not a propagated signal.

[0080] It is worth noting that references in this disclosure to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not necessarily every embodiment includes the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it would be within the knowledge of a person skilled in the relevant art to affect such feature, structure, or characteristic in conjunction with other embodiments (whether or not explicitly described).

[0081] In general, terms can be understood at least in part based on their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "one" or "the" can also be understood to express singular usage or to express plural usage. In addition, also depending at least in part on the context, the term "based on" can be understood to not necessarily be intended to convey a set of exclusive factors, but can allow for the presence of additional factors that are not necessarily explicitly described.

[0082] It should be readily understood that the meanings of "on", "above" and "over" in this disclosure should be interpreted in the broadest sense, such that "on" means not only "directly on" something, but also includes the meaning of being "on" something with intervening features or layers. Furthermore, "above" or "over" not only means "above" or "over" something, but can also include the meaning of being "above" or "over" something without intervening features or layers (i.e., directly on something).

[0083] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to describe the relationship of one element or feature to another (or multiple) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0084] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer can extend over the entire lower or upper structure, or can have a range less than the range of the lower or upper structure. In addition, the layer can be a region of a homogeneous or heterogeneous continuous structure, and the thickness of the region is less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure or between any pair of horizontal planes at the top surface and the bottom surface. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above and / or below it. The layer can include multiple layers. For example, the interconnect layer can include one or more conductive and contact layers (wherein contacts, interconnect lines and / or vertical interconnect paths (vias) are formed) and one or more dielectric layers.

[0085] As used herein, the term "nominal / nominally" refers to an expected or target value for a characteristic or parameter of a component or process operation set during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. As used herein, a range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" indicates a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "approximately" may indicate a value of a given quantity that varies, for example, within 10%-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0086] In the present disclosure, the term “horizontal / horizontally / lateral / laterally” means nominally parallel to a lateral surface of a substrate, and the term “vertical” or “vertically” means nominally perpendicular to a lateral surface of a substrate.

[0087] The present disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include an embodiment in which the first feature and the second feature may be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0088] The foregoing description of specific implementations can be easily modified and / or adapted to various applications. Therefore, based on the teaching and guidance presented herein, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments.

[0089] Although the present disclosure contains many specific implementation details, these should not be interpreted as limitations on the scope of the protection claimed as defined by the claims themselves, but rather as descriptions of features that may be specific to a particular embodiment. Certain features described in the present disclosure in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in multiple embodiments in any suitable subcombination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features may be deleted from the claimed combination in some cases, and claims may be directed to subcombinations or variations of subcombinations.

[0090] Similarly, although operations are described in the drawings and described in the claims in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in a continuous order, or that all of the operations shown be performed to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0091] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the appended claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying drawings do not necessarily require the particular order shown or sequential order to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

[0092] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device comprising: chip; as well as A redistribution layer (RDL) structure is provided on the chip, wherein the RDL structure comprises: a stack of conductive layers interleaved with isolation layers; a first pad located on a first interface of the RDL structure; a second pad located on a second interface of the RDL structure opposite to the first interface; a first connection region comprising first contact structures, wherein each of the first contact structures extends through portions of the conductive layer and the isolation layer, and wherein each of the first contact structures is connected to one of the first pads; and A second connection region includes second contact structures, wherein each of the second contact structures is connected to a corresponding one of the first contact structures through one of the conductive layers, and each of the second contact structures is connected to a second one of the second pads.

2. The semiconductor device according to claim 1, wherein The contact structure in the second contact structure includes a first end and a second end opposite to the first end, the second end is connected to one of the second pads, and a size of the first end is larger than a size of the second end.

3. The semiconductor device according to claim 1 or 2, wherein: A contact structure in the first contact structures includes a first end and a second end opposite to the first end, the first end is connected to one of the first pads, and a size of the first end is the same as a size of the second end.

4. The semiconductor device according to any one of claims 1 to 3, wherein: Each of the first contact structures includes a first conductive material, and each of the second contact structures includes a second conductive material.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The RDL structure includes a gap separating a pair of adjacent contact structures in the first contact structures and separating a pair of adjacent contact structures in the second contact structures, and the contact structures in the first contact structures and the contact structures in the second contact structures are located on the same side of the gap and are connected through one of the conductive layers.

6. The semiconductor device according to any one of claims 1 to 5, wherein: A pair of adjacent contact structures in the first contact structure connected to the same conductive layer in the conductive layer are separated by a first gap in the RDL structure, and a pair of adjacent contact structures in the second contact structure connected to the same conductive layer in the conductive layer are separated by a second gap in the RDL structure.

7. The semiconductor device according to claim 6, wherein: The first gap is the same as the second gap.

8. A semiconductor packaging structure, comprising: First chip; The second chip; as well as a redistribution layer (RDL) structure disposed on the second chip and connected to the first chip, wherein the first chip and the second chip are located on opposite sides of the RDL structure, and wherein the RDL structure comprises: a stack of conductive layers interleaved with isolation layers; a first pad located on a first interface of the RDL structure; a second pad located on a second interface of the RDL structure opposite to the first interface, wherein the RDL structure is connected to the first chip through the first pad and to the second chip through the second pad; a first connection region comprising first contact structures, wherein each of the first contact structures extends through portions of the conductive layer and the isolation layer, and wherein each of the first contact structures is connected to one of the first pads; and A second connection region includes second contact structures, wherein each of the second contact structures is connected to a corresponding one of the first contact structures through one of the conductive layers, and each of the second contact structures is connected to a second one of the second pads.

9. The semiconductor package structure according to claim 8, wherein: Each of the first pads is connected to the first chip through a micro bump or a hybrid bonding structure.

10. The semiconductor package structure according to claim 8 or 9, wherein: The contact structure in the second contact structure includes a first end and a second end opposite to the first end, the second end is connected to one of the second pads, and a size of the first end is larger than a size of the second end.

11. The semiconductor package structure according to any one of claims 8 to 10, wherein: A contact structure in the first contact structures includes a first end and a second end opposite to the first end, the first end is connected to one of the first pads, and a size of the first end is the same as a size of the second end.

12. The semiconductor package structure according to any one of claims 8 to 11, wherein: Each of the first contact structures includes a first conductive material, and each of the second contact structures includes a second conductive material.

13. The semiconductor package structure according to any one of claims 8 to 12, wherein: The RDL structure includes a gap separating a pair of adjacent contact structures in the first contact structure, the gap separating a pair of adjacent contact structures in the second contact structure, and the contact structures in the first contact structure and the contact structures in the second contact structure are located on the same side of the gap and are connected through one of the conductive layers.

14. The semiconductor package structure according to any one of claims 8 to 13, wherein: A pair of adjacent contact structures in the first contact structure connected to the same conductive layer in the conductive layer are separated by a first gap in the RDL structure, and a pair of adjacent contact structures in the second contact structure connected to the same conductive layer in the conductive layer are separated by a second gap in the RDL structure.

15. The semiconductor package structure according to claim 14, wherein: The first gap is the same as the second gap.

16. A method comprising: forming a stack of conductive layers interleaved with isolation layers in a redistribution layer (RDL) structure of a semiconductor device; as well as A first contact structure and a second contact structure are formed in the RDL structure, wherein: Each of the first contact structures extends through portions of the conductive layer and the isolation layer and connects to a pad on a first interface of the RDL structure; as well as Each of the second contact structures is connected to a corresponding one of the first contact structures through one of the conductive layers, and each of the second contact structures is connected to a pad on a second interface of the RDL structure opposite to the first interface.

17. The method according to claim 16, further comprising: A gap is formed in the RDL structure to separate a pair of adjacent contact structures in the first contact structure and to separate a pair of adjacent contact structures in the second contact structure, wherein the contact structures in the first contact structure and the contact structures in the second contact structure are located on the same side of the gap and are connected through one of the conductive layers.

18. The method according to claim 17, further comprising: filling the gap with a first insulating material; filling a second isolation material in each of the first contact structures to form an isolation layer on an inner surface of each of the first contact structures; as well as The first contact structure is filled with a first conductive material, and the second contact structure is filled with a second conductive material.

19. The method according to claim 18, further comprising: After the second conductive material is filled in the second contact structure, a third isolation material is formed in the second contact structure over the second conductive material.

20. The method according to any one of claims 16 to 19, wherein: Each of the first contact structures includes a first trench, and each of the second contact structures includes a second trench.

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