Cooperative control method and system for digital power amplifier driven by multiple transmitting array elements

Abstract

The invention discloses a digital power amplifier cooperative control method and system for multi-transmitting array element driving. The method comprises the following steps: acquiring a filter inductor voltage, a voltage at two ends of a load, a current at two ends of the load and respective direct current side capacitor voltages of two power amplifiers; carrying out an impedance identification algorithm by using the voltage at the two ends of the load and the current at the two ends of the load to obtain a transducer equivalent circuit model and the structure of the whole circuit; carrying out prediction model calculation on the power amplifier output end current and the two direct current side capacitor voltages; constructing a value function of dynamic change of the weight factor, substituting different switch states for rolling optimization, and selecting an optimal switch state which enables the value function to be minimum; according to the invention, the rapid dynamic response of the system can be realized when the load parameters change in real time, the tracking performance of the system is improved, the DC side capacitor voltage of the inverter has small fluctuation in the working process, and the problems that the DC side voltage exceeds the withstand voltage level of a switching device and the device is damaged due to instability and imbalance of the DC side voltage are avoided.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a digital power amplifier collaborative control method and system for multi-transmitting array element driving. Background Art

[0002] As the core system in underwater detection and underwater acoustic communication devices, the electroacoustic transducer system directly affects the detection distance and detection accuracy of the underwater system. In order to achieve long-distance, high-precision underwater target detection and communication, the electroacoustic transducer is developing towards multi-element and high sound source level. A single digital power amplifier can no longer meet the growing power supply requirements of the transducer array. The power supply method composed of multiple digital power amplifiers has become an important means to drive the multi-element transmission system. The control system is the "brain" of the digital power amplifier. The single-module low latency and multi-module high synchronization control performance of the multi-digital power amplifier are of great significance for improving the sound wave quality and sound source level of the multi-element transmission system. And because the transducer is a current-driven load, the load parameters will change in real time during the driving process, so the traditional fixed-parameter current closed-loop control method cannot meet the control requirements of the transducer. At the same time, the DC side capacitor voltage of the cascaded H-bridge inverter fluctuates at all times during the working process, and the unstable voltage causes power device damage. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a digital power amplifier collaborative control method and system for multi-transmitting array element driving in view of the shortcomings of the existing technology, so as to realize the rapid dynamic response of the system when the load parameters change in real time, improve the system tracking performance, and at the same time enable the capacitor voltage on the DC side of the inverter to have smaller fluctuations during the working process, thereby avoiding the problem of exceeding the withstand voltage level of the switching device due to unstable and unbalanced DC side voltage, resulting in device damage.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: a digital power amplifier collaborative control method for multi-transmitting array element driving, the digital power amplifier includes an upper H-bridge and a lower H-bridge; the upper H-bridge is connected to the lower H-bridge; the upper H-bridge is connected to a filter inductor, the lower H-bridge is connected to a filter capacitor, the filter inductor is connected to the filter capacitor; the filter capacitor is connected to a transducer; the following steps are included:

[0005] Construct the following value function J:

[0006] in, is the load current setting value, is the load current prediction value, λ1 is the weight factor of the voltage control of the upper H-bridge DC side capacitor C1, λ2 is the weight factor of the voltage control of the lower H-bridge DC side capacitor C2, U DCSet the voltage value for the DC side capacitor, is the predicted value of the voltage of the DC link capacitor C1, is the predicted value of the voltage of the DC side capacitor C2;

[0007] The predicted values ​​corresponding to different switch states Substitute the value function J into the switch state that minimizes the value function J as the optimal switch state. k+1 Predicted value of the DC link capacitor C1 voltage at time The calculation formula is:

[0008]

[0009] Among them, T S is the control system sampling period, i o (t k ) is the current system sampling t k Load current value at the moment, T1, T2, T3, T4 are the upper H-bridge switch power devices.

[0010] t k+1 Predicted value of the DC link capacitor C2 voltage at time The calculation formula is:

[0011]

[0012] Among them, T S is the control system sampling period, T5, T6, T7, and T8 are the lower H-bridge switch power devices. o (t k ) is the current system sampling t k Load current value at the moment.

[0013] t k+1 The predicted value of load current at time i o (t k+1 ) is calculated as:

[0014]

[0015] Where, L is the equivalent inductance of the transducer, R is the real part of the transducer impedance, and U is f (t k ) is the voltage across the filter inductor at t k The sampling value at the time.

[0016] Where P is the active power of the transducer, I max is the peak value of the load current.

[0017] Among them, U max is the load voltage peak value, and f is the load voltage frequency.

[0018] The selection process of λ1 and λ2 includes: when the difference between the DC side capacitor voltage and the set value is less than or equal to 5%, λ1 and λ2 are 0.1; when the difference between the DC side capacitor voltage and the set value is greater than 5% and less than or equal to 10%, λ1 and λ2 are 0.2; when the difference between the DC side capacitor voltage and the set value is greater than 10% and less than or equal to 20%, λ1 and λ2 are 0.3; when the difference between the DC side capacitor voltage and the set value is greater than 20%, λ1 and λ2 are 0.4.

[0019] As an inventive concept, the present invention also provides a digital power amplifier collaborative control system for multi-transmitting array element driving, including a memory, a processor and a computer program stored in the memory; the processor executes the computer program to implement the steps of the above method.

[0020] Compared with the prior art, the beneficial effects of the present invention are as follows: compared with the traditional fixed parameter current control method, the present invention can achieve rapid dynamic response of the system when the load parameters change in real time, improve the system tracking performance, and at the same time can make the capacitor voltage on the DC side of the inverter have smaller fluctuations during the working process, avoiding the problem of exceeding the withstand voltage level of the switching device due to unstable and unbalanced DC side voltage, resulting in device damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic diagram of the software architecture of the multi-element digital power amplifier collaborative control system;

[0022] Figure 2 This is a schematic diagram of the hardware architecture of a multi-element digital power amplifier collaborative control system;

[0023] Figure 3 A flow chart of a high-precision DC side voltage-stabilized constant current drive model predictive control method for adaptive time-varying load parameters;

[0024] Figure 4 This is the impedance parameter identification flow chart;

[0025] Figure 5 It is the topological structure diagram of the digital power amplifier and the equivalent load of the transducer;

[0026] Figure 6 It is the control circuit and control principle diagram. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] Example 1

[0029] Embodiment 1 of the present invention provides a digital power amplifier cooperative control method for driving multiple transmitting array elements, comprising the following steps:

[0030] Step 1: Collect the filter inductor voltage U f (t k ), voltage across the load u o (t k ), the current across the load i o (t k ) and the DC side capacitor voltage U of the two amplifiers dc1 (t k ), U dc2 (t k );

[0031] Step 2: Use the voltage u across the load o (t k ), the current across the load i o (t k ) to perform impedance identification algorithm to obtain the transducer equivalent circuit model and the structure of the entire circuit;

[0032] Step 3: Calculate the prediction model of the power amplifier output current and the two DC side capacitor voltages according to the KVL and KCL equations;

[0033] Step 4: Construct a value function with dynamically changing weight factors, and substitute 16 different switch states for rolling optimization to select the optimal switch state that minimizes the value function and apply it;

[0034] The system uses a dual-link architecture composed of ARM and FPGA to share the calculation of impedance identification and model predictive control algorithm, improve the system program running speed, and reduce the delay of waveform transmission. At the same time, the control system adopts a total-split star topology architecture, which can synchronously drive multiple transducers to work.

[0035] In step 2, the sampled load voltage and current instantaneous value data are sent to the peak value calculation module, which calculates the load voltage and current peak value U according to the load voltage and current instantaneous value. max and I max. At the same time, the instantaneous values ​​of the sampled voltage and current are multiplied and then sent to the low-pass filter module to calculate the active power P of the transducer. The obtained voltage and current peak values ​​are then sent to the sliding window filter module, in which the voltage and current peak values ​​are filtered, that is, a sliding window of 8 data is established, and the earliest collected data among the eight data is removed every time a new data comes in, and the average value of the eight voltage and current peak data is calculated each time. Each time a sampling is performed, a new load voltage and current peak average value is obtained.

[0036] The control system is used to drive multiple 100kW digital power amplifiers with multiple transducer loads. The 100kW amplifier is cascaded from two 50kW amplifiers, and each 100kW amplifier drives one transducer. The software and hardware architectures of the control system are as follows: Figure 1 and 2 As shown. The dual-link architecture composed of ARM and FPGA is used to share the calculation amount of impedance identification and model predictive control algorithm, improve the system program running speed, and reduce the delay of waveform transmission. At the same time, the control system adopts a total-point star topology architecture, which can synchronously drive multiple transducers to work. Since the control methods of each 100kW power amplifier are exactly the same, the high-precision DC side voltage-stabilized constant current drive model predictive control method with adaptive time-varying load parameters for a single 100kW power amplifier is described in detail below. Figure 3 It is a control flow chart.

[0037] The impedance parameters of the transducer load change with time during operation, so it is necessary to identify the impedance parameters of the load based on the sampled load voltage and current value data. The process of impedance parameter identification is as follows: Figure 4 shown.

[0038] After obtaining the load voltage and current peaks and active power for filtering, the real and imaginary parts of the transducer impedance are calculated. The real part of the impedance is:

[0039]

[0040] The imaginary part of impedance is:

[0041]

[0042] Then the equivalent inductance of the transducer is:

[0043]

[0044] During the waveform transmission process, the impedance calculation process is continuously performed, and the impedance model of the transducer is dynamically updated.

[0045] The digital power amplifier topology adopts a cascaded five-level H-bridge inverter topology. After obtaining the impedance model, combined with the power amplifier module circuit model, the entire circuit topology is as follows: Figure 5 As shown, the control structure is as follows Figure 6 As shown. dc1 is the voltage across the upper H-bridge DC side capacitor C1, U dc2 is the voltage across the capacitor C2 on the DC side of the lower H-bridge. T1, T2, T3, T4 are the upper H-bridge switch power devices, and T5, T6, T7, T8 are the lower H-bridge switch power devices. The output filter uses an LC filter, and the filter inductor is L f , the filter capacitor is C f .

[0046] For the output of the power amplifier, according to KVL:

[0047]

[0048] Among them U ab (t) is the output port voltage of the upper H-bridge, U cd (t) is the output port voltage of the lower H-bridge, i o (t) is the load current, U f (t) is the filter inductance L f The voltage between the two ends. To characterize U ab (t) and U cd (t) and DC side voltage U dc1 (t) and U dc2 (t), the switch function S is introduced ab (t) and S cd (t) are:

[0049]

[0050] At this time U ab (t) = S ab (t)U dc1 (t);

[0051]

[0052] At this time U cd (t) = S cd (t)U dc2 (t);

[0053] The load current is discretized according to the first-order Euler discretization method:

[0054]

[0055] where i o (t k+1 ) is the load current value to be predicted, i o (t k ) is the current system sampled load current value, T Sis the sampling period of the control system. Substituting this formula into the KVL equation, we can get:

[0056]

[0057] Right now:

[0058]

[0059] Simplifying the above formula, the load current prediction model is:

[0060]

[0061] The current model is updated in real time as the load impedance changes, which can effectively eliminate the impact of model mismatch on the stability of the control system.

[0062] In this topology, the energy in the two DC side capacitors C1 and C2 of the cascaded five-level H-bridge inverter is provided by two independent charging piles in the previous stage, and the dynamic response speed of the charging piles is low. s It is impossible to quickly charge and discharge the DC side capacitors C1 and C2. At the same time, due to the unknown nonlinear factors in the system model and the slight difference in the values ​​of the two capacitors C1 and C2, the DC side voltage U dc1 and U dc2 It can be considered to be in fluctuation all the time.

[0063] When T s When the time is small, the DC side voltage can be approximately considered to be determined by the switching function and the filter inductor current at this time. The setting value of the DC side capacitor voltage is U DC Therefore, in the control process, it is necessary to dynamically select the appropriate switch state so that the DC side voltage is always within U DC Fluctuates within a small range nearby.

[0064] At the output, according to the KCL equation, the filter inductor current i Lf for:

[0065]

[0066] For capacitor C1:

[0067]

[0068] will i Lf Substituting (t) into the above formula, we get:

[0069]

[0070] When the time scale is small enough, the load voltage remains almost unchanged, that is:

[0071]

[0072] Then the above formula becomes:

[0073]

[0074] The voltage across capacitor C1 is discretized according to the first-order Euler discretization method:

[0075]

[0076] Substituting this formula into the equation:

[0077]

[0078] Simplifying it, the voltage prediction model across the DC side capacitor C1 is:

[0079]

[0080] Similarly, for capacitor C2, the voltage prediction model across capacitor C2 is obtained as follows:

[0081]

[0082] Different value functions can be selected for different control systems and different control objectives. Since the control objectives of this control system are high-precision control of load current and voltage regulation control of DC side capacitor voltage, the value function is constructed as follows:

[0083]

[0084] in Set the value for the load current; is the load current prediction value; λ1 is the weight factor of the DC side C1 capacitor voltage control; λ2 is the weight factor of the DC side C2 capacitor voltage control; U DC Set the voltage value for the DC side capacitor; is the predicted value of the capacitor voltage of C1 on the DC side; is the predicted value of the DC side C2 capacitor voltage.

[0085] The selection of the above λ1 and λ2 complies with the following principles: when the difference between the DC side capacitor voltage and the set value is less than or equal to 5%, λ is taken as 0.1; when the difference between the DC side capacitor voltage and the set value is greater than 5% and less than or equal to 10%, λ is taken as 0.2; when the difference between the DC side capacitor voltage and the set value is greater than 10% and less than or equal to 20%, λ is taken as 0.3; when the difference between the DC side capacitor voltage and the set value is greater than 20%, λ is taken as 0.4; as the control continues, λ in the value function is dynamically updated.

[0086] Since the actual control system has a delay when executing the program algorithm, according to tk The data collected at each moment cannot be directly applied to the current moment after rolling optimization, so a two-step predictive control method is used to compensate for the delay, that is, the predicted i(t k+1 ) and U dc1 (t k+1 ), U dc2 (t k+1 ) is then substituted into the prediction model and traversed using 16 different switch states. The combination of is substituted into the value function to find the optimal switching state corresponding to its minimum value, thereby improving the control performance of the control system, reducing the impact of delay, and ultimately achieving a high dynamic response speed of the load current and stability of the DC side capacitor voltage of the upper and lower modules.

[0087] Example 2

[0088] Embodiment 2 of the present invention provides a control system corresponding to the above-mentioned embodiment 1, including a memory, a processor and a computer program stored in the memory; the processor executes the computer program in the memory to implement the steps of the method of the above-mentioned embodiment 1.

[0089] In some implementations, the memory may be a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk memory.

[0090] In some other implementations, the processor may be a central processing unit (CPU), a digital signal processor (DSP), or other general-purpose processors of various types, which are not limited herein.

[0091] Example 3

[0092] Embodiment 3 of the present invention provides a computer-readable storage medium corresponding to the above embodiment 1, on which a computer program / instruction is stored. When the computer program / instruction is executed by a processor, the steps of the method of the above embodiment 1 are implemented.

[0093] Computer readable storage media can be tangible devices that hold and store instructions used by instruction execution devices. Computer readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any combination thereof.

[0094] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. The scheme in the embodiments of the present application can be implemented in various computer languages, for example, object-oriented programming language Java and literal scripting language JavaScript, etc.

[0095] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0096] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0097] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0098] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A digital power amplifier collaborative control method for multi-transmitting array element driving, the digital power amplifier comprises an upper H-bridge and a lower H-bridge; the upper H-bridge and the lower H-bridge are connected; the upper H-bridge is connected to a filter inductor, the lower H-bridge is connected to a filter capacitor, the filter inductor is connected to the filter capacitor; the filter capacitor is connected to a transducer; characterized in that: The following steps are involved: Construct the following value function J: in, is the load current setting value, is the load current prediction value, λ1 is the weight factor of the voltage control of the upper H-bridge DC side capacitor C1, λ2 is the weight factor of the voltage control of the lower H-bridge DC side capacitor C2, U DC Set the voltage value for the DC side capacitor, is the predicted value of the voltage of the DC link capacitor C1, is the predicted value of the voltage of the DC side capacitor C2; The predicted values ​​corresponding to different switch states Substitute the value function J into the switch state that minimizes the value of the value function J and take it as the optimal switch state.

2. The digital power amplifier cooperative control method for multi-transmitting array element driving according to claim 1, characterized in that: t k+1 Predicted value of the DC link capacitor C1 voltage at time The calculation formula is: Among them, T S is the control system sampling period, i o (t k ) is the current system sampling t k Load current value at the moment, T1, T2, T3, T4 are the upper H-bridge switch power devices.

3. The digital power amplifier cooperative control method for multi-transmitting array element driving according to claim 1, characterized in that: t k+1 Predicted value of the DC link capacitor C2 voltage at time The calculation formula is: Among them, T S is the control system sampling period, T5, T6, T7, and T8 are the lower H-bridge switch power devices. o (t k ) is the current system sampling t k Load current value at the moment.

4. The digital power amplifier cooperative control method for multi-transmitting array element driving according to claim 2 or 3, characterized in that: t k+1 The predicted value of load current at time i o (t k+1 ) is calculated as: Where, L is the equivalent inductance of the transducer, R is the real part of the transducer impedance, and U is f (t k ) is the voltage across the filter inductor at t k The sampling value at the time.

5. The digital power amplifier cooperative control method for multi-transmitting array element driving according to claim 4, characterized in that: Where, P is the active power of the transducer, I max is the peak value of the load current.

6. The digital power amplifier cooperative control method for multi-transmitting array element driving according to claim 4, characterized in that: Among them, U max is the load voltage peak value, and f is the load voltage frequency.

7. The digital power amplifier cooperative control method for multi-transmitting array element driving according to claim 1, characterized in that: The selection process of λ1 and λ2 includes: when the difference between the DC side capacitor voltage and the set value is less than or equal to 5%, λ1 and λ2 are 0.1; when the difference between the DC side capacitor voltage and the set value is greater than 5% and less than or equal to 10%, λ1 and λ2 are 0.2; when the difference between the DC side capacitor voltage and the set value is greater than 10% and less than or equal to 20%, λ1 and λ2 are 0.3; when the difference between the DC side capacitor voltage and the set value is greater than 20%, λ1 and λ2 are 0.

4.

8. A digital power amplifier cooperative control system for driving multiple transmitting array elements, comprising a memory, a processor, and a computer program stored in the memory; characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 7.

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