Automatic trimming oscillator

Abstract

An automatic trimming oscillator relates to the technical field of integrated circuits and comprises an oscillation generator integrated on the same chip and used for generating output pulses; the trimming voltage generation circuit is used for generating trimming current related to a chip process corner and sampling the trimming current into trimming voltage through a sampling resistor; the trimming signal generation unit is used for generating a trimming signal according to the trimming voltage; and the bias current generation circuit comprises N bias current branches which are connected in parallel, each bias current branch is provided with a control switch, and each control switch is used for closing or conducting the corresponding bias current branch according to the received trimming signal and carrying out frequency trimming on the output pulse. According to the invention, the oscillator can be automatically trimmed after the circuit is electrified, a reference clock is not needed, and automatic trimming can be realized regardless of any chip process corner or any temperature.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an automatic trimming oscillator. Background Art

[0002] As a precision analog circuit, the design and implementation of the automatic trimming oscillator aims to solve the limitations of traditional oscillators in terms of frequency stability, environmental adaptability, reliability, etc.

[0003] Specifically, the automatic trimmed oscillator achieves the following goals through a series of sophisticated control and feedback mechanisms:

[0004] Improve frequency stability:

[0005] The automatic trimming oscillator monitors and adjusts the oscillator's output frequency in real time through the built-in frequency control circuit. This mechanism can significantly reduce the frequency drift caused by temperature changes, voltage fluctuations, and other factors, thereby ensuring that the oscillator can provide stable frequency output under various operating conditions.

[0006] Improved reliability:

[0007] In the manufacturing process of traditional oscillators, due to some process deviations, the frequency of the oscillators actually produced often deviates from the expected frequency, so traditional oscillators usually need to be adjusted. If the production scale is large, a lot of time will be wasted on the adjustment. The automatic trimmer can automatically adjust according to different process deviations.

[0008] In the patent Auto trimming device for oscillator and method of auto trimming device for oscillator (Patent NO: US11233517B2), the inventor processes the difference between the target oscillator and the desired oscillator frequency to obtain the desired trimming value. In the patent Oscillator auto-trimming method and semiconductor device using the method (Patent NO: US8810321B2), the inventor also uses a similar method to the above and adds a reference clock.

[0009] The above automatic adjustment methods all require the assistance of a reference clock. Although they can also reduce the workload of manual adjustment, for an independent oscillator chip or an oscillator embedded in other chips, a PAD is required to access the reference clock signal, so it is not a true automatic adjustment. Summary of the invention

[0010] The purpose of the present invention is to propose a new automatic trimming oscillator circuit structure, which can automatically complete the trimming of the oscillator after the circuit is powered on, does not require a reference clock, and can achieve automatic trimming regardless of any chip process angle or any temperature.

[0011] In order to achieve the above objectives, the technical solution adopted by the present invention is: an automatic trimming oscillator, comprising:

[0012] an oscillator generator for generating output pulses;

[0013] A trimming voltage generating circuit is used to generate a trimming current related to the chip process angle, and to sample the trimming current through a sampling resistor to obtain a trimming voltage;

[0014] A trimming signal generating unit, used for generating a trimming signal according to the trimming voltage, wherein the trimming signal is an N-bit binary digital signal, where N is a positive integer;

[0015] The bias current generating circuit comprises N bias current branches connected in parallel, each of the bias current branches is provided with a control switch, the control ends of the N control switches are connected to the N-bit binary digital signals one by one, and each control switch is used to close or turn on the corresponding bias current branch according to the received adjustment signal, so as to adjust the frequency of the output pulse.

[0016] Furthermore, the specific structure of the trimming voltage generating circuit is as follows: the drain of the first NMOS tube is connected to the power supply VDD, the gate is connected to the first bias voltage, the source is grounded through a sampling resistor, and the voltage on the sampling resistor is used as the trimming voltage.

[0017] Furthermore, the trimming signal generating unit includes an analog-to-digital converter and a decoder, wherein the analog signal input terminal of the analog-to-digital converter is connected to the trimming voltage, the digital signal output terminal of the analog-to-digital converter ADC is connected to the input terminal of the decoder, and the output terminal of the decoder outputs an N-bit binary digital signal as the trimming signal.

[0018] Furthermore, the analog-to-digital converter is a 4-bit converter, the decoder is a 4-line-16-line decoder, the adjustment signal is a 16-bit binary digital signal, and the bias current generating circuit includes 16 parallel bias current branches.

[0019] Furthermore, the specific structure of the bias current generating circuit is:

[0020] The second end of the control switch in each bias current branch is connected to a current source respectively, and the first end of each control switch is connected in parallel and then connected to the drain of the first PMOS tube, the drain of the first PMOS tube is connected to the gate, and the source of the first PMOS tube is connected to the drain of the second PMOS tube; the source of the second PMOS tube is connected to the power supply VDD, and the gate is connected to the fourth bias voltage;

[0021] The drain of the first PMOS tube is also connected to the bias input terminal of the oscillator generator.

[0022] Furthermore, the current source in each bias current branch is composed of two NMOS tubes, the second end of the control switch is connected to the drain of one NMOS tube, the source of the NMOS tube is connected to the drain of another NMOS tube, the source of the other NMOS tube is grounded, and the gates of the two NMOS tubes are respectively connected to the second bias voltage and the third bias voltage.

[0023] Furthermore, the control switch is an NMOS tube, whose drain serves as the first end of the control switch, the source serves as the second end of the control switch, and the gate serves as the control end of the control switch.

[0024] The beneficial effects of the present invention are:

[0025] Usually, the output of the oscillator is greatly affected by the process angle, and the chip needs to be manually adjusted after it is processed. Compared with the traditional adjustment or the patent mentioned above, the present invention can achieve automatic adjustment regardless of any chip process angle or any temperature. The traditional adjustment needs to give different adjustment schemes when facing different conditions, so the present invention saves a large part of the workload. Although the adjustment accuracy of the present invention is not as high as manual adjustment, it can meet the range of use requirements after adjustment. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of the circuit structure of an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] Figure 1 A specific embodiment of the present invention is an automatic trimming oscillator, comprising:

[0029] The oscillator generator OSC is used to generate output pulses; the oscillator generator adopts a common structure of the prior art;

[0030] The trimming voltage generating circuit is used to generate a trimming current related to the chip process angle, and its specific structure is as follows: the drain of the first NMOS tube MN1 is connected to the power supply VDD, the gate is connected to the first bias voltage VBIAS1, the source is grounded through the sampling resistor R, and the voltage on the sampling resistor R is used as the trimming voltage VI0;

[0031] The trimming signal generating unit is used to generate a trimming signal according to the trimming voltage VI0, and its specific structure is: the analog signal input terminal of the 4-bit analog-to-digital converter ADC is connected to the trimming voltage VI0, the digital signal output terminal of the 4-bit analog-to-digital converter ADC is connected to the input terminal of the 4-line-16-line decoder DC_4_16, and the output terminal of the 4-line-16-line decoder outputs 16-bit binary digital signals D0-D15 as the trimming signal;

[0032] The bias current generating circuit includes 16 bias current branches connected in parallel, each of the bias current branches is provided with a control switch, and the control switch is an NMOS tube. The control ends, i.e., the gates, of the 16 NMOS tubes are connected to the 16-bit binary digital signals D0-D15 in a one-to-one correspondence. Each control switch is used to close or conduct the corresponding bias current branch according to the received adjustment signal D0-D15, so as to adjust the frequency of the output pulse.

[0033] The specific structure of the bias current generating circuit in this embodiment is:

[0034] The source of the NMOS tube used as the control switch in each bias current branch is connected to a current source respectively, and the drain is connected in parallel and then connected to the drain of the first PMOS tube MP1. The drain of the first PMOS tube MP1 is connected to the gate, and its source is connected to the drain of the second PMOS tube MP2; the source of the second PMOS tube MP2 is connected to the power supply VDD, and the gate is connected to the fourth bias voltage VBIAS4;

[0035] The drain of the first PMOS tube MP1 is also connected to the bias input terminal of the oscillator generator OSC;

[0036] The current source in each bias current branch is composed of two NMOS tubes, the source of the NMOS tube serving as a control switch is connected to the drain of one of the NMOS tubes, the source of the NMOS tube is connected to the drain of another NMOS tube, the source of the other NMOS tube is grounded, and the gates of the two NMOS tubes of the current source in each current branch are respectively connected to the second bias voltage VBIAS2 and the third bias voltage VBIAS3.

[0037] like Figure 1 As shown, in this embodiment, a basic bias voltage generating unit VBIAS is also integrated in the same chip, which is used to generate the required first bias voltage VBIAS1, second bias voltage VBIAS2, third bias voltage VBIAS3 and fourth bias voltage VBIAS4. The basic bias voltage generating unit VBIAS also adopts the common structure of the prior art.

[0038] The working principle of this embodiment is:

[0039] like Figure 1As shown, after the power supply is powered on, an initial bias current IB and an adjustment current ID are obtained, wherein IB is the bias current of the oscillator generator OSC. By changing the bias current, the oscillator generator OSC can output clock signals of different frequencies.

[0040] The trimming current ID flows through the sampling resistor R to obtain a trimming voltage VI0. This trimming voltage VI0 is converted by a 4-bit analog-to-digital converter ADC to obtain a 4-bit digital signal, and then passes through a 4-line-16-line decoder to obtain a 16-bit binary digital signal D0~D15. The 16-bit digital signal is respectively connected to the gates of 16 NMOS tubes used as control switches to control their on and off, thereby closing or turning on the corresponding bias current branch to achieve the purpose of controlling the bias current of the oscillator generator OSC.

[0041] If the process corner of the processed chip is at TT, the trimmed current ID obtains VI0 of VREF / 2 through the sampling resistor R, then the output of the ADC is 1000, and the decoder outputs 0000 0000 1111 1111, then 8 NMOSs serving as control switches are turned on, that is, 8 bias current branches are turned on. At this time, the bias current of the oscillator generator OSC is IB. Assume that the frequency corresponding to IB is the desired frequency.

[0042] If the chip process angle is at FF, the bias current IB1 is greater than IB, and the output frequency of the oscillator generator OSC will also be higher than when the chip process angle is at TT. At this time, the trimming current ID1 is also affected by the chip process angle. If ID1 is greater than ID, the trimming current ID1 flowing through the sampling resistor R will get VI0 greater than VREF / 2. Assuming that the ADC outputs 1010 and the decoder outputs 00000000 0000 1111, only 4 NMOSs as control switches are turned on, that is, only 4 bias current branches are turned on, thereby reducing the current IB1 and the output frequency of the oscillator generator OSC.

[0043] If the chip process corner is at SS, the situation is opposite to that when the chip process corner is at FF, and the working process will not be described in detail here.

Claims

1. An automatic trimming oscillator, characterized in that: Includes integrated into the same chip: an oscillator generator (OSC) for generating output pulses; A trimming voltage generating circuit is used to generate a trimming current related to a chip process angle, and to sample the trimming current into a trimming voltage (VI0) through a sampling resistor (R); A trimming signal generating unit, used for generating a trimming signal according to the trimming voltage (VI0), wherein the trimming signal is an N-bit binary digital signal, where N is a positive integer; The bias current generating circuit comprises N bias current branches connected in parallel, each of the bias current branches is provided with a control switch, the control ends of the N control switches are connected to the N-bit binary digital signals one by one, and each control switch is used to close or turn on the corresponding bias current branch according to the received adjustment signal, so as to adjust the frequency of the output pulse.

2. The automatic trimming oscillator according to claim 1, characterized in that: The specific structure of the trimming voltage generating circuit is as follows: the drain of the first NMOS tube (MN1) is connected to the power supply VDD, the gate is connected to the first bias voltage (VBIAS1), the source is grounded through a sampling resistor (R), and the voltage on the sampling resistor (R) is used as the trimming voltage (VI0).

3. The automatic trimming oscillator according to claim 1, characterized in that: The trimming signal generating unit comprises an analog-to-digital converter (ADC) and a decoder, wherein an analog signal input terminal of the analog-to-digital converter (ADC) is connected to a trimming voltage (VI0), a digital signal output terminal of the analog-to-digital converter ADC is connected to an input terminal of the decoder, and an output terminal of the decoder outputs an N-bit binary digital signal as a trimming signal.

4. The automatic trimming oscillator according to claim 2, characterized in that: The analog-to-digital converter (ADC) is a 4-bit converter, the decoder is a 4-line-16-line decoder, the trimming signal is a 16-bit binary digital signal, and the bias current generating circuit includes 16 parallel bias current branches.

5. The automatic trimming oscillator according to claim 1, characterized in that: The specific structure of the bias current generating circuit is: The second end of the control switch in each bias current branch is respectively connected to a current source, and the first end of each control switch is connected in parallel and then connected to the drain of the first PMOS tube (MP1), the drain of the first PMOS tube (MP1) is connected to the gate, and its source is connected to the drain of the second PMOS tube (MP2); the source of the second PMOS tube (MP2) is connected to the power supply VDD, and the gate is connected to the fourth bias voltage (VBIAS4); The drain of the first PMOS transistor (MP1) is also connected to the bias input terminal of the oscillator generator (OSC).

6. The automatic trimming oscillator according to claim 5, characterized in that: The current source in each bias current branch is composed of two NMOS tubes, the second end of the control switch is connected to the drain of one NMOS tube, the source of the NMOS tube is connected to the drain of another NMOS tube, the source of the other NMOS tube is grounded, and the gates of the two NMOS tubes are respectively connected to the second bias voltage (VBIAS2) and the third bias voltage (VBIAS3).

7. The automatic trimming oscillator according to claim 5, characterized in that: The control switch is an NMOS tube, whose drain serves as the first end of the control switch, the source serves as the second end of the control switch, and the gate serves as the control end of the control switch.

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