ESD protection circuit and method, and electronic device

Abstract

The present invention provides an ESD protection circuit, method, and electronic device. The ESD protection circuit includes a discharge circuit and a control circuit. When an ESD event occurs, the control circuit connects the other end of a first capacitor to the gate of a discharge transistor, so that the discharge circuit has a GCNMOS structure, which has the advantage of fast response speed. During normal operation, the control circuit disconnects the other end of the first capacitor from the gate of the discharge transistor, so that the discharge circuit has a GGNMOS structure, which has the advantage of resisting high-power signal interference. Therefore, under the action of the control circuit, the ESD protection circuit can switch between the two structures, combining the advantages of both structures while eliminating their respective disadvantages. Not only can it quickly respond to ESD events and protect voltage ports, it also enhances the entire circuit's anti-interference capability against high-power signals, effectively preventing leakage current.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to an ESD protection circuit and method, and an electronic device. Background Art

[0002] Static electricity is the accumulation of static charges on the surface of objects. The transfer of static charge between objects is called electrostatic discharge (ESD). The ESD process is characterized by high voltage, low charge, and a short duration. Because semiconductor devices have limited voltage tolerance, they require electrostatic discharge (ESD) devices to protect external ports.

[0003] RF products have external ports that are divided into RF ports and DC ports. RF ports are responsible for the input and output of high-power signals, while DC ports serve as power supply ports and status control ports. The power supply port connects to the power supply, while the status control port controls the operating state of the switch based on various status signals. Different types of ports utilize different ESD protection methods. For example, stacking multiple MOS transistors between the RF port and the chip ground port can effectively protect the RF port. Typical ESD protection devices for DC ports are GGNMOS or GCNMOS.

[0004] See also Figure 1 In the GGNMOS protection method, the discharge transistor NM1 is an NMOS device. Taking the power supply port as an example, when an ESD event occurs at the VDD port, the VDD port voltage rises rapidly, and the parasitic transistor in the discharge transistor NM1 substrate will turn on, quickly discharging the electrostatic charge of the VDD port, thereby protecting the VDD port. When the product is operating normally, the gate and source of the discharge transistor NM1 are zero, and the discharge transistor NM1 remains off, without affecting the normal operation of the product. The advantage of the GGNMOS device is its simple structure, but its disadvantage is the high ESD protection turn-on voltage, which limits the use of GGNMOS in advanced processes.

[0005] See also Figure 2 In the GCNMOS protection method, the discharge transistor NM1 is an NMOS device, and its gate is connected to the first capacitor C1 and the first resistor R1 respectively. Continuing with the power supply port as an example, when an ESD event occurs at the DC port, the VDD port voltage rises rapidly. Taking advantage of the fact that the voltage across the first capacitor C1 cannot change suddenly, the voltage at point A on the gate of the discharge transistor NM1 rises rapidly, turning on the discharge transistor NM1. By turning on the NMOS channel, the electrostatic charge can be quickly discharged, thereby protecting the DC port.

[0006] The advantage of GCNMOS devices is that the ESD protection turn-on voltage is low. When the product is working normally, the first resistor R1 discharges the gate charge of the discharge transistor NM1, keeping the gate voltage at zero, and the discharge transistor NM1 remains closed, which does not affect the normal operation of the product. However, when the product is working in a high-power scenario, the ground terminal or the VDD terminal is interfered with by a large signal power. Since the gate potential cannot quickly follow the interference signal, the discharge transistor NM1 will be turned on periodically, resulting in a large leakage current, which increases the power consumption of the product in a high-power state. This limits the use of GCNMOS in small-size, high-power RF switches. In addition, as the size of RF switches becomes smaller and smaller, the isolation between the RF port and the DC port becomes worse and worse, and the high-power signal flowing through the RF port will leak to the DC port. GCNMOS is usually selected as the ESD protection device for the DC port of advanced process products, but under the influence of a large RF signal, the GCNMOS will be briefly turned on, resulting in a large leakage current.

[0007] Therefore, a new ESD protection circuit is urgently needed to solve the above technical problems. Summary of the Invention

[0008] The object of the present invention is to provide an ESD protection circuit and method, and an electronic device to solve at least one of the problems of how to avoid the formation of leakage current under high-power signal interference and how to improve the response speed of the ESD protection circuit.

[0009] In order to solve the above technical problems, the present invention provides an ESD protection circuit, comprising: a discharge circuit and a control circuit;

[0010] The discharge circuit includes a discharge transistor, a first resistor and a first capacitor; the source and drain of the discharge transistor are respectively connected to the ground and the voltage port; the opposite ends of the first resistor are respectively connected to the ground and the gate of the discharge transistor; one end of the first capacitor is connected to the voltage port, and the other opposite end of the first capacitor is connected to the control circuit; and

[0011] The control circuit is used to connect the other end of the first capacitor to the gate of the discharge transistor when an ESD event occurs, so that the discharge transistor is turned on and discharges electrostatic charge; and during normal operation, disconnect the other end of the first capacitor from the gate of the discharge transistor to keep the discharge transistor turned off.

[0012] Optionally, in the ESD protection circuit, the discharge transistor includes an NMOS; and the control circuit includes a control transistor; and the control transistor is connected to the other end opposite to the first capacitor and the gate of the discharge transistor.

[0013] Optionally, in the ESD protection circuit, the control transistor includes a PMOS; and the source of the control transistor is connected to the other end opposite to the first capacitor, and the drain of the control transistor is connected to the gate of the discharge transistor; wherein,

[0014] When an ESD event occurs, the gate of the control transistor is connected to a low potential, and the control transistor is turned on; and when operating normally, the gate of the control transistor is connected to a high potential, and the control transistor remains turned off.

[0015] Optionally, in the ESD protection circuit, the control transistor includes a PMOS; and the source and gate of the control transistor are both connected to the other end opposite to the first capacitor and the gate of the discharge transistor, and the drain of the control transistor is grounded; wherein,

[0016] When an ESD event occurs, the control transistor is turned off; and during normal operation, the control transistor remains on.

[0017] Optionally, in the ESD protection circuit, the control transistor includes a PMOS; and the source of the control transistor is connected to the other end opposite to the first capacitor and the gate of the discharge transistor, and the drain of the control transistor is grounded; wherein,

[0018] When an ESD event occurs, the gate of the control transistor is connected to a high potential, and the control transistor is turned off; and when operating normally, the gate of the control transistor is connected to a low potential, and the control transistor remains turned on.

[0019] Optionally, in the ESD protection circuit, the control transistor includes an NMOS; the source of the control transistor is grounded, and the drain of the control transistor is connected to the other end opposite to the first capacitor and the gate of the discharge transistor; wherein,

[0020] When an ESD event occurs, the gate of the control transistor is connected to a low potential, and the control transistor is turned off; and when operating normally, the gate of the control transistor is connected to a high potential, and the control transistor remains turned on.

[0021] Optionally, in the ESD protection circuit, the control transistor includes an NMOS; and the drain of the control transistor is connected to the other end opposite to the first capacitor, and the source of the control transistor is connected to the gate of the discharge transistor; wherein,

[0022] When an ESD event occurs, the gate of the control transistor is connected to a high potential, and the control transistor is turned on; and when operating normally, the gate of the control transistor is connected to a low potential, and the control transistor remains turned off.

[0023] Optionally, in the ESD protection circuit, the control circuit also includes a second capacitor and a second resistor; one end of the second capacitor is connected to the voltage port, and the other end of the second capacitor is connected to the gate of the control transistor and one end of the second resistor; and the other end of the second resistor is grounded.

[0024] Based on the same concept, the present invention also provides an ESD protection method, using the ESD protection circuit, and the ESD protection method includes:

[0025] When an ESD event occurs, the control circuit connects the other end of the first capacitor to the gate of the discharge transistor to turn on the discharge transistor and discharge the electrostatic charge; and

[0026] During normal operation, the control circuit disconnects the other end of the first capacitor from the gate of the discharge transistor, so that the discharge transistor remains turned off.

[0027] Based on the same concept, the present invention also provides an electronic device including the above-mentioned ESD protection circuit.

[0028] In summary, the present invention provides an ESD protection circuit and method, and an electronic device. Compared to the prior art, the ESD protection circuit includes a discharge circuit and a control circuit, and when an ESD event occurs, the control circuit connects the other end of the first capacitor to the gate of the discharge transistor so that the discharge circuit has a GCNMOS structure, which has the advantage of fast response speed; and when working normally, the control circuit disconnects the other end of the first capacitor from the gate of the discharge transistor so that the discharge circuit has a GGNMOS structure, which has the advantage of resisting high-power signal interference. Therefore, under the action of the control circuit, the ESD protection circuit can realize the switching of the two structures, and has the advantages of both structures while abandoning their respective shortcomings. Not only can it respond quickly to ESD events and protect voltage ports, but it also enhances the anti-interference ability of the entire circuit to high-power signals and effectively avoids leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0030] Figure 1 It is a schematic diagram of the GGNMOS structure in the prior art.

[0031] Figure 2 Schematic diagram of the GCNMOS structure in the prior art.

[0032] Figure 3 This is an ESD protection circuit diagram corresponding to the first example in the embodiment of the present invention.

[0033] Figure 4 4 is an ESD protection circuit diagram corresponding to the second example in the embodiment of the present invention.

[0034] Figure 5 4 is an ESD protection circuit diagram corresponding to the third example in the embodiment of the present invention.

[0035] Figure 6 4 is an ESD protection circuit diagram corresponding to the fourth example in the embodiment of the present invention.

[0036] Figure 7 4 is an ESD protection circuit diagram corresponding to the fifth example in the embodiment of the present invention.

[0037] Figure 8 4 is an ESD protection circuit diagram corresponding to the sixth example in the embodiment of the present invention.

[0038] Figure 9 This is a comparison diagram of the leakage current of the ESD protection circuit in the embodiment of the present invention and the GCNMOS structure in the prior art under high-power signal interference.

[0039] And, in the accompanying drawings:

[0040] PM1 - first switch tube; NM1 - discharge transistor; NM2 - second switch tube; C1 - first capacitor; C2 - second capacitor; R1 - first resistor; R2 - second resistor; VDD - voltage port. DETAILED DESCRIPTION

[0041] In order to make the objects, advantages and features of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis required to be shown in each drawing is different, and sometimes different scales are used. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third" and the like in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0042] See also Figure 3This embodiment provides an ESD protection circuit, including: a discharge circuit and a control circuit; the discharge circuit includes a discharge transistor NM1, a first resistor R1, and a first capacitor C1; the source and drain of the discharge transistor are respectively connected to the ground and the voltage port VDD; the opposite ends of the first resistor R1 are respectively connected to the ground and the gate of the discharge transistor NM1; one end of the first capacitor C1 is connected to the voltage port VDD, and the other opposite end of the first capacitor C1 is connected to the control circuit; and the control circuit is configured to connect the other opposite end of the first capacitor C1 to the gate of the discharge transistor NM1 when an ESD event occurs, so that the discharge transistor NM1 is turned on and discharges electrostatic charge; and during normal operation, disconnect the other opposite end of the first capacitor C1 from the gate of the discharge transistor NM1 to keep the discharge transistor NM1 off.

[0043] Based on this, when an ESD event occurs, the bleeder circuit adopts a GCNMOS structure, offering a fast response speed; while during normal operation, the bleeder circuit adopts a GGNMOS structure, offering superior resistance to high-power signal interference. Therefore, under the control of the control circuit, the ESD protection circuit can switch between these two structures, combining the advantages of both while eliminating their respective disadvantages. This not only enables a rapid response to ESD events and protects the voltage port VDD, but also enhances the overall circuit's resistance to high-power signal interference, effectively preventing leakage current.

[0044] The following is combined with Figures 3 to 9 , specifically describe the ESD protection circuit provided in this embodiment.

[0045] Please continue reading Figure 3 The ESD protection circuit provided in this embodiment includes a discharge circuit and a control circuit. The discharge circuit is used to discharge electrostatic charge when an ESD event occurs. The control circuit is used to switch the discharge circuit between a GCNMOS structure and a GGNMOS structure to ensure that the discharge circuit has the advantages of fast response speed and immunity to high-power signal interference.

[0046] Specifically, the discharge circuit includes a discharge transistor NM1, a first resistor R1, and a first capacitor C1. The discharge transistor NM1 is an NMOS transistor, and its source is grounded, its drain is connected to a voltage port VDD, and its gate is connected to one end of the first resistor R1; the other end of the first resistor R1 is grounded; one end of the first capacitor C1 is connected to the voltage port VDD, and the other end of the first capacitor C1 is connected to the control circuit, so that it is controlled by the control circuit to achieve switching between a GCNMOS structure and a GGNMOS structure. Furthermore, the control circuit includes a control transistor, and the control transistor is connected to the other end of the first capacitor C1 and the gate of the discharge transistor NM1. The control transistor can be either a PMOS or an NMOS.

[0047] In the first example, if Figure 3 As shown, the control transistor is a PMOS transistor and, in this embodiment, is named the first switch transistor PM1. The source of the first switch transistor PM1 is connected to one end of the first capacitor C1. That is, the opposite ends of the capacitor C1 are connected to the voltage port VDD and the source of the first switch transistor PM1, respectively. The drain of the first switch transistor PM1 is connected to the gate of the bleeder transistor NM1 and the non-grounded end of the first resistor R1. Furthermore, the gate of the first switch transistor PM1 provides signals to other circuits within the electronic device, such as circuit operation enable signals or product control signals. To ensure that the bleeder circuit has a GCNMOS structure when an ESD event occurs and a GGNMOS structure during normal operation, the first switch transistor PM1 needs to be turned on when an ESD event occurs and turned off during normal operation.

[0048] Based on this, when an ESD event occurs, i.e., an ESD pulse arrives, the potential of the voltage port VDD rises. The gate of the first switching transistor PM1 is connected to a low potential, turning on the first switching transistor PM1. The first capacitor C1 is connected to the discharge circuit, forming a GCNMOS structure. Because the potential across the capacitor has a delayed characteristic and cannot change suddenly, the end of the first capacitor C1 connected to the gate of the discharge transistor NM1 via the first switching transistor PM1 will rise as the potential of the voltage port VDD rises. In other words, the potential at point A at the gate of the discharge transistor NM1 will rise and reach the turn-on voltage of the discharge transistor NM1. The discharge transistor NM1 will then turn on when the ESD event occurs, rapidly discharging the electrostatic charge.

[0049] During normal operation, the potential of the voltage port VDD remains at a normal voltage and does not rise. Furthermore, a high potential is connected to point B at the gate of the first switch PM1, turning it off. The bleeder circuit utilizes a GGNMOS structure, and the first capacitor C1 is disconnected from the bleeder circuit. When a high-power signal interferes, the potential of the voltage port VDD also rises, but this rises significantly less than the voltage of the voltage port VDD during an ESD event. Furthermore, high-power signal interference is extremely short-lived and has minimal energy. Therefore, due to the high turn-on voltage of the GGNMOS structure, both the first switch PM1 and the bleeder transistor NM1 remain off, effectively resisting high-power signals and preventing leakage current.

[0050] See also Figure 4 , in the second example, the continuation Figure 3 The control circuit shown in the figure still only includes the first switch tube PM1. However, the connection mode of the first switch tube PM1 is different from the Figure 3 and Figure 4 The connection method in the circuit shown is different. Specifically, the source and gate of the first switch transistor PM1 are connected to the other end of the first capacitor C1 and the gate of the discharge transistor NM1, while the drain of the first switch transistor PM1 is grounded. Therefore, when an ESD event occurs, the potential of the voltage port VDD rises. Because the voltage across the first capacitor C1 cannot change suddenly, the potential at point A, where the first capacitor C1 connects with the source and gate of the first switch transistor PM1 and the gate of the discharge transistor NM1, rises as the potential of the voltage port VDD rises. In other words, the potential of the gate of the first switch transistor PM1 quickly responds to a high potential, causing the first switch transistor PM1 to turn off. At this point, the discharge circuit has a GCNMOS structure. Because the potential at point A rises and causes the discharge transistor NM1 to turn on, the discharge transistor NM1 quickly discharges the electrostatic charge. During normal operation, the potential of the voltage port VDD remains at a normal voltage and does not rise. The first resistor R1 pulls down the potential at point A, causing the gate of the first switch PM1 to reach a low potential, turning on the first switch PM1. Simultaneously, the bleeder transistor NM1 remains off. Furthermore, based on the principle of current flow priority, current preferentially flows along paths with lower resistance, so the bleeder circuit adopts a GGNMOS structure. Similarly, when a high-power signal arrives, due to the relatively high turn-on voltage of the GGNMOS structure, the rising potential of the voltage port VDD cannot drive the potential at point A to turn on the bleeder transistor NM1. Simultaneously, the first switch PM1 remains on, effectively resisting interference from high-power signals and preventing leakage current.

[0051] In the third example, Figure 5 As shown, in Figure 4 Based on the circuit structure shown in FIG, the control circuit also only includes the first switch tube PM1. The connection mode of the source and drain of the first switch tube PM1 is the same as that of FIG. Figure 4 The connection method of the first switch tube PM1 shown is the same, but its gate is not connected to the other end of the first capacitor C1 opposite to the gate of the discharge transistor NM1. Instead, it is directly provided with signals from other circuits within the electronic device, such as: circuit operation enable signal or product control signal. When an ESD event occurs, the gate of the first switch tube PM1 is connected to a high potential, and the first switch tube PM1 is turned off; when normal operation or a high-power signal arrives, the gate of the first switch tube PM1 is connected to a low potential, and the first switch tube PM1 remains on. Among them, Figure 5 The specific operation process of the circuit shown can refer to the above Figure 4 The operation process of the embodiment will not be described in detail here.

[0052] See also Figure 6 ,exist Figure 5 Based on the circuit structure shown, the control transistor can be replaced with an NMOS transistor, which in this embodiment is named the second switch transistor NM2. Because the characteristics of NMOS and PMOS are essentially opposite, to achieve switching between a GCNMOS structure and a GGNMOS structure, when an ESD event occurs, the gate of the second switch transistor NM2 needs to be connected to a low potential to turn off the second switch transistor NM2, and the bleeder circuit adopts a GCNMOS structure. During normal operation, the gate of the second switch transistor NM2 needs to be connected to a high potential to turn on the second switch transistor NM2, and the bleeder circuit adopts a GGNMOS structure.

[0053] Therefore, if Figure 6As shown, in the fourth example, the control circuit includes only the second switch NM2. The drain of the second switch NM2 is connected to the gate of the discharge transistor NM1 and the other end of the first capacitor C1. The source of the second switch NM2 is grounded. The gate of the second switch NM2 can be directly connected to other circuits within the electronic device, such as circuit operation enable signals or product control signals. When an ESD event occurs, the potential of the voltage port VDD rises. The gate of the second switch NM2 is connected to a low potential, turning off the second switch NM2. In this case, the discharge circuit has a GCNMOS structure. Because the voltage across the capacitor cannot change suddenly, the potential at point A at one end of the first capacitor C1 rises with the rise of the voltage port VDD, turning on the discharge transistor NM1 to quickly discharge the electrostatic charge. During normal operation, the potential of the voltage port VDD remains normal and does not rise. The gate of the second switch NM2 is connected to a high potential, turning on the second switch NM2. At the same time, under the action of the first resistor R1, the potential at point A on the gate of the discharge transistor NM1 is low, and the discharge transistor NM1 remains off. In this case, the discharge circuit has a GGNMOS structure. Because the GGNMOS structure has a high turn-on voltage, it can keep the discharge transistor NM1 off even when subjected to interference from high-power signals, effectively resisting interference from high-power signals and preventing leakage current.

[0054] It should be noted that if Figure 4 、 Figure 5 and Figure 6 As shown, based on the characteristics of the capacitor, when an ESD event occurs, the voltage of the voltage port VDD changes, which is equivalent to connecting the first capacitor C1 to the discharge circuit, and the discharge circuit has a GCNMOS structure; when working normally, the voltage of the voltage port VDD does not change, and the first capacitor C1 is equivalent to an open circuit. It can be considered that the first capacitor C1 is not connected to the discharge circuit, and the discharge circuit has a GGNMOS structure.

[0055] For further information, see Figure 7 and Figure 8 ,based on Figure 3 The circuit design idea can be Figure 3 The first switch tube PM1 in the corresponding circuit is replaced by the second switch tube NM2. Similarly, since the characteristics of NMOS and PMOS are basically opposite, the connection method of the second switch tube NM2 needs to be appropriately adjusted. Specifically, Figure 7As shown, in the fifth example, the control circuit includes a second switch NM2, a second capacitor C2, and a second resistor R2. The drain of the second switch NM2 is connected to the other end opposite the first capacitor C1, and the source of the second switch NM2 is connected to the gate of the discharge transistor and the non-grounded end of the first resistor R1. One end of the second capacitor C2 and one end of the second resistor R2 are connected to the gate of the second switch NM2, and the other end opposite the second capacitor C2 is connected to the voltage port VDD, while the other end opposite the second resistor R2 is grounded. Therefore, when an ESD event occurs, the potential of the voltage port VDD rises. Because the voltage across the capacitor cannot change suddenly, the potential at point B at one end of the second capacitor C2 rises rapidly, i.e., the gate potential of the second switch NM2 rises, causing the second switch NM2 to turn on. When the second switch NM2 turns on, the first capacitor C1 is connected to the discharge circuit, resulting in the discharge circuit adopting a GCNMOS structure. At the same time, the potential at point A at the gate of the discharge transistor NM1 also rises as the potential of the voltage port VDD rises, so that the discharge transistor NM1 is turned on and discharges the electrostatic charge quickly.

[0056] During normal operation, the potential of the voltage port VDD is at a normal voltage and does not increase. The second resistor R2 pulls down the potential at point B on one end of the second capacitor C2, effectively lowering the gate potential of the second switch NM2 to a low potential, turning off the second switch NM2. At this point, the first capacitor C1 is not connected to the bleeder circuit, and the bleeder circuit has a GGNMOS structure. Furthermore, the first resistor R1 causes the gate potential of the bleeder transistor NM1 to a low potential at point A, keeping the bleeder transistor NM1 off. Due to the high turn-on voltage of the GGNMOS structure, the bleeder transistor NM1 remains off even under interference from high-power signals, effectively preventing interference from high-power signals and preventing leakage current.

[0057] Similarly, in order to simplify the circuit structure, in the sixth example, as shown in FIG. Figure 8 As shown, the control circuit only includes the second switch NM2, and its connection method is the same as Figure 7The connection method for the second switch NM2 shown is similar. However, the gate of the second switch NM2 can be directly connected to other circuits within the electronic device, such as circuit enable signals or product control signals. This also allows the second switch NM2 to turn on when an ESD event occurs and remain closed during normal operation or when a high-power signal is received. Specifically, when an ESD event occurs, the potential of the voltage port VDD rises. The gate of the second switch NM2 is connected to a high potential, turning on the second switch NM2. The first capacitor C1 is connected to the discharge circuit, forming a GCNMOS structure. Because the potential across the capacitor is delayed and cannot change suddenly, the end of the first capacitor C1 connected to the gate of the discharge transistor NM1 via the second switch NM2 will rise as the potential of the voltage port VDD rises. That is, the potential at point A on the gate of the discharge transistor NM1 will rise and reach the turn-on voltage of the discharge transistor NM1. The discharge transistor NM1 will then turn on when an ESD event occurs, rapidly discharging the electrostatic charge. During normal operation, the potential of the voltage port VDD remains at a normal voltage and does not rise. Furthermore, a low potential is connected to point B on the gate of the second switch NM2, turning the second switch NM2 off. The discharge circuit then adopts a GGNMOS structure, and the first capacitor C1 is not connected to the discharge circuit. Furthermore, due to the high turn-on voltage of the GGNMOS structure, when high-power signal interference occurs, both the second switch NM2 and the discharge transistor NM1 remain off, effectively resisting high-power signals and avoiding leakage current issues.

[0058] Furthermore, in order to verify the ability of the ESD protection circuit provided in this embodiment to resist high-power interference, the applicant conducted a simulation test. Figure 9 As shown, the red line is the leakage current generated by a common GCNMOS device as the interference power increases, and the blue line is the leakage current generated by the ESD protection circuit provided by this embodiment as the interference power increases. Obviously, the ESD protection circuit provided by this embodiment does not generate leakage current under conditions of large interference power.

[0059] It should be noted that this embodiment does not limit the specific models and parameter value ranges of the resistors, capacitors, and transistors in the ESD protection circuit. Furthermore, the high and low potentials referred to in this embodiment are relative values ​​and are not specifically limited in this embodiment. However, they must all satisfy the corresponding on / off drive functions during operation of the aforementioned circuit.

[0060] Based on the same concept, this embodiment also provides an ESD protection method. This ESD protection method utilizes the aforementioned ESD protection circuit and includes: upon an ESD event, the control circuit connects the other end of the first capacitor to the gate of the discharge transistor, thereby turning on the discharge transistor and discharging electrostatic charge; and, during normal operation, the control circuit disconnects the other end of the first capacitor from the gate of the discharge transistor, thereby keeping the discharge transistor off. The specific operation process of the ESD protection method can be referenced to the specific operation process of the corresponding circuits in the six examples above, and this embodiment will not be elaborated on here.

[0061] Based on the same concept, this embodiment further provides an electronic device. The electronic device includes the above-mentioned ESD protection circuit. Exemplarily, the electronic device is a radio frequency device.

[0062] In summary, this embodiment provides an ESD protection circuit, method, and electronic device. The ESD protection circuit includes a discharge circuit and a control circuit. When an ESD event occurs, the control circuit connects the other end of the first capacitor C1 to the gate of the discharge transistor NM1, giving the discharge circuit a GCNMOS structure, which offers the advantage of fast response speed. During normal operation, the control circuit disconnects the other end of the first capacitor C1 from the gate of the discharge transistor NM1, giving the discharge circuit a GGNMOS structure, which offers the advantage of resisting high-power signal interference. Therefore, under the control of the control circuit, the ESD protection circuit can switch between these two structures, combining the advantages of both while eliminating their respective disadvantages. This not only allows for a rapid response to ESD events and protects the voltage port VDD, but also enhances the entire circuit's ability to resist high-power signal interference, effectively preventing leakage current.

[0063] Furthermore, it should be recognized that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. Any person skilled in the art can utilize the above disclosed technical content to make many possible changes and modifications to the technical solution of the present invention, or modify it into equivalent embodiments with equivalent variations, without departing from the scope of the technical solution of the present invention. Therefore, any simple modifications, equivalent variations, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. An ESD protection circuit, characterized in that: include: Bleeder circuit and control circuit; The discharge circuit includes a discharge transistor, a first resistor and a first capacitor; the source and drain of the discharge transistor are respectively connected to the ground and the voltage port; the opposite ends of the first resistor are respectively connected to the ground and the gate of the discharge transistor; one end of the first capacitor is connected to the voltage port, and the other opposite end of the first capacitor is connected to the control circuit; and The control circuit is used to connect the other end of the first capacitor to the gate of the discharge transistor when an ESD event occurs, so that the discharge transistor is turned on and discharges electrostatic charge; During normal operation, the other end of the first capacitor is disconnected from the gate of the discharge transistor to keep the discharge transistor turned off; The discharge transistor includes an NMOS; and the control circuit includes a control transistor; and the control transistor is connected to the other end of the first capacitor and the gate of the discharge transistor; The control transistor includes a PMOS; the source of the control transistor is connected to the other end opposite to the first capacitor, and the drain of the control transistor is connected to the gate of the discharge transistor; wherein, When an ESD event occurs, the gate of the control transistor is connected to a low potential, and the control transistor is turned on; and when operating normally, the gate of the control transistor is connected to a high potential, and the control transistor remains turned off.

2. An ESD protection circuit, characterized in that: include: Bleeder circuit and control circuit; The discharge circuit includes a discharge transistor, a first resistor and a first capacitor; the source and drain of the discharge transistor are respectively connected to the ground and the voltage port; the opposite ends of the first resistor are respectively connected to the ground and the gate of the discharge transistor; one end of the first capacitor is connected to the voltage port, and the other opposite end of the first capacitor is connected to the control circuit; and The control circuit is used to connect the other end of the first capacitor to the gate of the discharge transistor when an ESD event occurs, so that the discharge transistor is turned on and discharges electrostatic charge; During normal operation, the other end of the first capacitor is disconnected from the gate of the discharge transistor to keep the discharge transistor turned off; The discharge transistor includes an NMOS; and the control circuit includes a control transistor; and the control transistor is connected to the other end of the first capacitor and the gate of the discharge transistor; The control transistor includes an NMOS; the drain of the control transistor is connected to the other end opposite to the first capacitor, and the source of the control transistor is connected to the gate of the discharge transistor; wherein, When an ESD event occurs, the gate of the control transistor is connected to a high potential, and the control transistor is turned on; and when operating normally, the gate of the control transistor is connected to a low potential, and the control transistor remains turned off.

3. The ESD protection circuit according to claim 2, wherein: The control circuit also includes a second capacitor and a second resistor; one end of the second capacitor is connected to the voltage port, and the other end of the second capacitor is connected to the gate of the control transistor and one end of the second resistor; and the other end of the second resistor is grounded.

4. An ESD protection method, characterized in that: The ESD protection circuit according to any one of claims 1 to 3 is used, and the ESD protection method comprises: When an ESD event occurs, the control circuit connects the other end of the first capacitor to the gate of the discharge transistor to turn on the discharge transistor and discharge the electrostatic charge; and During normal operation, the control circuit disconnects the other end of the first capacitor from the gate of the discharge transistor, so that the discharge transistor remains turned off.

5. An electronic device, characterized in that: The device comprises an ESD protection circuit as claimed in any one of claims 1 to 3.

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