Two-line three-input circuit

Abstract

The disclosure provides a kind of two-line ternary circuit.The two-line ternary circuit is used to carry out ternary operation, comprising: two-line input terminal, more than one in number, each two-line input terminal includes high line input end for inputting high line input signal and low line input end for inputting low line input signal, high line input signal and low line input signal are one of high level signal and low level signal respectively;And two-line output terminal, one in number and including high line output end for outputting high line output signal and low line output end for outputting low line output signal, high line output signal and low line output signal are one of high level signal and low level signal respectively, high line output end and low line output end are connected the output of two binary logic gates respectively;Or respectively connect the output of one binary logic gate, and one of high line input end and low line input end;Or respectively connect low line input end and high line input end.

Description

Technical Field

[0001] This disclosure relates to a two-wire ternary circuit. Background Technology

[0002] In ternary circuits, ternary operations are performed using three state signals, such as 0, 1, and 2. Current ternary circuits suffer from low noise margins (due to the need to consider three different voltage levels), slow TFET implementation speed, and limited readily available chip implementation options, making efficient computation impossible. Furthermore, the non-parallel nature of single-wire representations leads to low circuit symmetry, requiring the introduction of complement representation and addressing issues like misalignment. Additionally, current ternary circuits struggle to implement operations in special states (such as high-impedance states). For example, GPIO ports typically exist in high, low, and high-impedance states; existing ternary circuits cannot handle high-impedance operations, nor can binary circuits. Summary of the Invention

[0003] This disclosure provides a two-wire ternary circuit.

[0004] According to one aspect of this disclosure, a two-wire ternary circuit is provided for performing ternary operations, comprising: one or more two-wire input terminals, each two-wire input terminal including a high-line input terminal for inputting a high-line input signal and a low-line input terminal for inputting a low-line input signal, wherein the high-line input signal and the low-line input signal are respectively a high-level signal and a low-level signal; and one two-wire output terminal including a high-line output terminal for outputting a high-line output signal and a low-line output terminal for outputting a low-line output signal, wherein the high-line output signal and the low-line output signal are respectively a high-level signal and a low-level signal, wherein the high-line output terminal and the low-line output terminal are respectively connected to the outputs of two binary logic gates; or respectively connected to the output of a binary logic gate and one of the high-line input terminal and the low-line input terminal; or respectively connected to the low-line input terminal and the high-line input terminal.

[0005] A two-wire ternary circuit according to an embodiment of the present disclosure further includes: binary logic gates, wherein the number of binary logic gates is one or more, and at least a portion of the inputs of the binary logic gates are connected to at least one of the high-line inputs and the low-line inputs.

[0006] According to an embodiment of the present disclosure, the two-wire ternary circuit is an inverter circuit, wherein there is one two-wire input terminal and one two-wire output terminal, wherein the high-line input terminal and the low-line input terminal of the two-wire input terminal are interleaved and respectively connected to the low-line output terminal and the high-line output terminal of the two-wire output terminal.

[0007] According to an embodiment of the present disclosure, the two-wire ternary circuit is a NAND gate circuit. The binary logic gate includes a NAND gate, a NOR gate, a first inverter, and a second inverter. The number of two-wire input terminals is two. The high-line input terminal of the first two-wire input terminal is connected to one input of the NAND gate, and the low-line input terminal of the first two-wire input terminal is connected to one input of the NOR gate. The high-line input terminal of the second two-wire input terminal is connected to the other input of the NAND gate, and the low-line input terminal of the second two-wire input terminal is connected to the other input of the NOR gate. The outputs of the NAND gate and the NOR gate are respectively connected to the inputs of the first inverter and the second inverter. The outputs of the first inverter and the second inverter are interleaved to output a low-line output signal and a high-line output signal, respectively.

[0008] According to an embodiment of the present disclosure, a two-wire ternary circuit is an AND gate circuit. The binary logic gate includes a NAND gate, a NOR gate, a first inverter, and a second inverter. The number of two-wire input terminals is two. The high-line input terminal of the first two-wire input terminal is connected to one input of the NAND gate, and the low-line input terminal of the first two-wire input terminal is connected to one input of the NOR gate. The high-line input terminal of the second two-wire input terminal is connected to the other input of the NAND gate, and the low-line input terminal of the second two-wire input terminal is connected to the other input of the NOR gate. The outputs of the NAND gate and the NOR gate are respectively connected to the inputs of the first inverter and the second inverter. The outputs of the first inverter and the second inverter are not interleaved and output a high-line output signal and a low-line output signal, respectively.

[0009] According to an embodiment of the present disclosure, the two-wire ternary circuit is a NOR gate circuit. The binary logic gate includes a NOR gate, a NAND gate, a first inverter, and a second inverter. The number of two-wire input terminals is two. The high-line input terminal of the first two-wire input terminal is connected to one input of the NOR gate, and the low-line input terminal of the first two-wire input terminal is connected to one input of the NAND gate. The high-line input terminal of the second two-wire input terminal is connected to the other input of the NOR gate, and the low-line input terminal of the second two-wire input terminal is connected to the other input of the NAND gate. The outputs of the NOR gate and the NAND gate are respectively connected to the inputs of the first inverter and the second inverter. The outputs of the first inverter and the second inverter are interleaved to output a low-line output signal and a high-line output signal, respectively.

[0010] According to an embodiment of the present disclosure, a two-wire ternary circuit is an OR gate circuit. The binary logic gate includes a NOR gate, a NAND gate, a first inverter, and a second inverter. The number of two-wire input terminals is two. The high-line input terminal of the first two-wire input terminal is connected to one input of the NOR gate, and the low-line input terminal of the first two-wire input terminal is connected to one input of the NAND gate. The high-line input terminal of the second two-wire input terminal is connected to the other input of the NOR gate, and the low-line input terminal of the second two-wire input terminal is connected to the other input of the NAND gate. The outputs of the NOR gate and the NAND gate are respectively connected to the inputs of the first inverter and the second inverter. The outputs of the first inverter and the second inverter are not interleaved and output a high-line output signal and a low-line output signal, respectively.

[0011] According to an embodiment of the present disclosure, the two-wire ternary circuit is an incrementing gate circuit. The binary logic gate includes a NOR gate. The number of two-wire input terminals is one. The high-line input terminal of the two-wire input terminal is connected to one input of the NOR gate, and the low-line input terminal of the two-wire input terminal is connected to the other input of the NOR gate. The NOR gate outputs a high-line output signal, and the low-line output signal is the high-line input signal of the high-line input terminal.

[0012] According to an embodiment of the present disclosure, the two-wire ternary circuit is a decrementing gate circuit. The binary logic gate includes a NOR gate. The number of two-wire input terminals is one. The high-line input terminal of the two-wire input terminal is connected to one input of the NOR gate, and the low-line input terminal of the two-wire input terminal is connected to the other input of the NOR gate. The NOR gate outputs a low-line output signal, and the high-line output signal is the low-line input signal of the low-line input terminal.

[0013] According to an embodiment of the present disclosure, the two-wire ternary circuit is an inverter circuit. The binary logic gate includes a first inverter and a second inverter. The number of two-wire input terminals is one. The high-line input terminal and the low-line input terminal of the two-wire input terminal are respectively connected to the input of the first inverter and the input of the second inverter. The outputs of the first inverter and the second inverter are interleaved to output a low-line output signal and a high-line output signal, respectively.

[0014] According to an embodiment of the present disclosure, the two-wire ternary circuit is a NAND gate circuit. The binary logic gate includes a first NAND gate and a second NAND gate. The number of two-wire input terminals is two. The high-line input terminal of the first two-wire input terminal is connected to one input of the first NAND gate, and the high-line input terminal of the second two-wire input terminal is connected to the other input of the first NAND gate. The low-line input terminal of the first two-wire input terminal is connected to one input of the second NAND gate, and the low-line input terminal of the second two-wire input terminal is connected to the other input of the second NAND gate. The outputs of the first NAND gate and the second NAND gate are interleaved to output a low-line output signal and a high-line output signal, respectively.

[0015] According to an embodiment of the present disclosure, a two-wire ternary circuit is an AND gate circuit. The binary logic gate includes a first NAND gate, a second NAND gate, a first inverter, and a second inverter. The number of two-wire input terminals is two. The high-line input terminal of the first two-wire input terminal is connected to one input of the first NAND gate, and the high-line input terminal of the second two-wire input terminal is connected to the other input of the first NAND gate. The low-line input terminal of the first two-wire input terminal is connected to one input of the second NAND gate, and the low-line input terminal of the second two-wire input terminal is connected to the other input of the second NAND gate. The outputs of the first NAND gate and the second NAND gate are respectively connected to the inputs of the first inverter and the second inverter. The outputs of the first inverter and the second inverter are not interleaved, and output high-line output signals and low-line output signals respectively.

[0016] According to an embodiment of the present disclosure, the two-wire ternary circuit is a NOR gate circuit. The binary logic gate includes a first NOR gate and a second NOR gate. The number of two-wire input terminals is two. The high-line input terminal of the first two-wire input terminal is connected to one input of the first NOR gate, and the high-line input terminal of the second two-wire input terminal is connected to the other input of the first NOR gate. The low-line input terminal of the first two-wire input terminal is connected to one input of the second NOR gate, and the low-line input terminal of the second two-wire input terminal is connected to the other input of the second NOR gate. The outputs of the first NOR gate and the second NOR gate are interleaved to output a low-line output signal and a high-line output signal, respectively.

[0017] According to an embodiment of the present disclosure, a two-wire ternary circuit is an OR gate circuit. The binary logic gate includes a first NOR gate, a second NOR gate, a first inverter, and a second inverter. The number of two-wire input terminals is two. The high-line input terminal of the first two-wire input terminal is connected to one input of the first NOR gate, and the high-line input terminal of the second two-wire input terminal is connected to the other input of the first NOR gate. The low-line input terminal of the first two-wire input terminal is connected to one input of the second NOR gate, and the low-line input terminal of the second two-wire input terminal is connected to the other input of the second NOR gate. The outputs of the first NOR gate and the second NOR gate are respectively connected to the inputs of the first inverter and the second inverter. The outputs of the first inverter and the second inverter are not interleaved, and output high-line output signals and low-line output signals respectively.

[0018] According to an embodiment of the present disclosure, the two-wire ternary circuit is an auto-incrementing gate circuit. The binary logic gates include an inverter, a NOR gate, and a NAND gate. The number of two-wire input terminals is one. The high-line input terminal of the two-wire input terminal is connected to one input of the NOR gate and one input of the NAND gate. The low-line input terminal of the two-wire input terminal is connected to the input of the inverter and the other input of the NAND gate. The output of the inverter is connected to the other input of the NOR gate. The NOR gate and the NAND gate output a high-line output signal and a low-line output signal, respectively.

[0019] According to an embodiment of the present disclosure, a two-wire ternary circuit is a decrementing gate circuit. The binary logic gates include an inverter, a NOR gate, and a NAND gate. The number of two-wire input terminals is one. The high-line input terminal of the two-wire input terminal is connected to one input of the NOR gate and the input of the inverter. The output of the inverter is connected to one input of the NAND gate. The low-line input terminal of the two-wire input terminal is connected to the other input of the NOR gate and the other input of the NAND gate. The NOR gate and the NAND gate respectively output a high-line output signal and a low-line output signal.

[0020] The two-wire ternary circuit disclosed herein possesses excellent symmetry and can introduce special states, making it the first integrated circuit scheme to practically implement balanced ternary arithmetic. The transistors have a logic depth of 1 or 2, which does not reduce circuit speed. It exhibits high symmetry, eliminating the need for complement representation, etc. Attached Figure Description

[0021] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0022] Figure 1 This is a circuit diagram of an inverter according to an embodiment of the present disclosure.

[0023] Figure 2 This is a schematic diagram of an inverter according to an embodiment of the present disclosure.

[0024] Figure 3 This is a circuit diagram of a NAND gate according to an embodiment of the present disclosure.

[0025] Figure 4 This is a diagram illustrating a NAND gate according to an embodiment of the present disclosure.

[0026] Figure 5 It is a truth table of NAND gates according to an embodiment of the present disclosure.

[0027] Figure 6 This is a circuit diagram of an AND gate according to an embodiment of the present disclosure.

[0028] Figure 7 This is a diagram illustrating an AND gate according to an embodiment of the present disclosure.

[0029] Figure 8 It is a truth table of AND gates according to an embodiment of the present disclosure.

[0030] Figure 9 This is a circuit diagram of a NOR gate according to an embodiment of the present disclosure.

[0031] Figure 10 This is a diagram illustrating a NOR gate according to an embodiment of the present disclosure.

[0032] Figure 11 It is a truth table of NOR gates according to an embodiment of this disclosure.

[0033] Figure 12 This is a circuit diagram of an OR gate according to an embodiment of the present disclosure.

[0034] Figure 13 This is a diagram illustrating an OR gate according to an embodiment of the present disclosure.

[0035] Figure 14 It is a truth table of an OR gate according to an embodiment of the present disclosure.

[0036] Figure 15 This is a circuit diagram of an increment gate according to an embodiment of the present disclosure.

[0037] Figure 16 This is a diagram illustrating an auto-incrementing gate according to an embodiment of the present disclosure.

[0038] Figure 17 This is a circuit diagram of a self-decreasing gate according to an embodiment of the present disclosure.

[0039] Figure 18 This is a diagram illustrating a self-decreasing gate according to an embodiment of the present disclosure.

[0040] Figure 19 This is a circuit diagram of a decoder according to an embodiment of the present disclosure.

[0041] Figure 20 This is a diagram illustrating a decoder according to an embodiment of the present disclosure.

[0042] Figure 21 This is a schematic diagram of a converter according to an embodiment of the present disclosure.

[0043] Figure 22 This is a schematic diagram of a converter according to an embodiment of the present disclosure.

[0044] Figure 23 This is a circuit diagram of a NAND gate with three two-wire inputs according to an embodiment of the present disclosure.

[0045] Figure 24 This is a diagram illustrating a NAND gate with three two-wire inputs according to an embodiment of the present disclosure.

[0046] Figure 25 This is a circuit diagram of an inverter according to another embodiment of the present disclosure.

[0047] Figure 26 This is a diagram illustrating an inverter according to another embodiment of the present disclosure.

[0048] Figure 27 This is a circuit diagram of a NAND gate according to another embodiment of the present disclosure.

[0049] Figure 28 This is a diagram illustrating a NAND gate according to another embodiment of the present disclosure.

[0050] Figure 29 It is a truth table of NAND gates according to another embodiment of this disclosure.

[0051] Figure 30 This is a circuit diagram of an AND gate according to another embodiment of the present disclosure.

[0052] Figure 31 This is a diagram illustrating an AND gate according to another embodiment of the present disclosure.

[0053] Figure 32 It is a truth table of AND gates according to another embodiment of this disclosure.

[0054] Figure 33 This is a circuit diagram of a NOR gate according to another embodiment of the present disclosure.

[0055] Figure 34 This is a diagram illustrating a NOR gate according to another embodiment of the present disclosure.

[0056] Figure 35 It is a truth table of NOR gates according to another embodiment of this disclosure.

[0057] Figure 36 This is a circuit diagram of an OR gate according to another embodiment of the present disclosure.

[0058] Figure 37 This is a diagram illustrating an OR gate according to another embodiment of the present disclosure.

[0059] Figure 38 It is a truth table of an OR gate according to another embodiment of this disclosure.

[0060] Figure 39 This is a circuit diagram of an increment gate according to another embodiment of the present disclosure.

[0061] Figure 40 This is a diagram illustrating an auto-incrementing gate according to another embodiment of the present disclosure.

[0062] Figure 41 This is a circuit diagram of a self-decreasing gate according to another embodiment of the present disclosure.

[0063] Figure 42 This is a diagram illustrating a self-decreasing gate according to another embodiment of the present disclosure.

[0064] Figure 43 This is a diagram illustrating a converter according to another embodiment of the present disclosure.

[0065] Figure 44 This is a diagram illustrating a converter according to another embodiment of the present disclosure.

[0066] Figure 45 This is a circuit diagram of a NAND gate with three two-wire inputs according to another embodiment of the present disclosure.

[0067] Figure 46 This is a diagram illustrating a NAND gate with three two-wire inputs according to another embodiment of the present disclosure. Detailed Implementation

[0068] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0069] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0070] According to one embodiment of this disclosure, a two-wire ternary circuit is provided for performing ternary operations. In the ternary circuit of this disclosure, a two-wire input and a two-wire output are used, thereby enabling high-impedance operations. Furthermore, ternary operations can be implemented using binary logic gates.

[0071] The two-wire ternary circuit disclosed herein may include: two-wire input terminals and two-wire output terminals. The number of two-wire input terminals may be one or more, for example, one or two, or even three or more. Each two-wire input terminal includes a high-line input terminal for inputting a high-line input signal and a low-line input terminal for inputting a low-line input signal, wherein the high-line input signal and the low-line input signal are respectively a high-level signal and a low-level signal. The number of two-wire output terminals may be one and include a high-line output terminal for outputting a high-line output signal and a low-line output terminal for outputting a low-line output signal, wherein the high-line output signal and the low-line output signal are respectively a high-level signal and a low-level signal. The high-line output terminal and the low-line output terminal are respectively connected to the outputs of two binary logic gates; or respectively connected to the output of a binary logic gate and one of the high-line input terminal and the low-line input terminal; or respectively connected to the low-line input terminal or the high-line input terminal. Additionally, binary logic gates may be included. The number of binary logic gates may be one or more, and at least a portion of the inputs of the binary logic gates are connected to at least one of the high-line input terminals and the low-line input terminals.

[0072] The following will describe various implementation methods of ternary circuits under the design concept of this disclosure through various embodiments. As can be seen from the following embodiments, the logic depth of the transistor is 1 or 2, thereby ensuring the ternary operation speed and enabling the representation of special states, etc.

[0073] According to one embodiment of this disclosure, various binary two-wire ternary circuits are provided, wherein the embodiment may include... Figures 1 to 24The illustrated embodiment uses a binary representation to implement the ternary states. These states include a first state (+), a second state (-), a third state (0), and a special state. The special state can be a high-impedance state, an error state, or something similar. Each binary two-wire input signal includes two input signals, such as the high wire corresponding to the first input signal (high-wire input signal) and the low wire corresponding to the second input signal (low-wire input signal). The two input signals can be either a first voltage level and a second voltage level, where the first voltage level is high and the second voltage level is low, or vice versa. The ternary signal is represented as +, 0, and -. When the high line input signal of a binary two-wire input signal is at the first level and the levels of the high line input signal and the low line input signal are different, the ternary signal is +; when the low line input signal is at the first level and the levels of the high line input signal and the low line input signal are different, the ternary signal is -; when the low line input signal and the high line input signal are the same, the ternary signal is 0 (e.g., both the low line input signal and the high line input signal are 0). For special cases, the low line input signal and the high line input signal can be the same, and the ternary signal represents the special case (e.g., both the low line input signal and the high line input signal are 1). In the various embodiments below, the binary two-wire input signals A, B, and C are each input from a single two-wire input terminal.

[0074] Figure 1 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is an inverter. The inverter of this embodiment can be implemented without transistors; only the high and low lines need to be interleaved. Thus, the logic depth of the transistors in this embodiment is 0, and it has high symmetry. The inverter includes two input terminals, which are respectively connected to the high-line input signal AH and the low-line input signal AL of the binary two-wire input signal A. The high-line input signal AH and the low-line input signal AL can be either high-level signals or low-level signals. The binary two-wire output signal O of the inverter includes a high-line output signal OH and a low-line output signal OL. The high-line input signal AH and the low-line input signal AL are interleaved to form the low-line output signal OL and the high-line output signal OH, respectively.

[0075] When the ternary signal is + (10), the high-line input signal AH is 1 and the low-line input signal AL is 0, so the high-line output signal OH is 0 and the low-line output signal OL is 1. This inverter can output the ternary signal + as the ternary signal - (01). When the ternary signal is - (01), the high-line input signal AH is 0 and the low-line input signal AL is 1, so the high-line output signal OH is 1 and the low-line output signal OL is 0. This inverter can output the ternary signal - as the ternary signal + (10). When the ternary signal is 0 (00), the high-line input signal AH is 0 and the low-line input signal AL is 0, so the high-line output signal OH is 0 and the low-line output signal OL is 0. This inverter can output the ternary signal - as the ternary signal 0 (00). Figure 2 It shows Figure 1 The representation of an inverter.

[0076] Figure 3 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is a NAND gate circuit. The NAND gate circuit of this embodiment has a transistor logic depth of 2 and is symmetrical.

[0077] like Figure 3 As shown, the NAND gate circuit includes a binary NAND gate 301, a binary NOR gate 302, a first binary NOT gate 303, and a second binary NOT gate 304. The two inputs of the binary NAND gate 301 are connected to the high-line input signal AH of the first binary two-line input signal A and the high-line input signal BH of the second binary two-line input signal B, respectively. The two inputs of the binary NOR gate 302 are connected to the low-line input signal AL of the first binary two-line input signal A and the low-line input signal BL of the second binary two-line input signal B, respectively. Both the binary NAND gate 301 and the binary NOR gate 302 include one output terminal. The output terminal of the binary NAND gate 301 is connected to one input terminal of the first binary NOT gate 303, and the output terminal of the binary NOR gate 302 is connected to one input terminal of the second binary NOT gate 304. The first binary NOT gate 303 and the second binary NOT gate 304 each include one input terminal and one output terminal. The output signal of the first binary NOT gate 303 is interleaved with the output signal of the second binary NOT gate 304 to form a two-line binary output signal O, wherein the two-line binary output signal O includes a high-line output signal OH and a low-line output signal OL. Figure 4 It shows Figure 3 The representation of a ternary NAND gate.

[0078] Figure 5 It shows Figure 3 and Figure 4 The truth table of the NAND gate circuit in the illustrated embodiment.

[0079] For the first binary two-line input signal A, when the high line input signal AH is 1 (high level) and the low line input signal AL is 0 (low level), the ternary signal + of the first binary two-line input signal A is 0 when the high line input signal AH is 0 and the low line input signal AL is 1. For the first binary two-line input signal -, when the high line input signal AH is 0 and the low line input signal AL is 0, the ternary signal - of the first binary two-line input signal A is 0.

[0080] For the second binary two-line input signal B, when the high line input signal BH is 1 (high level) and the low line input signal BL is 0 (low level), the ternary signal of the second binary two-line input signal B is +; when the high line input signal BH is 0 and the low line input signal BL is 1, the ternary signal of the second binary two-line input signal B is -; when the high line input signal BH is 0 and the low line input signal BL is 0, the ternary signal of the second binary two-line input signal B is 0.

[0081] For a binary two-line output signal O, when the high line output signal OH is 1 (high level) and the low line output signal OL is 0 (low level), the ternary signal of the binary two-line output signal O is +; when the high line output signal OH is 0 and the low line output signal OL is 1, the ternary signal of the binary two-line output signal O is -; when the high line output signal OH is 0 and the low line output signal OL is 0, the ternary signal of the binary two-line output signal O is 0.

[0082] The following description will follow the above method. Of course, there is another possibility: when AH is 0 and AL is 1, the ternary signal is +; when AH is 1 and AL is 0, the ternary signal is -; when AH is 0 and AL is 0, the ternary signal is 0.

[0083] Reference Figure 4 and Figure 5A detailed explanation follows. As an example, let's consider A as + and B as +. In ternary calculation, if the ternary signal of the first binary two-line input signal A is + and the ternary signal of the second binary two-line input signal B is +, then the ternary signal of the binary two-line output signal O is -. For example, if the high-line input signal AH is 1 and the low-line input signal AL is 0, and the high-line input signal BH is 1 and the low-line input signal BL is 0, then the two inputs of binary NAND gate 301 are connected to the high-line input signals AH and BH respectively. The output signal of binary NAND gate 301 is 0, and the output signal of the first binary NOT gate 303 is 1, then the low-line output signal OL is 1. The two inputs of binary NOR gate 302 are connected to the low-line input signals AL and BL respectively. The output signal of binary NOR gate 302 is 1, and the output signal of the second binary NOT gate 304 is 0, then the high-line output signal OH is 0. Thus, the output signal O is 10, and its ternary signal is +. For calculations in other ternary numbers, please refer to the relevant content in the truth table.

[0084] Figure 6 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is an AND gate circuit. The AND gate circuit of this embodiment has a transistor logic depth of 2 and is symmetrical.

[0085] like Figure 6 As shown, the AND gate circuit includes a binary NAND gate 601, a binary NOR gate 602, a first binary NOT gate 603, and a second binary NOT gate 604. The two inputs of the binary NAND gate 601 are connected to the high-line input signal AH of the first binary two-line input signal A and the high-line input signal BH of the second binary two-line input signal B, respectively. The two inputs of the binary NOR gate 602 are connected to the low-line input signal AL of the first binary two-line input signal A and the low-line input signal BL of the second binary two-line input signal B, respectively. Both the binary NAND gate 601 and the binary NOR gate 602 include one output terminal. The output terminal of the binary NAND gate 601 is connected to one input terminal of the first binary NOT gate 603, and the output terminal of the binary NOR gate 602 is connected to one input terminal of the second binary NOT gate 604. The first binary NOT gate 603 and the second binary NOT gate 604 each include one input terminal and one output terminal. The output signal of the first binary NOT gate 603 and the output signal of the second binary NOT gate 604 are not interleaved, forming a two-line binary output signal O, which includes a high-line output signal OH and a low-line output signal OL. Figure 7 It shows Figure 6 The representation of ternary AND gates.

[0086] Figure 8 It shows Figure 6and Figure 7 The truth table of the AND gate circuit in the illustrated embodiment. For ternary relationships, please refer to [link / reference needed]. Figure 5 The relevant description. (Refer to...) Figure 6 and Figure 8 A detailed explanation follows. As an example, let's consider A as - and B as 0. In ternary calculation, if the ternary signal of the first binary two-line input signal A is - and the ternary signal of the second binary two-line input signal B is 0, then the ternary signal of the binary two-line output signal O is -. For example, if the high-line input signal AH is 0 and the low-line input signal AL is 1, and the high-line input signal BH is 0 and the low-line input signal BL is 0, then the two inputs of binary NAND gate 601 are connected to the high-line input signals AH and BH respectively. The output signal of binary NAND gate 601 is 1, and the output signal of the first binary NOT gate 603 is 0, then the high-line output signal OH is 0. The two inputs of binary NOR gate 602 are connected to the low-line input signals AL and BL respectively. The output signal of binary NOR gate 602 is 0, and the output signal of the second binary NOT gate 604 is 1, then the low-line output signal OH is 1. Thus, the output signal O is 01, and its ternary signal is -. For calculations in other ternary numbers, please refer to the relevant content in the truth table.

[0087] Figure 9 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is a NOR gate circuit. The NOR gate circuit of this embodiment has a transistor logic depth of 2 and is symmetrical.

[0088] like Figure 9 As shown, the NOR gate circuit includes a binary NOR gate 901, a binary NAND gate 902, a first binary NOT gate 903, and a second binary NOT gate 904. The two inputs of the binary NOR gate 901 are connected to the high line input signal AH of the first binary two-line input signal A and the high line input signal BH of the second binary two-line input signal B, respectively. The two inputs of the binary NAND gate 902 are connected to the low line input signal AL of the first binary two-line input signal A and the low line input signal BL of the second binary two-line input signal B, respectively. Both the binary NOR gate 901 and the binary NAND gate 902 include one output terminal. The output terminal of the binary NOR gate 901 is connected to one input terminal of the first binary NOT gate 903, and the output terminal of the binary NAND gate 902 is connected to one input terminal of the second binary NOT gate 904. The first binary NOT gate 903 and the second binary NOT gate 904 each include one input terminal and one output terminal. The output signals of the first binary NOT gate 903 and the second binary NOT gate 904 are interleaved to form a two-line binary output signal O, which includes a high-line output signal OH and a low-line output signal OL. Figure 10 It shows Figure 9 The representation of a ternary NOR gate.

[0089] Figure 11 It shows Figure 9 and Figure 10 The truth table for the NOR gate circuit in the illustrated embodiment. For ternary relationships, please refer to [link / reference needed]. Figure 5 The relevant description. (Refer to...) Figure 9 and Figure 11 A detailed explanation follows. As an example, let's consider A as 0 and B as -. In ternary calculation, if the ternary signal of the first binary two-line input signal A is 0 and the ternary signal of the second binary two-line input signal B is -, then the ternary signal of the binary two-line output signal O is 0. For example, if the high-line input signal AH is 0 and the low-line input signal AL is 0, and the high-line input signal BH is 0 and the low-line input signal BL is 1. Connect the two inputs of binary NOR gate 901 to the high-line input signals AH and BH respectively. The output signal of binary NOR gate 901 is 1, and the output signal of the first binary NOT gate 903 is 0, then the low-line output signal OL is 0. Connect the two inputs of binary NAND gate 902 to the low-line input signals AL and BL respectively. The output signal of binary NAND gate 902 is 1, and the output signal of the second binary NOT gate 904 is 0, then the high-line output signal OH is 0. Thus, the output signal O is 00, and its ternary signal is 0. For calculations in other ternary numbers, please refer to the relevant content in the truth table.

[0090] Figure 12 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is an OR gate circuit. The OR gate circuit of this embodiment has a transistor logic depth of 2 and is symmetrical.

[0091] like Figure 12As shown, the OR gate circuit includes a binary NOR gate 1201, a binary NAND gate 1202, a first binary NOT gate 1203, and a second binary NOT gate 1204. The two inputs of the binary NOR gate 1201 are respectively connected to the high-line input signal AH of the first binary two-line input signal A and the high-line input signal BH of the second binary two-line input signal B. The two inputs of the binary NAND gate 1202 are respectively connected to the low-line input signal AL of the first binary two-line input signal A and the low-line input signal BL of the second binary two-line input signal B. Both the binary NOR gate 1201 and the binary NAND gate 1202 include one output terminal. The output terminal of the binary NOR gate 1201 is connected to one input terminal of the first binary NOT gate 1203, and the output terminal of the binary NAND gate 1202 is connected to one input terminal of the second binary NOT gate 1204. The first binary NOT gate 1203 and the second binary NOT gate 1204 each include one input terminal and one output terminal. The output signal of the first binary NOT gate 1203 is interleaved with the output signal of the second binary NOT gate 1204 to form a two-line binary output signal O, which includes a high-line output signal OH and a low-line output signal OL. Figure 13 It shows Figure 12 The representation of a ternary OR gate.

[0092] Figure 14 It shows Figure 12 and Figure 13 The truth table of the OR gate circuit in the illustrated embodiment. For ternary relationships, please refer to [link / reference needed]. Figure 5 The relevant description. (Refer to...) Figure 12 and Figure 14 A detailed explanation follows. As an example, let's consider A as - and B as -. In ternary calculation, if the ternary signal of the first binary two-line input signal A is - and the ternary signal of the second binary two-line input signal B is -, then the ternary signal of the binary two-line output signal O is -. For example, if the high-line input signal AH is 0 and the low-line input signal AL is 1, and the high-line input signal BH is 0 and the low-line input signal BL is 1. The two inputs of binary NOR gate 1201 are connected to the high-line input signals AH and BH respectively. The output signal of binary NOR gate 1201 is 1, and the output signal of the first binary NOT gate 1203 is 0, then the high-line output signal OH is 0. The two inputs of binary NAND gate 1202 are connected to the low-line input signals AL and BL respectively. The output signal of binary NAND gate 1202 is 0, and the output signal of the second binary NOT gate 1204 is 1, then the low-line output signal OL is 1. Thus, the output signal O is 01, and its ternary signal is -. Other ternary calculations can be found in the relevant sections of the truth table.

[0093] Figure 15A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is a loop gate circuit, specifically an increment gate circuit. The transistor logic depth of the increment gate circuit in this embodiment is 1.

[0094] like Figure 15 As shown, the self-incrementing gate circuit includes a binary NOR gate 1501. The two inputs of the binary NOR gate 1501 are connected to the high-line input signal AH and the low-line input signal AL of the binary two-line input signal A, respectively. According to this embodiment, the self-incrementing gate circuit can cycle between a first state +, a second state 0, and a third state -. The output of the binary NOR gate 1501 is the high-line output signal OH, and the high-line input signal AH serves as the low-line output signal OL. The cycle of this self-incrementing gate circuit can be, for example, -0+-0... For example, in the third state -, the high-line input signal AH is 0 and the low-line input signal AL is 1, then the output signal of the binary NOR gate 1501 is 0, that is, the high-line output signal OH is 0. The high-line input signal AH serves as the low-line output signal OL, that is, the low-line output signal OL is 0. Thus, the output of the self-incrementing gate is 00, that is, it transitions to the second state 0. In the second state (0), the high-line input signal AH is 0 and the low-line input signal AL is 0. Therefore, the output signal of the binary NOR gate 1501 is 1, meaning the high-line output signal OH is 1. The high-line input signal AH becomes the low-line output signal OL, meaning the low-line output signal OL is 0. Thus, the output of the auto-increment gate is 10, which is the first state (+). In the first state (+), the high-line input signal AH is 1 and the low-line input signal AL is 0. Therefore, the output signal of the binary NOR gate 1501 is 0, meaning the high-line output signal OH is 0. The high-line input signal AH becomes the low-line output signal OL, meaning the low-line output signal OL is 1. Thus, the output of the auto-increment gate is 01, which is the third state (-). This cycle continues. Figure 16 It shows Figure 15 The representation of an auto-incrementing gate.

[0095] Figure 17 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is a loop gate circuit, specifically a decrement gate circuit. The transistor logic depth of the decrement gate circuit in this embodiment is 1. Furthermore, the increment gate circuit and the decrement gate circuit are symmetrical.

[0096] like Figure 17As shown, the increment gate circuit includes a binary NOR gate 1701. The two inputs of the binary NOR gate 1701 are connected to the high-line input signal AH and the low-line input signal AL of the binary two-line input signal A, respectively. According to this embodiment, the decrement gate circuit can cycle between a first state +, a second state 0, and a third state -. The low-line output signal OL of the binary NOR gate 1701 is used as the high-line output signal OH. The cycle of this decrement gate circuit can be, for example, -+0-+0... For example, in the third state -, the high-line input signal AH is 0 and the low-line input signal AL is 1, then the output signal of the binary NOR gate 1701 is 0, that is, the low-line output signal OL is 0. The low-line input signal AL is used as the high-line output signal OH, that is, the high-line output signal OL is 1. Thus, the output of the increment gate is 10, which is the first state +. In the first state (+), the high-line input signal AH is 1 and the low-line input signal AL is 0. Therefore, the output signal of the binary NOR gate 1701 is 0, meaning the low-line output signal OL is 0. The low-line input signal AL becomes the high-line output signal OH, meaning the high-line output signal OH is 0. Thus, the output of the auto-increment gate is 00, which is the second state (0). In the second state (0), the high-line input signal AH is 0 and the low-line input signal is 0. Therefore, the output signal of the binary NOR gate 1701 is 1, meaning the low-line output signal OL is 1. The low-line input signal AL becomes the high-line output signal OH, meaning the high-line output signal OH is 0. Thus, the output of the auto-increment gate is 01, which is the third state (-). This cycle continues. Figure 18 It shows Figure 17 The representation of a decrement gate.

[0097] Figure 19 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is a decoder circuit. The transistor logic depth of the decoder circuit in this embodiment is only 1.

[0098] The decoder circuit is designed such that, in the first ternary state +, the output P is high and the outputs Z and N are low; in the second ternary state 0, the output Z is high and the outputs P and N are low; and in the third ternary state -, the output N is high and the outputs P and Z are low.

[0099] like Figure 19As shown, the decoder circuit includes a binary NOR gate 1901. The high-line input signal AH and the low-line input signal AL are connected to the two input terminals of the binary NOR gate 1901, respectively. The output terminal of the binary NOR gate 1901 is connected to output Z. The high-line input signal AH is connected to output P. The low-line input signal AL is connected to output N. As an example, in the first state +, AH is 1 and AL is 0. Thus, the high-line input signal AH (output P) is 1, the output of the binary NOR gate 1901 (output Z) is 0, and the low-line input signal AL (output N) is 0. Therefore, output P is 1 and outputs Z and N are 0, which corresponds to the first state +. The second and third states are the same and will not be described further. Figure 20 It shows Figure 19 The way the decoder is represented.

[0100] Figure 21 and Figure 22 A converter for switching between two-wire and single-wire systems is shown. This embodiment of the converter circuit reduces the number of pins, is more modular compared to conventional multi-valued logic circuits, and offers superior speed and noise tolerance. Figure 21 This illustrates a converter that transforms a two-wire system into a single-wire system. Figure 22 This illustrates a converter that transforms a single-wire system into a two-wire system. Figure 21 The converter in this embodiment converts a two-wire signal A into a single-wire signal O, for example, converting 00 to 0, 10 to +, and 01 to -. Additionally, when the two-wire signal A is 11, it can be converted to a special state. Conversely, it can be... Figure 22 The converter shown converts a single-wire signal O into a two-wire signal A. For Figure 22 The converter can be implemented using existing analog comparators. Figure 22 The converter in this embodiment can convert a ternary signal represented in ternary form into a two-line ternary signal, after which the two-line ternary signal can be input to... Figure 1-20 The high line input and low line input of the embodiment. Figure 21 The converter in this embodiment can convert a two-wire ternary signal into a ternary signal represented in ternary form. Figure 21 The input signals A (AH and AL) of the embodiments can be connected to the high line output terminal OH and the low line input terminal OL of the embodiments shown in the figure, respectively.

[0101] In the various embodiments described above, one or two two-wire input terminals (A or B) are included, but more than three two-wire input terminals may also be included. Figure 23 The text shows the relationship with... Figure 3 The example shown illustrates the three two-wire inputs of the NAND gate. Figure 23 and Figure 3 The difference in the circuit structure of the embodiments is that, Figure 23The embodiment includes three two-wire input terminals A, B, and C. High-line input signals AH, BH, and CH are connected to the three input terminals of NAND gate 2301, and low-line input signals AL, BL, and CL are connected to the three input terminals of NOR gate 2302. The output terminal of NAND gate 2301 is connected to the input terminal of first inverter 2303, and the output terminal of NOR gate 2302 is connected to the input terminal of second inverter 2304. The output terminals of the first inverter 2303 and the second inverter 2304 are interleaved, outputting a low-line output signal OL and a high-line output signal OH, respectively. Figure 24 It shows Figure 23 The representation method is as follows. Additionally, for other suitable embodiments of this implementation, three or more two-wire input terminals may be used, which will not be elaborated further here.

[0102] According to another embodiment of this disclosure, various binary two-wire ternary circuits are provided, wherein this embodiment may include... Figures 25 to 46 The illustrated embodiment. In this embodiment, the ternary states are implemented in binary form, where the three ternary states can include a first state +, a second state -, a third state 0, and a special state. The special state can be one of a high-impedance state, an error state, etc. Each binary two-wire input signal includes two input signals, such as the high line corresponding to the first input signal (high line input signal) and the low line corresponding to the second input signal (low line input signal). The two input signals can be either a first level or a second level, where the first level and the second level are high and the second level is low. The ternary signal is represented as +, 0, and -. When both the high line input signal and the low line input signal are high (1), the ternary signal is +; when both the high line input signal and the low line input signal are low (1), the ternary signal is 0; when both the high line input signal and the low line input signal are low (0), the ternary signal is -. In addition, when the high line input signal is high level (1) and the low line input signal is low level (0), the ternary signal is a special state signal.

[0103] Figure 25A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is an inverter. The inverter in this embodiment can be implemented by expanding binary logic gates in a symmetrical manner, consistent with the binary logic depth, without sacrificing circuit speed. The inverter includes two input terminals, which are respectively connected to the high-line input signal AH and the low-line input signal AL of the binary two-wire input signal A. The high-line input signal AH and the low-line input signal AL can be either high-level signals or low-level signals. The binary two-wire output signal O of the inverter includes a high-line output signal OH and a low-line output signal OL. The high-line input signal AH is connected to a first binary NOT gate 2501, and the low-line input signal AL is connected to a second binary NOT gate 2502. The outputs of the first binary NOT gate 2501 and the second binary NOT gate 2502 are interleaved to form the low-line output signal OL and the high-line output signal OH, respectively.

[0104] When the ternary signal is + (11), the high-line input signal AH is 1 and the low-line input signal AL is 1. The output of the first binary NOT gate 2501 is 0, and the output of the second binary NOT gate 2502 is 0, so the high-line output signal OH is 0 and the low-line output signal OL is 0. The inverter can output the ternary signal + as the ternary signal - (00). When the ternary signal is - (00), the high-line input signal AH is 0 and the low-line input signal AL is 0. The output of the first binary NOT gate 2501 is 1, and the output of the second binary NOT gate 2502 is 1, so the high-line output signal OH is 1 and the low-line output signal OL is 1. The inverter can output the ternary signal - as the ternary signal + (11). When the ternary signal is 0 (01), the high-line input signal AH is 0 and the low-line input signal AL is 1, so the high-line output signal OH is 0 and the low-line output signal OL is 1. This inverter can output the ternary signal 0 as the ternary signal 0(01). Figure 26 It shows Figure 25 The representation of an inverter.

[0105] Figure 27 A ternary circuit using a binary two-wire approach according to an embodiment of the present disclosure is shown, wherein the ternary circuit is a NAND gate circuit. The NAND gate circuit of this embodiment can be implemented by extending binary logic gates and the extension method is symmetrical, consistent with the logic depth of binary, without sacrificing circuit speed.

[0106] like Figure 27As shown, the NAND gate circuit includes a binary NAND gate 2701 and a binary NAND gate 2702. The two inputs of the binary NAND gate 2701 are connected to the high-line input signal AH of the first binary two-line input signal A and the high-line input signal BH of the second binary two-line input signal B, respectively. The two inputs of the binary NAND gate 2702 are connected to the low-line input signal AL of the first binary two-line input signal A and the low-line input signal BL of the second binary two-line input signal B, respectively. The output signals of the binary NAND gates 2701 and 2702 are interleaved to form a binary two-line output signal O, which includes a high-line output signal OH (the output signal of the binary NAND gate 2702) and a low-line output signal OL (the output signal of the binary NAND gate 2701). Figure 28 It shows Figure 27 The representation of a ternary NAND gate.

[0107] Figure 29 It shows Figure 27 and Figure 28 The truth table of the NAND gate circuit in the illustrated embodiment.

[0108] For the first binary two-line input signal A, when the high line input signal AH is 1 (high level) and the low line input signal AL is 1, the ternary signal of the first binary two-line input signal A is +; when the high line input signal AH is 0 (low level) and the low line input signal AL is 0, the ternary signal of the first binary two-line input signal A is -; when the high line input signal AH is 0 and the low line input signal AL is 1, the ternary signal of the first binary two-line input signal A is 0; when the high line input signal AH is 1 and the low line input signal AL is 0, the ternary signal of the first binary two-line input signal A represents a special state.

[0109] For the second binary two-line input signal B, when the high line input signal BH is 1 (high level) and the low line input signal BL is 1, the ternary signal of the second binary two-line input signal B is +; when the high line input signal BH is 0 (low level) and the low line input signal BL is 0, the ternary signal of the second binary two-line input signal B is -; when the high line input signal BH is 0 and the low line input signal BL is 1, the ternary signal of the second binary two-line input signal B is 0; when the high line input signal BH is 1 and the low line input signal BL is 0, the ternary signal of the second binary two-line input signal B represents a special state.

[0110] For a binary two-line output signal O, when the high line output signal OH is 1 (high level) and the low line output signal OL is 1, the ternary signal of the binary two-line output signal O is +; when the high line output signal OH is 0 (low level) and the low line output signal OL is 0, the ternary signal of the binary two-line output signal O is -; when the high line output signal OH is 0 and the low line output signal OL is 0, the ternary signal of the binary two-line output signal O is 0; when the high line output signal OH is 1 and the low line output signal OL is 0, the ternary signal of the binary two-line output signal O represents a special state.

[0111] Reference Figure 27 and Figure 29 A detailed explanation follows. As an example, let's consider A as + and B as +. In ternary calculations, if the ternary signal of the first binary two-line input signal A is + and the ternary signal of the second binary two-line input signal B is +, then the ternary signal of the binary two-line output signal O is -. For example, if the high-line input signal AH is 1 and the low-line input signal AL is 1, and the high-line input signal BH is 1 and the low-line input signal BL is 1, then the two inputs of binary NAND gate 2701 are connected to the high-line input signals AH and BH respectively. The output signal of binary NAND gate 2701 is 0, and the low-line output signal OL is 0. The two inputs of binary NAND gate 2702 are connected to the low-line input signals AL and BL respectively. The output signal of binary NAND gate 2702 is 0, and the high-line output signal OH is 0. Thus, the output signal O is 00, and its ternary signal is -. Other ternary calculations can be found in the relevant content of the truth table.

[0112] Figure 30 A ternary circuit using a binary two-wire approach according to an embodiment of this disclosure is shown, wherein the ternary circuit is an AND gate circuit. The AND gate circuit of this embodiment can be implemented by extending binary logic gates, and the extension method is symmetrical, consistent with the logic depth of binary, without sacrificing circuit speed.

[0113] like Figure 30As shown, the AND gate circuit includes binary NAND gate 3001, binary NAND gate 3002, a first binary NOT gate 3003, and a second binary NOT gate 3004. The two inputs of binary NAND gate 3001 are connected to the high line input signal AH of the first binary two-line input signal A and the high line input signal BH of the second binary two-line input signal B, respectively. The two inputs of binary NAND gate 3002 are connected to the low line input signal AL of the first binary two-line input signal A and the low line input signal BL of the second binary two-line input signal B, respectively. Binary NAND gates 3001 and 3002 each include one output terminal. The output terminal of binary NAND gate 3001 is connected to one input terminal of the first binary NOT gate 3003, and the output terminal of binary NAND gate 3002 is connected to one input terminal of the second binary NOT gate 3004. The first binary NOT gate 3003 and the second binary NOT gate 3004 each include one input terminal and one output terminal. The output signal of the first binary NOT gate 3003 and the output signal of the second binary NOT gate 3004 are not interleaved, forming a two-line binary output signal O. The two-line binary output signal O includes a high-line output signal OH and a low-line output signal OL. The high-line output signal OH is the output signal of the first binary NOT gate 3003, and the low-line output signal OL is the output signal of the second binary NOT gate 3004. Figure 31 It shows Figure 30 The representation of ternary AND gates.

[0114] Figure 32 It shows Figure 30 and Figure 31 The truth table of the AND gate circuit in the illustrated embodiment. For ternary relationships, please refer to [link / reference needed]. Figure 29 The relevant description. (Refer to...) Figure 30 and Figure 32A detailed explanation follows. As an example, let's consider A as - and B as 0. In ternary calculation, if the ternary signal of the first binary two-line input signal A is - and the ternary signal of the second binary two-line input signal B is 0, then the ternary signal of the binary two-line output signal O is -. For example, if the high-line input signal AH is 0 and the low-line input signal AL is 0, and the high-line input signal BH is 0 and the low-line input signal BL is 1, then the two inputs of binary NAND gate 3001 are connected to the high-line input signals AH and BH respectively. If the output signal of binary NAND gate 3001 is 1, and the output signal of the first binary NOT gate 3003 is 0, then the high-line output signal OH is 0. The two inputs of binary NAND gate 3002 are connected to the low-line input signals AL and BL respectively. If the output signal of binary NAND gate 3002 is 0 and the output signal of the second binary NOT gate 3004 is 1, then the low-line output signal OH is 0, so the output signal O is 00, and its ternary signal is -. Other ternary calculations can be found in the relevant content of the truth table.

[0115] Figure 33 A ternary circuit using a binary two-wire approach according to an embodiment of the present disclosure is shown, wherein the ternary circuit is a NOR gate circuit. The NOR gate circuit of this embodiment can be implemented by extending binary logic gates and the extension method is symmetrical, consistent with the logic depth of binary, without sacrificing circuit speed.

[0116] like Figure 33 As shown, the NOR gate circuit includes a binary NOR gate 3301 and a binary NOR gate 3302. The two inputs of the binary NOR gate 3301 are connected to the high-line input signal AH of the first binary two-line input signal A and the high-line input signal BH of the second binary two-line input signal B, respectively. The two inputs of the binary NOR gate 3302 are connected to the low-line input signal AL of the first binary two-line input signal A and the low-line input signal BL of the second binary two-line input signal B, respectively. The output signal of the first binary NOT gate 3303 is interleaved with the output signal of the second binary NOT gate 3304 to form a binary two-line output signal O, which includes a high-line output signal OH and a low-line output signal OL. The high-line output signal OH is the output signal of the second binary NOT gate 3304, and the low-line output signal OL is the output signal of the first binary NOT gate 3303. Figure 34 It shows Figure 33 The representation of a ternary NOR gate.

[0117] Figure 35 It shows Figure 33 and Figure 34 The truth table for the NOR gate circuit in the illustrated embodiment. For ternary relationships, please refer to [link / reference needed]. Figure 27The relevant description. (Refer to...) Figure 33 and Figure 35 A detailed explanation follows. As an example, let's consider A as 0 and B as -. In ternary calculations, if the ternary signal of the first binary two-line input signal A is 0 and the ternary signal of the second binary two-line input signal B is -, then the ternary signal of the binary two-line output signal O is 0. For example, if the high-line input signal AH is 0 and the low-line input signal AL is 1, and the high-line input signal BH is 0 and the low-line input signal BL is 0, then the two inputs of binary NOR gate 3301 are connected to the high-line input signals AH and BH respectively. If the output signal of binary NOR gate 3301 is 1, then the low-line output signal OL is 1. Similarly, the two inputs of binary NOR gate 3302 are connected to the low-line input signals AL and BL respectively. If the output signal of binary NOR gate 3302 is 0, then the high-line output signal OH is 0. Thus, the output signal O is 01, and its ternary signal is 0. Other ternary calculations can be found in the truth table.

[0118] Figure 36 A ternary circuit using a binary two-wire approach according to an embodiment of the present disclosure is shown, wherein the ternary circuit is an OR gate circuit. The OR gate circuit of this embodiment can be implemented by extending binary logic gates and the extension method is symmetrical, consistent with the logic depth of binary, without sacrificing circuit speed.

[0119] like Figure 36As shown, the OR gate circuit includes a binary NOR gate 3601, a binary NOR gate 3602, a first binary NOT gate 3603, and a second binary NOT gate 3604. The two inputs of the binary NOR gate 3601 are respectively connected to the high-line input signal AH of the first binary two-line input signal A and the high-line input signal BH of the second binary two-line input signal B. The two inputs of the binary NOR gate 3602 are respectively connected to the low-line input signal AL of the first binary two-line input signal A and the low-line input signal BL of the second binary two-line input signal B. Both the binary NOR gate 3601 and the binary NOR gate 3602 include one output terminal. The output terminal of the binary NOR gate 3601 is connected to one input terminal of the first binary NOT gate 3603, and the output terminal of the binary NOR gate 3602 is connected to one input terminal of the second binary NOT gate 3604. The first binary NOT gate 3603 and the second binary NOT gate 3604 each include one input terminal and one output terminal. The output signal of the first binary NOT gate 3603 and the output signal of the second binary NOT gate 3604 are not interleaved, forming a two-line binary output signal O. The two-line binary output signal O includes a high-line output signal OH and a low-line output signal OL. The high-line output signal OH is the output signal of the first binary NOT gate 3603, and the low-line output signal OL is the output signal of the second binary NOT gate 3604. Figure 37 It shows Figure 36 The representation of a ternary OR gate.

[0120] Figure 38 It shows Figure 36 and Figure 37 The truth table of the OR gate circuit in the illustrated embodiment. For ternary relationships, please refer to [link / reference needed]. Figure 29 The relevant description. (Refer to...) Figure 36 and Figure 38A detailed explanation follows. As an example, let's consider A as - and B as -. In ternary calculation, if the ternary signal of the first binary two-line input signal A is - and the ternary signal of the second binary two-line input signal B is -, then the ternary signal of the binary two-line output signal O is -. For example, if the high-line input signal AH is 0 and the low-line input signal AL is 0, and the high-line input signal BH is 0 and the low-line input signal BL is 0. The two inputs of binary NOR gate 3601 are connected to the high-line input signals AH and BH respectively. The output signal of binary NOR gate 3601 is 1, and the output signal of the first binary NOT gate 3603 is 0, then the high-line output signal OH is 0. The two inputs of binary NOR gate 3602 are connected to the low-line input signals AL and BL respectively. The output signal of binary NOR gate 3602 is 1, and the output signal of the second binary NOT gate 3604 is 0, then the low-line output signal OL is 0. Thus, the output signal O is 00, and its ternary signal is -. Other ternary calculations can be found in the relevant sections of the truth table.

[0121] Figure 39 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is a loop gate circuit, specifically an increment gate circuit.

[0122] like Figure 39As shown, the self-incrementing gate circuit includes a binary NOT gate 3901, a binary NOR gate 3902, and a binary NAND gate 3903. The binary NOT gate 3901 has one input terminal connected to the low-line input signal AL of the two-line binary input signal A. The binary NOR gate 3902 has two input terminals connected to the high-line input signal AH of the two-line binary input signal A and the output signal of the binary NOT gate 3901, respectively. The binary NAND gate 3903 has two input terminals connected to the high-line input signal AH and the low-line input signal AL of the two-line binary input signal A, respectively. The output signal of the binary NOR gate 3902 is the high-line output signal OH. The output signal of the binary NAND gate 3903 is the low-line output signal OL. According to this embodiment, the self-incrementing gate circuit can cycle between a first state +, a second state 0, and a third state -. The cycle of this self-incrementing gate circuit can, for example, be -0+-0... For example, in the third state -, the high-line input signal AH is 0 and the low-line input signal AL is 0. The output signal of binary NOT gate 3901 is 1, the output signal of binary NOR gate 3902 is 0, and the output signal of binary NAND gate 3903 is 1. Thus, the high-line output signal OH is 0 and the low-line output signal OL is 1, transitioning to the second state 0 (01). In the second state 0, the high-line input signal AH is 0 and the low-line input signal AL is 1. The output signal of binary NOT gate 3901 is 0, the output signal of binary NOR gate 3902 is 1, and the output signal of binary NAND gate 3903 is 1. Thus, the high-line output signal OH is 1 and the low-line output signal OL is 1, transitioning to the first state + (11). In the first state +, the high-line input signal AH is 1 and the low-line input signal AL is 1. The output signal of binary NOT gate 3901 is 0, the output signal of binary NOR gate 3902 is 0, and the output signal of binary NAND gate 3903 is 0. Thus, the high-line output signal OH is 0 and the low-line output signal OL is 0, transitioning to the third state - (00). This process is repeated. Figure 40 It shows Figure 39 The representation of an auto-incrementing gate.

[0123] Figure 41 A ternary circuit using a binary two-wire method according to an embodiment of the present disclosure is shown, wherein the ternary circuit is a loop gate circuit, specifically a decrement gate circuit.

[0124] like Figure 41As shown, the self-incrementing gate circuit includes a binary NOT gate 4101, a binary NOR gate 4102, and a binary NAND gate 4103. The binary NOT gate 4101 has one input terminal connected to the high-line input signal AH of the two-line binary input signal A. The binary NOR gate 4102 has two input terminals connected to the high-line input signal AH and the low-line input signal AL of the two-line binary input signal A, respectively. The binary NAND gate 4103 has two input terminals connected to the output signal of the binary NOT gate 4101 and the low-line input signal AL of the two-line binary input signal A, respectively. The output signal of the binary NOR gate 4102 is the high-line output signal OH. The output signal of the binary NAND gate 4103 is the low-line output signal OL. According to this embodiment, the self-incrementing gate circuit can cycle between a first state +, a second state 0, and a third state -. The cycle of this self-decrementing gate circuit can, for example, be -+0-+0... For example, in the third state -, with the high-line input signal AH being 0 and the low-line input signal AL being 0, the output signal of the binary NOR gate 4102 is 1, the output signal of the binary NOT gate 4101 is 1, and the output signal of the binary NAND gate 4103 is 1. Therefore, the high-line output signal OH is 1, and the low-line output signal OL is 1. Thus, the output of the auto-incrementing gate is 11, which corresponds to the first state +. In the first state +, with the high-line input signal AH being 1 and the low-line input signal AL being 1, the output signal of the binary NOR gate 4102 is 0, the output signal of the binary NOT gate 4101 is 0, and the output signal of the binary NAND gate 4103 is 1. Therefore, the high-line output signal OH is 0, and the low-line output signal OL is 1. Thus, the output of the auto-incrementing gate is 01, which corresponds to the second state 0. In the second state 0, the high-line input signal AH is 0 and the low-line input signal is 1. Therefore, the output signal of the binary NOR gate 4102 is 0, the output signal of the binary NOT gate 4101 is 1, and the output signal of the binary NAND gate 4103 is 0. Thus, the high-line output signal OH is 0, and the low-line output signal OL is 0. This results in the output of the auto-increment gate being 00, which corresponds to the third state -. This cycle continues. Figure 42 It shows Figure 41 The representation of a decrement gate.

[0125] Figure 43 and Figure 44 This illustrates a converter that transforms two-wire to single-wire systems. Figure 43 This illustrates a converter that transforms a two-wire system into a single-wire system. Figure 44 This illustrates a converter that transforms a single-wire system into a two-wire system. Figure 43 The converter in this embodiment converts a two-wire signal A into a single-wire signal O, for example, converting 11 to +, 00 to -, and 01 to 0. Additionally, when the two-wire signal A is 10, it can be converted to a special state. Conversely, it can be... Figure 44 The converter shown converts a single-wire signal O into a two-wire signal A. For Figure 42 The converter can be implemented using existing analog comparators. Figure 44 The converter in this embodiment can convert a ternary signal represented in ternary form into a two-line ternary signal. After conversion, the two-line ternary signal can be input to the high line input terminal and the low line input terminal of each embodiment of the other embodiment described above. Figure 43 The converter in this embodiment can convert a two-wire ternary signal into a ternary signal represented in ternary form. Figure 43 The input signals A (AH and AL) of the embodiment can be connected to the high line output terminal OH and the low line input terminal OL of each embodiment of the other embodiment described above.

[0126] In various embodiments of the other implementation described above, one or two two-wire input terminals (A or B) are included, but more than three two-wire input terminals may also be included. Figure 45 The text shows the relationship with... Figure 25 The example shown illustrates the three two-wire inputs of the NAND gate. Figure 45 and Figure 25 The difference in the circuit structure of the embodiments is that, Figure 45 The embodiment includes three two-wire input terminals A, B, and C. High-line input signals AH, BH, and CH are connected to the three input terminals of NAND gate 4501, and low-line input signals AL, BL, and CL are connected to the three input terminals of NOR gate 4502. The output terminals of NAND gate 4501 and NOR gate 4502 are interleaved to output a low-line output signal OL and a high-line output signal OH, respectively. Figure 46 It shows Figure 45 The representation method is as follows. Additionally, for other suitable embodiments of this implementation, three or more two-wire input terminals may be used, which will not be elaborated further here.

[0127] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0128] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A two-wire ternary circuit, wherein the two-wire ternary circuit is used for performing ternary operations, characterized in that, include: Two-wire input terminals, wherein the number of two-wire input terminals is one or more, and each two-wire input terminal includes a high-line input terminal for inputting a high-line input signal and a low-line input terminal for inputting a low-line input signal, wherein the high-line input signal and the low-line input signal are respectively a high-level signal and a low-level signal; as well as The two-wire output terminal has one number and includes a high-line output terminal for outputting a high-line output signal and a low-line output terminal for outputting a low-line output signal. The high-line output signal and the low-line output signal are respectively one of a high-level signal and a low-level signal. The high-line output terminal and the low-line output terminal are respectively connected to the outputs of two binary logic gates; or respectively connected to the output of a binary logic gate and one of the high-line input terminal and the low-line input terminal; or respectively connected to the low-line input terminal and the high-line input terminal. The two-wire ternary circuit is capable of high-impedance operation. Specifically, when the high-line input signal is low and the low-line input signal is high, the ternary signal of the two-wire ternary circuit is in a first state; when the high-line input signal is high and the low-line input signal is low, the ternary signal of the two-wire ternary circuit is in a second state; when the high-line and low-line input signals are at the same level, and the same level signal is high, the ternary signal of the two-wire ternary circuit is either a third state or a high-impedance state; and when the same level signal is low, the ternary signal of the two-wire ternary circuit is either a third state or a high-impedance state.

2. The two-wire ternary circuit as described in claim 1, characterized in that, Also includes: A binary logic gate, wherein the number of binary logic gates is one or more, and at least a portion of the inputs of the binary logic gates are connected to at least one of the high-line inputs and the low-line inputs.

3. The two-wire ternary circuit as described in claim 1, characterized in that, The two-wire ternary circuit is an inverter circuit. The number of the two-wire input terminal and the number of the two-wire output terminal are one each. The high line input terminal and the low line input terminal of the two-wire input terminal are interleaved and connected to the low line output terminal and the high line output terminal of the two-wire output terminal, respectively.

4. The two-wire ternary circuit as described in claim 2, characterized in that, The two-wire ternary circuit is a NAND gate circuit. The binary logic gates include NAND gates, NOR gates, a first inverter, and a second inverter. There are two two-wire inputs. The high-line input of the first two-wire input is connected to one input of the NAND gate, and the low-line input is connected to one input of the NOR gate. The high-line input of the second two-wire input is connected to the other input of the NAND gate, and the low-line input is connected to the other input of the NOR gate. The outputs of the NAND gate and the NOR gate are respectively connected to the inputs of the first inverter and the second inverter. The outputs of the first inverter and the second inverter are interleaved, outputting a low-line output signal and a high-line output signal, respectively.

5. The two-wire ternary circuit as described in claim 2, characterized in that, The two-wire ternary circuit is an AND gate circuit. The binary logic gates include NAND gates, NOR gates, a first inverter, and a second inverter. There are two two-wire inputs. The high-line input of the first two-wire input is connected to one input of the NAND gate, and the low-line input is connected to one input of the NOR gate. The high-line input of the second two-wire input is connected to the other input of the NAND gate, and the low-line input is connected to the other input of the NOR gate. The outputs of the NAND gate and the NOR gate are respectively connected to the inputs of the first inverter and the second inverter. The outputs of the first inverter and the second inverter are not interleaved, and they output a high-line output signal and a low-line output signal, respectively.

6. The two-wire ternary circuit as described in claim 2, characterized in that, The two-wire ternary circuit is a NOR gate circuit. The binary logic gates include NOR gates, NAND gates, a first inverter, and a second inverter. There are two two-wire inputs. The high-line input of the first two-wire input is connected to one input of the NOR gate, and the low-line input is connected to one input of the NAND gate. The high-line input of the second two-wire input is connected to the other input of the NOR gate, and the low-line input is connected to the other input of the NAND gate. The outputs of the NOR gate and the NAND gate are respectively connected to the inputs of the first inverter and the second inverter. The outputs of the first inverter and the second inverter are interleaved, outputting a low-line output signal and a high-line output signal, respectively.

7. The two-wire ternary circuit as described in claim 2, characterized in that, The two-wire ternary circuit is an OR gate circuit. The binary logic gates include NOR gates, NAND gates, a first inverter, and a second inverter. There are two two-wire inputs. The high-line input of the first two-wire input is connected to one input of the NOR gate, and the low-line input is connected to one input of the NAND gate. The high-line input of the second two-wire input is connected to the other input of the NOR gate, and the low-line input is connected to the other input of the NAND gate. The outputs of the NOR gate and the NAND gate are respectively connected to the inputs of the first inverter and the second inverter. The outputs of the first inverter and the second inverter are not interleaved, and they output a high-line output signal and a low-line output signal, respectively.

8. The two-wire ternary circuit as described in claim 2, characterized in that, The two-wire ternary circuit is an incrementing gate circuit. The binary logic gate includes a NOR gate, and the number of two-wire input terminals is one. The high line input terminal of the two-wire input terminal is connected to one input of the NOR gate, and the low line input terminal of the two-wire input terminal is connected to the other input of the NOR gate. The NOR gate outputs a high line output signal, and the low line output signal is the high line input signal of the high line input terminal.

9. The two-wire ternary circuit as described in claim 2, characterized in that, The two-wire ternary circuit is a decrementing gate circuit. The binary logic gate includes a NOR gate, and the number of two-wire input terminals is one. The high line input terminal of the two-wire input terminal is connected to one input of the NOR gate, and the low line input terminal of the two-wire input terminal is connected to the other input of the NOR gate. The NOR gate outputs a low line output signal, and the high line output signal is the low line input signal of the low line input terminal.

10. The two-wire ternary circuit as described in claim 2, characterized in that, The two-wire ternary circuit is an inverter circuit. The binary logic gate includes a first inverter and a second inverter. The number of two-wire input terminals is one. The high-line input terminal and the low-line input terminal of the two-wire input terminal are respectively connected to the input of the first inverter and the input of the second inverter. The outputs of the first inverter and the second inverter are interleaved to output low-line output signals and high-line output signals respectively.

11. The two-wire ternary circuit as described in claim 2, characterized in that, The two-wire ternary circuit is a NAND gate circuit. The binary logic gate includes a first NAND gate and a second NAND gate. There are two two-wire input terminals. The high-line input terminal of the first two-wire input terminal is connected to one input of the first NAND gate, and the high-line input terminal of the second two-wire input terminal is connected to the other input of the first NAND gate. The low-line input terminal of the first two-wire input terminal is connected to one input of the second NAND gate, and the low-line input terminal of the second two-wire input terminal is connected to the other input of the second NAND gate. The outputs of the first NAND gate and the second NAND gate are interleaved to output low-line output signals and high-line output signals, respectively.

12. The two-wire ternary circuit as described in claim 2, characterized in that, The two-wire ternary circuit is an AND gate circuit. The binary logic gate includes a first NAND gate, a second NAND gate, a first inverter, and a second inverter. There are two two-wire inputs. The high-line input of the first two-wire input is connected to one input of the first NAND gate, and the high-line input of the second two-wire input is connected to the other input of the first NAND gate. The low-line input of the first two-wire input is connected to one input of the second NAND gate, and the low-line input of the second two-wire input is connected to the other input of the second NAND gate. The outputs of the first and second NAND gates are respectively connected to the inputs of the first and second inverters. The outputs of the first and second inverters are not interleaved, and each outputs a high-line output signal and a low-line output signal, respectively.

13. The two-wire ternary circuit as described in claim 2, characterized in that, The two-wire ternary circuit is a NOR gate circuit. The binary logic gate includes a first NOR gate and a second NOR gate. There are two two-wire input terminals. The high line input of the first two-wire input terminal is connected to one input of the first NOR gate, and the high line input of the second two-wire input terminal is connected to the other input of the first NOR gate. The low line input of the first two-wire input terminal is connected to one input of the second NOR gate, and the low line input of the second two-wire input terminal is connected to the other input of the second NOR gate. The outputs of the first NOR gate and the second NOR gate are interleaved to output low line output signals and high line output signals, respectively.

14. The two-wire ternary circuit as described in claim 2, characterized in that, The two-wire ternary circuit is an OR gate circuit. The binary logic gate includes a first NOR gate, a second NOR gate, a first inverter, and a second inverter. There are two two-wire input terminals. The high-line input of the first two-wire input terminal is connected to one input of the first NOR gate, and the high-line input of the second two-wire input terminal is connected to the other input of the first NOR gate. The low-line input of the first two-wire input terminal is connected to one input of the second NOR gate, and the low-line input of the second two-wire input terminal is connected to the other input of the second NOR gate. The outputs of the first NOR gate and the second NOR gate are respectively connected to the inputs of the first inverter and the second inverter. The outputs of the first inverter and the second inverter are not interleaved, and each outputs a high-line output signal and a low-line output signal, respectively.

15. The two-wire ternary circuit as described in claim 2, characterized in that, The two-wire ternary circuit is an incrementing gate circuit. The binary logic gate includes an inverter, a NOR gate, and a NAND gate. The number of two-wire input terminals is one. The high-line input terminal of the two-wire input terminal is connected to one input of the NOR gate and one input of the NAND gate. The low-line input terminal of the two-wire input terminal is connected to the input of the inverter and the other input of the NAND gate. The output of the inverter is connected to the other input of the NOR gate. The NOR gate and the NAND gate output a high-line output signal and a low-line output signal, respectively.

16. The two-wire ternary circuit as described in claim 2, characterized in that, The two-wire ternary circuit is a decrementing gate circuit. The binary logic gate includes an inverter, a NOR gate, and a NAND gate. The number of two-wire input terminals is one. The high-line input terminal of the two-wire input terminal is connected to one input of the NOR gate and the input of the inverter. The output of the inverter is connected to one input of the NAND gate. The low-line input terminal of the two-wire input terminal is connected to the other input of the NOR gate and the other input of the NAND gate. The NOR gate and the NAND gate output a high-line output signal and a low-line output signal, respectively.

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