A cascaded error correction coding method, device, and storage medium

Abstract

The present invention discloses a cascade error correction coding method, device and storage medium, which relates to the technical field of error correction coding and solves the technical problem that traditional cascade codes increase redundant information and cause the information transmission rate to decrease in communication scenarios with relatively small data volumes. The method includes performing Viterbi decoding on the soft decision results of received information to obtain a decoded bit sequence; performing a cyclic redundancy check on the decoded bit sequence; if no check is performed, performing convolutional coding on the decoded bit sequence to obtain a coded bit sequence; obtaining a high-frequency error pattern and correcting the decoded bit sequence according to the high-frequency error pattern; performing a cyclic redundancy check on the decoded bit sequence after error correction; if the decoded bit sequence after error correction and / or the decoded bit sequence passes the cyclic redundancy check, the cascade error correction coding is terminated. The present invention can also ensure efficient and reliable information transmission in communication scenarios with relatively small data volumes.

Description

Technical Field

[0001] The present invention relates to the technical field of error correction coding, and in particular to a cascade error correction coding method, device and storage medium. Background Art

[0002] In modern communication systems, data transmission reliability is crucial. Due to factors such as channel noise and interference, data at the receiving end often contains errors. To improve the system's ability to resist interference, error-correcting coding (ECC) technology is widely used in the communications field. The basic principle of ECC is to detect and correct errors during transmission by introducing redundant information, but this comes at the expense of a reduced information transmission rate. Therefore, the core goal of ECC research is to improve error detection and correction capabilities while minimizing redundancy.

[0003] To further improve the performance of traditional error-correcting coding methods (such as linear block codes and convolutional codes), the code length must be increased (e.g., increasing the code length n for block codes or the information length k for convolutional codes). However, increasing the code length dramatically increases the encoding and decoding complexity, even exceeding the acceptable range for practical systems. To address this issue, concatenated codes have emerged. Concatenated codes combine two or more coding methods (e.g., in series or parallel) to achieve higher error correction performance while maintaining low complexity.

[0004] Currently, convolutional codes combined with Reed-Solomon (RS) codes are a widely used concatenated coding scheme. In this scheme, RS coding typically uses RS(8+k, k) or RS(16+k, k), resulting in 8 or 16 bytes of additional redundancy in the encoded data compared to using convolutional codes alone. While this scheme effectively improves error correction capabilities, in communications scenarios with smaller data volumes (such as small packets of only a few dozen bytes), the introduction of redundant information can significantly reduce the transmission rate, impacting communication efficiency.

[0005] In the process of implementing the present invention, the inventors discovered that the prior art has at least the following problems:

[0006] For communication scenarios with smaller data volumes, traditional concatenated codes will increase redundant information, resulting in a decrease in information transmission rate. Summary of the Invention

[0007] The purpose of the present invention is to provide a cascade error correction coding method, device and storage medium to solve the technical problem in the prior art that for communication scenarios with small data volumes, traditional cascade codes increase redundant information, resulting in a decrease in the information transmission rate.

[0008] The various technical effects that can be produced by the preferred technical solutions among the various technical solutions provided by the present invention are described in detail below.

[0009] To achieve the above objectives, the present invention provides the following technical solutions:

[0010] The present invention provides a cascade error correction coding method, comprising the following steps: performing Viterbi decoding on a soft decision result of received information to obtain a decoded bit sequence; performing a cyclic redundancy check on the decoded bit sequence; if the decoded bit sequence fails the cyclic redundancy check, performing convolutional coding on the decoded bit sequence to obtain a coded bit sequence; obtaining a high-frequency error pattern, and correcting the decoded bit sequence according to the high-frequency error pattern; wherein the high-frequency error pattern includes a decoding error pattern of the decoded bit sequence and an encoding error pattern of the encoding bit sequence; performing a cyclic redundancy check on the decoded bit sequence after error correction; and terminating the cascade error correction coding if the decoded bit sequence after error correction and / or the decoded bit sequence pass the cyclic redundancy check.

[0011] Optionally, obtaining a high-frequency word error pattern of the decoding bit sequence and correcting the decoding bit sequence according to the high-frequency error pattern includes: obtaining a decoding error pattern of the decoding bit sequence and an encoding error pattern of the encoding bit sequence; wherein the error bits in the decoding error pattern correspond one-to-one to the error bits in the encoding error pattern; detecting the sequence number yi of the minimum value and the sequence number yj of the second minimum value in the encoding bit sequence according to the encoding error pattern; performing a cyclic redundancy check on the yi-th bit of the decoding bit sequence and the decoding error pattern after performing modulo-2 addition error correction; if the cyclic redundancy check passes, terminating the cascade error correction coding; otherwise, performing a modulo-2 addition error correction on the yj-th bit of the decoding bit sequence and the decoding error pattern.

[0012] Optionally, after performing modulo-2 addition correction on the yj-th bit of the decoded bit sequence and the error pattern, a cyclic redundancy check is performed. If the cyclic redundancy check fails, error correction is performed on the next decoded bit sequence until error correction is completed on all the decoded bit sequences.

[0013] Optionally, detecting the minimum value subscript yi and the second minimum value subscript yj in the coding bit sequence according to the coding error pattern includes: performing a sliding multiplication of the coding error pattern and the coding bit sequence and summing them to obtain a convolution sequence; calculating the sequence number of the minimum value and the sequence number of the second minimum value of the convolution sequence; and using the sequence number of the minimum value and the sequence number of the second minimum value of the convolution sequence as the sequence number yi and the sequence number yj of the minimum value of the coding bit sequence, respectively.

[0014] Optionally, after performing convolutional coding on the decoded bit sequence to obtain a coded bit sequence, the method further includes: mapping the coded bit sequence to obtain a mapping sequence; and performing a point multiplication on the soft decision result and the mapping sequence to obtain the preprocessed coded bit sequence.

[0015] Optionally, mapping the coded bit sequence to obtain a mapping sequence includes: mapping "1" in the coded bit sequence to "+1" and "0" to "-1" to obtain the mapping sequence consisting of "+1" and "-1".

[0016] Optionally, the decoding error pattern of the decoding bit sequence is obtained through a Viterbi decoder; and the encoding error pattern of the encoding bit sequence is obtained through a convolutional encoder.

[0017] Optionally, in performing Viterbi decoding on the soft decision result of the received information to obtain a decoded bit sequence, soft decision Viterbi decoding is adopted and the decoding depth is 16.

[0018] A terminal device comprises: a decoding module for performing Viterbi decoding on a soft decision result of received information to obtain a decoded bit sequence; a check module for performing a cyclic redundancy check on the decoded bit sequence or the decoded bit sequence after error correction; an encoding module for performing convolutional coding on the decoded bit sequence to obtain a coded bit sequence; and an error correction module for obtaining a high-frequency error pattern and performing error correction on the decoded bit sequence based on the high-frequency error pattern.

[0019] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements any of the steps of the above-mentioned cascade error correction coding method.

[0020] Implementing one of the above technical solutions of the present invention has the following advantages or beneficial effects:

[0021] The cascade error correction coding method provided by the present invention significantly reduces the system's requirements for the signal-to-noise ratio without increasing coding redundancy by utilizing the classification of high-frequency error patterns after Viterbi decoding and combining it with dynamic verification of cyclic redundancy check. It is particularly suitable for communication scenarios with small data volumes and can ensure efficient and reliable information transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive work. In the drawings:

[0023] Figure 1 is a flow chart of a cascade error correction coding method according to an embodiment of the present invention;

[0024] Figure 2 This is a diagram showing the percentage of decoding error patterns in the first embodiment of the present invention;

[0025] Figure 3 This is a flowchart of step S3 of the cascade error correction coding method according to an embodiment of the present invention;

[0026] Figure 4 1 is a diagram showing the simulation results of the bit error rate (BER) of the first embodiment of the present invention;

[0027] Figure 5 1 is a diagram showing simulation results of the packet error rate PER according to the first embodiment of the present invention;

[0028] Figure 6 This is a structural block diagram of a terminal device according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to make the objects, technical solutions and advantages of the present invention clearer, the various exemplary embodiments to be described below will refer to the corresponding drawings, which constitute a part of the exemplary embodiments, in which various exemplary embodiments that may be used to implement the present invention are described. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation methods described in the following exemplary embodiments do not represent all implementation methods consistent with the present disclosure. It should be understood that they are only examples of processes, methods and devices that are consistent with some aspects of the present disclosure as detailed in the appended claims, and other embodiments may also be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and essence of the present invention.

[0030] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", etc. indicate the orientation or position relationship based on the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the elements referred to must have a specific orientation, be constructed and operate in a specific orientation. The terms "first", "second", etc. are only used for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The term "plurality" means two or more. The terms "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, an integral connection, a mechanical connection, an electrical connection, a communication connection, a direct connection, an indirect connection through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more related listed items. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0031] In order to illustrate the technical solution of the present invention, a specific embodiment is provided below, in which only the parts related to the embodiment of the present invention are shown.

[0032] Example 1:

[0033] like Figure 1 As shown, the present invention provides a cascade error correction coding method, comprising the following steps: S1, performing Viterbi decoding on the soft decision result of the received information to obtain a decoded bit sequence; S2, performing a cyclic redundancy check on the decoded bit sequence; if the decoded bit sequence fails the cyclic redundancy check, performing convolution coding on the decoded bit sequence to obtain a coded bit sequence; S3, obtaining a high-frequency error pattern, and correcting the decoded bit sequence according to the high-frequency error pattern; wherein the high-frequency error pattern includes a decoding error pattern of the decoding bit sequence and an encoding error pattern of the encoding bit sequence; S4, performing a cyclic redundancy check on the decoded bit sequence after error correction; if the decoded bit sequence after error correction and / or the decoded bit sequence pass the cyclic redundancy check, the cascade error correction coding is terminated.

[0034] The cascade error correction coding method provided in this embodiment significantly reduces the system's requirements for the signal-to-noise ratio without increasing coding redundancy by utilizing the classification of high-frequency error patterns after Viterbi decoding and combining it with dynamic verification of a cyclic redundancy check. This method is particularly suitable for communication scenarios with smaller data volumes and can ensure efficient and reliable information transmission.

[0035] Next, combine Figures 1 to 5 , the specific implementation steps of the cascade error correction coding method provided by this embodiment are described in detail:

[0036] First, step S1 is executed to perform Viterbi decoding on the soft decision results of the received information to obtain a decoded bit sequence. Soft decision means that the demodulator outputs not only the most likely bit value corresponding to each symbol, but also the confidence information of each possible bit value. This output with confidence information is the soft decision result of the received information. Compared with hard decision (which only outputs the most likely bit value), soft decision retains more signal information, which helps improve error correction performance in the subsequent decoding process.

[0037] Viterbi decoding is a maximum likelihood decoding algorithm commonly used for decoding convolutional codes. Its basic principle is to find a path in a trellis graph that minimizes a metric (typically Hamming distance or Euclidean distance) with the received soft decision result. During the decoding process, the Viterbi algorithm continuously extends, compares, and backtracks paths, gradually selecting the most likely path by calculating and comparing the metrics of different paths. After Viterbi decoding, the optimal path found in the trellis graph corresponds to the originally transmitted bit sequence. This sequence is the decoded bit sequence, which represents the recovery of the original information from the sender.

[0038] Suppose the transmitter sends a string of binary information (i.e., the received information). After transmission through the channel, the receiver receives a signal contaminated by noise. The receiver first makes a soft decision, obtaining a confidence score for each symbol being "0" or "1." The Viterbi decoding algorithm then searches for the optimal path within the trellis graph based on these confidence scores. The binary sequence ultimately extracted from this optimal path is the decoded bit sequence.

[0039] Preferably, in this step, soft-decision Viterbi decoding is used to decode the soft-decision results of the received information, with a decoding depth of 16. Soft-decision Viterbi decoding can more accurately reflect the likelihood of the transmitted signal, thereby effectively reducing the bit error rate and improving communication reliability. The decoding depth is a key parameter in Viterbi decoding. The decoding depth should not be too deep or too shallow. Setting the decoding depth to 16 can ensure decoding performance to a certain extent without increasing computational complexity and delay.

[0040] Then, step S2 is executed to perform a cyclic redundancy check on the decoded bit sequence. If the decoded bit sequence fails the cyclic redundancy check, the decoded bit sequence is convolutionally encoded to obtain a coded bit sequence. If the cyclic redundancy check passes, the cascade error correction coding process ends. A cyclic redundancy check (CRC) is an error-checking code that detects errors during data transmission. In this embodiment, a cyclic redundancy check is used to detect whether there are any error bits in the decoded bit sequence to ensure data integrity and reliability. If there are any error bits, convolution encoding is performed to prepare for subsequent error correction. If the cyclic redundancy check passes, it indicates that there are no more error bits in the decoded bit sequence.

[0041] As an optional implementation, after performing convolutional coding on the decoded bit sequence to obtain the coded bit sequence, the method further includes: mapping the coded bit sequence to obtain a mapping sequence; performing point multiplication on the soft decision result and the mapping sequence to obtain a preprocessed coded bit sequence. In subsequent steps, the preprocessed coded bit sequence is used. Specifically, mapping the coded bit sequence to obtain a mapping sequence includes: mapping "1" in the coded bit sequence to "+1" and "0" to "-1" to obtain a mapping sequence consisting of "+1" and "-1". In signal processing, using "+1" and "-1" for calculations is more convenient than using "0" and "1" because they can directly participate in multiplication and addition operations, avoiding additional logical conversions to improve signal processing efficiency.

[0042] Next, step S3 is executed to obtain a high-frequency error pattern, and the decoded bit sequence is corrected based on the high-frequency error pattern. During information transmission or storage, data may contain errors. An error pattern refers to a specific pattern of errors in the data. High-frequency error patterns are those error patterns that occur frequently. Statistical analysis of large amounts of decoded data can be performed to identify error patterns that occur frequently. After obtaining the high-frequency error pattern, it is applied to the decoded bit sequence currently being processed. By comparing the decoded bit sequence with the known high-frequency error pattern, possible error locations are identified. These errors are then corrected according to pre-set error correction rules, thereby improving decoding accuracy.

[0043] If there are still error bits in the received information after Viterbi decoding, these error bits contain some high-frequency error patterns. By identifying these possible error patterns and then using CRC checksums, cascaded error correction can be achieved. The following simulation analysis is performed using an AWGN channel (abbreviated as Additive White Gaussian Noise, an idealized communication channel model) with BPSK modulation, channel signal-to-noise ratios set to [0, 0.5, 1.0, 1.5, 2.0, 2.5] dB, (15, 17) convolutional code, soft-decision Viterbi decoding, a decoding depth of 16, and a 100-byte data packet:

[0044] First, the number of error bits after Viterbi decoding is analyzed: when the signal-to-noise ratio (SNR) is [0, 0.5, 1.0, 1.5, 2.0, 2.5] dB, the number of data packets with 1 to 4 error bits after Viterbi decoding, P14, accounts for [64.37%, 79.10%, 87.47%, 94.70%, 97.47%, 100%] of the total number of data packets containing error bits, P14 / Pall, respectively. Among them, the proportion is 64.37% when SNR=0dB, 79.10% when SNR=0.5dB, 87.47% when SNR=1.0dB, 94.70% when SNR=1.5dB, 97.47% when SNR=2.0dB, and 100% when SNR=2.5dB. Therefore, in most cases, the number of error bits in a data packet after Viterbi decoding is within 4. Correcting the data packets with 1 to 4 error bits can significantly improve system performance.

[0045] Then, the decoding error pattern of the decoded bit sequence is obtained through the Viterbi decoder, and the decoding error pattern after Viterbi decoding is analyzed:

[0046] In all decoding error patterns with 1 to 4 error bits in the decoded bit sequence, such as Figure 2 As shown in FIG, the decoding error pattern with 1 error bit accounts for 16.61%.

[0047] The proportions of decoding error patterns with two error bits are [37.46%, 2.83%, 0.36%, 0.80%] respectively. Among them, the decoding error pattern with

[11] accounts for 37.46%; the decoding error pattern with

[101] accounts for 2.83%; the decoding error pattern with

[1001] accounts for 0.36%; and the decoding error pattern with [10…01] accounts for 0.80%. The "0…0" in [10…01] indicates that there are more than or equal to 3 "0". Taking the decoding error pattern

[1001] as an example, the two "1"s indicate that there are two error bits, and the "00" in the middle indicates that there are 2 bits between the first and second error bits.

[0048] The proportions of decoding error patterns with 3 error bits are [9.87%, 9.67%, 0.66%, 0.13%, 0.80%, 2.61%, 0.43%, 0.52%] respectively, among which the proportion of decoding error pattern of

[111] is 9.87%; the proportion of decoding error pattern of

[1101] is 9.67%; the proportion of decoding error pattern of [110…01] and [10…011] is 2.61%; the proportion of decoding error pattern of [11 The "0…0" in [0…01] and [10…011] indicates that there are three or more "0" bits. The decoding error pattern of

[11001] accounts for 0.66%; the decoding error pattern of

[1011] accounts for 0.13%; the decoding error pattern of

[10011] accounts for 0.80%; the decoding error pattern of

[10101] accounts for 0.43%; and the proportion of other decoding error patterns with three error bits is 0.52%. Taking the decoding error pattern

[10011] as an example, the three "1" bits indicate three error bits. The middle "00" indicates that the first and second error bits are separated by two bits, and the following "11" indicates that the second and third error bits are consecutive.

[0049] The proportions of decoding error patterns with 4 error bits are [2.77%, 0.11%, 2.54%, 2.55%, 2.80%, 0.23%, 0.63%, 2.63%, 0.21%, 0.74%, 2.03%] respectively, among which the decoding error pattern of

[1111] accounts for 2.77%; the decoding error pattern of [110011] accounts for 2.54%; the decoding error pattern of [110…011] accounts for 2.55%; the "0…0" in [110…011] means that there are more than or equal to 3 "0"s; the decoding error pattern of

[11101] accounts for 2.80%; the decoding error pattern of [110101] accounts for 2.63%; and 2.03% The proportion of other decoding error patterns with 4 error bits; the decoding error pattern of

[11011] accounts for 0.11%; the decoding error pattern of [111001] accounts for 0.23%; the decoding error patterns of [1110…01] and [10…0111] account for 0.63%, and the "0…0" in [1110…01] and [10…0111] means that there are more than or equal to 3 "0"s; the decoding error pattern of [1101001] accounts for 0.21%; the decoding error patterns of [11010…01] and [10…01101] account for 0.74%, and the "0…0" in [11010…01] and [10…01101] means that there are more than or equal to 3 "0"s. Taking the decoding error pattern [1101001] as an example, the four "1"s indicate four error bits. The first "11" indicates that the first and second error bits are consecutive. The middle "0" indicates that there is a one-bit gap between the second and third error bits. The middle "00" indicates that there are two bits between the third and fourth error bits.

[0050] According to the above statistical results, there are 11 high-frequency error patterns that can be used for cascade error correction and account for more than 2%, as shown in Table 1:

[0051]

[0052] Table 1 High-frequency error patterns for cascaded error correction

[0053] Then, these error bits need to be corrected. The decoded bit sequence is convolutionally encoded, and the encoding error pattern of the encoded bit sequence is obtained through the convolutional encoder. If there is a single error bit in the decoded bit sequence, the encoder will output multiple error bits from the time the error bit enters the convolutional encoder until it exits the convolutional encoder, with a fixed encoding error pattern. Taking the (15, 17) convolutional code as an example, the decoding error pattern EV after Viterbi decoding corresponds to the encoding error pattern EO output by the convolutional encoder. The corresponding relationship is shown in Table 2:

[0054]

[0055] Table 2 Correspondence between decoding error pattern EV and encoding error pattern EO

[0056] According to the above correspondence, the decoding error pattern EV and its starting position EV_i can be determined by detecting the encoding error pattern EO. Then, starting from the EV_i bit of the decoding bit sequence, the decoding bit sequence and the decoding error pattern EV are subjected to a Modulo 2 addition (also known as an exclusive OR operation (XOR), which is a binary operation), and then a CRC check is performed. If the check passes, the error correction is successful. Figure 3 As shown, specifically, step S3 includes:

[0057] S31. Obtain a decoding error pattern for a decoding bit sequence and an encoding error pattern for an encoding bit sequence; wherein the error bits in the decoding error pattern correspond one-to-one to the error bits in the encoding error pattern. S32. Detect the sequence number yi of the minimum value and the sequence number yj of the next minimum value in the encoding bit sequence based on the encoding error pattern; yi and yj are the possible locations of the error bits. S33. Perform modulo-2 error correction on the yi-th bit of the decoding bit sequence and the decoding error pattern, and then perform a cyclic redundancy check. If the cyclic redundancy check passes, the cascaded error correction coding is terminated. Otherwise, perform modulo-2 error correction on the yj-th bit of the decoding bit sequence and the decoding error pattern. If the check passes, error correction has been completed for all decoding bit sequences.

[0058] If the cyclic and redundancy check fails, the next decoded bit sequence is corrected until all decoded bit sequences are corrected. For example, to correct a 1-bit error: first detect the position of the error bit in the decoding error pattern EV=[1], that is, the minimum value sequence number yi and the second minimum value sequence number yj in the corresponding coding bit sequence; then correct the 1-bit error: first perform a modulo-2 addition on the yi-th bit of the decoding bit sequence and the decoding error pattern EV=[1], and perform a CRC check. If the check passes, the error correction ends; if the check fails, the yj-th bit of the decoding bit sequence is added to the decoding error pattern EV=[1] and a CRC check is performed. If the check passes, the error correction ends; if the check fails, the next decoded bit sequence is corrected.

[0059] Assume that the next decoded bit sequence is to correct a 2-bit error. Similarly, to correct a 2-bit error, we first detect the position of the error bit in the decoding error pattern EV=

[11] , use modulo-2 addition to correct the yi-th bit, and perform a CRC check. If the check passes, the error correction ends. Otherwise, we correct the yj-th bit and perform a CRC check. If the check passes, the error correction ends. Otherwise, we use the same method to correct the next decoded bit sequence until all decoded bit sequences with 1 to 4 error bits are corrected.

[0060] Furthermore, step S32 includes: performing a sliding multiplication of the coding error pattern and the coding bit sequence and summing the results to obtain a convolution sequence; calculating the sequence number of the minimum value and the sequence number of the second minimum value of the convolution sequence; and using the sequence number of the minimum value and the sequence number of the second minimum value of the convolution sequence as the sequence number yi and the sequence number yj of the minimum value and the second minimum value of the coding bit sequence, respectively. By processing and analyzing the convolution coding bit sequence, the position of the error bit in the decoded bit sequence is found, so that the error bit can be corrected.

[0061] Finally, step S4 is executed to perform a cyclic redundancy check on the decoded bit sequence after error correction; if the decoded bit sequence after error correction and / or the decoded bit sequence passes the cyclic redundancy check, the cascade error correction coding is terminated. In step S3, most of the decoded bit sequences with error bits have been corrected, and this error correction method does not increase coding redundancy, and can significantly improve performance while maintaining the information transmission rate unchanged. Since in step S3, all decoded bit sequences with 1 to 4 error bits have been corrected, and the proportion of decoded bit sequences with 1 to 4 error bits is relatively large, error correction of decoded bit sequences with 1 to 4 error bits can significantly improve communication quality. Therefore, if the decoded bit sequence fails to pass the check after error correction, it means that only individual error bits exist and will not affect system performance.

[0062] This embodiment uses (15, 17) convolutional code and CRC16 (16-bit cyclic redundancy check) cascade error correction. Under the AWGN channel, BPSK modulation, soft-decision Viterbi decoding, and decoding depth of 16 are adopted to simulate data packets of 50 bytes, 100 bytes, and 200 bytes respectively. The bit error rate BER and packet error rate PER are statistically compared with those using only (15, 17) convolutional code error correction. The results are as follows: Figure 4 and Figure 5As shown in the figure, it can be seen that compared with using only the (15, 17) convolutional code for error correction, the convolutional code + CRC cascade error correction has a lower requirement for the signal-to-noise ratio (SNR): when the bit error rate BER = 1.0e-5, the SNR is about 0.7dB lower; when the packet error rate BER = 10%, the SNR is about 0.6dB lower; when the packet error rate PER = 1%, the SNR is about 0.8dB lower.

[0063] Example 2:

[0064] like Figure 6 As shown, the present invention also provides a terminal device, including: a decoding module 1, used to perform Viterbi decoding on the soft decision result of the received information to obtain a decoded bit sequence; a check module 2, used to perform cyclic redundancy check on the decoded bit sequence or the decoded bit sequence after error correction; an encoding module 3, used to perform convolution code encoding on the decoded bit sequence to obtain a coded bit sequence; an error correction module 4, used to obtain a high-frequency error pattern and correct the decoded bit sequence according to the high-frequency error pattern.

[0065] The terminal device provided in this embodiment adopts the cascaded error correction decoding method provided in Example 1 for decoding, which significantly reduces the system's requirements for the signal-to-noise ratio without increasing the coding redundancy. It is particularly suitable for communication scenarios with small data volumes and can ensure efficient and reliable transmission of information.

[0066] Example 3:

[0067] Based on the same inventive concept, the third embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the steps of any method of the cascade error correction coding method described in the first embodiment above are implemented.

[0068] The foregoing is merely a preferred embodiment of the present invention. Those skilled in the art will appreciate that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. Furthermore, under the guidance of the present invention, these features and embodiments may be modified to suit specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are intended to be within the scope of the present invention.

Claims

1. A cascade error correction coding method, characterized in that: The following steps are involved: Perform Viterbi decoding on the soft decision result of the received information to obtain a decoded bit sequence; Performing a cyclic redundancy check on the decoded bit sequence; if the decoded bit sequence fails the cyclic redundancy check, performing convolutional coding on the decoded bit sequence to obtain a coded bit sequence; Acquire a high-frequency error pattern, and perform error correction on the decoded bit sequence according to the high-frequency error pattern; wherein the high-frequency error pattern includes a decoding error pattern of the decoded bit sequence and an encoding error pattern of the encoding bit sequence; performing a cyclic redundancy check on the decoded bit sequence after error correction; If the decoded bit sequence after error correction and / or the decoded bit sequence passes the cyclic redundancy check, then terminating the cascade error correction coding; The obtaining of a high-frequency error pattern of the decoded bit sequence and performing error correction on the decoded bit sequence according to the high-frequency error pattern includes: Obtaining a decoding error pattern of the decoding bit sequence and an encoding error pattern of the encoding bit sequence; wherein error bits in the decoding error pattern correspond one-to-one to error bits in the encoding error pattern; Detecting the minimum value sequence number yi and the second minimum value sequence number yj in the coded bit sequence according to the coding error pattern; After performing modulo-2 addition error correction on the yi-th bit of the decoded bit sequence and the decoding error pattern, a cyclic redundancy check is performed; if the cyclic redundancy check passes, the cascade error correction coding is terminated; otherwise, performing modulo-2 addition error correction on the yj-th bit of the decoded bit sequence and the decoding error pattern.

2. A cascade error correction coding method according to claim 1, characterized in that: After performing modulo-2 addition error correction on the yj-th bit of the decoded bit sequence and the error pattern, a cyclic redundancy check is performed. If the cyclic redundancy check fails, error correction is performed on the next decoded bit sequence until error correction is completed on all decoded bit sequences.

3. The cascade error correction coding method according to claim 1, wherein: The detecting, according to the coding error pattern, a minimum value subscript yi and a second minimum value subscript yj in the coding bit sequence includes: Performing sliding multiplication on the coding error pattern and the coding bit sequence and summing the results to obtain a convolution sequence; Calculating the sequence number of the minimum value and the sequence number of the second minimum value of the convolution sequence; The sequence number of the minimum value and the sequence number of the second minimum value of the convolution sequence are respectively used as the sequence number yi of the minimum value and the sequence number yj of the second minimum value of the coding bit sequence.

4. The cascade error correction coding method according to claim 1, wherein: After performing convolutional coding on the decoded bit sequence to obtain a coded bit sequence, the method further includes: Mapping the coded bit sequence to obtain a mapping sequence; Performing a point multiplication on the soft decision result and the mapping sequence to obtain the preprocessed coded bit sequence.

5. The cascade error correction coding method according to claim 4, wherein: Mapping the coded bit sequence to obtain a mapping sequence includes: Map "1" in the coded bit sequence to "+1" and map "0" to "-1" to obtain the mapping sequence consisting of "+1" and "-1".

6. The cascade error correction coding method according to claim 1, wherein: The decoding error pattern of the decoding bit sequence is obtained through a Viterbi decoder; and the encoding error pattern of the encoding bit sequence is obtained through a convolutional encoder.

7. The cascade error correction coding method according to claim 1, wherein: In performing Viterbi decoding on the soft decision result of the received information to obtain a decoded bit sequence, soft decision Viterbi decoding is adopted, and the decoding depth is 16.

8. A terminal device, characterized in that: include: A decoding module, configured to perform Viterbi decoding on a soft decision result of received information to obtain a decoded bit sequence; a check module, configured to perform a cyclic redundancy check on the decoded bit sequence or the decoded bit sequence after error correction; an encoding module, configured to perform convolutional coding on the decoded bit sequence to obtain an encoded bit sequence; an error correction module, configured to obtain a high-frequency error pattern and perform error correction on the decoded bit sequence according to the high-frequency error pattern; The error correction module is further configured to obtain a decoding error pattern of the decoding bit sequence and an encoding error pattern of the encoding bit sequence; wherein the error bits in the decoding error pattern correspond one-to-one to the error bits in the encoding error pattern; detect the sequence number yi of the minimum value and the sequence number yj of the second minimum value in the encoding bit sequence based on the encoding error pattern; perform modulo-2 addition error correction on the yi-th bit of the decoding bit sequence and the decoding error pattern, and then perform a cyclic redundancy check; if the cyclic redundancy check passes, the cascade error correction coding is terminated; otherwise, perform modulo-2 addition error correction on the yj-th bit of the decoding bit sequence and the decoding error pattern.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the cascade error correction coding method according to any one of claims 1 to 7 are implemented.

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