Data packet software processing time delay monitoring method, electronic equipment and storage medium

Abstract

The invention relates to the technical field of chip design, in particular to a data packet software processing time delay monitoring method, electronic equipment and a storage medium. Wherein the server is connected with the processor through a high-speed interface; the expansion card is interconnected with the server through a high-speed interface and is interconnected with the processor through an output interface; the server sends a data packet to the processor; when the expansion card monitors a data packet sent by the server, a control signal is sent to the processor; when the processor receives the control signal, recording the time t1 when the control signal is received; when the processor receives the data packet, recording the time t2 when the data packet is received; and obtaining the software processing time delay of the data packet according to the t1 and the t2. T1 and t2 are timestamps of the processor, so that the problem that the time when the server sends the data packet and the time when the processor receives the data packet are not synchronous is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a method for monitoring the software processing delay of a data packet, an electronic device and a storage medium. Background Art

[0002] During the data transmission process, when the server sends a data packet to the processor, the data packet needs to go through multiple processing stages before it can be finally obtained by the processor. First, the data packet needs to be transmitted through the physical connection between the server and the processor, and this process will produce a certain time delay. Secondly, after the data packet reaches the processor, it needs to be processed by the software inside the processor, and this step will also introduce additional time delay. Therefore, the time it takes for the processor to actually obtain the data packet includes the time delay of the physical connection and the time delay of the software processing inside the processor, resulting in a longer overall time delay.

[0003] In addition, a data packet usually carries a timestamp when it is sent to record the time when the data packet was sent. However, due to the existence of the above-mentioned time delay, there is a significant difference between the timestamp and the time when the processor actually obtains the data packet. This time difference may make it difficult for the system to perform effective synchronization processing, thereby affecting the accuracy of synchronization. Especially in application scenarios with strict requirements on time accuracy, this time delay and reduced synchronization accuracy may have adverse effects. Summary of the invention

[0004] In view of the above technical problems, the technical solution adopted by the present invention is: a method for monitoring the delay of data packet software processing, the method comprising: S100, obtaining a server, a processor and an expansion card; wherein the server and the processor are interconnected via a high-speed interface; the expansion card is interconnected with the server via the high-speed interface and is interconnected with the processor via an output interface.

[0005] S200, the server sends a data packet to the processor.

[0006] S300, when the expansion card detects that the server sends the data packet, the expansion card sends a control signal to the processor.

[0007] S400: When the processor receives the control signal, the processor internally records the current timestamp t1.

[0008] S500, when the processor receives the data packet, the processor records a timestamp t2 of when the processor receives the data packet; and obtains a software processing delay of the data packet according to t1 and t2.

[0009] In addition, the present invention also provides a non-transitory computer-readable storage medium, in which at least one instruction or at least one program is stored, and the at least one instruction or the at least one program is loaded and executed by a processor to implement the above method.

[0010] In addition, the present invention also provides an electronic device, including a processor and the above-mentioned non-transitory computer-readable storage medium.

[0011] The present invention has at least the following beneficial effects: The present invention provides a method for monitoring the software processing delay of a data packet, an electronic device and a storage medium. When an expansion card detects that a server sends a data packet, a control signal is sent to a processor, so that the processor records the time t1 when the control signal is received; the processor records the time t2 when the data packet is received; and the software processing delay of the data packet is obtained according to t1 and t2, wherein t1 and t2 are both timestamps of the processor itself, thereby solving the problem of the time when the server sends the data packet and the time when the processor receives the data packet are not synchronized. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A flow chart of a method for monitoring data packet software processing delay provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0015] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meanings as commonly understood by those skilled in the art.

[0016] See also Figure 1 , which shows a flow chart of a method for monitoring data packet software processing delay, the method comprising: S100, obtaining a server, a processor and an expansion card; wherein the server and the processor are interconnected via a high-speed interface; the expansion card is interconnected with the server via the high-speed interface and is interconnected with the processor via an output interface.

[0017] In one embodiment, the processor is a graphics processing unit (GPU), a tensor processing unit (TPU) or a neural network processing unit (NPU). Other types of processors also fall within the protection scope of the present invention.

[0018] In one embodiment, the expansion card is a general purpose input / output (GPIO) port. Other expansion cards that can be used to monitor data packets sent by the microcontroller and send level signals to the processor fall within the protection scope of the present invention.

[0019] In one embodiment, the high-speed interface is a high-speed bus interface (Peripheral Component Interconnect Express, PCIE), a CXL interface (Compute Express Link) or an NVLink interface, and other high-speed interfaces for interconnection fall within the protection scope of the present invention.

[0020] In one embodiment, the high-speed interface between the server and the processor and the high-speed interface between the expansion card and the server can be the same type of high-speed interface or different types. When the two are the same type of high-speed interface, the monitored delay is more accurate than when the two are different types of high-speed interfaces.

[0021] S200, the server sends a data packet to the processor.

[0022] S300, when the expansion card detects that the server sends the data packet, the expansion card sends a control signal to the processor.

[0023] The control signal is a level signal. In one embodiment, the effective edge of the level signal is a rising edge or a falling edge. Other types of effective edges also fall within the protection scope of the present invention.

[0024] S400: When the processor receives the control signal, the processor internally records the current timestamp t1.

[0025] Among them, the processor receives a control signal, and t1 is the time when the control signal triggers the processor to record according to the processor's own time base. After the server sends a data packet, it is directly captured by the hardware expansion card and sends a control signal to the processor. The whole process is completed by hardware. The hardware delay is very small compared to the software delay and is within an acceptable range. Among them, software delay refers to the additional time delay introduced by software-level factors such as the processing of the operating system and network protocol stack, the preparation and scheduling of applications, the interaction of databases, and security processing before the processor receives the data packet. The software delay is larger than the hardware delay. For example, the hardware delay may be in nanoseconds, while the software delay may be in milliseconds or microseconds.

[0026] In one embodiment, S400 also includes that when the processor receives the control signal, the processor performs a preprocessing operation for receiving the data packet. In one embodiment, the preprocessing operation includes one or more of the following operations: time synchronization through t1 to ensure that the communication between the processor and the server is consistent in time; pre-allocating necessary resources, such as buffers and processing units, etc., to improve processing efficiency; dynamically adjusting resource allocation to achieve better load balancing; pre-configuring parallel processing data paths so that data packets can be processed immediately after arrival to reduce waiting time. Other types of preprocessing operations performed after t1 and before receiving the data packet fall within the scope of protection of the present invention.

[0027] S500, when the processor receives the data packet, the processor records a timestamp t2 of when the processor receives the data packet; and obtains a software processing delay of the data packet according to t1 and t2.

[0028] In one embodiment, the software processing delay Δt of the data packet satisfies: Δt=t2-t1. In another embodiment, Δt may also satisfy: Δt=t2-(t1+tt1), where tt1 is a preset hardware delay. Other solutions for obtaining the software processing delay of the data packet based on t1 and t2 fall within the protection scope of the present invention.

[0029] In one embodiment, the processor records the timestamp internally by using one or more hardware counters to track time; when the processor receives a control signal, it immediately reads the value of the counter and stores it in a register or memory location. Other types of timestamp recording methods also fall within the scope of protection of the present invention.

[0030] The reason why the software processing delay is calculated by t1, rather than by the timestamp carried in the data packet, is that the timestamp carried in the data packet is the time point when the server sends the data packet, which is based on the internal time of the server. It is impossible to achieve very accurate time synchronization between the server and the processor. Once there is a time difference between the two, the calculated software delay will be inaccurate. The hardware delay of t1 is very short. If the hardware delay is ignored, t1 can be approximately considered as the time point when the server sends the data packet. The timestamp t1 is recorded by the processor according to its own time base, and t2 is also recorded according to the processor's own time base. The bases of the two are the same, which solves the problem of the time when the server sends the data packet and the processor receives the data packet is not synchronized.

[0031] In one implementation, S100 further includes a network analyzer, which is connected between the server and the processor and is used to obtain data packets transmitted between the server and the processor.

[0032] Among them, a network analyzer is also called a protocol analyzer or a packet capturer, which is used to capture and analyze network data packets.

[0033] In one embodiment, the network analyzer and the server are interconnected via a high-speed interface, wherein the definition of the high-speed interface between the network analyzer and the server is the same as that of the high-speed interface between the server and the processor, and will not be repeated herein.

[0034] In one implementation, the network analyzer and the processor are interconnected via a high-speed interface, wherein the definition of the high-speed interface between the network analyzer and the processor is the same as that of the high-speed interface between the server and the processor, and will not be repeated herein.

[0035] It should be noted that the high-speed interfaces used to connect different components can be high-speed interfaces of the same type or high-speed interfaces of different types, and can be adjusted according to specific application scenarios.

[0036] In one embodiment, S100 further includes: the network analyzer is interconnected with the expansion card via a high-speed interface. S300 further includes: when the expansion card detects the data packet sent by the server, it also sends the control signal to the network analyzer. That is, the expansion card sends the control signal to the processor and the network analyzer at the same time, and triggers the processor and the network analyzer to record the corresponding timestamp and perform preprocessing operations for the received data packet.

[0037] In one embodiment, the network analyzer is also used to: obtain the timestamp t3 of the data packet, track the target control signal that triggers the network analyzer to obtain the data packet through the t3, obtain the data packet sent by the server within the error range through the target control signal, and the target function called before the server sends the data packet, and obtain the alignment information between the target control signal, t3, the data packet and the target function. That is, in this way, the data packet currently received by the processor and the target function that generates the data packet can be clearly known, and the mapping relationship between the data packet and the target function can be obtained, which is convenient for subsequent analysis.

[0038] In summary, the present invention provides a method for monitoring the software processing delay of a data packet. When the expansion card detects that the server has sent a data packet, the method sends a control signal to the processor, so that the processor records the time t1 when the control signal is received; the processor records the time t2 when the data packet is received; and the software processing delay of the data packet is obtained according to t1 and t2, wherein t1 and t2 are both timestamps of the processor itself, thereby solving the problem of the time when the server sends the data packet and the time when the processor receives the data packet are not synchronized.

[0039] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in a method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0040] An embodiment of the present invention further provides an electronic device, comprising a processor and the aforementioned non-transitory computer-readable storage medium.

[0041] An embodiment of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0042] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0043] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A method for monitoring data packet software processing delay, characterized in that: The method comprises: S100, obtaining a server, a processor and an expansion card; wherein the server and the processor are interconnected via a high-speed interface; the expansion card is interconnected with the server via the high-speed interface and is interconnected with the processor via an output interface; S200, the server sends a data packet to the processor; S300, when the expansion card detects that the server sends the data packet, the expansion card sends a control signal to the processor; S400, when the processor receives the control signal, the processor records the current timestamp t1 internally; S500, when the processor receives the data packet, the processor records a timestamp t2 of when the processor receives the data packet; and obtains a software processing delay of the data packet according to t1 and t2.

2. The method according to claim 1, characterized in that S100 also includes a network analyzer, which is connected between the server and the processor and is used to obtain data packets transmitted between the server and the processor.

3. The method according to claim 2, characterized in that The S100 also includes: The network analyzer is interconnected with the expansion card via a high-speed interface; S300 also includes: when the expansion card detects the data packet sent by the server, the expansion card also sends the control signal to the network analyzer at the same time.

4. The method according to claim 3, characterized in that The network analyzer is also used to: obtain the timestamp t3 of the data packet, track and trigger the network analyzer to obtain the target control signal of the data packet through the t3, obtain the data packet sent by the server within the error range through the target control signal, and the target function called before the server sends the data packet, and obtain the alignment information among the target control signal, t3, the data packet and the target function.

5. The method according to claim 1, characterized in that S400 also includes: when the processor receives the control signal, the processor performs a preprocessing operation for receiving the data packet.

6. The method according to claim 5, characterized in that The preprocessing operation includes one or more of the following operations: Time synchronization is performed through t1; Pre-allocate buffers and processing units; Dynamically adjust resource allocation; Preconfigure the data path for parallel processing.

7. The method according to claim 1, characterized in that The software processing delay △t of the data packet satisfies: △t=t2-t1.

8. The method according to claim 1, characterized in that The processor records timestamps internally by using one or more hardware counters to track time; when the processor receives a control signal, it immediately reads the value of the counter and stores it in a register or memory location.

9. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by the processor to implement the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 9.

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