Ethernet data transmission method and system based on single-phase CMC network transformer

Abstract

The present invention discloses an Ethernet data transmission method based on a single-phase CMC network transformer, which aims to improve signal integrity and reduce electromagnetic interference. This method receives the feedback differential signal from the RJ45 connector through the MAC layer main control module, and restores it to a digital signal after decoding by the PHY chip; after the MAC layer verifies the data integrity, if data needs to be sent, the data packet is transmitted to the PHY chip, and the parallel data is serialized and physically encoded. The coil current of the CMC in the network transformer is monitored in real time, the common mode impedance and common mode voltage are calculated, and the differential signal voltage and its electromagnetic interference PSD are further obtained. If the PSD is lower than the set threshold, the signal is output; otherwise, the gradient descent optimization method is used to adjust the signal voltage to ensure compliance with the standard. The present invention can effectively reduce common mode noise, improve signal stability, optimize Ethernet communication quality, and is suitable for high-speed, low bit error rate network equipment.

Description

Technical Field

[0001] The present invention belongs to the technical field of Ethernet network data exchange communication, and in particular relates to an Ethernet data transmission method and system based on a single-phase CMC network transformer. Background Art

[0002] With the rapid development of information technology and the internet, Ethernet has become one of the most widely used wired communication technologies worldwide, widely used in fields such as computer networks, industrial automation, smart homes, data centers, and embedded devices. For example, in the prior art, the Chinese invention patent application with publication number CN116319605A discloses an Ethernet data exchange module, circuit board, and electronic device. The module comprises a first housing, a first end of which is provided with at least two network cable connection ports. The first housing contains a metal spring, a network transformer, a PHY chip, and an embedded microcontroller. Each network transformer is connected to a corresponding PHY chip, and each PHY chip is connected to the first end of the embedded microcontroller. The module can receive both 100M and 1G network signals.

[0003] Another example is Chinese utility model patent publication number CN214627012U, which discloses a single-master, multiple-slave real-time communication system based on Ethernet PHY. The system includes a master node and slave nodes. The master node includes an industrial computer and a NIC (Network Interface Card) unit, while the slave nodes include an FPGA (Field Programmable Gate Array) main control unit, a PHY unit, a network transformer unit, and an RJ45 network port. The master node connects the NIC to the input port of a slave node via a network cable, and the output port of a slave node connects to the input port of the next slave node, forming a single-master, multiple-slave communication network. Leveraging the physical layer communication link provided by the Gigabit Ethernet PHY and programming FPGA control logic, data transmission with strong real-time performance, high throughput, and high reliability can be achieved.

[0004] In modern high-speed Ethernet networks (such as 100Base-TX, 1000Base-T, and 10GBase-T), signal frequencies are typically above 100 MHz. During Ethernet data communication, network transformers (Ethernet transformers), such as those described in Publication No. CN208045213U, serve as crucial signal transmission components, performing key functions such as signal isolation, common-mode noise suppression, and impedance matching to ensure data integrity and reliability during transmission. Their operating principle is to convert electrical signals at the transmitter into magnetic flux through electromagnetic induction, and then convert the magnetic flux into electrical signals at the receiver, achieving lossless data transmission. This is achieved through differential signaling, thereby suppressing common-mode noise and improving communication quality. However, existing Ethernet data transmission systems and methods do not provide specific technical solutions for dynamically optimizing the differential signaling of the network transformer to achieve high-speed, lossless data transmission that is effectively resistant to electromagnetic interference. Summary of the Invention

[0005] To address these shortcomings, the present invention provides an Ethernet data transmission method and system based on a single-phase CMC (common mode choke) network transformer. This system utilizes an Ethernet data transmission system that combines a MAC layer, a physical layer hysteresis (PHY) chip, a network transformer, and a single-phase common mode choke (CMC). The system also employs a gradient descent optimization algorithm to continuously optimize the multiple differential signal pairs that are converted from the digital signals received by the PHY chip into parallel serial streams. This achieves efficient, low-interference, and low-bit-error-rate Ethernet data transmission.

[0006] The present invention provides the following technical solution: an Ethernet data transmission method based on a single-phase CMC network transformer, wherein the method dynamically optimizes electromagnetic interference during Ethernet data transmission based on a network transformer having a single-phase common-mode choke, and the method comprises the following steps:

[0007] S1: The MAC layer main control module receives a feedback differential signal pair from an external network device connected to the RJ45 connector via an Ethernet cable. The feedback differential signal pair is processed by a corresponding network transformer and then transmitted to the feedback differential signal pair receiving first pin and feedback differential signal pair receiving second pin of the PHY chip.

[0008] S2: The PHY chip decodes the feedback differential signal pair and restores it to a digital signal, which is then transmitted to the MAC layer main control module. The MAC layer main control module verifies the feedback differential signal pair restored to a digital signal, and transmits the processed data to a higher layer for further data analysis and processing.

[0009] S3: The MAC layer main control module sends the data to be sent to the PHY chip according to the situation. After receiving the digital signal input from the MAC layer main control module, the PHY chip converts the received parallel data into serial stream data, encodes the serial stream data according to the encoding rules of the physical layer, and controls the differential signal pair of the PHY chip to send the first pin and the differential signal pair to send the second pin to the network transformer; at the same time, the real-time current in the first coil of the single-phase common mode choke in the nth signal-sending network transformer is monitored in real time , Real-time current in the second coil ;

[0010] S4: Calculate the impedance of the single-phase common mode choke in the corresponding nth transmission signal network transformer , according to the voltage level of the input analog voltage signal , calculate the common mode voltage of the single-phase common mode choke ;

[0011] S5: Calculate the differential signal voltage output from the first port corresponding to the single-phase common-mode choke in the nth transmitting signal network transformer , differential signal voltage output from the second port and differential mode voltage ;

[0012] S6: Calculate the power spectrum density of the total electromagnetic interference of the differential signal generated by the single-phase common mode choke in the nth transmitting signal network transformer , determine whether it is lower than the differential signal output PSD threshold If so, the differential signal pair of the PHY chip is controlled to transmit the first pin and the differential signal pair to transmit the second pin respectively. and to the RJ45 connector and further output to the external network device; otherwise, the MAC layer main control module continues to optimize using the gradient descent optimization method and .

[0013] Furthermore, the S3 step includes:

[0014] S31: Collect the received parallel data to obtain a parallel data set D: ,in, is the i+1th binary parallel data, =0 or 1; I is the total number of binary parallel data in the parallel data set D; I=4 or 8;

[0015] S32: The PHY chip stores the data in the parallel data set D in step S31 in the order of the most significant bit. To the least significant bit Arrange them from front to back and output them bit by bit in the order of arrangement;

[0016] S33: According to the NRZ encoding rule, the binary parallel data outputted bit by bit in step S32 is converted into Convert to analog voltage signal according to the following mapping rules:

[0017] ;in, 、 They are the high voltage level and low voltage level after digital signal conversion, =3.3V or 5V, =0V.

[0018] Furthermore, the S4 step includes:

[0019] S41: Calculate the total impedance of the first coil of the K component in the nth signal transmission network transformer and the total impedance of the second coil ; ;q=1 or 2; 、 、 and are the resistance, self-inductance, leakage inductance of the qth coil of the K component in the nth transmitting signal network transformer and the impedance of the nth magnetic core, q=1 or 2;

[0020] S42: Calculate the total impedance generated by the two coils in the single-phase common mode choke in the nth signal transmission network transformer according to the result of step S41 :

[0021] ;

[0022] S43: Calculate the common mode voltage of the single-phase common mode choke in the nth transmitting signal network transformer:

[0023] ;in, is the capacitance value of the third capacitor C3 commonly connected before the N signal transmission network transformers and the RJ45 connector are commonly grounded; N is the total number of signal transmission network transformers included in the system, N=1 or 2, n=1, 2, ..., N; 、 、 and The resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4; j is an imaginary number; ω is the angular frequency of the input digital signal, , f is the frequency of the input digital signal, f=125MHz.

[0024] Furthermore, the S5 step includes:

[0025] S51: Calculate the stray capacitance of each coil in the nth signal transmission network transformer , stray capacitance between the qth coil and the core :

[0026] ;

[0027] ;

[0028] in, is the dielectric constant of the coil insulation layer; is the radius of the circular cross section of the coil wire, is the vacuum dielectric constant of the coil, =8.854×10 -12 F / m; It is the outer diameter of the coil wire after it is surrounded by a circle of insulating medium; is the horizontal winding distance between the inside and outside of each coil of a K-piece magnetic core, is the effective capacitance area between the two coils of a K-piece; is the effective capacitance area between the qth coil and the magnetic core in a K-piece, It is the height difference between the center point of the cross section of a coil wire in a K piece and the surface of the magnetic core; , is the vertical height of the coil when it is wrapped around the core, is the inner diameter of the core, is the outer diameter of the core; is the average path length of the qth coil wound around the toroidal core in a K-piece;

[0029] S52: Calculate the self-inductance of the qth coil in the nth signal transmission network transformer , leakage inductance of the qth coil :

[0030] ; ;

[0031] Among them, M q is the number of times the qth coil is wound around the core;

[0032] ;in, is the angle covered by the area wound by the qth coil on the toroidal core;

[0033] S53: Calculate the resistance of the i-th coil , the resistance of the core of the single-phase common mode choke in the nth transmission signal network transformer and its impedance :

[0034] ;in, is the density of the coil, =8.9g / cm 3 ; is the skin depth of the coil material, , is the resistivity of the coil, =1.68×10 −8 Ω⋅m; is the relative magnetic permeability of the enameled copper wire coil, =1; is the vacuum permeability, =4π×10 - 1 H / m;

[0035] Among them, A e is the cross-sectional area of ​​the core, ; , a and b are the first, second and third Steinmetz coefficients of the magnetic core respectively. It is related to the material of the magnetic core, a=1.5~2, b=2~2.5; is the equivalent RMS current in the core of the single-phase common-mode choke in the nth transmitting signal network transformer, ; for and Phase difference;

[0036] ;

[0037] in, is the relative magnetic permeability of the core material;

[0038] S54: Calculate the differential signal voltage output from the first port corresponding to the single-phase common-mode choke in the nth transmitting signal network transformer , differential signal voltage output from the second port :

[0039] ;

[0040] ;

[0041] in, 、 are the differential signal currents flowing through the first and second coils of the single-phase common-mode choke in the nth transmitting signal network transformer, , , ; 、 are the common-mode signal currents flowing through the first and second coils of the single-phase common-mode choke coil in the nth transmitting signal network transformer;

[0042] S55: Further calculation of differential mode voltage :

[0043] .

[0044] Furthermore, when the Ethernet is Gigabit Ethernet (1000BASE-T), the differential voltage of the analog signal converted by the PHY chip is In the range of 0.4V to 2V; when the Ethernet is 100M Ethernet (100BASE-TX), the differential voltage of the analog signal converted by the PHY chip In the range of 0.2V to 2.5V.

[0045] Furthermore, in step S6, the power spectrum density of the total electromagnetic interference of the differential signal generated by the single-phase common mode choke in the nth signal transmission network transformer is calculated. The formula is as follows:

[0046] ;

[0047] in, is the differential mode voltage Power spectral density of the generated electromagnetic interference; is the common mode voltage Power spectral density of the generated electromagnetic interference;

[0048] ;

[0049] ; The differential signal output PSD threshold Adopting CISPR32 international standard, =43.5dBμV / m.

[0050] Furthermore, the step S6 uses the gradient descent optimization method to optimize and The steps are as follows:

[0051] S61: Construct optimization objective function: ;

[0052] S62: Constructing the gradient function of the objective function :

[0053] ; is the expected differential mode voltage signal electromagnetic interference value, is the expected common mode voltage signal electromagnetic interference value;

[0054] S63: The p-th generation optimized value of the differential signal voltage outputted from the first port corresponding to the single-phase common mode choke in the n-th transmitting signal network transformer at a learning rate α , the pth generation optimized value of the differential signal voltage output from the second port corresponding to the single-phase common mode choke in the nth transmitting signal network transformer Perform target gradient update:

[0055] ;

[0056] ;

[0057] in, 、 are the p+1th generation optimized values ​​of the differential signal voltage output from the first and second ports corresponding to the single-phase common-mode choke in the nth transmitting signal network transformer; α=0.215;

[0058] S64: Determine the modulus of the gradient function of the p+1th generation objective function Is it less than the gradient optimization stopping threshold 0.005? If so, stop the iteration; otherwise, repeat S61-S63.

[0059] The present invention also provides an Ethernet data transmission system based on a single-phase CMC network transformer using the above method, the system includes a MAC layer main control module, a PHY chip, multiple feedback signal transformers, multiple transmission signal network transformers and an RJ45 connector, and also includes a device for real-time monitoring of the real-time current of the two coils of each network transformer. and Coil current monitoring module;

[0060] The MAC layer main control module is used to receive a feedback differential signal pair from an external network device connected to the RJ45 connector via an Ethernet cable, and transmit the feedback differential signal pair to the first feedback differential signal pair receiving pin and the second feedback differential signal pair receiving pin of the PHY chip after processing through a corresponding network transformer; and verify the feedback differential signal pair restored to a digital signal, and transmit the processed data to a higher layer for further data analysis and processing;

[0061] The PHY chip is used to process the conversion between the input digital signal and the analog signal transmitted from the physical network line fed back through the RJ45 connector; the PHY chip decodes the feedback differential signal pair and restores it to a digital signal for transmission to the MAC layer main control module, and is used to receive the digital signal input from the MAC layer main control module, convert the received parallel data into serial stream data, and encode the serial stream data according to the encoding rules of the physical layer; and monitor the real-time current in the first coil of the single-phase common mode choke in the nth transmitting signal network transformer in real time , Real-time current in the second coil ;

[0062] The MAC layer main control module is also used to calculate the impedance of the single-phase common mode choke in the corresponding nth signal transmission network transformer , according to the voltage level of the input analog voltage signal , calculate the common mode voltage of the single-phase common mode choke ;

[0063] And calculate the differential signal voltage output from the first port corresponding to the single-phase common mode choke in the nth transmitting signal network transformer , differential signal voltage output from the second port and differential mode voltage ; and calculate the power spectrum density of the total electromagnetic interference of the differential signal generated by the single-phase common mode choke in the nth transmission signal network transformer , determine whether it is lower than the differential signal output PSD threshold If so, the differential signal pair of the PHY chip is controlled to transmit the first pin and the differential signal pair to transmit the second pin respectively. and to the RJ45 connector and further output to the external network device; otherwise, the MAC layer main control module continues to optimize using the gradient descent optimization method and .

[0064] Furthermore, the sending signal network transformer includes a transformer as a T-piece and a single-phase common-mode choke, the coil ratio of the transformer is 1:1, the center tap of the left coil and the center tap of the right coil of the transformer are both grounded, and the two ends of the right coil are respectively connected in series with the first coil and the second coil of the single-phase common-mode choke.

[0065] Furthermore, the PHY chip is a voltage-driven chip.

[0066] The beneficial effects and advantages of the present invention over the prior art are:

[0067] 1. The present invention uses the S1-S2 control system to receive differential feedback signals from external devices via the RJ45 interface. The signals are then passed through the network transformer, PHY chip, and MAC layer main control module to ensure data integrity. Specifically, the PHY decodes and recovers the digital signal, reducing the bit error rate during data transmission. The digital signal recovered by the PHY chip is then transmitted to the MAC layer main control module. The MAC layer performs a frame check (CRC) to detect and correct possible transmission errors, thereby improving data accuracy. The integrity-checked data is then uploaded to the IP and transport layers for further processing, ensuring stable data transmission to higher-level protocol layers. This achieves efficient communication while improving signal integrity and data accuracy.

[0068] 2. The present invention controls the system through the S3 step. When the upper layer data (IP layer, application layer) needs to be transmitted to the network device connected to the RJ45 connector, the MAC layer main control module encapsulates and sends it to the PHY chip physical layer. Then, the serial stream data is encoded according to the encoding rules of the PHY chip physical layer (such as 1000Base-T PAM-5 encoding), reducing signal loss and optimizing the stability of high-speed signal transmission. At the same time, the real-time current in the two coils in the K-piece single-phase common mode choke (CMC) of the network transformer with a T-piece + K-piece structure is monitored in real time to ensure that the coils in the network transformer can calculate the differential signal output by the two coils in real time. and , reduce signal distortion and error accumulation, and improve signal quality.

[0069] 3. The present invention introduces the calculation of the common mode voltage generated by the differential signal output by each network transformer, the calculation of the differential signal, and the calculation of the common mode electromagnetic interference EMI value and the differential mode electromagnetic interference EMI value generated by the common mode voltage through steps S4-S6, and further uses PSD (power spectrum density) analysis to ensure that the output differential signal is dynamically regulated to make the common mode electromagnetic interference EMI value ( ) and differential mode electromagnetic interference EMI value ( ) is the sum of the power spectrum density of the total electromagnetic interference Below the differential signal output PSD threshold , thereby achieving effective control of EMI of the output differential signal.

[0070] 4. In step S6 of the present invention, the differential signal voltage output by the network transformer is and The common mode electromagnetic interference EMI value obtained by the calculation result ( ) and differential mode electromagnetic interference EMI value ( ) and its ideal value 、 gap, and then build dynamic optimization and The objective function is: , and then and Gradients are optimized to minimize electromagnetic interference while maintaining signal integrity. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] The present invention will be described in more detail below based on embodiments and with reference to the accompanying drawings, wherein:

[0072] Figure 1 A schematic flow chart of the Ethernet data transmission method based on a single-phase CMC network transformer provided by the present invention;

[0073] Figure 2 A comparison chart of simulation results and actual test results of encoding the signal to be sent by the MAC layer main control module using the method provided by the present invention and the 4B / 5B encoding method;

[0074] Figure 3 A structural diagram of a single-phase common-mode choke as a K component in a network transformer in the method and system provided by the present invention;

[0075] Figure 4 Schematic diagram of the equivalent circuit structure of the network transformer and the time variation of the electromagnetic interference and differential signal generated by the transformer in an embodiment of the present invention;

[0076] Figure 5 In the embodiment of the present invention, Figure 3 The direction of the electromagnetic interference magnetic field, the direction of the common-mode signal current, and the direction of the differential signal current in the single-phase common-mode choke;

[0077] Figure 6 In the embodiment of the present invention, Figure 3 Schematic diagram of calculation parameters for the stray capacitance of a coil itself and the stray capacitance between it and the magnetic core in a single-phase common mode choke;

[0078] Figure 7In the embodiment of the present invention, Figure 3 Another schematic diagram of the calculation parameters of the stray capacitance of a coil itself and the stray capacitance between it and the magnetic core in a single-phase common mode choke;

[0079] Figure 8 A schematic diagram illustrating the coil winding magnetic core and related parameters in a single-phase common mode choke in an embodiment of the present invention;

[0080] Figure 9 Schematic diagram comparing the total electromagnetic interference (EMI) noise level versus monitoring time and number of iterations using the method of the present invention and two other comparative methods that omit some steps of the present invention in an embodiment of the present invention;

[0081] Figure 10 An Ethernet data transmission system based on a single-phase CMC for 100M Ethernet data transmission provided by an embodiment of the present invention;

[0082] Figure 11 An embodiment of the present invention provides an Ethernet data transmission system based on a single-phase CMC for Gigabit Ethernet data transmission. DETAILED DESCRIPTION

[0083] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0084] The present invention provides an Ethernet data transmission method based on a single-phase CMC network transformer. CMC is the abbreviation of common mode choke, and single-phase CMC is a single-phase common mode choke. It is used as a K component and a T component to form a network transformer. The method is based on the network transformer with a single-phase common mode choke to dynamically optimize the electromagnetic interference (EMI) during Ethernet data transmission to improve the reliability and anti-interference capability of Ethernet data transmission. Figure 1 As shown, the method of the present invention comprises the following steps:

[0085] S1: The MAC layer main control module receives a feedback differential signal pair from an external network device connected to an RJ45 connector via an Ethernet cable (such as Cat5e or Cat6). The feedback differential signal pair is processed by a corresponding feedback signal network transformer and then transmitted to the feedback differential signal pair receiving pin 1 (positive end) and the feedback differential signal pair receiving pin 2 (negative end) of the PHY chip.

[0086] S2: The PHY chip decodes the feedback differential signal pair (analog signal) and restores it to a digital signal, which is then transmitted to the MAC layer main control module. The MAC layer main control module verifies the feedback differential signal pair that has been restored to a digital signal (generally by parsing the Ethernet frame of the feedback differential signal pair that has been restored to a digital signal and checking the data integrity (such as CRC)). The processed data is then transmitted to higher layers (such as the IP layer and transport layer) for further data analysis and processing.

[0087] S3: If there is data to be sent (such as data from upper-layer applications), MAC will prepare the data packet and transmit it to the PHY chip for physical layer encoding and transmission; the MAC layer main control module will send the data to be sent to the PHY chip according to the situation. After the PHY chip receives the digital signal input from the MAC layer main control module, it will convert the received parallel data into serial stream data, encode the serial stream data according to the encoding rules of the physical layer (that is, perform digital-to-analog conversion to obtain a voltage change signal suitable for physical transmission), and control the differential signal pair of the PHY chip to send the first pin and the differential signal pair to send the second pin to the network transformer; at the same time, the real-time current in the first coil of the single-phase common-mode choke as the K component in the nth sending signal network transformer is monitored in real time , Real-time current in the second coil ;

[0088] S4: Calculate the impedance of the single-phase common mode choke as K component in the corresponding nth transmission signal network transformer , according to the voltage level of the input analog voltage signal , calculate the common mode voltage of a single-phase common mode choke ;

[0089] S5: Calculate the differential signal voltage output from the first port corresponding to the single-phase common-mode choke in the nth transmitting signal network transformer , differential signal voltage output from the second port and differential mode voltage ;

[0090] S6: Calculate the power spectrum density of the total electromagnetic interference of the differential signal generated by the single-phase common mode choke in the nth transmitting signal network transformer , determine whether it is lower than the differential signal output PSD threshold If so, control the differential signal pair receiving first pin and differential signal pair receiving second pin of the RJ45 connector to receive the differential signal pair respectively. and , and further output to the external network device; otherwise, the MAC layer main control module continues to use the gradient descent optimization method to optimize and .

[0091] The MAC layer's main control module operates alongside the PHY chip in network devices such as Ethernet network cards (NICs), routers, and switches. Specifically, the MAC layer, typically part of a network controller, is responsible for address management, data frame management, flow control, and collision detection for data transmission. In address management, the MAC address is a unique identifier for a physical layer device and is used by the MAC layer for inter-device communication. The MAC layer is responsible for converting upper-layer data into a frame format, transmitting or receiving it, and verifying data integrity. In shared-media networks, the MAC layer manages how devices access data on the shared transmission channel and avoids data collisions (e.g., CSMA / CD in Ethernet).

[0092] The RJ45 connector is a standardized connection interface commonly used for physical connections between Ethernet devices. The RJ45 connector is a plug interface used to connect devices with Ethernet ports, such as computers, routers, switches, printers, smart TVs, industrial equipment, and embedded devices. It is generally used for network communications using twisted-pair cables (such as Cat5e and Cat6).

[0093] By combining signal monitoring, EMI optimization, and an adaptive gradient descent algorithm, this invention provides a stable, low-interference, high-speed data transmission method for high-performance Ethernet. Therefore, the method is particularly suitable for applications with strict requirements on network signal quality, such as industrial Ethernet, data centers, smart homes, and in-vehicle Ethernet.

[0094] In the Ethernet communication architecture, data transmission between the MAC layer and the physical layer of the PHY chip is usually parallel, while the transmission of physical signals is usually serial. The MAC layer main control module processes data frames (Ethernet frames) and usually sends 8-bit or 16-bit parallel data to the PHY chip through the MII, GMII or RGMII interface. If the unencoded digital signal is directly output, the receiving end will not be able to accurately extract the clock signal from the data stream, and the clock recovery will be difficult, which will lead to data synchronization difficulties. At the same time, if there are long periods of "0" or "1" in the data stream, it may cause signal offset (DC bias), unstable signal transmission, and affect the transmission quality. Therefore, the physical layer of the PHY chip needs to convert these parallel data into serial streams to adapt to the serial transmission requirements of the physical medium (twisted pair). As a preferred embodiment of the present invention, step S3 includes:

[0095] S31: When the PHY chip receives parallel data from the MAC layer, this data is usually transmitted in a fixed bit width (such as 8 bits, 16 bits, etc.). The PHY chip needs to convert this parallel data into a serial stream for physical transmission; the received parallel data is collected to obtain a parallel data set D: ,in, is the i+1th binary parallel data, = 0 or 1; I is the total number of binary parallel data in the parallel data set D, is the most significant bit (MSB), The least significant bit (LSB); I = 4 or 8; when 100M Ethernet data transmission, I = 4, when Gigabit Ethernet transmission, I = 8;

[0096] This step ensures that data is serially output from the PHY chip in the correct order, in compliance with Ethernet protocol requirements. It also reduces the interface bandwidth requirements between the MAC layer main control module and the PHY layer. The conversion of data streams from parallel to serial reduces the need for a high-speed data bus.

[0097] S32: The PHY chip stores the data in the parallel data set D in step S31 in the order of the most significant bit. To the least significant bit Arrange from front to back and output them one by one in the order of arrangement; that is, according to 、 The number of significant bits is gradually reduced and output bit by bit until D0 is output last;

[0098] S33: According to the NRZ encoding rule, the binary parallel data outputted bit by bit in step S32 is converted into Convert to analog voltage signal according to the following mapping rules:

[0099] ;in, 、 They are the high voltage level and low voltage level after digital signal conversion, =3.3V or 5V, =0V.

[0100] The functions of the PHY chip include converting the parallel digital signals from the MAC layer into a serial data stream and encoding the serial data according to the encoding rules of the physical layer (such as non-return-to-zero encoding, NRZ encoding). Non-return-to-zero encoding (NRZ encoding) is a common physical layer encoding method that converts each binary parallel data D of the digital signal received by the PHY chip into a serial data stream. iDirectly mapped to a high or low voltage state. Using the NRZ encoding rule, the PHY chip converts the incoming parallel data stream into a serial voltage signal and processes it according to the physical layer's encoding rules. NRZ encoding is simple and efficient. By directly mapping each data bit to a fixed voltage level, it ensures stable data transmission at the physical layer. The core of the entire process is converting the incoming parallel data into a serial format. Once the parallel data is converted into a serial stream, the PHY chip can process data faster, improving throughput.

[0101] Both 100M Ethernet (100Base-TX) and Gigabit Ethernet (1000Base-T) support NRZ encoding as the basic physical layer encoding scheme. Therefore, they support full-duplex communication and are suitable for high-speed Ethernet transmission. The encoding method of the present invention is directly compatible with current mainstream PHY chips, eliminating the need for additional decoding or conversion steps, and possesses strong versatility.

[0102] In order to verify the accuracy of data transmission by encoding serial data using the NRZ encoding method in the steps S31-S33 provided by the present invention, the following is used: Figure 10 The Ethernet data transmission system shown in FIG. 1 performs Ethernet data transmission. In Comparative Example 1, the 4B / 5B encoding method is used to replace the NRZ encoding method of steps S31-S33 of the present invention. Figure 2 As shown, Figure 2 The red × points and blue × points in the figure are the real-time monitoring results of the present invention method and the 4B / 5B method respectively as the monitoring frequency changes. The yellow dotted line is the DC bias rate of the simulation results of the 4B / 5B encoding method as the monitoring frequency changes. The green solid line is the DC bias rate of the simulation results of the NRZ encoding method using the S31-S33 steps of the present invention as the monitoring frequency changes. Figure 2 Comparing the red × dots in the figure with the green solid line, we can see that the difference between the simulation results and the actual real-time monitoring results of the method of the present invention is very small. When the monitoring frequency is low, the DC bias rate is around 0.02. As the monitoring frequency increases and gradually approaches the transmission data frequency of 100M Ethernet and Gigabit Ethernet (125MHz), the red × dots and the green solid line almost coincide, and the DC bias rate is close to 0. Figure 2The real-time monitoring results represented by the blue × dots in the figure differ significantly from the simulation results represented by the yellow dashed line. Although the difference gradually decreases with increasing monitoring frequency, the difference between the two is still significant. This demonstrates that the 4B / 5B encoding method does not perform well in converting serial stream data into Ethernet data using the single-phase common-mode choke network transformer of the present invention, resulting in a high bit error rate. Furthermore, the DC offset rate of the 4B / 5B encoding method is consistently higher than that of the NRZ encoding method of the present invention, both in simulation and real-time monitoring results. This demonstrates that the present invention utilizes NRZ encoding to output a corresponding level signal based on the input digital signal according to the NRZ encoding rules. This ensures data accuracy, reduces signal transmission bit error rate (BER), reduces signal switching loss, improves signal integrity, and reduces the complexity of the PHY transmitter, allowing it to focus on signal amplification, equalization, and transmission optimization.

[0103] The network transformer used in the present invention is as follows Figure 4 The network transformer with a T-piece + K-piece structural equivalent circuit shown on the left plays a role in signal isolation, impedance matching, and EMI suppression during Ethernet data transmission. However, in the differential signal output calculation of the network transformer in the prior art, the impedance calculation of the single-phase common-mode choke as the K-piece is usually fixed, but different transmission environments (such as different network cable lengths, electromagnetic interference environments) will affect the common-mode impedance, thereby affecting EMI and signal quality. In addition, the impedance of the K-piece is not accurately calculated, resulting in unstable common-mode noise suppression capabilities, affecting the data transmission of the PHY chip. At the same time, the common-mode voltage calculation lacks a dynamic optimization mechanism and is difficult to adapt to high-speed signal transmission environments, which may lead to an increase in the bit error rate (BER). Therefore, it is necessary to dynamically calculate the impedance and common-mode voltage of the K-piece to ensure that the network transformer can provide optimal signal quality and minimize EMI in different environments. As another preferred embodiment of the present invention, step S4 includes:

[0104] S41: Calculate the total impedance of the first coil of the K component in the nth signal transmission network transformer and the total impedance of the second coil ; ;q=1 or 2; 、 、 and are the resistance, self-inductance, leakage inductance of the qth coil of the K-component in the nth signal transmission network transformer and the impedance of the nth magnetic core, q = 1 or 2; Figure 3As shown, the windings of the first coil and the second coil of each network transformer are wound on the magnetic core to form a single-phase common mode choke. The first coil is the first winding, and the second coil is the second winding. The two coils form a coupled winding, and the common mode current of the first coil; K pieces are set in the network transformer because K pieces are not sensitive to useful data voltage signals. and (ie differential signal and ) has no attenuation effect, but can attenuate electromagnetic interference EMI; adding K components can further block the mutual propagation of EMI between its primary and secondary coils;

[0105] like Figure 4 As shown, the orange sine wave solid lines on the right are the common mode data voltage signals 、 Waveform of the common-mode electromagnetic interference generated. The blue solid line on the right is the differential-mode data voltage differential signal. 、 Periodic variation diagram of Figure 4 In the network transformer equivalent circuit on the left, a differential data pair in the encoded serial data stream obtained from the MAC layer main control module enters the T-piece coil and then enters the K-piece. The orange arrow represents the common-mode data voltage signal. Split into two common-mode current signals 、 Flows from Pin4 through the first coil of K piece ( from Figure 3 as well as Figure 5 A1 end flows to A2 end), flows from Pin6 through the second coil of K component ( from Figure 3 as well as Figure 5 The current flows from the B1 end to the B2 section), and then enters the T-piece coil in the direction of the current; Figure 4 In the network transformer equivalent circuit on the left, the blue arrows represent two differential mode current signals 、 Flows from Pin4 through the first coil of K piece ( from Figure 3 as well as Figure 5 A1 end flows to A2 end), flows from Pin6 through the second coil of K component ( from Figure 3 as well as Figure 5 The B2 end flows to the B1 section), and then

[0106] like Figure 5As shown by the blue solid arrows in J-2, when the data voltage signal flows through the upper and lower coils of the K-piece and flows out from Pin4 and Pin6 respectively, the currents are equal in magnitude and opposite in direction. The magnetic flux of the first coil inside the K-piece magnetic ring is , the magnetic flux in the second coil is , the flux changes caused by them cancel each other out partially, and ideally the flux change is zero ( ), at this time, it means that the common mode impedance presented by the first coil on the top of the K component and the second coil on the bottom is zero. The differential mode EMI of the K component to the data voltage signal depends on the difference in the differential mode signal magnetic flux generated by the two coils of the K component. .

[0107] like Figure 4 The orange solid arrows show that when two common mode current signals 、 When flowing through the upper and lower coils of the K-piece, the currents generated are equal in magnitude and in the same direction. The magnetic flux of the first coil inside the K-piece magnetic ring is , the magnetic flux of the second coil is , the magnetic flux of the common mode signal is superimposed on each other, so the EMI value of the common mode signal formed by the common mode signal at the K part depends on , the inductive reactance presented by the K component will increase linearly with the increase of the frequency f of the input digital signal;

[0108] S42: Based on the result of step S41, calculate the total impedance generated by the two coils in the single-phase common mode choke coil as the K component in the nth transmitting signal network transformer :

[0109] ;

[0110] S43: Calculate the common mode voltage of the single-phase common mode choke as the K component in the nth transmission signal network transformer:

[0111] ;in, is the capacitance value of the third capacitor C3 commonly connected before the N signal transmission network transformers and the RJ45 connector are commonly grounded; N is the total number of signal transmission network transformers included in the system, N=1 or 2, n=1, 2, ..., N; 、 、 and The resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4; j is an imaginary number; ω is the angular frequency of the input digital signal, , f is the frequency of the input digital signal. The data transmission frequency of 100M Ethernet and Gigabit Ethernet is 125MHz, so f=125MHz.

[0112] Figure 4 In the figure, the orange arrow represents the common mode data voltage signal. Split into two common-mode current signals 、 Common mode data voltage signal The current generated in the total resistance of K is one-half, so ;

[0113] Furthermore, step S5 includes:

[0114] S51: Calculate the stray capacitance of each coil in the nth signal transmission network transformer , stray capacitance between the qth coil and the core :

[0115] ;

[0116] ;

[0117] in, is the dielectric constant of the coil insulation layer, for The reciprocal of Figure 6 、 Figure 7 As shown, is the radius of the circular cross section of the coil wire, is the vacuum dielectric constant of the coil, =8.854×10 -12 F / m; It is the outer diameter of the coil wire after it is surrounded by a circle of insulating medium; is the horizontal winding distance between the inside and outside of the core of each coil of a K piece (i.e. the distance between conductors), is the effective capacitance area between the two coils of a K-piece; Figure 8 As shown, is the effective capacitance area between the qth coil and the magnetic core in a K-piece, such as Figure 7 As shown, It is the height difference between the center point of the cross section of a coil wire in a K piece and the surface of the magnetic core; ,like Figure 8 As shown, is the vertical height of the coil when it is wrapped around the core, is the inner diameter of the core, is the outer diameter of the core; is the average path length of the qth coil wound around the toroidal core in a K-piece, ;like Figure 8 As shown in (a), is the magnetic induction area between the coil and the core when the coil is wound around the core once, is the arc length of a coil surrounding the magnetic core. Therefore, the volume area of ​​the magnetic core surrounded by a coil can be regarded as For the bottom, For high solid volume calculation, the calculated solid volume is the magnetic induction area of ​​a coil and the magnetic core, that is, the effective capacitance area; Figure 8 (b) Schematic diagram of K coils wrapped around a circular magnetic core once, i.e., N = 1.

[0118] In the present invention, it is assumed that the insulation material used for the two coils in the K part of all network transformers is the same, and the thickness of the insulation material coated on the coil metal wire is the same;

[0119] S52: Calculate the self-inductance of the qth coil in the nth signal transmission network transformer , leakage inductance of the qth coil :

[0120] ; ;

[0121] Among them, M q is the number of times the qth coil is wound around the core;

[0122] Among them, Figure 7 As shown, is the angle covered by the area wound by the qth coil on the toroidal core;

[0123] S53: Calculate the resistance of the i-th coil , the resistance of the core of the single-phase common mode choke coil as the K element in the nth transmission signal network transformer and its impedance :

[0124] ;in, The density of the coil. Generally, the coil of K piece is enameled copper wire. =8.9g / cm 3 ; is the skin depth of the coil material, , is the resistivity of the coil, =1.68×10 −8 Ω⋅m; is the relative magnetic permeability of the enameled copper wire coil, =1; is the vacuum permeability, =4π×10 -1 H / m;

[0125] Among them, A e is the cross-sectional area of ​​the core, ;in, , a and b are the first, second and third Steinmetz coefficients of the magnetic core respectively. It is related to the material of the magnetic core. The core material of the K part is generally Mn-Zn ferrite (generally suitable for operating frequencies of tens of kHz to hundreds of kHz, such as for switching power supplies, signal transmission, etc.) or Ni-Zn ferrite (generally suitable for operating frequencies of hundreds of kHz to several MHz, suitable for high-frequency applications such as radio frequency (RF) transformers and inductors). When the core of the K part is Mn-Zn ferrite, =1.5×10 -3 ~3.0×10 -3 , when the core of K is Ni-Zn ferrite, =5.0×10 -6 ~5.0×10 -4 ;a=1.5~2,b=2~2.5; is the equivalent RMS current in the core of the single-phase common-mode choke in the nth transmitting signal network transformer, ; for and Phase difference; f is the input digital signal frequency, that is, the voltage level of the input analog voltage signal The frequency, and thus 、 frequency;

[0126] During the operation of the transformer, the current in the coil generates an alternating magnetic field through winding, and the change of this magnetic field will pass through the magnetic core. The magnetic material of the core responds to this changing magnetic field, generating a certain amount of eddy current (related to the material's electrical conductivity and magnetic permeability) and hysteresis loss (related to the rate of change of the magnetic field, the material's magnetic permeability, etc.). The effective value of these losses per unit time can be calculated by the equivalent root mean square current I rms,n To describe.

[0127] ;in, is the total inductance of the core, which is the result of the coupling of the two coils' respective self-inductances. and the mutual inductance of the two coils composition is the total capacitance of the core, which is composed of the capacitance between the two coils wound around the core And the capacitance formed by the two coils and the magnetic core The sum of is the vacuum permeability, =4π×10 -1 H / m, The relative magnetic permeability of the core material; the network transformer is based on its operating frequency, and the core of the K part uses the relative magnetic permeability of Mn-Zn ferrite material. The relative magnetic permeability of Ni-Zn ferrite material is between 2000 and 5000. Between 50 and 1000;

[0128] S54: Calculate the differential signal voltage output from the first port corresponding to the single-phase common-mode choke in the nth transmitting signal network transformer , differential signal voltage output from the second port :

[0129] ;

[0130] ;

[0131] in, 、 are the differential signal currents flowing through the first and second coils of the single-phase common-mode choke in the nth transmitting signal network transformer, , , ; 、 are the common-mode signal currents flowing through the first and second coils of the single-phase common-mode choke coil in the nth transmitting signal network transformer; 、 That is, Figure 4 、 Figure 5 in 、 , 、 They are Figure 4 、 Figure 5 in 、

[0132] S55: Further calculation of differential mode voltage :

[0133] .

[0134] When Ethernet is Gigabit Ethernet (1000BASE-T), the differential voltage of the analog signal converted by the PHY chip In the range of 0.4V to 2V; when Ethernet is 100M Ethernet (100BASE-TX), the differential voltage of the analog signal converted by the PHY chip In the range of 0.2V to 2.5V.

[0135] In step S6, the power spectrum density of the total electromagnetic interference of the differential signal generated by the single-phase common mode choke in the nth transmitting signal network transformer is calculated. The formula is as follows:

[0136] ;

[0137] in, is the differential mode voltage Power spectral density of the generated electromagnetic interference; is the common mode voltage Power spectral density of the generated electromagnetic interference;

[0138] ;

[0139] ; Differential signal output PSD threshold Adopting CISPR32 international standard, =43.5dBμV / m.

[0140] Traditional EMI control methods for Ethernet transmission, such as fixed resistor and capacitor filtering solutions, are only effective within a specific frequency range and cannot adapt to changes in network cable lengths and electromagnetic environments. Although the digital signal processing (DSP) method of existing PHY chips can compensate for signal distortion to a certain extent, it is still difficult to ensure signal quality when high-frequency EMI interference is severe. Therefore, as another preferred embodiment of the present invention, the gradient descent optimization method is used to optimize the S6 step. and The steps are as follows:

[0141] S61: Construct optimization objective function: ；

[0142] S62: Constructing the gradient function of the objective function ：

[0143]

[0144] is the desired differential mode voltage signal electromagnetic interference (EMI) value, is the expected common mode voltage signal electromagnetic interference (EMI) value;

[0145] ;

[0146] ;

[0147] in, is the real-time expected differential voltage of the nth signal transmission network transformer, which meets the above requirements of 0.4V~2V or 0.2V~2.5V for different transmission speeds. The real-time expected common-mode voltage of the single-phase common-mode choke of the nth transmitting signal network transformer is:

[0148] ;

[0149] The desired input digital signal level is 3.3V or 5V;

[0150] S63: The p-th generation optimized value of the differential signal voltage outputted from the first port corresponding to the single-phase common mode choke in the n-th transmitting signal network transformer at a learning rate α , the pth generation optimized value of the differential signal voltage output from the second port corresponding to the single-phase common mode choke in the nth transmitting signal network transformer Perform target gradient update:

[0151] ;

[0152] ;

[0153] in, The differential signal voltages outputted from the first and second ports of the single-phase common-mode choke coil in the nth transmission signal network transformer obtained by the pth generation optimization are: 、 The gradient function of the objective function is obtained by further taking the two as independent variables and calculating the optimization objective function J as the basis; 、 are the p+1th generation optimized values ​​of the differential signal voltage output from the first and second ports corresponding to the single-phase common-mode choke in the nth transmitting signal network transformer; α=0.215;

[0154] S64: Determine the modulus of the gradient function of the p+1th generation objective function Is it less than the gradient optimization stopping threshold 0.005? If so, stop the iteration; otherwise, repeat S61-S63.

[0155] In order to verify the effect of the method provided by the present invention on eliminating the electromagnetic interference generated by the common mode signal and the differential signal, Figure 9 The comparison chart shown, Figure 9(a) is the change of the total EMI electromagnetic interference level using the method of the present invention with the monitoring time and the number of iterations, Figure 9 (b) Only the S4 and S5 steps of the method of the present invention are used to calculate the impedance of the K component. However, in the S6 step, when the differential mode signal output condition is not met, the ANN (artificial neural network) algorithm is used to calculate the impedance of the K component. and The change of the total EMI electromagnetic interference level after optimization with monitoring time and number of iterations; Figure 9 (c) The impedance of the K component is calculated without using the steps S4 and S5 of the present invention, i.e., without considering the stray capacitance of each coil in the two coils K. , stray capacitance between the qth coil and the core , their own feelings , leakage inductance ,resistance and the resistance of the core and the impedance of the core The impact of the impedance calculation accuracy of the K component is calculated by only using the impedance of the K component marked in the conventional T component + K component (such as the publication number CN208045213U) network transformer in the prior art. and , and in step S6, the gradient optimization method of the present invention is used to iteratively optimize the total EMI electromagnetic interference noise level.

[0156] Depend on Figure 9 (a) Figure 9 (b) and Figure 9 From the comparison of (c), we can see that in the initial stage of iteration (i.e., the stage of iteration 0-5), as the monitoring time increases, we can find that Figure 9 (c) The EMI noise fluctuation frequency of the method represented is the largest. Figure 9 (b) Secondly, the method of the present invention Figure 9 (a) The frequency is the lowest. It can be seen that the accurate calculation of the impedance parameters of the K element in the present invention can effectively improve the differential signal output of the network transformer. and The control accuracy of , with the increase of the number of iterations, can be seen at the 30th iteration Figure 9 (b) The total EMI noise level of electromagnetic interference still has certain fluctuations, and the gradient iteration method of step S6 of the present invention is used. Figure 9 (a) and Figure 9 (c) The optimized iterative and The optimization result will no longer cause the overall EMI noise level to fluctuate. It can be seen that the precise calculation of the impedance parameters of the K component in steps S4-S5 of the method of the present invention, combined with the gradient optimization method in step S6, produces the optimal differential mode signal.

[0157] The present invention also provides an Ethernet data transmission system using the above network transformer, the system includes a MAC layer main control module, a PHY chip, multiple feedback signal network transformers, multiple transmission signal network transformers and an RJ45 connector, and also includes a device for real-time monitoring of the real-time current of the two coils of each network transformer. and Coil current monitoring module; such as Figure 10 、 Figure 11 As shown are respectively a 100M Ethernet data transmission system and a Gigabit Ethernet data transmission system using a network transformer having a single-phase common mode choke as a K component of the present invention; Figure 4 As shown on the left, the feedback signal transformer and the transmission signal network transformer are both network transformers with single-phase common-mode chokes (CMCs), including a transformer as a T-piece and a single-phase common-mode choke as a K-piece. The coil ratio of the transformer as the T-piece is 1:1. The center taps of the left coil and the right coil of the transformer as the T-piece are both grounded, and the two ends of the right coil are respectively connected in series with the first coil and the second coil of the single-phase common-mode choke as the K-piece.

[0158] Because non-ideal transformers have parasitic capacitance, some EMI signals will be coupled to the primary side of the transformer through the parasitic capacitance. Therefore, to further block the mutual propagation of EMI between the primary and secondary coils, a K-type (common mode choke) can be connected in series on the primary or secondary side of the transformer based on the single T-type network transformer. This is a T-type + K-type network transformer.

[0159] K components (common mode chokes) are used to suppress coupled EMI. Their inductive reactance to balanced signals (differential mode) is almost zero, and their inductive reactance to unbalanced signals (common mode) is proportional to the frequency and inductance value.

[0160] Although placing the K element on the line side can effectively suppress EMI interference, the increased impedance of the common-mode inductor will affect the 75R termination effect of the transformer center tap (affecting impedance matching). Therefore, for voltage-type PHY, a network transformer with the common-mode inductor on the PHY side is generally selected. In addition, if Power over Ethernet (PoE) is used, the common-mode inductor on the line side will cause magnetic saturation due to the POE power supply current, greatly reducing the common-mode suppression effect. Therefore, transformers with the common-mode inductor on the line side cannot be used in PoE scenarios.

[0161] The MAC layer main control module receives feedback differential signal pairs from external network devices connected via an RJ45 connector via an Ethernet cable (such as Cat5e or Cat6). These feedback differential signal pairs are processed by the corresponding network transformer and transmitted to the first (positive) and second (negative) receiving pins of the PHY chip. The MAC layer also verifies the digitally restored feedback differential signal pairs and transmits the processed data to higher layers (such as the IP layer and transport layer) for further analysis and processing. When transmitting over 100M Ethernet, as shown in Table 1, RX+ and RX- form a pair of differential signals, and TX+ and TX- form a second pair of differential signals. When transmitting over Gigabit Ethernet, as shown in Table 2, MX0+ and MX0- form the first pair of differential signals, MX1+ and MX1- form the second pair of differential signals, MX2+ and MX2- form the third pair of differential signals, and MX3+ and MX3- form the fourth pair of differential signals.

[0162] Table 1 100M Ethernet data transmission system RJ45 connector pin numbers and signal names

[0163]

[0164] Combined with Table 1 and Figure 10 As shown in the figure, when the system is a 100M Ethernet data transmission system, the system includes two network transformers. Counting from top to bottom, the second transformer circuit composed of T and K is the signal transmission network transformer. The RJ45 connector only uses four pins, namely 1, 2, 3, and 6. At this time, the feedback differential signal in step S1 is RX+ and RX-. The external network device transmits the preliminary feedback differential signal to the RJ45 connector to obtain the feedback differential signal pair RX+ and RX-. RX+ and RX- then pass through pins 3 and 6 in the RJ45 connector and the feedback signal network transformer (i.e. Figure 10 The second transformer circuit composed of T and K components from top to bottom) is respectively transmitted to the feedback differential signal of the PHY chip to receive the first pin (i.e. Figure 10 RXIP pin in the ), and the feedback differential signal of the PHY chip receives the second pin (i.e. Figure 10 The RXIN pin in the PHY chip is used for analog-to-digital conversion and then transmitted to the MAC layer main control module connected to the PHY chip;

[0165] After the MAC layer main control module sends the data to be sent to the PHY chip, the digital signal pair to be sent is processed through steps S3-S6. The differential signal pair that meets the output standard in step S6 is TX+ and TX-, which are respectively sent through the differential signal pair of the PHY chip to the first pin (i.e. Figure 10TXOP pin in the ), and the differential signal pair of the PHY chip sends the second pin (i.e. Figure 10 The RJ45 connector receives the TXON pin in the differential signal pair respectively (ie, pin 1) and the second pin (ie, pin 2) of the differential signal pair, which meets the requirements of the differential signal output PSD threshold. And the differential signal pair after optimization by gradient descent optimization method: and , and further through Figure 10 The right end of the RJ45 connector in the jack is transmitted to the external network device connected to it. In this case, N=1 and n=1.

[0166] Table 2 Gigabit Ethernet data transmission system RJ45 connector pin numbers and signal names

[0167]

[0168] Combined with Table 2 and Figure 11 As shown in FIG, when the system is a 100M Ethernet data transmission system, in this case, N=2, n=1 or 2. Figure 11 Counting from top to bottom, the first and third transformer circuits composed of T and K components are the sending signal network transformers, namely the 1st sending signal network transformer and the 2nd sending signal network transformer; Figure 11 Counting from top to bottom, the second and fourth transformer circuits consisting of T and K components are the feedback signal network transformers, namely the first feedback signal network transformer and the second feedback signal network transformer; all eight pins of the RJ45 connector are used. At this time, there are two pairs of feedback differential signal pairs in S1, namely the first feedback differential signal pair: MX1+ and MX-, and the second feedback differential signal pair: MX3+ and MX3-. In step S6, the differential signal pair received by the RJ45 connector is lower than the differential signal output PSD threshold. And the differential signal pairs optimized by the gradient descent optimization method also have two pairs: the first optimized output differential signal pair MX0+ and MX0-, that is, and ; The second optimization has output differential signal pair MX2+ and MX2-, that is and .

[0169] After the external network device transmits two pairs of preliminary feedback differential signals to the RJ45 connector, it obtains the first feedback differential signal pair MX1+ and MX1-, and the second feedback differential signal pair: MX3+ and MX3-. MX1+ and MX1- are processed by the first feedback signal network transformer, and MX3+ and MX3- are processed by the second feedback signal network transformer; MX1+ and MX1- are transmitted to the first feedback signal network transformer through pins 3 and 6 of the RJ45 connector respectively, and MX3+ and MX3- are transmitted to the second feedback signal network transformer through pins 7 and 8 of the RJ45 connector respectively. After the first feedback signal network transformer and the second feedback signal network transformer process the two pairs of feedback differential signals respectively, the processed differential signals corresponding to MX1+ and MX- are further received through the first feedback differential signal pair receiving first pin MDIP1 and the first feedback differential signal pair receiving second pin MDIN1 of the PHY chip, and are further transmitted to the MAC layer main control module; the processed differential signals corresponding to MX3+ and MX3- are further received through the second feedback differential signal pair receiving first pin MDIP3 and the second feedback differential signal pair receiving second pin MDIN3 of the PHY chip, and are further transmitted to the MAC layer main control module.

[0170] In this case, the data that the MAC layer main control module needs to send is also two digital signals. After the two are sent to the PHY chip, the digital signal pair to be sent is processed by the control PHY chip, the first transmitting signal network transformer, and the second transmitting signal network transformer through steps S3-S6. The differential signals that meet the output standard in step S6 include the first pair of differential signals: MX0+ and MX0- (corresponding to MX1+ and MX1-, that is, MX1+ and MX1- are feedback data information that the external network device needs to transmit to the MAC layer main control module. After analysis and processing, the MAC layer main control module needs to send digital signals MX0+ and MX0- corresponding to the feedback data information MX1+ and MX1- to the external network device). The differential signals that meet the output standard in step S6 also include the second pair of differential signals: MX2+ and MX2- (corresponding to MX3+ and MX3-).

[0171] The first pair of differential signals: MX0+ and MX0-, are sent to the first pin (i.e. Figure 11 MDIP1 pin in the PHY chip), and the first differential signal pair of the PHY chip sends the second pin (i.e. Figure 11 The RJ45 connector receives the first differential signal pair through the first pin (i.e., pin 1) and the second differential signal pair (i.e., pin 2), respectively, which meets the requirements of the differential signal output PSD threshold. And the differential signal pair after optimization by gradient descent optimization method: and .

[0172] The second pair of differential signals: MX2+ and MX2-, are sent to the first pin (i.e. Figure 11 MDIP2 pin in the PHY chip), and the second differential signal pair of the PHY chip sends the second pin (i.e. Figure 11 Finally, the RJ45 connector receives the first pin (i.e., pin 4) through the second differential signal pair and the second pin (i.e., pin 5) through the second differential signal pair, which meets the requirements of the differential signal output PSD threshold. And the differential signal pair after optimization by gradient descent optimization method: and .

[0173] The PHY chip in the Ethernet data transmission system provided in the present invention is preferably a voltage-driven chip. The PHY (physical layer) chip is located at the physical layer of Ethernet communication. The PHY chip converts digital data from the MAC layer into a signal suitable for transmission through a physical medium (such as a twisted pair) and performs signal reception and transmission operations. It is used to process the conversion between the input digital signal and the analog signal transmitted from the physical network line fed back through the RJ45 connector; the PHY chip decodes the feedback differential signal pair (analog signal) and restores it to a digital signal and transmits it to the MAC layer main control module. After receiving the digital signal input from the MAC layer main control module, the PHY chip converts the received parallel data into serial stream data and encodes the serial stream data according to the encoding rules of the physical layer; and monitors the real-time current in the first coil of the single-phase common-mode choke coil as the K component in the nth transmitting signal network transformer in real time. , Real-time current in the second coil ;

[0174] The MAC layer main control module is also used to calculate the impedance of the single-phase common mode choke coil as the K component in the corresponding nth transmission signal network transformer. , according to the voltage level of the input analog voltage signal , calculate the common mode voltage of a single-phase common mode choke ;

[0175] And calculate the differential signal voltage output from the first port corresponding to the single-phase common mode choke of the nth signal transmission network transformer , differential signal voltage output from the second port and differential mode voltage ; and calculate the power spectrum density of the total electromagnetic interference of the differential signal generated by the single-phase common mode choke of the nth transmitting signal network transformer , determine whether it is lower than the differential signal output PSD threshold If so, the differential signal pair of the PHY chip is controlled to transmit the first pin and the differential signal pair to transmit the second pin respectively. and to the RJ45 connector and further output to the external network device; otherwise, the MAC layer main control module continues to use the gradient descent optimization method to optimize and .

[0176] The communication connection between the MAC layer main control module and the PHY chip in the present invention can adopt the MII interface (100M Ethernet data transmission), RMII interface (100M Ethernet data transmission), GMII interface (100M or 1000M), and RGMII interface (100M or 1000M) according to the requirements of Ethernet transmission rate of 100M or 1000M.

[0177] While the present invention has been described with reference to preferred embodiments, various modifications may be made thereto, and corresponding technical features or sub-technical solutions may be substituted with equivalents without departing from the scope of the present invention. In particular, the various technical features described in the various embodiments may be combined in any manner, provided that there are no conflicts between the technical steps and sub-technical solutions. The present invention is not limited to the specific embodiments disclosed herein, but encompasses all technical solutions within the scope of the claims.

Claims

1. An Ethernet data transmission method based on a single-phase CMC network transformer, wherein the method dynamically optimizes electromagnetic interference during Ethernet data transmission based on a network transformer with a single-phase common mode choke, and is characterized in that: The method comprises the following steps: S1: The MAC layer main control module receives a feedback differential signal pair from an external network device connected to the RJ45 connector via an Ethernet cable. The feedback differential signal pair is processed by a corresponding feedback signal network transformer and then transmitted to the feedback differential signal pair receiving first pin and feedback differential signal pair receiving second pin of the PHY chip; S2: The PHY chip decodes the feedback differential signal pair and restores it to a digital signal, which is then transmitted to the MAC layer main control module. The MAC layer main control module verifies the feedback differential signal pair restored to a digital signal, and transmits the processed data to a higher layer for further data analysis and processing. S3: The MAC layer main control module sends the data to be sent to the PHY chip according to the situation. After receiving the digital signal input from the MAC layer main control module, the PHY chip converts the received parallel data into serial stream data, encodes the serial stream data according to the encoding rules of the physical layer, and controls the differential signal pair of the PHY chip to send the first pin and the differential signal pair to send the second pin to the network transformer; at the same time, the real-time current in the first coil of the single-phase common mode choke in the nth signal-sending network transformer is monitored in real time , Real-time current in the second coil ; S4: Calculate the impedance of the single-phase common mode choke in the corresponding nth transmission signal network transformer , according to the voltage level of the input analog voltage signal , calculate the common mode voltage of the single-phase common mode choke ; S5: Calculate the differential signal voltage output from the first port corresponding to the single-phase common-mode choke in the nth transmitting signal network transformer , differential signal voltage output from the second port and differential mode voltage ; S6: Calculate the power spectrum density of the total electromagnetic interference of the differential signal generated by the single-phase common mode choke in the nth transmitting signal network transformer , determine whether it is lower than the differential signal output PSD threshold If so, the differential signal pair of the PHY chip is controlled to transmit the first pin and the differential signal pair to transmit the second pin respectively. and to the RJ45 connector and further output to the external network device; otherwise, the MAC layer main control module continues to optimize using the gradient descent optimization method and .

2. The Ethernet data transmission method based on the single-phase CMC network transformer according to claim 1 is characterized in that: The S3 step includes: S31: Collect the received parallel data to obtain a parallel data set D: ,in, is the i+1th binary parallel data, =0 or 1; I is the total number of binary parallel data in the parallel data set D; I=4 or 8; S32: The PHY chip stores the data in the parallel data set D in step S31 in the order of the most significant bit. To the least significant bit Arrange them from front to back and output them bit by bit in the order of arrangement; S33: According to the NRZ encoding rule, the binary parallel data outputted bit by bit in step S32 is converted into Convert to analog voltage signal according to the following mapping rules: ;in, 、 They are the high voltage level and low voltage level after digital signal conversion, =3.3V or 5V, =0V.

3. The Ethernet data transmission method based on the single-phase CMC network transformer according to claim 1 is characterized in that: The S4 step includes: S41: Calculate the total impedance of the first coil of the single-phase common mode choke in the nth transmitting signal network transformer and the total impedance of the second coil ; ;q=1 or 2; 、 、 and are the resistance, self-inductance, leakage inductance of the qth coil of the single-phase common-mode choke in the nth transmitting signal network transformer and the impedance of the nth magnetic core, q=1 or 2; S42: Calculate the total impedance generated by the two coils in the single-phase common mode choke in the nth signal transmission network transformer according to the result of step S41 : ； S43: Calculate the common mode voltage of the single-phase common mode choke in the nth transmitting signal network transformer: ;in, is the capacitance value of the third capacitor C3 commonly connected before the N signal transmission network transformers and the RJ45 connector are commonly grounded; N is the total number of signal transmission network transformers included in the system, N=1 or 2, n=1, 2, ..., N; 、 、 and The resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4; j is an imaginary number; ω is the angular frequency of the input digital signal, , f is the frequency of the input digital signal, f=125MHz.

4. The Ethernet data transmission method based on a single-phase CMC network transformer according to claim 3, characterized in that: The S5 step includes: S51: Calculate the stray capacitance of each coil in the nth signal transmission network transformer , stray capacitance between the qth coil and the core : ； ； in, is the dielectric constant of the coil insulation layer; is the radius of the circular cross section of the coil wire, is the vacuum dielectric constant of the coil, =8.854×10 -12 F / m; It is the outer diameter of the coil wire after it is surrounded by a circle of insulating medium; is the horizontal winding distance between the inside and outside of the core of each coil of a single-phase common mode choke coil, is the effective capacitance area between the two coils of a single-phase common-mode choke; is the effective capacitance area between the qth coil and the core in a single-phase common mode choke coil, It is the height difference between the center point of the cross section of a coil conductor in a single-phase common mode choke and the surface of the magnetic core; , is the vertical height of the coil when it is wrapped around the core, is the inner diameter of the core, is the outer diameter of the core; is the average path length of the qth coil wound around the toroidal core in a single-phase common mode choke; S52: Calculate the self-inductance of the qth coil in the nth signal transmission network transformer , leakage inductance of the qth coil : ； ； Among them, M q is the number of times the qth coil is wound around the core; ;in, is the angle covered by the area wound by the qth coil on the toroidal core; S53: Calculate the resistance of the i-th coil , the resistance of the core of the single-phase common mode choke in the nth transmission signal network transformer and its impedance : ;in, is the density of the coil, =8.9g / cm 3 ; is the skin depth of the coil material, , is the resistivity of the coil, =1.68×10 −8 Ω⋅m; is the relative magnetic permeability of the enameled copper wire coil, =1; is the vacuum permeability, =4π×10 -1 H / m; Among them, A e is the cross-sectional area of ​​the core, ; , a and b are the first, second and third Steinmetz coefficients of the magnetic core respectively. It is related to the material of the magnetic core, a=1.5~2, b=2~2.5; is the equivalent RMS current in the core of the single-phase common-mode choke in the nth transmitting signal network transformer, ; for and Phase difference; ； S54: Calculate the differential signal voltage output from the first port corresponding to the single-phase common-mode choke in the nth transmitting signal network transformer , differential signal voltage output from the second port : ； ； in, 、 are the differential signal currents flowing through the first and second coils of the single-phase common-mode choke in the nth transmitting signal network transformer, , , ; 、 are the common-mode signal currents flowing through the first and second coils of the single-phase common-mode choke coil in the nth transmitting signal network transformer; in, is the relative magnetic permeability of the core material; S55: Further calculation of differential mode voltage : 。 5. The Ethernet data transmission method based on the single-phase CMC network transformer according to claim 3 is characterized in that: When the Ethernet is Gigabit Ethernet (1000BASE-T), the differential mode voltage of the analog signal converted by the PHY chip is In the range of 0.4V to 2V; when the Ethernet is 100M Ethernet (100BASE-TX), the differential mode voltage of the analog signal converted by the PHY chip In the range of 0.2V to 2.5V.

6. The Ethernet data transmission method based on a single-phase CMC network transformer according to claim 4, characterized in that: In the step S6, the power spectrum density of the total electromagnetic interference of the differential signal generated by the single-phase common mode choke in the nth transmitting signal network transformer is calculated. The formula is as follows: ； in, is the differential mode voltage Power spectral density of the generated electromagnetic interference; is the common mode voltage Power spectral density of the generated electromagnetic interference; ； ; The differential signal output PSD threshold Adopting CISPR32 international standard, =43.5dBμV / m.

7. The Ethernet data transmission method based on a single-phase CMC network transformer according to claim 6, characterized in that: The S6 step uses the gradient descent optimization method to optimize and The steps are as follows: S61: Construct optimization objective function: ; S62: Constructing the gradient function of the objective function : ; is the expected differential mode voltage signal electromagnetic interference value, is the expected common mode voltage signal electromagnetic interference value; S63: The p-th generation optimized value of the differential signal voltage outputted from the first port corresponding to the single-phase common mode choke in the n-th transmitting signal network transformer at a learning rate α , the pth generation optimized value of the differential signal voltage output from the second port corresponding to the single-phase common mode choke in the nth transmitting signal network transformer Perform target gradient update: ； ； in, 、 are the p+1th generation optimized values ​​of the differential signal voltage output from the first and second ports corresponding to the single-phase common-mode choke in the nth transmitting signal network transformer; α=0.215; S64: Determine the modulus of the gradient function of the p+1th generation objective function Is it less than the gradient optimization stopping threshold 0.005? If so, stop the iteration; otherwise, repeat S61-S63.

8. An Ethernet data transmission system based on a single-phase CMC network transformer using the method according to any one of claims 1 to 7, characterized in that: The system includes a MAC layer main control module, a PHY chip, multiple feedback signal transformers, multiple transmission signal network transformers and an RJ45 connector, and also includes a device for real-time monitoring of the real-time current of the two coils of each network transformer. and Coil current monitoring module; The MAC layer main control module is used to receive a feedback differential signal pair from an external network device connected to the RJ45 connector via an Ethernet cable, and transmit the feedback differential signal pair to the first feedback differential signal pair receiving pin and the second feedback differential signal pair receiving pin of the PHY chip after processing through a corresponding feedback signal network transformer; and verify the feedback differential signal pair restored to a digital signal, and transmit the processed data to a higher layer for further data analysis and processing; The PHY chip is configured to process the conversion between the input digital signal and the analog signal transmitted from the physical network line fed back through the RJ45 connector; the PHY chip decodes the feedback differential signal pair and restores the digital signal to transmit to the MAC layer main control module; and after receiving the digital signal input from the MAC layer main control module, the PHY chip converts the received parallel data into serial stream data and encodes the serial stream data according to the encoding rules of the physical layer; And monitor the real-time current in the first coil of the single-phase common mode choke in the nth signal transmission network transformer in real time , Real-time current in the second coil ; The MAC layer main control module is also used to calculate the impedance of the single-phase common mode choke in the corresponding nth signal transmission network transformer , according to the voltage level of the input analog voltage signal , calculate the common mode voltage of the single-phase common mode choke ; And calculate the differential signal voltage output from the first port corresponding to the single-phase common mode choke in the nth transmitting signal network transformer , differential signal voltage output from the second port and differential mode voltage ; And calculate the power spectrum density of the total electromagnetic interference of the differential signal generated by the single-phase common mode choke in the nth transmission signal network transformer , determine whether it is lower than the differential signal output PSD threshold If so, the differential signal pair of the PHY chip is controlled to transmit the first pin and the differential signal pair to transmit the second pin respectively. and to the RJ45 connector and further output to the external network device; otherwise, the MAC layer main control module continues to optimize using the gradient descent optimization method and .

9. The Ethernet data transmission system based on a single-phase CMC network transformer according to claim 8, characterized in that: The network transformer includes a transformer and a single-phase common-mode choke. The coil ratio of the transformer is 1:

1. The center taps of the left coil and the right coil of the transformer are both grounded, and the two ends of the right coil are respectively connected in series with the first coil and the second coil of the single-phase common-mode choke.

10. The Ethernet data transmission system based on a single-phase CMC network transformer according to claim 8, characterized in that: The PHY chip is a voltage-driven chip.

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