Ultra wide band (UWB) transmitter and receiver circuit

Abstract

An ultra wide band (UWB) wireless technology transmits digital data as modulation coded pulses over a wide spectrum over a short distance at very low power. To support extended operations, in particular through battery power, the inventors have established UWB devices that support wakeup from a deep sleep mode when these devices utilize a low frequency clock source of ultra low power consumption. Furthermore, power consumption may be reduced by utilizing transistors or so-called composite MOSFET structures (their effective gain and output resistance exceeds any single transistor, regardless of length) or by utilizing unbiased low power differential (exponential) transconductance stages within the operational transconductance amplifier to provide a very high gain low power amplification stage. In addition, the inventors have established a voltage reference source that consumes very low current (several nA) and an ultra-low power low dropout regulator.

Description

[0001] This case is a divisional application based on the invention patent with application date of 2020-03-18, application number 202080022544.1, and name “Ultra-wideband (UWB) transmitter and receiver circuit” as the parent case. CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 819,847, filed on March 18, 2019, entitled “Ultra Wideband (UWB) Transmitter and Receiver Circuits,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to an ultra-wideband wireless communication system, and more particularly to an ultra-wideband transmitter and an ultra-wideband receiver for such an ultra-wideband wireless communication system. Background Art

[0004] Ultra-wideband (UWB) technology is a wireless technology that transmits large amounts of digital data as modulated coded pulses over a wide spectrum over short distances at very low power. Such pulse-based transmissions are an alternative to transmissions using sinusoidal waves that are then turned on or off to present digital states, as employed in today's wireless communication standards and systems such as IEEE 802.11 (Wi-Fi), IEEE 802.15 Wireless Personal Area Networks (PANs), IEEE 802.16 (WiMAX), Universal Mobile Telecommunications System (UMTS), Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), and those networks accessing the Industrial, Scientific and Medical (ISM) bands and International Mobile Telecommunications 2000 (IMT-2000).

[0005] UWB systems are well suited for short-range applications in a variety of environments, such as Figure 1 The environments described in , include peripheral and device interconnection as exemplified by a first residential environment 110, sensor networks as exemplified by a second residential environment 120, control and communication as exemplified by an industrial environment 130, medical systems as exemplified by medical imaging 150, and personal area networks (PANs) as exemplified by PANs 140. Such UWB systems tend to be short-range indoor applications due to the low emission levels permitted by regulatory agencies, but it is clear that a variety of other applications may be considered in the event that such regulatory restrictions are relaxed and / or absent, addressing, for example, military and civilian needs for communications between individuals, electronic devices, control centers, and electronic systems.

[0006] Therefore, it would be beneficial for UWB transmitters, UWB receivers, and UWB transceivers to know precisely when to wake up from a deep sleep mode, even if these devices utilize a low frequency clock source to achieve ultra-low power consumption.

[0007] Advantageously, electronic circuits forming wireless radios support low power operation by reducing current consumption, using transistors or so-called compounded MOSFET structures where possible (their effective gain and output resistance exceed any single transistor, regardless of length).

[0008] Advantageously, radio wave generating electronic circuits and other devices support low power operation by employing an unbiased low power differential (exponential) transconductance stage within operational transconductance amplifiers to provide a very high gain low power amplification stage.

[0009] Advantageously, the electronic circuitry that forms the radio waves supports low power operation by employing a voltage reference source that consumes very low current (a few nA).

[0010] Advantageously, the electronic circuits that form the radio waves support low power operation by employing ultra-low power low dropout regulators.

[0011] Other aspects and features of the present invention will become apparent to those of ordinary skill in the art upon reading the following description of specific embodiments of the invention in conjunction with the accompanying drawings. Summary of the invention

[0012] An object of the present invention is to alleviate the limitations of the prior art with respect to ultra-wideband wireless communication systems, and more particularly to ultra-wideband transmitters and ultra-wideband receivers for use in such ultra-wideband wireless communication systems.

[0013] According to an embodiment of the present invention, a method is provided, comprising: providing an electronic circuit comprising at least a DC-DC converter; establishing a sleep signal associated with powering down the electronic circuit into a sleep mode; Turning off the DC-DC converter in response to the establishment of a sleep signal; Establishing a PLL clock counter to count the number of PLL clock cycles between the time when the sleep signal rises and the time when the DC-DC converter is turned off; Maintaining the value of the PLL clock counter during sleep mode; A time value established based on the maintained PLL clock counter value is subtracted from a predetermined delay associated with when to wake the electronic circuitry to exit the sleep mode.

[0014] According to an embodiment of the present invention, there is provided a circuit, comprising: a port for receiving a first signal and coupling to a circuit; A PMOS gate and an NMOS gate electrically connected in parallel to the port and each connected to each other; a first portion of the circuit electrically connected to the PMOS gate; and The second part of the circuit is electrically connected to the NMOS gate; wherein, The ports function in the same manner as if the PMOS gate and NMOS gate were not present; and The first and second parts of the circuit now have twice the voltage threshold of the port.

[0015] According to an embodiment of the present invention, a method is provided, comprising: providing a port for receiving a first signal and coupled to the circuit; providing a PMOS gate and an NMOS gate electrically connected in parallel to the port and each connected to each other; providing a first portion of the circuit electrically connected to the PMOS gate; and providing a second portion of the circuit electrically connected to the NMOS gate; wherein, For a slow rising transition in the first signal, the actual input voltage has risen by the threshold voltage of the NMOS gate before the first node between the NMOS gate and the second portion of the circuit begins to rise in voltage and then becomes conductive; When the gate connection of the NMOS gate is connected to the drain connection of the PMOS gate, the voltage of the first node lags the voltage of the second node between the PMOS gate and the first portion of the circuit; The effect between the NMOS gate and the PMOS gate is a falling transition in the first signal.

[0016] According to an embodiment of the present invention, a method is provided, comprising: providing a first MOSFET including a first drain, a first gate, a first source and a first substrate connection portion; providing a second MOSFET including a second drain, a second gate, a second source, and a second substrate connection portion; providing a first port electrically connected to the first gate, the second gate, and the first substrate connection portion; providing a second port electrically connected to the first drain; and A third port electrically connected to the second source electrode and the second substrate connection portion is provided; wherein, The first MOSFET and the second MOSFET are identical and are one of an n-channel MOSFET and a p-channel MOSFET.

[0017] According to an embodiment of the present invention, there is provided a transconductance operational amplifier, comprising: At least one differential pair of composite MOSFETs, each composite MOSFET comprising: A first MOSFET, comprising a first drain, a first gate, a first source and a first substrate connection portion; A second MOSFET, comprising a second drain, a second gate, a second source, and a second substrate connection portion; a first port electrically connected to the first gate, the second gate and the first substrate connection portion; a second port electrically connected to the first drain; A third port electrically connected to the second source electrode and the second substrate connection portion; and The electrical connection portion is located between the first source and the second drain; wherein, The first MOSFET and the second MOSFET are of the same type and are at least one of an n-channel MOSFET and a PMOS MOSFET.

[0018] According to an embodiment of the present invention, there is provided a current mirror, comprising: First to fourth composite MOSFETs, each composite MOSFET includes A first MOSFET, comprising a first drain, a first gate, a first source and a first substrate connection portion; A second MOSFET including a second drain, a second gate, a second source, and a second substrate connection portion; and The third MOSFET is arranged between the first MOSFET and the second MOSFET, and includes a third drain, a third gate, a third source and a third substrate connection portion; wherein, The first port is electrically connected to the first gate, the second gate, the third gate and the first substrate connection portion; The second port is electrically connected to the first drain; The third port is electrically connected to the second source electrode and the second substrate connection portion; The third drain is connected to the first source; A third source is connected to the second drain; and The third substrate connection portion is connected to the third drain, so that the bias voltage of the third n-channel MOSFET is between the bias voltages of the first n-channel MOSFET and the second n-channel MOSFET; wherein, The first MOSFET, the second MOSFET, and the third MOSFET are all n-channel MOSFETs or p-channel MOSFETs.

[0019] According to an embodiment of the present invention, there is provided a circuit, comprising: Unbiased differential (exponential) transconductance stage, including: A pair of differential signal input ports; A first NMOS gate and a second NMOS gate, both coupled to one of the differential signal input ports; The first PMOS gate and the second PMOS gate are both coupled to one of the differential signal input ports; wherein, or: The source of each of the first NMOS transistor and the second NMOS transistor and the source of the first PMOS gate and the second PMOS gate are all connected together; or The sources of the first NMOS transistor and the second NMOS transistor are connected together at a first node of the circuit, and the sources of the first PMOS gate and the second PMOS gate are connected together at a second node of the circuit.

[0020] According to an embodiment of the present invention, there is provided an operational amplifier comprising an unbiased differential (exponential) transconductance stage, the transconductance stage comprising: A pair of differential signal input ports; A first NMOS gate and a second NMOS gate, both coupled to one of the differential signal input ports; The first PMOS gate and the second PMOS gate are both coupled to one of the differential signal input ports; wherein, or: The source of each of the first NMOS transistor and the second NMOS transistor and the source of the first PMOS gate and the second PMOS gate are all connected together; or The sources of the first NMOS transistor and the second NMOS transistor are connected together at a first node of the circuit, and the sources of the first PMOS gate and the second PMOS gate are connected together at a second node of the circuit.

[0021] According to an embodiment of the invention there is provided a voltage source forming part of an electronic circuit, comprising: a current source; and A plurality of transistors are arranged along a ladder of N electrical nodes; wherein, Node 0 is ground; A gate of an i-th transistor among the plurality of transistors is connected to a node (i-1); A source of an i-th transistor among the plurality of transistors is connected to a node i; The drain of the i-th transistor of the plurality of transistors is connected to the node (i+1); and A current source is provided in the gap left in the current path between node 0 and node 1 .

[0022] According to an embodiment of the present invention, there is provided a method of providing a voltage source forming part of an electronic circuit, comprising: A plurality of N native transistors are provided in a series array; wherein, A source of a native transistor i among a plurality of N native transistors is coupled to a drain of a native transistor (i-1) among a plurality of N active transistors, where i=2, ..., N; A source of a first native transistor of the plurality of N native transistors is coupled to ground; A substrate of a native transistor j of a plurality of N native transistors is coupled to ground, where j=1, ..., N; and The gate of native transistor k among the plurality of N native transistors is coupled to a node located between the source of transistor (k-1) among the plurality of N active transistors and the drain of native transistor (k-2) among the plurality of N active transistors, where k=3,…,N and k is an integer.

[0023] According to an embodiment of the present invention, there is provided a method for providing a low voltage dropout regulator for an electronic circuit, comprising: Provide a high impedance reference voltage source; A pair of first transistors is provided to isolate the output of the reference voltage circuit from any digital noise fed from the source of the second transistor to the gate of the second transistor; wherein, A first upper transistor and a first lower transistor are arranged in series between an upper power rail and ground; The drain of the first upper transistor is connected to the upper power rail and the source of the first lower transistor is connected to ground; The gate of the second transistor, the source of the first upper transistor, and the drain of the first lower transistor are all coupled to a common node; and A high impedance reference voltage source is coupled to the gate of the first lower transistor and the gate of the first upper transistor.

[0024] According to an embodiment of the present invention, there is provided an electronic circuit comprising: a plurality of electronic circuit elements; and Dynamically biased preamplifier with latching comparator, including: An NMOS input differential pair is provided between a pair of differential input ports; A PMOS input differential pair disposed between the pair of differential input ports; and The dynamic bias circuit is coupled to the sources of the PMOS input differential pair.

[0025] Other aspects and features of the present invention will become apparent to those of ordinary skill in the art by reviewing the following description of specific embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0027] Figure 1 Describes the application of UWB transmitters, receivers and systems according to embodiments of the present invention;

[0028] Figure 2 depicts a block diagram of a UWB transmitter according to an embodiment of the present invention;

[0029] Figure 3A Depicts a block diagram of a UWB transmitter supporting dual-phase phase scrambling according to an embodiment of the present invention;

[0030] Figure 3B depicts a block diagram of a UWB transmitter employing dynamically configurable and programmable pulse sequences in accordance with an embodiment of the present invention;

[0031] Figure 3C Schematically depicting a multi-pulse symbol UWB protocol according to an embodiment of the present invention;

[0032] Figure 4 depicts a block diagram of a UWB receiver according to an embodiment of the present invention;

[0033] Figure 5 Depicts a receiver circuit schematic of a UWB receiver / transceiver according to an embodiment of the present invention;

[0034] Figure 6 Depicts a circuit schematic diagram of a UWB transceiver according to an embodiment of the present invention;

[0035] Figure 7 schematically depicts the use of a counter maintained during a deep sleep level to be subtracted from an additive delay in an exemplary timing scenario of UWB radio waves according to an embodiment of the present invention;

[0036] Figure 8 depicts a CMOS crossbar current reduction stage connected to a conventional Schmitt trigger in accordance with an embodiment of the present invention;

[0037] Fig. 9A A UWB receiver according to an embodiment of the present invention is depicted;

[0038] Fig. 9B depicts a "composite MOSFET" according to an embodiment of the present invention;

[0039] Fig.10 Depicts a schematic diagram of a current mirror using the composite MOSFET of FIG. 9 according to an embodiment of the present invention;

[0040] Fig.11 Depicts a full circuit schematic of a custom current source including a reference circuit according to an embodiment of the present invention;

[0041] Fig.12 and Fig.13 Describes an embodiment of the present invention Fig.11 The spread of the custom current source and the final desired "flatness";

[0042] Fig.14 Describes the embodiment of the present invention relative to the use of Fig.10 The hysteresis transfer function of the composite MOSFET transconductance operational amplifier (OTA) for a small differential input signal is depicted;

[0043] Fig.15 and Fig.16 depicts simulation results of a transconductance operational amplifier in a unity gain configuration according to an embodiment of the present invention;

[0044] Fig.17 shows the output from an OTA according to an embodiment of the present invention with a DC voltage offset between the inputs;

[0045] Fig.18 depicts simulation results of a transconductance operational amplifier according to an embodiment of the present invention, the transconductance operational amplifier exhibiting an open-loop gain of 76 dB and a gain-bandwidth product of 25 MHz;

[0046] Fig.19 depicts a power spectral density of a noise simulation of a transconductance operational amplifier according to an embodiment of the present invention;

[0047] Fig. 20 depicts rise time / fall time simulation results of a transconductance operational amplifier according to an embodiment of the present invention;

[0048] Fig.21 An exemplary schematic diagram of an operational amplifier employing an unbiased low power differential (exponential) transconductance stage in accordance with an embodiment of the present invention is depicted;

[0049] Fig. 22 Describes an embodiment of the present invention. Fig.21 Depicted is the DC transfer function of an operational amplifier employing an unbiased low-power differential (exponential) transconductance stage with an open-loop DC gain of ~85dB and an input range between V_SS+0.2V and V_DD-0.7V;

[0050] Fig.23Describes an embodiment of the present invention. Fig.21 Depicted are continuous current results for an operational amplifier employing an unbiased low-power differential (exponential) transconductance stage;

[0051] Figure 24 to Figure 27 Describes an embodiment of the present invention. Fig.21 Depicted are transient operating results of an operational amplifier employing an unbiased low power differential (exponential) transconductance stage;

[0052] Fig.28 Describes an embodiment of the present invention Fig.21 Transient power consumption of the transconductance stage in ;

[0053] Fig.29 depicts a MOSFET circuit according to an embodiment of the present invention;

[0054] Fig.30 Depicts an exemplary circuit layout employing a native / negative threshold MOSFET totem according to an embodiment of the present invention;

[0055] Fig.31 and Fig.32 Depicted Fig.30 DC response and DC analysis of the depicted native / negative threshold MOSFET totem;

[0056] Fig.33 depicts a resistor ladder having a power supply dependent on a reference ladder according to an embodiment of the present invention;

[0057] Fig.34 Depicts the reference voltage expansion versus temperature for a native / negative threshold MOSFET totem according to an embodiment of the present invention;

[0058] Fig.35 Depicted Fig.33 Transient noise performance of an exemplary native / negative MOSFET totem depicted;

[0059] Fig.36 Depicts an exemplary schematic diagram of an ultra-low power low dropout regulator according to an embodiment of the present invention;

[0060] Fig.37A depicts a self-contained dynamic comparator circuit according to an embodiment of the present invention; and

[0061] Fig.37B A regenerative latch according to an embodiment of the present invention is depicted to provide context for an innovative ultra-low power low dropout regulator. DETAILED DESCRIPTION

[0062] The present invention relates to an ultra-wideband wireless communication system, and more particularly to an ultra-wideband transmitter and an ultra-wideband receiver for such an ultra-wideband wireless communication system.

[0063] The following description provides only exemplary embodiments and is not intended to limit the scope, applicability or configuration of the present disclosure. On the contrary, the following description of the exemplary embodiments will provide an enabling description for implementing the exemplary embodiments to those skilled in the art. It should be understood that various changes may be made to the functions and arrangements of the elements without departing from the spirit and scope set forth in the appended claims.

[0064] 0. Pulse radio ultra-wideband system

[0065] As mentioned above, the above-mentioned UWB provides many potential advantages, such as high data rate, low cost implementation and low transmit power, ranging, multipath immunity and low interference. The regulations of the Federal Communications Commission (FCC) on UWB reserve unlicensed frequency bands between 3.1 GHz and 10.6 GHz for indoor UWB wireless communication systems, where low regulated transmit power allows such UWB systems to coexist with other authorized and unauthorized narrowband systems. Therefore, limited spectrum resources can be used more efficiently. On the other hand, the capacity of UWB systems with their ultra-wide bandwidth for short-range applications is much higher than that of current narrowband systems. Two possible technologies for implementing UWB communication are impulse radio (IR) UWB and multi-carrier or multi-band (MB) UWB. IR-UWB utilizes the transmission of ultra-short (nanosecond order) pulses, but in some cases, in order to increase processing gain, more than one pulse represents a symbol. In contrast, MB-UWB systems use orthogonal frequency division multiplexing (OFDM) technology to transmit information on each sub-band in the sub-band. Although OFDM has several desirable properties, including high spectral efficiency, robustness to RF and multipath interference. However, it has several disadvantages, such as up-conversion and down-conversion, the need for mixers and their associated high power consumption, and is very sensitive to frequency, clock, and phase inaccuracies. Similarly, nonlinear amplification destroys the orthogonality of OFDM. Therefore, MB-UWB is not suitable for low-power and low-cost applications.

[0066] In contrast, IR-UWB has several advantages, including unlicensed use of several gigahertz of spectrum, providing great flexibility in spectrum usage, and adaptive transceiver design can be used to optimize system performance based on data rate, operating range, available power, required quality of service, and user preferences. In addition, multi-Gb / s data rate transmissions are possible over very short distances, and due to the ultra-short pulses within IR-UWB, it is very robust to multipath interference, and in some implementations, more multipath components can be resolved at the receiver, resulting in higher performance. In addition, ultra-short pulses support sub-centimeter ranging, while the lack of up- and down-conversion allows for reduced implementation costs and lower power transceiver implementations. Beneficially, the ultra-short pulses and low-power transmissions make IR-UWB communications difficult to eavesdrop on.

[0067] As follows Figure 2 The IR-UWB transmitter described in relation to an embodiment of the present invention in FIG. 3 utilizes a pulse generator and then an on-demand oscillator, respectively, to up-convert the pulses from the generated pulses while avoiding the need for a separate mixer. Both the pulse generator and the on-demand oscillator can be digitally tuned by being implemented in standard CMOS logic to provide control over the pulse bandwidth and center frequency. In addition, by utilizing a digitally controlled ring oscillator for the on-demand oscillator, the IR-UWB transmitter is designed to allow very fast frequency adjustments on the order of the pulse repetition rate (PRR). Advantageously, the technology provides the same advantages as MB-OFDM in terms of spectrum configurability, which is achieved by sequentially changing the transmit spectrum using a frequency hopping scheme, while maintaining the advantages of IR-UWB. In addition, by providing an advanced duty cycle with a fast power-up time combined with on-off shift keying (OOK) modulation, the IR-UWB according to an embodiment of the present invention allows for significant reductions in power consumption by utilizing the low duty cycle of the UWB symbol and only half of the symbol requiring energy to be transmitted.

[0068] In addition to defining the operating frequency range of the UWB system, different regulatory agencies specify and enforce specific power spectral density (PSD) masks for UWB communications. The PSD mask that can be used for embodiments of the present invention is the FCC mask, for which the following Table 1 summarizes the mask data for the range of 3100MHz-10600MHz (3.1GHz-10.6GHz). Table 1: Indoor and outdoor FCC masks for different frequency bands

[0069] Therefore, it is clear that the upper limit of -41.3dB / MHz in the 3.1GHz-10.6GHz frequency range is the same as the limit imposed on unintentional radiation at a given frequency in order not to interfere with other radios. Basically, for a given frequency, the UWB radio operates at an allowed noise level, which is in the E p , transmission energy per pulse, maximum spectrum power S, bandwidth B, bit rate R b and the number of pulses per bit N ppb The relationship presented in formula (1) is generated between them. E p ·N ppb ·R b ≤S·B (1)

[0070] IEEE has published some standards for the physical layer (PHY) of UWB radios in personal area networks (IEEE 802.15.4a-2007), body area networks (IEEE802.15.4a-2007), and radio frequency identification (IEEE 802.15.4f-2012). These standards mainly use relatively large pulses, resulting in relatively narrow bandwidths that are upconverted to a specific center frequency in order to fill a predetermined channel. Data is encoded using pulse position modulation (PPM), and dual phase shift keying (BPSK) is used to encode redundant data. Each bit consists of one or more pulses that are phase-scrambled according to the target data rate. These standards allow for considerable flexibility in channel availability and data rates. The standards also define the preamble, header, and ranging protocol for the data packet.

[0071] These IEEE standards were designed with multiple users in mind, using different channels to transmit data, thus imposing strict constraints on the pulse bandwidth and limiting the energy transmitted. The prior art regarding non-standard transmitters attempts to make better use of the available spectrum by using narrow pulses, thus having a larger bandwidth, thereby increasing the maximum transmitted energy according to equation (1). Therefore, these transmitters are non-standard and are also designed for different data rates, frequencies, pulse widths, etc. In addition, they also use various coding schemes, most notably PPM, OOK or BPSK.

[0072] In the work described below, the inventors have established improvements to UWB systems, UWB transmitters, and energy-based UWB receivers that are capable of generating and adapting to a variety of IR-UWB pulse and bit encoding schemes, thereby supporting communications from both IEEE-compliant and non-standard IR-UWB transmitters. These improvements are made to UWB transmitters, UWB receivers, UWB transceivers and UWB systems, such as those described and depicted by the inventors in the following documents: WO / 2019 / 000075UWB "Energy Efficient Ultra-Wideband Impulse Radio Systems and Methods" (PCT / CA2018 / 000,135 filed on June 29, 2018); WO 2016 / 191851 "Systems and Methods for Spectrally Efficient and Energy Efficient Ultra-Wideband Impulse Radio with Scalable Data Rates" (PCT / CA2016 / 000,161 filed on May 31, 2016); and WO / 2015 / 103,692 "Systems and Methods Related to Ultra-Wideband Broadcasting Including Dynamic Frequency and Bandwidth Hopping" (PCT / CA2015 / 000,007 filed on January 7, 2015).

[0073] 1.IR-UWB transmitter circuit

[0074] refer to Figure 2 , schematically depicts an exemplary architecture of an IR-UWB transmitter 200 according to an embodiment of the present invention, which consists of five main blocks plus an antenna. First, when the data signal from the AND gate 210 is high based on the control signal provided to the AND gate 210, the pulse generator 230 generates programmable pulses at clock intervals. Then, the pulses from the pulse generator 230 are up-converted by the programmable multi-loop digitally controlled ring oscillator (DCRO) 240. Then, the output from the DCRO 240 is coupled to the variable gain amplifier (VGA) 250 to compensate for any frequency dependence of the pulse amplitude. Finally, the driver 260 feeds the antenna 270 to overcome typical packaging parasitics, such as parasitics caused by packaging the transceiver in a quad flat no-lead (QFN) package. In order to further reduce the power consumption of the IR-UWB transmitter (IR-UWB-Tx) 200 according to an embodiment of the present invention, the power cycle controller 220 dynamically turns these functional blocks on or off when the data signal is low.

[0075] Reference now Figure 3A , schematically depicts a block diagram 300 of an exemplary IR-UWB transmitter supporting dual-phase phase scrambling according to an embodiment of the present invention. Figure 2Compared to the IR-UWB transmitter 200 without dual-phase phase shift for IR-UWB according to an embodiment of the present invention, the dual-phase phase shift IR-UWB (BPS-IR-UWB) transmitter is not composed of five main blocks plus the antenna, but includes 6 main blocks. First, when the data signal from the AND gate 310 is high based on the control signal provided to the AND gate 310, the pulse generator 330 generates programmable pulses at clock intervals. The pulses from the pulse generator 330 are then up-converted using a programmable multi-loop digitally controlled ring oscillator (DCRO) 340. The output from the DCRO 340 is then coupled to a dual output amplifier (VGA) 350 to compensate for any frequency dependence of the pulse amplitude and also produce a dual-phase shifted output signal coupled to a switch 360, which selects one of the two signals to be coupled to the output power amplifier (driver) 380 under the action of a switch control signal "S" applied to the switch 360. Note that a similar phase selection scheme can be implemented by affecting the start condition of the DCRO 340 to provide two phases. This would eliminate the need for switch 360 at the expense of adding a control enable condition control signal on DCRO 340 .

[0076] The output power amplifier 380 feeds the antenna 370, thereby overcoming typical packaging parasitics, such as those resulting from packaging the transceiver in a quad flat no-lead (QFN) package. In order to reduce the power consumption of the BPS-IR-UWB transmitter represented by the block diagram 300 according to an embodiment of the present invention, the power cycling controller 320 dynamically switches these functional blocks on or off when the data signal "PC" is at a low level. Therefore, the BPS-IR-UWB transmitter according to an embodiment of the present invention transmits pulses with or without phase shift based on the control signal "S" applied to the switch 360. If this control signal is now fed from a random data generator or a pseudo-random data generator, the resulting pulses coupled to the antenna of the BPS-IR-UWB transmitter will be pseudo-randomly or randomly phase shifted.

[0077] Reference now Figure 3B, schematically depicts a block diagram 3000 of an exemplary IR-UWB transmitter according to an embodiment of the present invention. As depicted, the pulse mode block 3010 maintains the configuration of the pulse for representing the current symbol. Multiple phases are generated by a delay locked loop (DLL) 3030 according to the symbol rate clock (i.e., 20 MHz). The rising edge of each clock phase represents the beginning of a pulse in the symbol pulse beam. The multiplexer 3020 is triggered by the edge of the clock phase and selects the configuration of the current pulse from the pulse mode block 3010. The pulse generator (Pulser) 3050 generates a pulse with a pulse width set by the multiplexer 3020, and enables a digitally controlled oscillator (DCO) 3040 and a power amplifier (PA) 3060. When enabled, the DCO 3040 generates a Gaussian shaped pulse with a frequency set by the multiplexer 3020, which is then amplified by the PA 3060 and radiated by the antenna 3070.

[0078] Thus, the pulse pattern block 3010 establishes pulses for a symbol or sequence of symbols. In this manner, the update pulse pattern block 3010 adjusts the pulse sequence for each symbol, and thus, the pulse pattern block 3010 may be dynamically updated based on one or more factors, including but not limited to network environment data, a predetermined sequence, date, time, geographic location, signal-to-noise ratio (SNR) of a received signal, and regulatory masks.

[0079] refer to Figure 3C , schematically depicting a multi-pulse symbol UWB protocol according to an embodiment of the present invention. Referring to the first image 3100A, a bit 3160 is depicted comprising a series of sub-pulses 3160A to 3160C, each sub-pulse being at a frequency f1; f2; f3. Thus, a multi-pulse spectrum 3180 of the symbol (bit 3160) is depicted in the second image 3100B, which is conceptually obtained by adding the individual pulse spectra of the sub-pulses 3160A to 3160C (phase scrambling is omitted for clarity), which increases bandwidth while increasing the total symbol duration while maintaining maximum power below the UWB mask 3120 compared to the single-pulse prior art approach. This allows symbol energy to be maximized while relaxing the timing requirements and synchronization levels required by the receiver. Any number of pulses with different sets of parameters can be included in the beam to tailor the pulse spectrum to meet given requirements.

[0080] 2.IR-UWB Receiver

[0081] refer to Figure 4, schematically depicts the architecture of an IR-UWB receiver 400 according to an embodiment of the present invention. Thus, a signal from an IR-UWB transmitter is received via an antenna 410 and coupled to a low noise amplifier (LNA) 420, and then to a first amplifier 430, where the resulting signal is squared by a squaring circuit 440 in order to evaluate the amount of energy in the signal. The output of the squaring circuit 440 is then amplified by a second amplifier 450, integrated by an integrating circuit 460, and evaluated by a flash ADC 470 to generate an output signal. A power cycling controller 480 is also depicted, which is coupled to Figure 2 In a similar manner to the power cycle controller 220 of the IR-UWB transmitter 200, the LNA 420, the first amplifier 430 and the second amplifier 450, the square circuit 440 and the flash ADC 470 are dynamically powered on and off respectively to further reduce power consumption according to circuit requirements.

[0082] refer to Figure 5 , depicts a schematic diagram of a receiver 500 according to an embodiment of the present invention. The RF signal from the antenna 510 is initially amplified by a low noise amplifier (LNA) 520 and then passed to a two-stage RF amplifier (AMP1) 530. The first square mixer (MIX1) 540 multiplies the signal by itself to convert to an intermediate frequency (IF). The three-stage variable gain amplifier (VGA) 550 further amplifies the signal and implements a bandpass filter function. The VGA 550 output is then coupled to a second square mixer (MIX2) 560, which down-converts the signal to a baseband frequency. The processing circuit 580 includes a pair of parallel integrators (INT1 and INT2) that sum the signal energy, which is digitized by analog-to-digital converters (ADC1 and ADC2) within a digital processor (not depicted for clarity).

[0083] 3.IR-UWB Receiver

[0084] As described in WO / 2019 / 000075 and WO 2016 / 191851, the inventors established design parameters of millisecond range startup time from sleep mode and microsecond range startup time from idle mode by establishing a custom integrated DC / DC converter and duty cycle transceiver circuit, which can achieve fast circuit startup / shutdown at low (1kbps) and medium data rates (10Mbps) to obtain optimal power consumption.

[0085] In order to maintain good energy efficiency, the components of the overall UWB transceiver (such as those according to embodiments of the present invention) Figure 6 The transceiver 600 depicted in FIG. 6 has been designed for low quiescent sleep current and fast startup / sleep times. Figure 6 , battery (3.0V≤V BATT ≤3.6V) (not depicted for clarity) powers the low frequency crystal oscillator 615, the sleep counter 620, and the bandgap reference 610, which are all generally always operational, although the bandgap reference 610 can be duty cycled in other embodiments of the invention without changing the scope of the claimed invention. Their power consumption limits the minimum power consumption of the system to sub-microwatt levels. When the system is not in sleep mode, the integrated step-down DC-DC converter 605 is powered by the battery, and this provides the supply voltage to the rest of the system with high conversion efficiency. The startup time of the DC-DC converter 605 is on the order of several symbol periods in order to minimize wasted energy. Between sleep cycles, the PLL 655 is activated to provide a basic clock for the system. The receiver 625 and the DLL 660 have dedicated power-off controllers and are only activated during frame transmission / reception. In addition, the transmitter also performs power cycling through its all-digital architecture, which is not described as having a separate controller. Since the basic clock is low (e.g., 20MHz), the power consumption of the digital synthesis module is low.

[0086] In principle, a power-cycling transceiver achieves linear scaling of power consumption with data rate, thus achieving constant energy efficiency. With a fixed frame size, multiple data rates are obtained by adjusting the length of the sleep period, where the maximum achievable data rate is determined by the symbol rate in the frame itself. To preserve energy efficiency, the power consumption during sleep must be lower than the average power consumption. For high data rates, the PLL does not need to be powered down when its power consumption does not significantly reduce the overall efficiency. For low data rates, the entire system can be shut down during sleep mode, except for the bandgap reference, crystal oscillator, and sleep counter. In this case, the millisecond range startup time of the PLL may be insignificant compared to the sleep period, and the overall efficiency will not be significantly reduced.

[0087] As depicted, the UWB transceiver 600 also includes a receive / transmit switch 690 coupled to the antenna to selectively couple the transmitter 6000 or the receiver 625 to the antenna during transmission and reception, respectively. The UWB transceiver 600 also includes a spectrum configuration circuit 665 (equivalent to Figure 3BThe UWB transceiver 600 may include a pulse pattern 3010 in the transmitter 3000, a PHY processing circuit 650, a link controller 645, a buffer and interface circuit 640, an analog-to-digital converter (ADC) 630, a multiplexer (MUX 670), a pulse generator 675, a mixer 680, and a power amplifier (PA) 685, and a PHY formatting circuit 635. The UWB transceiver 600 communicates with the client 695 via the link controller 645. In this way, the link controller 645 may communicate with the client 695 using, for example, a wired protocol.

[0088] 4. Crystal clock drift compensation

[0089] The inventors achieve ultra-low power consumption in the UWB transmitter, UWB receiver and UWB transceiver described in WO / 2019 / 000075 and WO 2016 / 191851 through basic design considerations of the electronic circuits themselves, the use of low-frequency clocks and the implementation of active sleep cycles of parts of the electronic circuits depending on the state of the device and those parts of the electronic circuits required to perform specific functions in each state.

[0090] In these devices, a phase-locked loop (PLL) generates a high-speed clock that operates significantly faster than a crystal oscillator, providing the underlying fundamental frequency of the electronic circuit. Therefore, instead of using a high-power high-frequency clock and dividing it to generate the required sub-clocks, the electronic circuit uses the PLL to up-convert the low-power low-frequency clock and generate the required sub-clocks.

[0091] However, when an electronic circuit enters a low power consumption mode, even a DC-DC converter such as Figure 6 In the embodiment of the present invention, the DC-DC converter 605 in the embodiment of the present invention is powered off in a state referred to by the inventors as "DCDC sleep", the PLL clock signal is not propagated to the digital part of the electronic circuit and therefore cannot be used to determine when to wake up the electronic circuit again and therefore wake up the radio waves including these electronic circuits. In this DCDC sleep, the only clock propagated is the 32kHz crystal clock signal, which, if used alone, will provide an error of possibly more than 30s as to when to wake up the electronic circuit and the radio waves. Although other "deep" sleep power modes of the wireless circuit according to embodiments of the present invention may exist, the solution described herein addresses the current situation and these deep sleep modes. The limitation is that in the sleep mode to which the present invention relates, there is no longer a PLL clock to implement the digital circuit containing the PLL clock counter.

[0092] Therefore, to alleviate this problem, a PLL clock counter is implemented which counts the number of PLL clock cycles between the moment the signal to go to sleep rises and the moment the DC-DC converter is actually turned off. Due to the design of the electronic circuit, this is always at a predetermined edge of the next crystal clock cycle, e.g. Figure 7 The value of this counter is retained during the deep sleep level and after the DC-DC converter wakes up, Figure 7 In scenario #1, the transceiver wake-up delay is 710 and Figure 7 The additional delay marked as delay 720 under scenario #2 in FIG. 2 is subtracted. Therefore, the sleep duration of the electronic circuit and the radio wave is now independent of the point within the crystal clock cycle when the sleep signal rises and the electronic circuit and the radio wave are turned off. Although embodiments of the present invention have been described with respect to a 32kHz clock as described in WO / 2019 / 000075 and WO 2016 / 191851, it is clear that other basic clock frequencies may be employed and the method described is also independent of the phase of the clock (e.g. a crystal clock). The DC-DC converter is turned off at a predetermined edge of the crystal clock cycle.

[0093] 5.CMOS cross current reduction stage

[0094] In UWB transmitters, UWB receivers, and UWB transceivers utilizing complementary metal oxide semiconductor (CMOS) technology, it is beneficial that many applications provide ultra-low power consumption as required. Therefore, minimizing the current within the CMOS circuit is a requirement, and any reduction is beneficial to the entire electronic circuit. According to an embodiment of the present invention, in Figure 8 The two-transistor structure identified as transistors M8 and M9 in FIG. 1 is inserted into the input to increase the required fraction of any voltage transition to turn on the transistor of the connected digital input. The two-transistor structure is used to double the effective voltage threshold of the digital input, which has the benefit of reducing crossover current during long voltage transitions at the input. This circuit is also beneficial for a Schmitt trigger and can replace a Schmitt trigger, although it is beneficial to place this circuit before the Schmitt trigger.

[0095] Therefore, reference Figure 8 , the digital input operates in the same way, but now as if the transistors it was connected to previously (i.e., M0 and M1) had twice the voltage threshold. While the two-transistor structure does not actually reduce the leakage current beyond its nominal level, at V gs = 0, it adjusts the energy efficiency during any voltage transition. Therefore, the voltage difference between the electrical nodes pmos_gate and nmos_gate is approximately one times the voltage threshold of the transistors used in the two-transistor structure (i.e., M8 and M9), so as long as the result is above 0 volts, the V of transistors M0 and M1 is set to zero. gs Reduce a voltage threshold. Figure 8 The body contacts of M8 and M9 do not have to be connected to V DD or V SSThese body contacts may alternatively be connected to corresponding sources or drains of transistors M8 and M9.

[0096] Therefore, the result is that for each (slow) rising transition, the actual input voltage will have to rise to the threshold voltage of NMOS M9 before the node nmos_gate starts to rise in voltage, because transistor M9 must first become conductive. Then because its gate is connected to the drain of M8 through the node pmos_gate, the voltage of the node nmos_gate "lags" behind the voltage of pmos_gate. This is because it must wait for the pmos_gate node to further charge the gate of M9 to allow the node nmos_gate to keep the voltage rising during the transition. For the falling transition, between M8 and M9, the roles are simply swapped, and the basic concept is the same.

[0097] Therefore, the main benefit of this design is that when the input voltage is in the middle of a transition and both M0 and M1 are on, the crossover current is reduced, just like the supply voltage is reduced by one transistor V th Likewise, less energy is wasted during slow digital state transitions. A secondary benefit of this two-transistor structure layout is that no transistor gate is directly electrically connected to the input node IN. Figure 8 The transistors M4 and M5 in the input pair do not play any role in the dual transistor structure. In addition, by connecting only the transistor source contacts to the outside of the electronic module, the design is also more robust to ESD damage.

[0098] 6. Body contact cross-coupled transistor stack body pair

[0099] At a high level, the basic concepts described in the following detailed description of this section can be applied to any pair of matched transistors to significantly increase their effective drain impedance, generally to near infinity, and in some regions into the realm of negative impedance. Applications of the inventive concepts include, but are not limited to: Current mirrors / references, where the quality factor of such circuit elements is defined by how little overdrive is required for the current mirror to reach its saturation (high impedance) region and how flat the current response is (i.e., how high the impedance is) for any given voltage; and B) Operational amplifiers (OpAmps), where very high gain and very high energy efficiency can be achieved.

[0100] The present invention is based on two core ideas: 1) stacking a pair of transistors with the same voltage threshold and connecting the body and gate contacts of the transistors on the drain side of the stack together, while connecting the well contacts of the transistors on the source side to their sources or to ground; and ·2) Adjusting the body contacts to produce an unbiased cascode transistor structure with higher output impedance.

[0101] A trade-off of the present inventive concepts is that they cannot be used with large V gs Essentially, the present invention is conceived for near-threshold transistor operation.

[0102] 6A. Overview

[0103] refer to Fig. 9A , depicts a UWB receiver 900A according to an embodiment of the present invention, allowing the UWB receiver 900A to detect pulses received by an antenna 905, which have been transmitted by a transmitter according to an embodiment of the present invention. Thus, the antenna receives a pulsed UWB signal, which consists of a carrier signal that is pulsed according to a fast envelope. The received signal is initially coupled to a low noise amplifier 910, which amplifies the signal, wherein the amplified signal is bandpass filtered by a first filter 915 to suppress out-of-band interference. Optionally, other amplifiers may be present in the RF stage before the mixer 920. For example, the first filter 915 may be a bandpass filter.

[0104] Next, the in-phase quadrature mixer 920 multiplies the received filtered and amplified signal with a square clock, thereby down-converting the pulse to an uncertain intermediate frequency IF1, where the IF1 frequency is the difference between the pulse carrier frequency and the clock frequency. Since the UWB receiver 900A is an energy receiver, the paths are required to be orthogonal (90 degrees out of phase) so that the total energy of the pulse is preserved while separating the in-phase signal I and the quadrature signal Q between the two paths according to the phase difference between the RF signal and the clock. Even if the UWB receiver 900A is not an energy receiver, two paths are required to avoid the scenario of using a single path I or Q, and the received RF signal and the clock are out of phase to not generate a signal in a single path.

[0105] The IF1 signals in the I arm and the Q arm are processed by the first signal processing circuit 940 and the second signal processing circuit 950, respectively. Each of these filters includes an amplifier 925, so that the mixed and down-converted IF1 signals are amplified, and these signals are then filtered by the second filter 930, which is, for example, a sharp low-pass filter or a band-pass filter established according to the UWB frequency band in which the receiver is currently operating. The output of each second filter 930 is then squared by the square operation performed by the first squarer 935 to extract the instantaneous power on the path. The outputs from the first signal processing circuit 940 and the second signal processing circuit 950, respectively, are summed by the summing circuit 945 to be the total instantaneous power. The output of the summing circuit 945 is then coupled to the amplifier stage 955. The amplified signal is then filtered by the third filter 960, squared by the square operation performed by the second squarer 965, and then integrated by the integrator 970. The amplifier stage 955 , the third filter 960 , the second squarer 965 and the integrator 970 form a third signal processing circuit 980 .

[0106] The signal from the summing circuit 945 follows the envelope of the pulse signal with the RF carrier removed. Therefore, without knowing the exact pulse carrier frequency, the signal can still be received while applying sharpening filtering. The amplifiers within each of the first signal processing circuit 940 and the second signal processing circuit 950 and the amplifier of the third signal processing circuit 980 can be fixed gain amplifiers or variable gain amplifiers. In embodiments of the present invention that employ variable gain, variable gain can be employed to amplify the signal to full strength, which is combined with bandpass filtering to allow the removal of narrowband interfering signals.

[0107] The amplifier 925 in each of the first signal processing circuit 940 and the second signal processing circuit 950 is respectively required to amplify the low signal from the mixer 920 for subsequent processing. Therefore, for the UWB receiver according to the embodiment of the present invention, the amplifier 925 has performance requirements such as those listed in the following Table 2. In the following description, the implementation of the amplifier 925 using a transconductance operational amplifier (OTA) is described, which is intended for a commercial factory CMOS process using 0.13μm technology. Table 2: Target OTA performance

[0108] An additional design goal is to establish dominant Laplace poles at approximately 10kHz and 100MHz in an open-loop configuration, although the actual pole locations are only guidelines since the only real requirements for this criterion are stability and equivalent gain-bandwidth (GBW) product (which in this case should be above 10MHz). Furthermore, the primary criterion for establishing the relative figure of merit of this design is power consumption, making it a key differentiating parameter. In the following description, this criterion and the absence of stringent silicon area requirements are motivations for the design decisions used for the OTA.

[0109] 6B. Selected Operational Amplifier (Op-Amp) Circuit

[0110] It is clear that there are different ways to build a circuit that meets the criteria listed in Table 1. The traditional model for an OTA that meets these requirements is a typical 2-stage amplifier with a PMOS differential input pair connected to an NMOS current steering mirror followed by a simple common-source NMOS voltage amplifier. However, using multiple stages on different current branches involves considering and placing at least two poles already specified in the standard list and involves using passive components for compensation, which raises design stability issues. Trying to push the pole of the last stage of such a 2-stage amplifier requires reducing the output resistance as much as possible, since the output capacitance should be at least 500fF. Since the frequency of the output pole follows the simple RC constant law given in equation (1), it is necessary to have a second pole of at least 100MHz (i.e., ω p2 = 628.3Mrad / s) and the capacitance should be at least 500fF and there should be some additional capacitance on the output transistor drain, R O It must be below 3183Ω, which means a tight constraint for power-constrained designs.

[0111] The 3kΩ output impedance means that to charge or discharge the output node by 1 volt, the output current must vary (linearly) by 1 / 3000 of an ampere. Considering the supply voltage is 1.2V, the output current must therefore vary by about 400μA from rail to rail. This is physically impossible without a nominal current source with a minimum quiescent current of 200μA, which at most produces a source current of 200μA when the final regulated voltage is 0.6V and the starting voltage is 0 volts. The gain of the last stage must be very low, so that the PMOS used as the current source of the last stage must be replaced by a resistor, and even then, the required quiescent current of 200μA requires a quiescent power dissipation of 240μW, which in itself exceeds the entire power budget of the OTA. Faced with the impossibility of meeting the target criteria in Table 1 simultaneously with conventional op amp designs, new architectures that can meet all of these criteria must be explored.

[0112] The simplest and most straightforward adjustment to the conventional op amp that can help meet the speed requirement is to insert a common drain as a third stage between the 500fF load and the last voltage amplifier stage, which will produce a much lower output impedance for a given current. Early simulations showed that the required current in each of the last two stages could be reduced to about 40μA, which ensured that the performance criteria combination with respect to pole frequency and quiescent power consumption was no longer out of reach. However, the highly nonlinear impedance of the output of the common-drain stage is suitable for a voltage op amp, not the required transconductance op amp. The difference between the two is the nature of the output signal; one is a voltage and the other is a current, so the current response must be more or less linear for at least half the supply voltage. In addition, for the common-drain stage, three poles are placed instead of two, which further complicates the stability requirements for the unity-gain configuration.

[0113] One way to solve all the multipole instability problems and the power requirements that necessarily follow is to design the OTA as a single current branch. To do this, the OTA must consist of a single differential pair, but with only one dominant pole. This pole must therefore be set as the only dominant pole at only 10 kHz, rather than as a secondary pole at 100 MHz, which makes a significant difference in terms of power requirements and acceptable capacitive loads. Furthermore, in principle, no passive compensation network is required to obtain stability. The requirement for a pole at 10 kHz and a minimum DC gain of 60 dB is due to the need for a gain-bandwidth product of at least 10 MHz. This value becomes the switching frequency of the system, and in the case of capacitive loads, the bias current of the differential pair is narrowed to a limited range of values, around which a preliminary design can be developed. The switching frequency is always limited by equation (2). ω t =g m / C load (3)

[0114] Therefore, due to the parasitic capacitance of the OTA itself, C load Slightly greater than 500fF and ω t Obviously higher than 62.83MHz (2π×10MHz), g m 40 μA / V is sufficient. Due to the sharp current transfer function of the MOSFET in subthreshold operation, this transconductance specification can be achieved with a total bias current of the differential pair below 5 μA. However, due to concerns about noise constraints and distortion, the incremental search for the optimal design started with a bias current of 8 μA.

[0115] When everything is built from a single current branch (or leg), new difficulties arise. The DC gain that was easily obtained with two cascaded stages now becomes more challenging with only a differential pair and a 1.2 volt supply voltage. Further complicating the problem, half of the supply voltage range must fall within the linear operating range of the output and keep the OTA distortion cap below 0.2%.

[0116] Basically there is a way to make a transistor (at its g m The gain of the transistor (when fixed) is doubled to a level beyond what can be achieved with a long MOSFET channel, that is, the effective drain impedance of the transistor is increased (this is the role of the cascode). However, traditional cascode structures provide very small voltage swings in low voltage processes because they have very high overdrive voltages. In addition, traditional cascode stages require additional bias voltages, which must be different from the input signal in the case of differential pairs and must closely follow the common-mode voltage of the input signal to always have the maximum amount of available output voltage. A common compromise to the overdrive problem is to stack two or more transistors in series and connect them to share the same gate voltage. Although the overdrive voltage of this structure is not significantly higher than that of its single transistor equivalent, the benefits of this technology are small and insufficient to meet the requirements of the target OTA. This ineffective increase in gain is increased because only the transistor whose drain is directly connected to the output does not operate squarely in its triode bias region; the drain-source voltage of all other transistors in the stack is too low. If multiple transistors of the same stack must share the same gate voltage (which is necessary for differential pairs in OTAs), the benefits of stacking transistors will inevitably be limited by this effect, unless they all have different voltage thresholds. Therefore, it is convenient and common practice to connect the drain of a first transistor in series to the source of a second transistor with a lower voltage threshold than the first transistor. In this case, the drain-source voltage of the first transistor is much higher, allowing it to operate in or near its saturation region and obtain most of the benefits of cascading without the need for additional bias voltage and with little additional overdrive to the structure.

[0117] However, this method uses additional photolithography masks for additional doping steps, which typically have high variability and will result in multiple V t The threshold voltage difference between the transistors of the stack varies significantly, which in turn makes the cascade performance unreliable and more expensive to manufacture. However, an alternative to this is to operate all transistors at a low overdrive voltage, which allows the voltage threshold of any transistor in the stack to be accurately and reliably shifted. The body contacts of transistors have a variety of uses, most of which involve the back gate effect. This effect produces a shift in the voltage threshold, and as Fig. 9BConnecting the two transistors as depicted (which the inventors call composite MOSFET 900B) allows for the creation of a composite MOSFET structure whose effective gain and output resistance exceed that of any single transistor, regardless of length. Polarizing the transistors in this manner does cause forward polarization of the pn junction in the second transistor, but because the bias current is always limited to very low values ​​under the conditions in which this structure will be used, this forward voltage is rarely higher than 0.2 volts, and the junction leakage is typically less than or about equal in magnitude to the gate leakage of the same transistor, so there is no negative impact on circuit performance. Fig. 9B As depicted, the composite MOSFET consists of a pair of N-channel MOSFETs.

[0118] The inventors have proved through simulation that this is effective in improving the effective gain and output impedance, but Fig. 9B Replacing each individual transistor of the OTA differential pair with an equivalent in will still produce an OTA that is below the target 60 dB gain requirement. Therefore, the composite MOSFET 900B can be further adjusted to significantly increase the gain without significantly increasing the minimum drain-source operating voltage. This adjustment can only be used if the transistor is paired in some way with another identical transistor (which is used in both the differential pair and any current mirrors). Therefore, in order to further increase Fig. 9B In order to reduce the drain impedance of the composite MOSFET 900B in the stack without increasing its minimum channel operating voltage, a third transistor is introduced in an intermediate position in the stack, where the body-source bias voltage of the third transistor must also be between the body-source bias voltages of the two other transistors already present in the stack. To achieve this, the inventors connected the body contact of the middle transistor to its drain, and since its drain voltage is not much higher than its source voltage (because they are squeezed between the two other transistors), the body-source junction voltage of the middle transistor is not high enough for any significant leakage. However, connecting the body contact to the drain of the same transistor makes it behave as weakly as a transistor connected with a diode, because the body contact behaves like a weak gate, and a transistor connected with a diode does not present a high impedance through its drain, which in this case defeats the purpose of having a third transistor. This is where paired transistors come into play, and the disadvantage of the effect of being connected with a diode becomes an advantage. Since paired transistors are meant to behave relative to each other, as Fig.10 The depicted connection of the body contact of the middle transistor to the drain of the middle transistor on the opposite side of the mating transistor stack causes the effect of the diode connection to favor, rather than disadvantage, a higher drain impedance.

[0119] for Fig.10The current mirror shown in FIG. 1 , which reacts to changes in drain voltage in the following manner. An increase in the drain-to-source voltage of transistor M6B causes a slight increase in the current response of that transistor until its source voltage also drops, because M5B and M4B do not provide the same current at this moment. This is the principle behind each cascade branch so far. This slight drop in the absolute source voltage of M6B directly involves an equal increase in the body-source voltage of transistor M5A, which has the effect of slightly lowering the effective voltage threshold of M5A and slightly increasing its conductivity. Therefore, when the conductivity of M5A increases, the current flow in the transistor stack M4A to M6A temporarily increases until its diode-connected gate-source voltage decreases to compensate for it, which in turn reduces the gate-source voltage of the transistor stack M4B to M6b equally. Therefore, an increase in the drain-source voltage on the output side of such a current mirror should cause a proportional decrease in the gate-source voltage of the entire current mirror and compensate for the channel modulation effect of transistor M6B and allow the transistor stack M4B to M6B to present an effective output impedance closer to infinity. In fact, the inventors have experimentally determined that given the correct device dimensions, this output impedance can even be negative. The same general idea is used for the differential input pair, such as Fig.10 The dimensions of transistors in an exemplary embodiment of the present invention are given in Table 3 below. Table 3: Example transistor parameters for OTA

[0120] The decision to use an NMOS differential pair instead of PMOS was based on the fact that this OTA does not have a second current branch, NMOS performance is better, and it was found through simulation that the drain-source voltage required to achieve linear behavior with NMOS is lower. Therefore, a differential pair including NMOS transistors is part of a current branch that puts two NMOS transistors and only one PMOS transistor in the current path, while a PMOS differential pair would be in the opposite situation and, in principle, require a higher operating voltage.

[0121] therefore, Fig.11 The full circuit schematic of the custom current source including the reference circuit is depicted, which also uses the same ideas that inspired the differential pair design, as they are suitable for most low polarization, low speed transistor applications. This provides a current reference with excellent output resistance and very small minimum operating voltage, which is not possible with any prior art current mirror circuit. Table 2 above lists Fig.10 and Fig.11The dimensions of each MOSFET for the two circuits are shown in the table, where the instance names M1 to M6 refer to the two units with the suffixes A and B. The two units match and mean the same, so they hold the same value in the table. "W" refers to the overall width.

[0122] 6C. Current Source Analysis

[0123] In order to benefit from the maximum input and output voltage swings necessary to achieve a good total harmonic distortion (THD) index, current OTAs must have a minimum minimum operating voltage. On the other hand, in order to benefit from the best common-mode rejection ratio (which can also cause distortion), the same current source must sink as constant a current as possible across its output voltage, which corresponds to the highest impedance. These two conflicting requirements involve the need for high-quality current sources.

[0124] Enter Fig.11 I ref The current at the terminal is mainly absorbed by the transistor stack M7A to M9A through the same kind of composite MOSFET structure that is now the hallmark of this OTA. However, simulations have shown that the most "linear" current response to the output voltage is not the flattest response (closest to infinite impedance) at the lowest minimum operating voltage. In other words, the device parameters that keep the impedance constant over the widest voltage range are not the highest possible impedance, but fortunately a negative impedance of about -20MΩ. Therefore, current branches that present a total of +20MΩ when connected to the output can be connected in parallel with the main current source of -20MΩ. Since the current branches do not have to provide the same current as the main current source, but can be much smaller current sources, it is not difficult to achieve an impedance of ~20MΩ. These secondary current sources sink about 95nA through transistor M14 and source about 400nA through M13, and these currents vary slightly to compensate for the negative impedance created by the drain of M9A, which sinks about 7.2μA.

[0125] Bias sensitivity to external factors was not part of the equation when evaluating the OTA design. Transistors M16 to M19 and the 1MΩ ideal resistor form the basic bias source that defines the current in all other branches of the entire OTA, but does not vary much over the supply voltage range. Fig.12 The range of the custom current source for all values ​​of supply voltage is shown, along with the resulting desired "flatness". Fig.13 The current variation over the output voltage range is plotted and the variation is less than 3nA (<400ppm of nominal current) from 120mV to 1V, showing the high performance of this current source in 0.13μm CMOS. The very low overdrive voltage is important to get enough output voltage swing and a good distortion figure at low frequencies.

[0126] 6D. DC analysis

[0127] Given that the ultra-high impedance structure constructed by the custom current source also constitutes the entire OTA, the optimized MOSFET parameters put the OTA in a state where its output impedance is also negative. Fig.10 In Figure 1, resistors Ro1 and Ro2 are added at the output of the OTA to compensate for the negative impedance, but the resistors are left undefined because their optimal values ​​vary depending on the gain factor β of the feedback path. However, for β = 1 (in unity gain configuration), the optimal resistive network impedance is approximately 15MΩ, and the neutral voltage is 0.3V, at which the net current leaving the voltage divider is zero. These two values ​​represent equations (3) and (4) for Ro1 and Ro2 at a desired supply voltage of 1.2V. 3Ro1=Ro2 (5)

[0128] In formula (3), "3 / Ro2" is used to replace "1 / Ro1" to obtain "4 / Ro2 = 1 / 15MΩ", thereby obtaining Ro2 = 60MΩ and Ro1 = 20MΩ. Hereinafter, unless otherwise stated, for all simulation results, by making Ro1 and Ro2 20MΩ and 60MΩ respectively, the total impedance of this voltage divider is Ro = 15MΩ.

[0129] The OTA's inherent negative output impedance in open loop prevents its large signal transfer function from showing a definite, identifiable DC gain. Fig.14 The hysteretic transfer function is depicted from a small differential input signal around Vcm=0.5V, which fortunately only appears in open loop operation. This is because this OTA is not meant to operate in open loop, as the design was performed under the assumption that the OTA will not need to operate in open loop. Although there is no standard defined for OTA design, given that the desired open loop gain must be anything above 60dB and not within a narrow range of values, it itself means that there should be some kind of negative feedback around the OTA so that once integrated into another circuit, the OTA will work as expected, so the above assumption is reasonable. Even without the compensation resistors Ro1 and Ro2, the hysteretic "opening" in the transfer function spans less than 2 millivolts of differential input signals and is completely suppressed even with a weak feedback factor (β<0.01).

[0130] Fig.14 The two relatively constant voltages labeled "PMOS mirror gate" and "differential pair source" in the figure can be used to directly provide clues to the available input common-mode range. A quick simulation at different common-mode voltages up to a nominal value of 0.5V shows that the hysteresis spread is insensitive to the common-mode voltage, so as long as the operating input voltage range is within the range, Fig.14The results of are valid and have nothing to do with Vcm. In addition, Fig.15 and Fig.16 The performance of the OTA in a unity-gain configuration is shown in more detail, along with the extent of its "tight" and "loose" operating ranges. The OTA enters its optimum operating range, where the current is maximized and is stable somewhere above 0.3 volts common mode, because the PMOS mirror gate voltage is constant beyond that point, and the voltage at the source terminals of the differential input pair faithfully follows changes in the input signal. This voltage range ends near 1V, where Fig.15 The transfer function in inevitably starts to decrease.

[0131] also, Fig.16 By drawing Fig.15 The derivative of the output curve can more accurately determine the start and end of the OTA's optimal operating range. The final result shows that the compensation resistor slightly narrows this optimal range, but this is due to a more accurate reproduction of the input signal at the output, as the curve "RO = 15MΩ" is within 50ppm of the ideal unity gain transfer curve. In addition to the hysteresis effect, Fig.16 This indicates an open-loop gain of more than 20 kV / V, or more than 86 dB. This is simply accomplished by separating A from equation (5). open-loop get.

[0132] In the case of simulated open-loop gain that does not require adjustment via compensation resistors, the voltage range is slightly wider without these resistors; at least from 0.3V to 0.92V, with the lower limit reduced to 0.32V with 15MΩ output resistance compensation. This leaves enough range for the half-supply voltage sine wave required to evaluate the distortion index.

[0133] As for the effective offset, due to the hysteresis effect, only Fig.14 The transfer function of cannot accurately determine the effective offset. Therefore, Fig.17 Shows the Fig.13 and Fig.14 The voltage difference between the two inputs is exactly the same. As can be predicted, the offset is a constant +0.4mV over the entire optimal range of the 15MΩ compensation.

[0134] 6E. Communication Analysis

[0135] Without a stable DC bias point at the optimum DC transfer slope, open-loop AC analysis may seem irrelevant. However, to meet the allocation requirements and still perform gain-bandwidth product simulations, small-signal AC simulations were performed with a 0.4mV signal offset (and an output compensation resistor of 15MΩ) to obtain a reasonable bias point. These simulation results are shown in Figure 2. Fig.18As depicted, the open loop gain is 76dB and the GBW is 25MHz. The pole placement is not strictly adhered to, but the low frequency pole at about 4kHz, which must be at 10kHz, is compensated by the very high DC gain and GBW above 10MHz. Looking at the phase plot just below its corresponding magnitude, it can be seen that the phase margin is just below 74 degrees, which is just above the ideal phase margin and is typically obtained with an OTA that has only one dominant pole instead of two.

[0136] The power spectral density of the noise simulation is plotted in Fig.19 , showing that it produces results below the target 100nV / √Hz allowed maximum at 1MHz.

[0137] 6F. Transient Analysis

[0138] All transient analysis of this OTA was performed in unity gain configuration with a compensated output resistor of 15MΩ. Fig. 20 The rise time (~20ns) is shown to be much shorter than the fall time (~200ns), which is contrary to the performance of the conventionally designed OTA. The slew rate of this OTA is also much slower, due to the trade-off of achieving ultra-low current consumption exponentially in any case. Therefore, considering that power consumption is specified as the main (and only) differentiating parameter, and no constraints on slew rate are specified, the trade-off between slew rate and power consumption is relatively straightforward.

[0139] These slew rate indices also show the extent of the voltage swing, e.g. Fig.15 The main difference here is that Fig. 20 shows how quickly a given voltage can be reached. Therefore, if there are no timing constraints, it is reasonable to expect the output signal to swing from ~25mV to ~1.08V without the compensation resistor, or from ~85mV to ~1.08V with 15MΩ compensation. If there are timing constraints, the lower bound can be raised to ~0.2V. This is always in response to a full supply range input signal and discounting distortion. Frequency (kHz) 0.01 10 1000 10000 THD(ppm) 2.183 5.18 3214 301500 Table 4: THD results based on distortion analysis

[0140] Regarding the distortion figure, Table 4 lists the total harmonic distortion values ​​at key signal frequency points when the signal is a 600mVpp sine wave centered at 620mV. The value at 10Hz is used to show that the DC transfer function contributes negligibly to the distortion and only high-frequency effects are responsible for the distortion. The THD at 10kHz is of most interest for the work because in an open loop, THD is most important near the edge of the op amp bandwidth. Therefore, the nominal THD figure (the standard consideration for OTAs) is approximately 0.000518%. Although the open-loop bandwidth is less than 10kHz, the expected bandwidth and frequency of interest for THD is still 10kHz. Such a small figure is due to the very high gain of the OTA itself (even with the compensation resistor). For the last two data points, they show that without sufficient gain and slew rate, the THD figure drops dramatically.

[0141] 6G. Summary

[0142] A potential limitation of this OTA is that the output voltage range may be variable and limited to the input common-mode voltage, but fortunately this is not always the case. In unity-gain configuration, the OTA produces an excellent THD figure in this configuration because the output voltage is directly connected to the input voltage, so it is physically impossible to pull the output voltage below the input voltage. It is clear that the different candidate topologies result in OTAs that exceed the minimum requirement at a moderate silicon area cost, although this was not a design parameter.

[0143] 7. Unbiased low power differential (exponential) transconductance stage

[0144] The innovative concept consists in generating a differential current simply from the voltage difference between the two inputs.

[0145] Fig.21 An exemplary schematic diagram of an embodiment of the present invention is depicted by transistors M0, M1, M4, and M7. Fig.21 In the figure, note that the NMOS transistor is a native transistor, so in V gs It still conducts when it is close to 0 volts.

[0146] The circuit works like two class AB power amplifier stages with the outputs shorted together. When one input has a higher voltage than the other, the transistor it is connected to tends to pull the voltage higher at its source, at which point the NMOS transistor will conduct a little more current and the PMOS transistor will conduct a little less. The opposite is true for the lower voltage input, and if the transistors are perfectly matched, the PMOS at one input will always sink the exact current that the NMOS at the other input sources. If this symmetry exists, then in the first configuration all four transistor sources can be shorted together, just like Fig.26The same is true for the central node (net023) of , since the voltage between all four transistor sources is the same anyway. In a second embodiment of the invention, the source of M4 is connected only to the source (and bulk) of M1, and the sources of M7 and M0 will be part of separate nodes.

[0147] In an embodiment of the present invention, this configuration can be Fig.21 The operational amplifier depicted is implemented in the following manner: when the voltage of the positive input is higher than the voltage of the negative input, the current in transistors M4 and M1 becomes negligible, while the current in M7 and M0 rises exponentially, which pulls node net15 low and node net07 high, starving the PMOS current mirror and overfeeding the NMOS current mirror. Both net15 and net13 have a lower voltage to turn off the output NMOS and turn on the output PMOS.

[0148] Compared with the existing technology, the benefit of this idea is that m The first and most important of these stages is that it has very low quiescent current yet provides large gain and strong current response to large voltage differences. Furthermore, it does so without the need for bias circuitry.

[0149] Figure 22 to Figure 28 The simulation results of the embodiments of the present invention are respectively described, wherein the simulation results include: · Fig. 22 The DC transfer function is plotted, with an open-loop DC gain of ~85dB over the input range of V SS +0.2V to V DD -0.7V; · Fig.23 The continuous current results are depicted with a maximum quiescent current of 500nA and a typical current of only 6nA when the output is saturated; · Figure 24 to Figure 27 depicts transient operation where nonlinear currents allow very steep transitions from 1V to 2V and vice versa (large signal response) where the op amp is optimized with a series resistor with a capacitive load; and · Fig.28 Transient power consumption is depicted where the power consumption is more efficient for a given load.

[0150] 8. Native / Negative Threshold MOSFET Totem

[0151] In exemplary UWB transmitter circuits, UWB receiver circuits, and UWB transceiver circuits according to embodiments of the present invention, there is a need for a voltage reference. However, current consumption of prior art techniques such as those employing "bandgap" reference modules is as low as hundreds of nA. Therefore, it would be beneficial to provide a reference voltage source that consumes only a few nA. Exemplary embodiments of the present invention utilize the ability of native (and depletion mode, i.e., negative Vth) transistors to operate even when their V gs When negative, it also conducts a low but usable current.

[0152] The concept is based on stacking native (or depletion) transistors along a "ladder" of electrical nodes from the ground voltage level to the highest reference voltage required by the circuit. If each node of the ladder is a "rung" numbered from 0 to N (where node 0 is ground), then for a native transistor, the electrical node of its gate is equal to i-1, the electrical node of its source = i, and the electrical node of its drain = i+1, where i is the transistor number from 1 to N. Next, a tunable current source is placed in the gap left in the current path between nodes (rungs) 0 and 1, since there is no -1 node for the gate contact of another native transistor. Tuning of the current source enables a calibrated reference voltage source to pull more or less current through the transistor "ladder", depending on the design of the current source, which can be implemented digitally. Obviously, the tunable current source can be implemented through a range of designs. Beneficially, the design is insensitive to power supply variations due to the significant transistor stacking, and is insensitive to temperature variations, as long as the current source is affected in a similar way to the native transistors in the ladder. Therefore, all that is needed is a calibration process change.

[0153] Considering the original problem, at high voltage (i.e. 3.3V), the digital domain transistors are large due to the need for large thick oxide transistors, which are necessary to keep the quiescent current leakage to reasonable levels (~100s nA instead of ~10s uA). Therefore, deep sleep power consumption is dominated by the bandgap voltage reference circuit and sometimes by the activity and clock on the serial-to-parallel interface (SPI) interface (when used). An initial approach to solving this problem is to replace the 3.3V I / O transistors with 1.8V I / O transistors, which have a minimum channel length (almost half that of 3.3V transistors) but still have the same V th , resulting in the same low channel leakage.

[0154] So in addition to reducing the die area there is also lower parasitic capacitance, thus reducing dynamic power consumption and propagation delay, the latter allowing the use of a faster SPI clock. So even if the digital circuit power is regulated by a linear regulator, the low voltage swing and less charge required to charge the voltage node per unit capacitance further reduces power consumption. Furthermore, lower voltage means that static current leakage is also reduced. However, the operating voltage range of the chip must now be limited to ~1.8V or must be adjusted for thick oxide digital circuits to allow a wider operating range (e.g. up to ~3.6V).

[0155] Therefore, without a voltage regulation solution that will consume only tens of nA or less of quiescent current, there is virtually no saving in the total energy budget, and without proper care, the design may even waste more energy through the solution. Helpfully, the requirements for the regulator are relaxed, namely: Requires extremely low voltage accuracy (it is powering digital circuits) Requires very low current supply (when the radio wave uses full-speed SPI and modem operation, The average value is as high as tens of μA.

[0156] Initially, discrete transistors were considered because the drain current is insensitive to the drain voltage when the transistor is in saturation and is best suited for connection to an external voltage source. In addition, since the source has very low impedance, it is well suited to supply a wide range of current requirements. In addition, by fixing the gate voltage, the source voltage can be suppressed to within a few hundred mV. An exemplary circuit layout using this concept is depicted in Fig.29 middle.

[0157] However, this simple solution also has some disadvantages, which are: Channel modulation effects are additive with each additional stage; Temperature variations in the range of 0 to 85°C cause current variations of multiple orders of magnitude in subthreshold transistors and tend to cause significant variations in the reference voltage; and Output voltage varies significantly with process (~±40%)

[0158] Therefore, the inventors have developed the concept of native transistor totems, where instead of using one current branch for each "boost" in voltage, and since each native transistor for the voltage boost requires a minimum voltage drop that does not overlap each other, they can be connected in series and share the same current. The final voltage at the node depends entirely on the voltage threshold of the native transistor and the current source of the branch. In addition, at V ctrl = 0V, no external voltage reference or precision voltage supply is required. The circuit is depicted in Fig.30 In Fig.31and Fig.32 Describes the V b =V ctrl Time V b DC response and DC analysis.

[0159] Typical analog design issues to consider include: Transient operation stability: Minimum capacitive decoupling is sufficient; Transient noise: ultra-low due to being driven by the transistor source; Sensitivity to voltage supply variations (power supply rejection ratio, PSRR): prevented by compound cascade effect; Temperature changes: These changes are largely compensated by the temperature effects that act opposite to each change and are therefore mostly canceled out; Process variations: These variations cannot be addressed with this approach and therefore require a design solution; Component matching: can be addressed in die layout; and Component aging: This is not a problem as it is caused by components being under high voltage stress for a long time.

[0160] However, process variation is a fixed characteristic and does not change over the life of the integrated circuit, which can be used to account for process variation. An exemplary embodiment for addressing process variation issues is a resistor ladder with a power supply that depends on the reference ladder itself. Such a circuit is Fig.33 This provides several benefits, including: A wide tuning range is covered because the current of the bottom transistor follows an exponential curve of the required control voltage; ·No factory calibration is required, it can be automatically calibrated when the radio wave containing the circuit is turned on; Independent of supply voltage; Includes a negative feedback loop, which further reduces residual temperature induced variations.

[0161] Fig.34 Describes an embodiment of the present invention. Fig.33 The reference voltage expansion vs. temperature of an exemplary native / negative MOSFET totem is depicted, while Fig.35 Depicted Fig.33 The transient noise performance of an exemplary native / negative MOSFET totem is depicted. Fig.33 The compiled characteristics of the depicted exemplary native / negative MOSFET totem are: · Maximum reference voltage extended to ~26mV / 1V; Transient noise is typically ~1mVpp, 2-3mVpp at 85°C; DC current consumption is typically 12nA, with a maximum current of <300nA; and The die area used for decoupling (excluding tuning branches) is ~11 x ~22 m.

[0162] 9. Ultra-low power low dropout regulator

[0163] The radio wave device according to the embodiment of the present invention (as described above, UWB receiver, UWB transmitter and UWB transceiver circuit) supports active dual loop to provide a very low power design. In order to achieve this active power reduction, the internal voltage converter (such as linear voltage reference buffer and DC-DC converter) should also be powered off to achieve a sleep state power consumption of less than one microampere, while ensuring that the SPI interface and all important digital parts of the circuit remain powered. Therefore, these circuit parts on the always-on digital circuit are limited to extremely low leakage current (~100nA), so thick gate oxide input / output transistors must be included. However, since the main operating voltage of the chip ranges from 1.8V to 3.6V, the digital transistors without voltage regulation must be large, thereby occupying a large amount of die area and exhibiting excessive dynamic power consumption. Therefore, the inventors have established an innovative feedback-free low dropout (LDO) regulator that does not have to perform significant voltage regulation, but its output voltage will be low enough and independent enough from the main chip power supply, so that the transistors used to always turn on the digital core are small enough.

[0164] In addition, the lower supply voltage reduces the degree of charging and discharging of all parasitic capacitances required for each digital signal transition, resulting in very low dynamic power consumption. Furthermore, to actually save energy overall, the LDO should have a very low quiescent current (on the order of a few nanoamps), so it does not require or include feedback. Fig.36 The output of the depicted circuit can vary by well over a hundred millivolts, depending on operating conditions, digital core clock rate, and activity, but since this is only powering the digital circuitry, the output voltage accuracy is not particularly important for proper operation of the circuit, as long as the output voltage accuracy does not degrade so low that the circuit becomes too slow. Fig.36 In FIG. 1 , an LDO is shown in the context and is comprised of transistors M15 , M31 , and M32 . As depicted, these transistors are disposed between the reference bandgap circuit and the rest of the digital circuitry.

[0165] Thus, similar to the unbiased low power differential (exponential) transconductance stage described above with respect to Section 7, the first two transistors M15 and M31 embody the equivalent of a CMOS Class AB power amplifier which, with the help of heavy capacitive decoupling (C28), isolates the sensitive high impedance node at the bandgap output from any digital noise fed from the source of the large transistor M32 to its gate. Apart from this noise, the intermediate current branch of transistors M15 and M31 has no activity and only a quiescent current consumption (typically 3nA). This is the only current that prevents the LDO from achieving 100% current efficiency, but isolates the sensitive input node and, since the voltage threshold of the native NMOS M31 is much lower than that of M15, allows a slight voltage increase from the 1.3 volt bandgap output voltage. In this case, the M32 transistor operates in the subthreshold or near-threshold region where the voltage from V gs The transfer function to current is essentially exponential, allowing the current demand to vary by several orders of magnitude from one transient to the next without causing a voltage drop of more than a few hundred mV, although the circuit using the output is not sensitive to this.

[0166] 10. Dynamically biased preamplifier with latching comparator

[0167] exist Fig.37A In the paper, the innovative circuit is depicted as a self-contained circuit, where Fig.37B The regenerative latch depicted in is used only to provide context for the new innovative circuit and explain its functionality.

[0168] When designing a dynamic preamplification stage, a constant challenge for circuit designers is the trade-off between power consumption and accuracy. Due to the unavoidable current noise sources in MOSFETs, especially thermal noise, a large amount of current needs to be sunk through the differential pair of NMOS, PMOS (in this case, both) transistors to "average out" the current noise and provide an accurate comparison. However, the more current is sunk, the higher the energy consumption.

[0169] Therefore, it is useful to reduce g relative to the total current in the differential pair. m (transconductance factor) is maximized. Therefore, reference Fig.37A , solves this problem by providing both NMOS and PMOS input differential pairs (i.e., M0 / M1 and M4 / M5, respectively) that together form a structure similar to a current-starved inverter. Originally, the PMOS transistors were intended to be connected directly to VDD and made slightly weaker than the NMOS transistors so that the output node was eventually pulled low enough to turn on the input transistors of the latch (including M33 and M35). This causes a certain amount of quiescent current to be wasted waiting for the regenerative latch to "make a decision" after the latch's input PMOS transistors are turned on.

[0170] Therefore, in order to solve this problem and the need to adjust the strength (effective width) of the various power supply voltages / reference voltages, a "dynamic bias" technique is implemented for the PMOS differential pair (M4 / M5) instead of the NMOS differential pair (M0 / M1). This will limit the amount of charge absorbed unevenly (by default) between the two PMOS transistors when the differential input voltage (INp-INn) is non-zero, thereby reducing energy consumption, which helps to further amplify the difference between the preamplifier outputs. Through this dynamic bias, as long as the start-up of the PMOS transistor is stronger than that of the NMOS transistor, the voltage of the nodes OUTp and OUTn will remain high until sufficient current is absorbed from the dynamic bias capacitor C10. When C10 is sufficiently consumed and there is not enough V gs To keep the PMOS transistor more strongly turned on than the NMOS transistor, the PMOS transistor changes state from triode to saturation, and the slightest voltage difference between the PMOS transistors will cause one of the PMOS to enter saturation slightly before the other, allowing the drain voltage to be pulled down more quickly. To further amplify the difference between the outputs, the drain (preamp output) voltage will be pulled down faster than its counterpart because of the lower V gs This means that the higher V gs , since they share the same gate voltage, this is "fighting" current. Therefore, one node starts to drop before the other and is also being consumed at a faster rate than its counterpart, which helps produce a comparator circuit that makes more accurate decisions.

[0171] refer to Fig.37A , not to node n well and p well Since it can be connected to any common voltage node or biased, it is obvious that there are multiple options for achieving this, which can be combined with Fig.37A Furthermore, transistors M20 and M21 are optional provided that their drains are shorted to their respective sources before removal and their only purpose is to prevent the OUTp and OUTn nodes from saturating when the PMOS differential pair enters their saturation state (when V ds It is obvious to those skilled in the art that for the sake of clarity, the recharging of nodes OUTp and OUTn to V after the comparison is not described. DD A pair of PMOS transistors are required, which should have their gates connected to the clock "clk" node.

[0172] Alternatively, in another embodiment of the present invention, the common source node for the PMOS transistor can be split into two separate nodes with two separate but equal capacitors. The benefit of this optional configuration is that it may be that the NMOS transistor without dynamic bias actually determines how much current is absorbed from each output node. In this way, a larger output voltage difference or at least an equivalent output voltage difference can be achieved by separating the charge that must be absorbed between the two NMOS transistors, so that one NMOS transistor that absorbs more current does not inadvertently absorb more charge than is intended to be absorbed by the other slower NMOS. Therefore, dumping more charge on a node that is set to drop in voltage before another node will be counterproductive.

[0173] Specific details are given in the above description to provide a thorough understanding of the embodiments. However, it should be understood that the embodiments can be practiced without these specific details. For example, circuits can be shown in block diagrams so as not to obscure the embodiments with unnecessary details. In other examples, well-known circuits, processes, algorithms, structures, and techniques can be shown without unnecessary details to avoid obscuring the embodiments.

[0174] The implementation of the above-mentioned techniques, blocks, steps and devices can be accomplished in various ways. For example, these techniques, blocks, steps and devices can be implemented in hardware, software or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, other electronic units designed to perform the above-mentioned functions and / or a combination thereof.

[0175] For the purpose of illustration and description, the foregoing disclosure of exemplary embodiments of the present invention has been given. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed. From the above disclosure, many variations and modifications of the embodiments described herein will be apparent to those of ordinary skill in the art. The scope of the present invention is limited only by the appended claims and their equivalents.

[0176] In addition, when describing representative embodiments of the present invention, the specification may have provided the method and / or process of the present invention as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific sequence of steps set forth herein, the method or process should not be limited to the specific sequence of steps described. As will be appreciated by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process of the present invention should not be limited to the steps performed in the order written, and those skilled in the art can easily understand that the sequence can be changed and still remain within the spirit and scope of the present invention.

Claims

1. A method comprising: providing an electronic circuit comprising a portion of one of a wireless transmitting circuit, a wireless receiving circuit, and a wireless transceiver circuit for processing a wireless signal; in The electronic circuit comprises a reference voltage source, wherein the reference voltage source comprises: a current source; and A plurality of transistors are arranged along a ladder of N electrical nodes; Node 0 is grounded; A gate of an i-th transistor of the plurality of transistors is connected to a node (i-1); A source of an i-th transistor of the plurality of transistors is connected to a node i; The drain of the i-th transistor of the plurality of transistors is connected to the node (i+1); and The current source is provided in the gap left in the current path between node 0 and node 1 .

2. The method according to claim 1, wherein At least one of the following conditions exists: Each transistor is either a native transistor or a depletion mode transistor; and The reference voltage source also includes a tuning circuit for tuning the current source to allow calibration of the reference voltage source.

3. The method according to claim 1, wherein The reference voltage source also includes a tuning circuit for tuning the current source to allow calibration of the reference voltage source.

4. The method according to claim 1, wherein Each transistor is a depletion mode transistor.

5. The method according to claim 1, wherein The voltage at the node depends on the voltage threshold of the transistor and the current source.

6. The method according to claim 1, wherein controlling the current source disposed in the current path between node 0 and node 1 by controlling a voltage; setting the control voltage according to a selected tap of a multi-tap voltage divider, wherein the voltage divider is coupled between one end of the linear transistor array and ground; and The linear transistor array includes another plurality of transistors equal in number to the plurality of transistors, and the other end of the linear transistor array is coupled to a source voltage.

7. An electronic circuit forming part of one of a wireless transmitting circuit, a wireless receiving circuit and a wireless transceiver circuit for processing wireless signals; in The electronic circuit includes a reference voltage source, wherein the reference voltage source includes a current source and a plurality of transistors arranged along a ladder of N electrical nodes; Node 0 is grounded; A gate of an i-th transistor of the plurality of transistors is connected to a node (i-1); A source of an i-th transistor of the plurality of transistors is connected to a node i; The drain of the i-th transistor of the plurality of transistors is connected to the node (i+1); and The current source is provided in the gap left in the current path between node 0 and node 1 .

8. The electronic circuit according to claim 7, wherein At least one of the following conditions exists: Each transistor is either a native transistor or a depletion mode transistor; and The reference voltage source also includes a tuning circuit for tuning the current source to allow calibration of the reference voltage source.

9. The electronic circuit according to claim 7, wherein The reference voltage source also includes a tuning circuit for tuning the current source to allow calibration of the reference voltage source.

10. The electronic circuit according to claim 7, wherein Each transistor is a depletion mode transistor.

11. The electronic circuit according to claim 7, wherein The voltage at the node depends on the voltage threshold of the transistor and the current source.

12. The electronic circuit according to claim 7, wherein controlling the current source disposed in the current path between node 0 and node 1 by controlling a voltage; setting the control voltage according to a selected tap of a multi-tap voltage divider, wherein the voltage divider is coupled between one end of the linear transistor array and ground; and The linear transistor array includes another plurality of transistors equal in number to the plurality of transistors, and the other end of the linear transistor array is coupled to a source voltage.

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