Semiconductor device

Abstract

A semiconductor device includes a substrate, a transistor on the substrate, a bit line structure electrically connected to the transistor, a channel layer on the bit line structure, a gate structure intersecting the bit line structure, a first conductive line electrically connecting the transistor and the bit line structure, an upper shield line overlapping the first conductive line, and a side shield line, the side shield lines are spaced apart from each other with the first conductive line interposed therebetween. The upper shield line and the side shield line are electrically separated from the first conductive line and the bit line structure.

Description

Technical Field

[0001] Certain aspects of the present disclosure provide semiconductor devices with improved electrical characteristics and integration. Background Art

[0002] Semiconductor devices are widely used in the electronics industry due to their small size, multifunctional characteristics and / or low manufacturing cost. Semiconductor devices can be divided into semiconductor memory devices that store logic data, semiconductor logic devices that perform logic data operation processes, and hybrid semiconductor devices including memory elements and logic elements.

[0003] In view of the recent trend of electronic devices towards lower power consumption and higher operating speed, many contemporary and emerging semiconductor devices are required to operate at high speed and / or low operating voltage. In addition, it is necessary to improve the integration density of many semiconductor devices. However, as the integration density of semiconductor devices increases, some semiconductor devices may suffer from electrical performance degradation and reduced reliability. Summary of the invention

[0004] A semiconductor device according to some implementations of the present disclosure may include: a substrate; a transistor on the substrate; a bit line structure electrically connected to the transistor; a channel layer on the bit line structure; a gate structure intersecting the bit line structure; a first conductive line electrically connecting the transistor and the bit line structure; an upper shielding line overlapping the first conductive line; and side shielding lines, the side shielding lines being spaced apart from each other and the first conductive line interposed therebetween, the upper shielding line and the side shielding line being electrically separated from the first conductive line and the bit line structure.

[0005] A semiconductor device according to some implementations of the present disclosure may include: a substrate; a first transistor on the substrate; a bit line structure electrically connected to the first transistor; a channel layer on the bit line structure; a gate structure intersecting the bit line structure; a first conductive line and a second conductive line electrically connecting the first transistor and the bit line structure; an upper shielding line overlapping the first conductive line; and side shielding lines, the side shielding lines being spaced apart from each other and the first conductive line interposed therebetween, the upper shielding line may be located at the same level as the second conductive line, and the first conductive line may be located at the same level as the side shielding line.

[0006] A semiconductor device according to some implementations of the present disclosure may include: a substrate; a first transistor and a second transistor on the substrate; a bit line structure electrically connected to the first transistor; a channel layer on the bit line structure; a gate structure intersecting the bit line structure; a data storage structure electrically connected to the channel layer; a first conductive wire and a second conductive wire electrically connecting the first transistor and the bit line structure; an upper shielding wire and a side shielding wire electrically connected to the second transistor; a first lower insulating layer surrounding the first conductive wire and the side shielding wire; and a second lower insulating layer surrounding the second conductive wire and the upper shielding wire, the upper shielding wire may overlap with the first conductive wire, and the side shielding wires may be spaced apart from each other with the first conductive wire interposed therebetween. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Implementations will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings represent non-limiting examples as described herein.

[0008] Figure 1 is a block diagram of a semiconductor device according to some implementations.

[0009] Figure 2 and Figure 3 is a schematic perspective view of a semiconductor device according to some implementations.

[0010] Figure 4A is a plan view of a semiconductor device according to some implementations.

[0011] Figure 4B yes Figure 4A Magnified view of area “E1” in FIG.

[0012] Figure 4C is along Figure 4B A cross-sectional view taken along line AA'.

[0013] Figure 4D is along Figure 4B A cross-sectional view taken along line BB'.

[0014] Figure 5A and Figure 5B is a cross-sectional view of a semiconductor device according to some implementations.

[0015] Fig. 6A and Figure 6B is a cross-sectional view of a semiconductor device according to some implementations.

[0016] Fig. 7A is a cross-sectional view of a semiconductor device according to some implementations.

[0017] Figure 7B yes Fig. 7A Magnified view of area “E2” in FIG.

[0018] Figure 7C is based on Fig. 7A An enlarged cross-sectional view of a semiconductor device.

[0019] Figure 8 is a cross-sectional view of a semiconductor device according to some implementations. DETAILED DESCRIPTION

[0020] Figure 1 is a block diagram of a semiconductor device according to some implementations.

[0021] Reference Figure 1 , a semiconductor device may include a memory cell array 1 , a row decoder 2 , a sense amplifier 3 , a column decoder 4 , and a control logic 5 .

[0022] The memory cell array 1 may include a plurality of memory cells MC arranged two-dimensionally or three-dimensionally. Each memory cell MC may be provided between and connected to a word line WL and a bit line BL disposed to intersect each other.

[0023] Each memory cell MC may include a selection element TR and a data storage device DS electrically connected in series. The selection element TR may be electrically connected to both the data storage device DS and the word line WL. For example, the selection element TR may be provided at a point where the word line WL and the bit line BL intersect each other.

[0024] The selection element TR may include a field effect transistor. The data storage device DS may include at least one of a capacitor, a magnetic tunnel junction pattern, or a variable resistor. As an example, the selection element TR may include a transistor, a gate electrode of the transistor may be connected to a word line WL, and a drain / source terminal of the transistor may be connected to a bit line BL and the data storage device DS, respectively.

[0025] The row decoder 2 may be configured to decode address information input from the outside and select one of the word lines WL of the memory cell array 1 based on the decoded address information. The address information decoded by the row decoder 2 may be provided to a row driver, in which case the row driver may provide corresponding voltages to the selected one of the word lines WL and unselected word lines WL in response to control of the control circuit.

[0026] The sense amplifier 3 may be configured to sense, amplify, and output a voltage difference between one of the bit lines BL selected based on address information decoded by the column decoder 4 and a reference bit line.

[0027] The column decoder 4 may provide a data transmission path between the sense amplifier 3 and an external device (eg, a memory controller) and may be configured to decode address information input from the outside and select one of the bit lines BL based on the decoded address information.

[0028] The control logic 5 may be configured to generate a control signal for controlling a data write or read operation on the memory cell array 1 .

[0029] Figure 2 and Figure 3 is a schematic perspective view of a semiconductor device according to some implementations.

[0030] Reference Figure 2 and Figure 3 , the semiconductor device may include a peripheral circuit structure PS and a cell array structure CS connected to the peripheral circuit structure PS.

[0031] The peripheral circuit structure PS may include a core circuit and a peripheral circuit formed on the semiconductor substrate SUB. The core circuit and the peripheral circuit may include a reference Figure 1 The row decoder 2 and column decoder 4 , sense amplifier 3 and control logic 5 are described.

[0032] The cell array structure CS may include a memory cell array 1, the memory cell array 1 including Figure 1 The memory cells MC are two-dimensionally or three-dimensionally arranged on a plane parallel to two different directions (eg, a first direction D1 and a second direction D2). As described above, each memory cell MC may include a selection element TR and a data storage device DS.

[0033] In some implementations, a vertical channel transistor (VCT) may be provided as a selection element TR of each memory cell MC. The vertical channel transistor may be a transistor whose channel region extends in a direction perpendicular to the upper surface of the semiconductor substrate SUB. In addition, a capacitor may be provided as a data storage device DS of each memory cell MC.

[0034] like Figure 2 As shown in the example of , in some implementations, the peripheral circuit structure PS may be provided on the substrate SUB, and the cell array structure CS may be provided on the peripheral circuit structure PS.

[0035] like Figure 3 As shown in the example of , in some implementations, the peripheral circuit structure PS may be provided on the first substrate SUB1, and the cell array structure CS may be provided on the second substrate SUB2. The first substrate SUB1 and the second substrate SUB2 may face each other.

[0036] The first metal pad LMP may be provided at the uppermost portion of the peripheral circuit structure PS. The first metal pad LMP may be electrically connected to the core and peripheral circuits 2, 3, 4, and 5.

[0037] The second metal pad UMP may be provided at the lowermost portion of the cell array structure CS. The second metal pad UMP may be electrically connected to the memory cell array 1. For example, the second metal pad UMP may directly contact and bond with the first metal pad LMP of the peripheral circuit structure PS.

[0038] Figure 4A is a plan view of a semiconductor device according to some implementations. Figure 4B yes Figure 4A Magnified view of area “E1” in FIG. Figure 4C is along Figure 4B A cross-sectional view taken along line AA'. Figure 4D is along Figure 4B A cross-sectional view taken along line BB'.

[0039] Reference FIG. 4A to FIG. 4D , the semiconductor device may include a peripheral circuit structure 10 and a cell array structure 20 on the peripheral circuit structure 10. The peripheral circuit structure 10 may include a sub-word line driver area 11, a row decoder area 12, a control logic area 13, and a sense amplifier area 14. The sub-word line driver area 11, the row decoder area 12, the control logic area 13, and the sense amplifier area 14 may be two-dimensionally divided areas defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may intersect with each other. For example, the first direction D1 and the second direction D2 may be horizontal directions perpendicular to each other. The sub-word line driver area 11, the row decoder area 12, the control logic area 13, and the sense amplifier area 14 may overlap with the cell array structure 20 in a third direction D3 (for example, may be below the cell array structure 20). The third direction D3 may intersect with the first direction D1 and the second direction D2. For example, the third direction D3 may be a vertical direction perpendicular to the first direction D1 and the second direction D2.

[0040] The sub word line driver may be placed in the sub word line driver region 11. The row decoder may be placed in the row decoder region 12. The control logic may be placed in the control logic region 13. The sense amplifier may be placed in the sense amplifier region 14. FIG. 4A to FIG. 4D These and other elements of the semiconductor device may have specific Figures 1 to 3 The characteristics and arrangements of the components of the devices correspond to those described unless otherwise stated.

[0041] In some implementations, only the sense amplifier region 14 may overlap with the cell array structure 20 in the third direction D3 (e.g., below the cell array structure 20), and the sub-word line driver region 11, the row decoder region 12, and the control logic region 13 may not overlap with the cell array structure 20 in the third direction D3 (e.g., may be horizontally spaced apart from the cell array structure 20).

[0042] like Figure 4C As shown, a substrate 100 may be provided. The substrate 100 may be, for example, a semiconductor substrate, an insulator substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0043] A first lower insulating layer 121 on the substrate 100 , a first lower cover layer 122 on the first lower insulating layer 121 , a second lower insulating layer 123 on the first lower cover layer 122 , a second lower cover layer 124 on the second lower insulating layer 123 , and a third lower insulating layer 125 on the second lower cover layer 124 may be provided.

[0044] The first to third lower insulating layers 121, 123, and 125 may include an insulating material. As an example, the first to third lower insulating layers 121, 123, and 125 may include oxide.

[0045] The first and second lower capping layers 122 and 124 may include an insulating material different from those of the first to third lower insulating layers 121, 123, and 125. As an example, the first and second lower capping layers 122 and 124 may include nitride.

[0046] In some implementations, each of the first to third lower insulating layers 121 , 123 , and 125 and the first and second lower capping layers 122 and 124 may be a multi-layer structure including a plurality of insulating layers.

[0047] The first transistor TR1 and the second transistor TR2 may be provided on the substrate 100. Each of the first transistor TR1 and the second transistor TR2 may include an impurity region 111, a peripheral gate insulating layer 112, a first peripheral gate electrode layer 113, and a second peripheral gate electrode layer 114. The impurity region 111 may be formed by doping the substrate 100 with impurities. The peripheral gate insulating layer 112 may include an insulating material. The first peripheral gate electrode layer 113 and the second peripheral gate electrode layer 114 may include a conductive material. As an example, the first peripheral gate electrode layer 113 may include polysilicon, and the second peripheral gate electrode layer 114 may include a metal. In some implementations, the first transistor TR1 may be a transistor constituting a sense amplifier.

[0048] A first transistor contact 126, a second transistor contact 127, and a third transistor contact 128 that penetrate / extend through the first lower insulating layer 121 and the first lower capping layer 122 may be provided. The first to third transistor contacts 126, 127, and 128 may be surrounded (e.g., laterally surrounded) by the first lower insulating layer 121 and the first lower capping layer 122. The first transistor contact 126 may be electrically connected to the impurity region 111 of the first transistor TR1. The second transistor contact 127 may be electrically connected to the impurity region 111 of the second transistor TR2. The third transistor contact 128 may be electrically connected to the impurity region 111 of the second transistor TR2. The first to third transistor contacts 126, 127, and 128 may include a conductive material.

[0049] The first conductive wire 131, the second conductive wire 134 and the side shield wire 141 may be provided in the second lower insulating layer 123. The first conductive wire 131, the second conductive wire 134 and the side shield wire 141 may be surrounded by the second lower insulating layer 123 (e.g., surrounded laterally). The first conductive wire 131, the second conductive wire 134 and the side shield wire 141 may be located at the same level. The lower surfaces of the first conductive wire 131, the second conductive wire 134 and the side shield wire 141 may be coplanar. The lower surfaces of the first conductive wire 131, the second conductive wire 134 and the side shield wire 141 may contact the upper surface of the first lower cover layer 122. The upper surfaces of the first conductive wire 131, the second conductive wire 134 and the side shield wire 141 may be coplanar. The upper surfaces of the first conductive wire 131, the second conductive wire 134 and the side shield wire 141 may contact the lower surface of the second lower cover layer 124.

[0050] The distance between the first conductive line 131 and the substrate 100 in the third direction D3, the distance between the second conductive line 134 and the substrate 100 in the third direction D3, and the distance between the side shield line 141 and the substrate 100 in the third direction D3 may be the same. The first conductive line 131, the second conductive line 134, and the side shield line 141 may include the same conductive material. For example, the first conductive line 131, the second conductive line 134, and the side shield line 141 may include a metal (e.g., the same metal).

[0051] The first conductive wire 131, the second conductive wire 134, and the side shield wire 141 may be arranged to be spaced apart in the first direction D1, for example, horizontally spaced apart. The first conductive wire 131, the second conductive wire 134, and the side shield wire 141 may extend in the second direction D2. The length of each of the first conductive wire 131, the second conductive wire 134, and the side shield wire 141 in the second direction D2 may be greater than the length of each of the first conductive wire 131, the second conductive wire 134, and the side shield wire 141 in the first direction D1.

[0052] The first conductive line 131 may be disposed between two side shield lines 141 adjacent to each other in the first direction D1. The first conductive line 131 and the side shield lines 141 may be alternately arranged in the first direction D1. The side shield lines 141 disposed on both sides of the first conductive line 131 may be spaced apart from each other (e.g., horizontally spaced apart) in the first direction D1 with the first conductive line 131 interposed therebetween.

[0053] The first conductive line 131 may be electrically connected to the first transistor contact 126. A lower surface of the first conductive line 131 may be in contact with an upper surface of the first transistor contact 126. The second conductive line 134 may be electrically connected to the second transistor contact 127. A lower surface of the second conductive line 134 may be in contact with an upper surface of the second transistor contact 127. The side shield line 141 may be electrically connected to the third transistor contact 128. A lower surface of the side shield line 141 may be in contact with an upper surface of the third transistor contact 128.

[0054] A first contact 133 and a second contact 136 that penetrate / extend through the second lower cover layer 124 may be provided. The first contact 133 and the second contact 136 may be surrounded (e.g., laterally surrounded) by the second lower cover layer 124. The first contact 133 may be electrically connected to the first conductive line 131. A lower surface of the first contact 133 may be in contact with an upper surface of the first conductive line 131. The second contact 136 may be electrically connected to the second conductive line 134. A lower surface of the second contact 136 may be in contact with an upper surface of the second conductive line 134. The first contact 133 and the second contact 136 may include a conductive material.

[0055] The third conductive wire 132, the fourth conductive wire 135 and the upper shield wire 142 may be provided in the third lower insulating layer 125. The third conductive wire 132, the fourth conductive wire 135 and the upper shield wire 142 may be surrounded by the third lower insulating layer 125. The third conductive wire 132, the fourth conductive wire 135 and the upper shield wire 142 may be located at the same level. The lower surfaces of the third conductive wire 132, the fourth conductive wire 135 and the upper shield wire 142 may be coplanar. The lower surfaces of the third conductive wire 132, the fourth conductive wire 135 and the upper shield wire 142 may contact the upper surface of the second lower cover layer 124. The upper surfaces of the third conductive wire 132, the fourth conductive wire 135 and the upper shield wire 142 may be coplanar. The lower surface of the upper shield wire 142 may face the upper surface of the first conductive wire 131.

[0056] The distance between the third conductive line 132 and the substrate 100 in the third direction D3, the distance between the fourth conductive line 135 and the substrate 100 in the third direction D3, and the distance between the upper shield line 142 and the substrate 100 in the third direction D3 may be the same. The third conductive line 132, the fourth conductive line 135, and the upper shield line 142 may include the same conductive material. For example, the third conductive line 132, the fourth conductive line 135, and the upper shield line 142 may include a metal (e.g., the same metal).

[0057] The third conductive line 132, the fourth conductive line 135, and the upper shielding line 142 may be disposed to be spaced apart in the first direction D1. The third conductive line 132, the fourth conductive line 135, and the upper shielding line 142 may extend in the second direction D2. The length of each of the third conductive line 132, the fourth conductive line 135, and the upper shielding line 142 in the second direction D2 may be greater than the length of each of the third conductive line 132, the fourth conductive line 135, and the upper shielding line 142 in the first direction D1. The upper shielding line 142 may overlap with the first conductive line 131 in the third direction D3.

[0058] The third conductive line 132 may be electrically connected to the first contact 133. A lower surface of the third conductive line 132 may contact an upper surface of the first contact 133. The fourth conductive line 135 may be electrically connected to the second contact 136. A lower surface of the fourth conductive line 135 may contact an upper surface of the second contact 136.

[0059] A third contact 143 penetrating / extending through the second lower cover layer 124 may be provided. The third contact 143 may be surrounded (e.g., laterally surrounded) by the second lower cover layer 124. The third contact 143 may be electrically connected to the upper shield line 142 and the side shield line 141. The upper surface of the third contact 143 may be in contact with the lower surface of the upper shield line 142. The lower surface of the third contact 143 may be in contact with the upper surface of the side shield line 141. The third contact 143 may include a conductive material.

[0060] The upper shield line 142 may be electrically connected to the second transistor TR2 through the third contact 143, the side shield line 141, and the third transistor contact 128. Power may be applied to the upper shield line 142 and the side shield line 141 through the second transistor TR2.

[0061] An intermediate insulating layer 157 may be provided on the third lower insulating layer 125. The intermediate insulating layer 157 may include an insulating material.

[0062] A first interlayer insulating layer 151, a second interlayer insulating layer 152, and a third interlayer insulating layer 153 may be provided. The first interlayer insulating layer 151 may be provided on the third lower insulating layer 125. The second interlayer insulating layer 152 may be provided on the first interlayer insulating layer 151. The third interlayer insulating layer 153 may be provided on the second interlayer insulating layer 152. The first to third interlayer insulating layers 151, 152, and 153 may be disposed between the intermediate insulating layers 157 adjacent to each other in the first direction D1. The first to third interlayer insulating layers 151, 152, and 153 may include insulating materials.

[0063] A bit line structure BS and a connection line 156 may be provided. The bit line structure BS may be provided on the third interlayer insulating layer 153. The connection line 156 may be provided on the third interlayer insulating layer 153. The bit line structure BS and the connection line 156 may extend in the second direction D2. The bit line structure BS and the connection line 156 may be arranged to be spaced apart in the first direction D1. The bit line structure BS and the connection line 156 may include a conductive material. The bit line structure BS may be a single conductive layer or a plurality of conductive layers.

[0064] A first connection contact 154 and a second connection contact 155 penetrating / extending through the first to third interlayer insulating layers 151, 152, and 153 may be provided. The first connection contact 154 may be electrically connected to the third conductive line 132 and the bit line structure BS. The lower surface of the first connection contact 154 may be in contact with the upper surface of the third conductive line 132. The upper surface of the first connection contact 154 may be in contact with the lower surface of the bit line structure BS. The second connection contact 155 may be electrically connected to the fourth conductive line 135 and the connection line 156. The lower surface of the second connection contact 155 may be in contact with the upper surface of the fourth conductive line 135. The upper surface of the second connection contact 155 may be in contact with the lower surface of the connection line 156. The first connection contact 154 and the second connection contact 155 may include a conductive material.

[0065] The channel layer CL (eg, Figure 4D ) may be provided on the bit line structure BS. A plurality of channel layers CL may be in contact with one bit line structure BS. The channel layers CL provided on one bit line structure BS may be arranged in the second direction D2.

[0066] The channel layer CL may include a semiconductor material or an oxide semiconductor material. The oxide semiconductor material may include, for example, at least one of InGaZnO, InGaSiO, InSnZnO, InZnO, ZnO, ZnSnO, ZnON, ZrZnSnO, SnO, HfInZnO, GaZnSnO, AlZnSnO, YbGaZnO or InGaO. The semiconductor material may include, for example, at least one of Si or Ge. In some implementations, the channel layer CL may be a multilayer structure including a plurality of material layers. In some implementations, the channel layer CL may include a two-dimensional material.

[0067] The gate structure GS (eg, Figure 4B ) may be provided on the channel layer CL. The gate structure GS may extend in the first direction D1. The gate structure GS may intersect with the bit line structure BS. The gate structure GS may include a gate insulating layer GI on the channel layer CL and a gate electrode layer GE on the gate insulating layer GI. The gate insulating layer GI may include an insulating material. As an example, the gate insulating layer GI may include an oxide.

[0068] The gate electrode layer GE may include a conductive material. For example, the gate electrode layer GE may be made of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal (e.g., tungsten, titanium, tantalum, etc.), or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0069] A first mold insulating layer 165 and a second mold insulating layer 166 may be provided. The first mold insulating layer 165 may be provided on the channel layer CL and the gate structure GS. The second mold insulating layer 166 may be provided on the first mold insulating layer 165. A gate capping layer 167 may be provided on the first mold insulating layer 165, the second mold insulating layer 166, and the gate electrode layer GE. The first mold insulating layer 165, the second mold insulating layer 166, and the gate capping layer 167 may include an insulating material.

[0070] A fourth interlayer insulating layer 161 may be provided on the bit line structure BS. The channel layer CL may penetrate / extend through the fourth interlayer insulating layer 161. A third mold insulating layer 162 may be provided on the fourth interlayer insulating layer 161. The fourth interlayer insulating layer 161 and the third mold insulating layer 162 may include insulating materials.

[0071] A landing pad LP may be provided (e.g. Figure 4C). A landing pad LP may be provided on the channel layer CL and the gate cap layer 167. The landing pad LP may be electrically connected to the channel layer CL. The landing pad LP may include a conductive material. In some implementations, the landing pad LP may include a barrier layer and a conductive layer on the barrier layer. As an example, the barrier layer of the landing pad LP may include at least one of titanium or tantalum, and the conductive layer of the landing pad LP may include tungsten.

[0072] A connection pad 164 may be provided. The connection pad 164 may be provided on the third mold insulating layer 162. The connection pad 164 may be located at a level higher than the channel layer CL. The connection pad 164 may be located at the same level as the landing pad LP. The connection pad 164 may be electrically connected to an external power supply device. The connection pad 164 may include a conductive material.

[0073] A third connection contact 163 may be provided penetrating / extending through the third mold insulating layer 162 and the fourth interlayer insulating layer 161. The third connection contact 163 may be electrically connected to the connection line 156 and the connection pad 164. The third connection contact 163 may include a conductive material.

[0074] An external power supply device may supply power to the side shield line 141 and the upper shield line 142 through the connection pad 164 , the third connection contact 163 , the connection line 156 , the second connection contact 155 , the fourth conductive line 135 , the second contact 136 , the second conductive line 134 , the second transistor TR2 , and the third transistor contact 128 .

[0075] A separation structure DI may be provided to separate the landing pad LP from the connection pad 164. The separation structure DI may include an insulating material. In some implementations, the separation structure DI may be a multi-layer including a plurality of insulating layers.

[0076] A data storage structure DA may be provided, for example Figure 4D As shown in . The data storage structure DA can be connected to the landing pad LP. In some implementations, the data storage structure DA can be a capacitor. In this case, the data storage structure DA can include a lower electrode, an upper electrode, and a capacitor dielectric layer interposed therebetween. In some implementations, the data storage structure DA can be a variable resistance pattern that can be switched between two resistance states by an electric pulse. In this case, the data storage structure DA can be a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material whose crystal state changes depending on the amount of current.

[0077] The data storage structure DA may be electrically connected to the first transistor TR1 through the landing pad LP, the channel layer CL, the bit line structure BS, the first connection contact 154 , the third conductive line 132 , the first contact 133 , the first conductive line 131 , and the first transistor contact 126 .

[0078] The upper shield line 142, the third contact 143 and the side shield line 141 may be electrically separated / isolated from the data storage structure DA, the landing pad LP, the channel layer CL, the bit line structure BS, the first connection contact 154, the third conductive line 132, the first contact 133, the first conductive line 131, the first transistor contact 126 and the first transistor TR1.

[0079] In the semiconductor device according to some implementations, the side shield lines 141 may be disposed on both sides of the first conductive line 131, and the upper shield line 142 may be disposed on the first conductive line 131, thereby preventing or reducing coupling between adjacent first conductive lines 131. Therefore, parasitic capacitance between the first conductive lines 131 may be prevented or reduced.

[0080] Power may be applied to the side shield lines 141 and the upper shield lines 142 , thereby improving shielding effects of the side shield lines 141 and the upper shield lines 142 .

[0081] Figure 5A and Figure 5B is a cross-sectional view of a semiconductor device according to some implementations. Figure 5A and Figure 5B The semiconductor device can be similar to FIG. 4A to FIG. 4D semiconductor devices, except as described below.

[0082] Reference Figure 5A and Figure 5B , a first lower insulating layer 221 on the substrate 100, a first lower cover layer 222 on the first lower insulating layer 221, a second lower insulating layer 223 on the first lower cover layer 222, a second lower cover layer 224 on the second lower insulating layer 223, a third lower insulating layer 225 on the second lower cover layer 224, a third lower cover layer 226 on the third lower insulating layer 225, and a fourth lower insulating layer 227 on the third lower cover layer 226 can be provided.

[0083] A first conductive line 231, a second conductive line 234, and a lower shield line 245 may be provided in the second lower insulating layer 223. The first conductive line 231 may be electrically connected to the first transistor TR1 through the first transistor contact 126. The second conductive line 234 may be electrically connected to the second transistor TR2 through the second transistor contact 127. The lower shield line 245 may be electrically connected to the second transistor TR2 through the third transistor contact 128.

[0084] The third conductive line 232, the fourth conductive line 235 and the side shield line 241 may be provided in the third lower insulating layer 225. The third conductive line 232 may be disposed between two side shield lines 241 adjacent to each other in the first direction D1. The third conductive line 232 may overlap the lower shield line 245 in the third direction D3.

[0085] A first contact 233 and a second contact 236 penetrating / extending through the second lower cover layer 224 may be provided. The first contact 233 may be electrically connected to the first conductive line 231 and the third conductive line 232. The second contact 236 may be electrically connected to the second conductive line 234 and the fourth conductive line 235.

[0086] A third contact 244 penetrating / extending through the second lower cover layer 224 may be provided. The third contact 244 may electrically connect the side shield line 241 and the lower shield line 245.

[0087] The fifth conductive line 271, the sixth conductive line 273 and the upper shield line 242 may be provided in the fourth lower insulating layer 227. The upper shield line 242 may overlap the third conductive line 232 and the lower shield line 245 in the third direction D3. The third conductive line 232 may be disposed between the lower shield line 245 and the upper shield line 242.

[0088] A fourth contact 272 and a fifth contact 274 penetrating / extending through the third lower cover layer 226 may be provided. The fourth contact 272 may be electrically connected to the third conductive line 232 and the fifth conductive line 271. The fifth contact 274 may be electrically connected to the fourth conductive line 235 and the sixth conductive line 273.

[0089] A sixth contact 243 penetrating / extending through the third lower cover layer 226 may be provided. The sixth contact 243 may electrically connect the upper shield line 242 and the side shield line 241.

[0090] The upper shield line 242 , the sixth contact 243 , the side shield line 241 , the third contact 244 , the lower shield line 245 , and the third transistor contact 128 may be connected to the second transistor TR2 , and power may be applied to the second transistor TR2 .

[0091] The fifth conductive line 271 may be electrically connected to the bit line structure BS through the first connection contact 154. The sixth conductive line 273 may be electrically connected to the connection line 156 through the second connection contact 155.

[0092] In the semiconductor device according to some implementations, the side shielding lines 241 may be disposed on both sides of the third conductive line 232, and the upper shielding lines 242 and the lower shielding lines may be disposed above and below the third conductive line 232, thereby preventing or reducing coupling between adjacent third conductive lines 232. Power may be applied to the side shielding lines 241, the lower shielding lines 245, and the upper shielding lines 242, thereby improving the shielding effects of the side shielding lines 241, the lower shielding lines 245, and the upper shielding lines 242.

[0093] Fig. 6A and Figure 6B is a cross-sectional view of a semiconductor device according to some implementations. Fig. 6A and Figure 6B The semiconductor device can be used with FIG. 4A to FIG. 4D The semiconductor device is similar except as described below.

[0094] Reference Fig. 6A and Figure 6B , a first lower insulating layer 321 on the substrate 100, a first lower cover layer 322 on the first lower insulating layer 321, a second lower insulating layer 323 on the first lower cover layer 322, a second lower cover layer 324 on the second lower insulating layer 323, a third lower insulating layer 325 on the second lower cover layer 324, a third lower cover layer 326 on the third lower insulating layer 325, a first bonding insulating layer 327 on the third lower cover layer 326, a second bonding insulating layer 328 on the first bonding insulating layer 327, a fourth lower cover layer 329 on the second bonding insulating layer 328, and a fourth lower insulating layer 330 on the fourth lower cover layer 329 can be provided.

[0095] A first conductive line 331, a second conductive line 334, and a side shield line 341 may be provided in the second lower insulating layer 323. The first conductive line 331 may be disposed between two side shield lines 341 adjacent to each other in the first direction D1.

[0096] A third conductive line 332 , a fourth conductive line 335 , and an upper shielding line 342 may be provided in the third lower insulating layer 325 .

[0097] A first contact 333 and a second contact 336 penetrating / extending through the second lower cover layer 324 may be provided. The first contact 333 may be electrically connected to the first conductive line 331 and the third conductive line 332. The second contact 336 may be electrically connected to the second conductive line 334 and the fourth conductive line 335. A third contact 343 penetrating / extending through the second lower cover layer 324 may be provided. The third contact 343 may electrically connect the side shield line 341 and the upper shield line 342.

[0098] The first bonding pad 372 and the second bonding pad 377 may be provided in the first bonding insulating layer 327. The third bonding pad 373 and the fourth bonding pad 378 may be provided in the second bonding insulating layer 328. The first bonding pad 372 may be in contact with the third bonding pad 373 by a wafer bonding process. The second bonding pad 377 may be in contact with the fourth bonding pad 378 by a wafer bonding process. The first to fourth bonding pads 372, 377, 373, and 378 may include a conductive material.

[0099] A third contact 371 and a fourth contact 376 penetrating / extending through the third lower cover layer 326 may be provided. The third contact 371 may be electrically connected to the first bonding pad 372 and the third conductive line 332. The fourth contact 376 may be electrically connected to the second bonding pad 377 and the fourth conductive line 335.

[0100] A fifth conductive line 375 and a sixth conductive line 380 may be provided in the fourth lower insulating layer 330 .

[0101] A fifth contact 374 and a sixth contact 379 penetrating / extending through the fourth lower capping layer 329 may be provided. The fifth contact 374 may be electrically connected to the third bonding pad 373 and the fifth conductive line 375. The sixth contact 379 may be electrically connected to the fourth bonding pad 378 and the sixth conductive line 380.

[0102] The fifth conductive line 375 may be electrically connected to the bit line structure BS through the first connection contact 154. The sixth conductive line 380 may be electrically connected to the connection line 156 through the second connection contact 155.

[0103] Fig. 7A is a cross-sectional view of a semiconductor device according to some implementations. Figure 7B yes Fig. 7A Magnified view of area “E2” in FIG. Figure 7C is based on Fig. 7A An enlarged cross-sectional view of a semiconductor device.

[0104] Reference Fig. 7A , a substrate 400 may be provided. A first lower insulating layer 421 on the substrate 400, a first lower cover layer 422 on the first lower insulating layer 421, a second lower insulating layer 423 on the first lower cover layer 422, a second lower cover layer 424 on the second lower insulating layer 423, and a third lower insulating layer 425 on the second lower cover layer 424 may be provided.

[0105] The first transistor TR41 and the second transistor TR42 may be provided on the substrate 100. In some implementations, the first transistor TR41 may be a transistor constituting a sense amplifier.

[0106] A first transistor contact 426, a second transistor contact 427, and a third transistor contact 428 may be provided that penetrate / extend through the first lower insulating layer 421 and the first lower capping layer 422. The first transistor contact 426 may be electrically connected to the impurity region 111 of the first transistor TR41. The second transistor contact 427 may be electrically connected to the impurity region 111 of the second transistor TR42. The third transistor contact 428 may be electrically connected to the impurity region 111 of the second transistor TR42.

[0107] A first conductive line 431, a second conductive line 434, and a side shield line 441 may be provided in the second lower insulating layer 423. The first conductive line 431 may be disposed between two side shield lines 441 adjacent to each other in the first direction D1.

[0108] A third conductive line 432 , a fourth conductive line 435 , and an upper shielding line 442 may be provided in the third lower insulating layer 425 .

[0109] A first contact 433 and a second contact 436 penetrating / extending through the second lower cover layer 424 may be provided. The first contact 433 may be electrically connected to the first conductive line 431 and the third conductive line 432. The second contact 436 may be electrically connected to the second conductive line 434 and the fourth conductive line 435.

[0110] An interlayer insulating layer 461 may be provided on the third lower insulating layer 425. The interlayer insulating layer 461 may include an insulating material. A shielding layer 462 may be provided on the interlayer insulating layer 461. The shielding layer 462 may include a conductive material. A shielding insulating layer 463 may be provided on the shielding layer 462. The shielding insulating layer 463 may include an insulating material. A bit line capping layer 464 may be provided on the shielding insulating layer 463. The bit line capping layer 464 may include an insulating material. A bit line structure BS4 may be provided on the bit line capping layer 464.

[0111] A first cover insulating layer 465 may be provided on the interlayer insulating layer 461. A second cover insulating layer 481 may be provided on the first cover insulating layer 465. A third cover insulating layer 482 may be provided on the second cover insulating layer 481. A fourth cover insulating layer 483 may be provided on the third cover insulating layer 482. The first to fourth cover insulating layers 465, 481, 482, and 483 may include insulating materials.

[0112] A channel structure CH4 and a gate structure GS4 may be provided on the bit line structure BS4. The channel structure CH4 may be disposed between the gate structures GS4. The channel structure CH4 and the gate structure GS4 may be surrounded (eg, laterally surrounded) by a first capping insulating layer 465.

[0113] A pad structure PA4 and an insulating structure IS4 may be provided on the channel structure CH4 and the gate structure GS4. The pad structure PA4 may be disposed between the insulating structures IS4. The pad structure PA4 and the insulating structure IS4 may be surrounded (eg, laterally surrounded) by a second capping insulating layer 481.

[0114] A data storage structure DA4 may be provided on the pad structure PA4 . The data storage structure DA4 may be surrounded by a third capping insulating layer 482 .

[0115] A first connection contact 472, a second connection contact 473, and a first connection line 474 may be provided. The first connection contact 472 may be in contact with the third conductive line 432. The second connection contact 473 may be in contact with the bit line structure BS4. The first connection line 474 may be in contact with the first connection contact 472 and the second connection contact 473. The first connection contact 472 and the second connection contact 473 may be surrounded by the first cover insulating layer 465 and the second cover insulating layer 481. The first connection line 474 may be surrounded by the second cover insulating layer 481.

[0116] The data storage structure DA4 may be electrically connected to the first transistor TR41 through the pad structure PA4, the channel structure CH4, the bit line structure BS4, the second connection contact 473, the first connection line 474, the first connection contact 472, the third conductive line 432, the first contact 433, the first conductive line 431 and the first transistor contact 426.

[0117] A third connection contact 471 and a connection pad 484 may be provided. The third connection contact 471 may be in contact with the fourth conductive line 435. The connection pad 484 may be in contact with the third connection contact 471. The third connection contact 471 may be surrounded (e.g., laterally surrounded) by the first to fourth cover insulating layers 465, 481, 482, and 483. The connection pad 484 may be surrounded (e.g., laterally surrounded) by the fourth cover insulating layer 483.

[0118] The connection pad 484 may be electrically connected to the second transistor TR42 through the third connection contact 471 , the fourth conductive line 435 , the second contact 436 , the second conductive line 434 , and the second transistor contact 427 .

[0119] A fourth connection contact 486 and a second connection line 485 may be provided. The fourth connection contact 486 may contact the data storage structure DA4. The second connection line 485 may contact the fourth connection contact 486. The fourth connection contact 486 may be surrounded (e.g., laterally surrounded) by a fourth cover insulating layer 483. The second connection line 485 may be surrounded (e.g., laterally surrounded) by a fourth cover insulating layer 483.

[0120] The first to fourth connection contacts 472 , 473 , 471 , and 486 and the first and second connection lines 474 and 485 may include a conductive material.

[0121] Reference Figure 7B and Figure 7C The bit line structure BS4 may include a first bit line layer BL41 on the bit line capping layer 464, a second bit line layer BL42 on the first bit line layer BL41, and a third bit line layer BL43 on the second bit line layer BL42. The first to third bit line layers BL41, BL42, and BL43 may include different conductive materials.

[0122] A portion of the shielding insulating layer 463 and a portion of the shielding layer 462 may be disposed between the bit line capping layers 464 and between the bit line structures BS4 .

[0123] The channel structure CH4 may include a channel layer CL4, a back gate spacer BA4, a back gate insulating layer BI41, a back gate electrode layer BG4, and a back gate capping layer BI42. The back gate spacer BA4, the back gate insulating layer BI41, the back gate electrode layer BG4, and the back gate capping layer BI42 may be disposed between the channel layers CL4 in the first direction D1. The back gate insulating layer BI41, the back gate electrode layer BG4, and the back gate capping layer BI42 may be disposed between the back gate spacers BA4 in the first direction D1. The back gate insulating layer BI41 may be disposed on the third bit line layer BL43. The back gate electrode layer BG4 may be disposed on the back gate insulating layer BI41. The back gate capping layer BI42 may be disposed on the back gate electrode layer BG4.

[0124] The channel layer CL4 and the back gate electrode layer BG4 may include a conductive material. The back gate spacer BA4, the back gate insulating layer BI41, and the back gate capping layer BI42 may include an insulating material.

[0125] The gate structure GS4 may include a gate electrode layer GE4, a first gate insulating layer GI41, a second gate insulating layer GI42, a third gate insulating layer GI43, and a gate capping layer GP4. The gate electrode layer GE4, the second gate insulating layer GI42, and the third gate insulating layer GI43 may be disposed in the first gate insulating layer GI41. The first gate insulating layer GI41 may be provided between the gate electrode layer GE4 and the channel layer CL4. The second gate insulating layer GI42 may be provided between the gate electrode layer GE4. The third gate insulating layer GI43 may be provided between the gate electrode layer GE4 and the bit line structure BS4. The first to third gate insulating layers GI41, GI42, and GI43 and the gate capping layer GP4 may include insulating materials.

[0126] The pad structure PA4 may include a first pad layer PL41, a second pad layer PL42 on the first pad layer PL41, a third pad layer PL43 on the second pad layer PL42, and a fourth pad layer PL44 on the third pad layer PL43. The first pad layer PL41 may contact the channel layer CL4. The first pad layer PL41 and the second pad layer PL42 may form a node contact. The third pad layer PL43 and the fourth pad layer PL44 may form a landing pad. The first to fourth pad layers PL41, PL42, PL43 and PL44 may include a conductive material.

[0127] The insulating structure IS4 may include a first insulating layer II41 and a second insulating layer II42 on the first insulating layer II41. A first pad layer PL41 may be disposed between the first insulating layers II41. Second to fourth pad layers PL42, PL43, and PL44 may be disposed between the second insulating layer II42. The first insulating layer II41 and the second insulating layer II42 may include insulating materials.

[0128] Figure 8 is a cross-sectional view of a semiconductor device according to some implementations. Figure 8 The semiconductor device can be used with FIG. 7A to FIG. 7C The semiconductor devices are similar except as described below.

[0129] Reference Figure 8 , the first transistor TR51, the second transistor TR52, and the third transistor TR53 may be provided on the substrate 400. A first lower insulating layer 521 on the substrate 400, a first lower capping layer 522 on the first lower insulating layer 521, a second lower insulating layer 523 on the first lower capping layer 522, a second lower capping layer 524 on the second lower insulating layer 523, a third lower insulating layer 525 on the second lower capping layer 524, a third lower capping layer 526 on the third lower insulating layer 525, a first bonding insulating layer 527 on the third lower capping layer 526, and a second bonding insulating layer 528 on the first bonding insulating layer 527 may be provided.

[0130] A first transistor contact 516 , a second transistor contact 517 , a third transistor contact 518 , and a fourth transistor contact 519 penetrating / extending through the first lower insulating layer 521 and the first lower capping layer 522 may be provided.

[0131] First conductive lines 531, second conductive lines 532, third conductive lines 533, and side shielding lines 541 may be provided in the second lower insulating layer 523. Each of the first conductive lines 531 and the second conductive lines 532 may be disposed between two side shielding lines 541 adjacent to each other in the first direction D1.

[0132] A fourth conductive line 537, a fifth conductive line 538, a sixth conductive line 539, and an upper shielding line 542 may be provided in the third lower insulating layer 525. The upper shielding line 542 may overlap the first conductive line 531 or the second conductive line 532 in the third direction D3.

[0133] A first contact 534 , a second contact 535 , and a third contact 536 penetrating / extending through the second lower cover layer 524 may be provided.

[0134] The first bonding pad 552, the second bonding pad 555, and the third bonding pad 558 may be provided in the first bonding insulating layer 527. The fourth bonding pad 553, the fifth bonding pad 556, and the sixth bonding pad 559 may be provided in the second bonding insulating layer 528. The first bonding pad 552 may be in contact with the fourth bonding pad 553 through a wafer bonding process. The second bonding pad 555 may be in contact with the fifth bonding pad 556 through a wafer bonding process. The third bonding pad 558 may be in contact with the sixth bonding pad 559 through a wafer bonding process.

[0135] A fourth contact 551 , a fifth contact 554 , and a sixth contact 557 penetrating the third lower cover layer 526 may be provided.

[0136] A through contact 574 and a through contact insulating layer 573 may be provided that penetrate / extend through the interlayer insulating layer 461, the shielding layer 462, the shielding insulating layer 463, and the bit line capping layer 464. The through contact 574 may include a conductive material. The through contact insulating layer 573 may surround (e.g., laterally surround) the through contact 574. The through contact insulating layer 573 may include an insulating material.

[0137] The first connection contact 572 may be provided to be in contact with the data storage structure DA4 and the fifth bonding pad 555. The second connection contact 571 may be provided to be in contact with the sixth bonding pad 559 and the connection pad 584.

[0138] The bit line structure BS4 may be electrically connected to the first transistor TR51 through the through-contact 574 , the fourth bonding pad 553 , the first bonding pad 552 , the fourth contact 551 , the fourth conductive line 537 , the first contact 534 , the first conductive line 531 , and the first transistor contact 516 .

[0139] The data storage structure DA4 may be electrically connected to the first transistor TR51 through the through-contact 574 , the fourth bonding pad 553 , the first bonding pad 552 , the fourth contact 551 , the fourth conductive line 537 , the first contact 534 , the first conductive line 531 , and the first transistor contact 516 .

[0140] The connection pad 584 may be electrically connected to the third transistor TR53 through the second connection contact 571 , the sixth bonding pad 559 , the third bonding pad 558 , the sixth contact 557 , the sixth conductive line 539 , the third contact 536 , the third conductive line 533 , and the second transistor contact 517 .

[0141] Power may be applied to the side shield line 541 and the upper shield line 542 through the third transistor TR53 .

[0142] Therefore, according to some implementations FIG. 4A to FIG. 8 The described semiconductor device can prevent or reduce coupling between conductive lines.

[0143] Although the present disclosure includes many specific implementation details, these details should not be interpreted as limiting the scope of the protection that can be claimed. Certain features described in the context of separate implementations in the present disclosure may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately in multiple implementations or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, in some cases, one or more features from a combination may be deleted from the combination, and the combination may be directed to a sub-combination or a variation of a sub-combination.

[0144] Although various examples are described above, those skilled in the art will appreciate that many modifications and variations may be made without departing from the spirit and scope of the appended claims. Therefore, the above examples should be considered in all aspects as illustrative rather than restrictive.

[0145] This application claims the priority benefit of Korean Patent Application No. 10-2023-0157636 filed in the Korean Intellectual Property Office on November 14, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: substrate; a transistor on the substrate; a bit line structure electrically connected to the transistor; a channel layer on the bit line structure; a gate structure intersecting the bit line structure; a first conductive line electrically connecting the transistor and the bit line structure; an upper shielding line vertically overlapping the first conductive line; as well as a plurality of side shielding lines horizontally spaced apart from each other and with the first conductive line interposed therebetween, The upper shield line and the plurality of side shield lines are electrically isolated from the first conductive line and the bit line structure.

2. The semiconductor device according to claim 1, further comprising a second conductive line electrically connecting the first conductive line and the bit line structure, The lower surface of the second conductive line is coplanar with the lower surface of the upper shielding line. 3 . The semiconductor device according to claim 2 , further comprising a lower insulating layer laterally surrounding the second conductive line and the upper shield line. 4 . The semiconductor device according to claim 1 , wherein lower surfaces of the plurality of side shield lines and a lower surface of the first conductive line are coplanar. 5 . The semiconductor device according to claim 1 , further comprising a lower insulating layer laterally surrounding the plurality of side shield lines and the first conductive line.

6. The semiconductor device according to claim 1, further comprising a lower shield line vertically overlapping the first conductive line, wherein the first conductive line is vertically arranged between the upper shielding line and the lower shielding line, and The lower shielding line is electrically isolated from the bit line structure and the first conductive line. 7 . The semiconductor device according to claim 1 , wherein the upper shield line and the plurality of side shield lines are configured to receive power from a power source.

8. A semiconductor device comprising: substrate; a first transistor on the substrate; a bit line structure electrically connected to the first transistor; a channel layer on the bit line structure; a gate structure intersecting the bit line structure; a first conductive line and a second conductive line electrically connecting the first transistor and the bit line structure; an upper shielding line vertically overlapping the first conductive line; as well as a plurality of side shielding lines horizontally spaced apart from each other and with the first conductive line interposed therebetween, wherein the upper shielding line is located at the same vertical level as the second conductive line, and The first conductive line is located at the same vertical level as the plurality of side shielding lines. 9 . The semiconductor device of claim 8 , wherein the upper shield line and the plurality of side shield lines are electrically isolated from the first conductive line, the second conductive line, and the bit line structure. 10 . The semiconductor device according to claim 8 , wherein a lower surface of the upper shield line and an upper surface of the first conductive line face each other.

11. The semiconductor device according to claim 8, further comprising: a lower cover layer between the upper shielding line and the first conductive line; as well as a first contact extending through the lower cover layer, The first contact contacts an upper surface of the first conductive line and a lower surface of the second conductive line.

12. The semiconductor device according to claim 11, wherein the upper surface of the first conductive line and the upper surfaces of the plurality of side shield lines are in contact with a lower surface of the lower cover layer, and The lower surface of the second conductive line and the lower surface of the upper shielding line are in contact with the upper surface of the lower cover layer.

13. The semiconductor device according to claim 11, further comprising a second contact extending through the lower cap layer, The second contact contacts a lower surface of the upper shield line and an upper surface of one of the plurality of side shield lines. 14 . The semiconductor device of claim 8 , wherein the bit line structure is located at a higher vertical level than the first conductive line, the second conductive line, the upper shield line, and the side shield line.

15. The semiconductor device according to claim 8, further comprising: a landing pad electrically connected to the channel layer; as well as A data storage structure is electrically connected to the landing pad.

16. The semiconductor device according to claim 8, wherein the first transistor comprises an impurity region and a peripheral gate electrode layer, and The semiconductor device includes a transistor contact electrically connecting the first conductive line and the impurity region.

17. The semiconductor device according to claim 8, further comprising a second transistor on the substrate, The upper shield line and the plurality of side shield lines are configured to receive power through the second transistor.

18. The semiconductor device according to claim 8, wherein the bit line structure extends in a first direction, wherein the gate structure extends in a second direction orthogonal to the first direction, the first direction and the second direction are horizontal directions, and A length of each of the plurality of side shield lines and the first conductive line in the first direction is greater than a length of each of the plurality of side shield lines and the first conductive line in the second direction.

19. A semiconductor device comprising: substrate; a first transistor and a second transistor on the substrate; a bit line structure electrically connected to the first transistor; a channel layer on the bit line structure; a gate structure intersecting the bit line structure; a data storage structure electrically connected to the channel layer; a first conductive line and a second conductive line electrically connecting the first transistor and the bit line structure; an upper shield line and a plurality of side shield lines electrically connected to the second transistor; a first lower insulating layer laterally surrounding the first conductive wire and the plurality of side shield wires; as well as a second lower insulating layer laterally surrounding the second conductive line and the upper shielding line, wherein the upper shielding line vertically overlaps with the first conductive line, and wherein the plurality of side shielding lines are horizontally spaced apart from each other and the first conductive line is interposed therebetween.

20. The semiconductor device according to claim 19, further comprising a connection pad located at a higher vertical level than the channel layer, The upper shield line and the plurality of side shield lines are configured to receive power through the connection pad and the second transistor.

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