Two-dimensional heterojunction floating gate device with reconfigurable function and preparation method thereof

Abstract

The invention provides a two-dimensional heterojunction floating gate device with a reconfigurable function and a preparation method thereof, and relates to the technical field of semiconductors. An insulating dielectric layer of the lower plate is provided with a plurality of metal input electrodes, and a first two-dimensional material insulating dielectric layer is provided with a plurality of preset two-dimensional material floating gate layers; the first two-dimensional material tunneling layer is provided with a plurality of preset two-dimensional material channel layers, a first two-dimensional material conducting medium layer and a plurality of preset metal output electrodes; the second two-dimensional material tunneling layer is provided with a plurality of target two-dimensional material channel layers, a second two-dimensional material conducting medium layer and a plurality of target metal output electrodes; the third two-dimensional material tunneling layer is provided with a plurality of target two-dimensional material floating gate layers; the second two-dimensional material insulating dielectric layer is provided with an upper plate of a plurality of metal input electrodes; and the upper plates of the plurality of metal input electrodes are connected with the lower plates of the plurality of metal input electrodes through fly wires. The two-dimensional heterojunction floating gate device can realize a memory function and realize a complex logic function under the same device architecture.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a two-dimensional heterojunction floating gate device with reconfigurable function and a preparation method thereof. Background Art

[0002] With the development of artificial intelligence and the explosive growth of information in the era of big data, the requirements for information storage space and storage speed are getting higher and higher. Current computers are all based on the traditional von Neumann architecture, but the storage unit and computing unit of the traditional von Neumann architecture are separated, which will cause time delays and increase power consumption during data transmission. Combining the storage unit that performs logical operations with the storage unit that saves data can be used as a new type of integrated storage and computing chip to surpass the traditional von Neumann architecture.

[0003] Two-dimensional layered materials are thin, have a flat surface, and have excellent electrical properties. Two-dimensional materials with different properties are stacked to construct a two-dimensional heterojunction, which can be used in floating gate memory devices. When the size of traditional semiconductor floating gate memory is reduced to the limit, it will have performance degradation and serious leakage. Compared with traditional semiconductor floating gate memory, two-dimensional material heterojunction floating gate memory has a small size, low storage cost, high storage density, a certain storage window, a high switching ratio, a faster erase and read speed, and excellent charge retention and durability.

[0004] Existing two-dimensional material heterojunction floating gate memory uses heavily doped silicon substrate as control gate, SiO2 or high-k dielectric as control gate dielectric layer, graphene as floating gate layer, hexagonal boron nitride (h-BN) as tunneling layer, and transition metal sulfide as channel layer. However, although the existing two-dimensional material heterojunction floating gate memory can realize storage function, it cannot realize complex logic function under the same device architecture. Summary of the invention

[0005] The purpose of the embodiments of the present invention is to provide a two-dimensional heterojunction floating gate device with reconfigurable function and a preparation method thereof, which solves the problem that the existing two-dimensional material heterojunction floating gate memory cannot realize complex logic functions under the same device architecture.

[0006] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0007] The first aspect of the present invention provides a two-dimensional heterojunction floating gate device with a reconfigurable function, comprising a semiconductor substrate, an insulating dielectric layer, a first two-dimensional material insulating dielectric layer, a first two-dimensional material tunneling layer, a second two-dimensional material tunneling layer, a third two-dimensional material tunneling layer and a second two-dimensional material insulating dielectric layer, which are arranged in sequence from bottom to top;

[0008] A bottom plate of a plurality of metal input electrodes is disposed in the top region of the insulating dielectric layer, and a plurality of floating gate layers of a preset two-dimensional material is disposed in the top region of the first two-dimensional material insulating dielectric layer;

[0009] A top region of the first two-dimensional material tunneling layer is provided with a plurality of preset two-dimensional material channel layers, a first two-dimensional material conductive medium layer and a plurality of preset metal output electrodes, and the plurality of preset two-dimensional material channel layers and the first two-dimensional material conductive medium layer are in contact;

[0010] A top region of the second two-dimensional material tunneling layer is provided with a plurality of target two-dimensional material channel layers, a second two-dimensional material conductive medium layer, and a plurality of target metal output electrodes, and the plurality of target two-dimensional material channel layers and the second two-dimensional material conductive medium layer are in contact;

[0011] The top area of ​​the third two-dimensional material tunneling layer is provided with multiple target two-dimensional material floating gate layers; the top area of ​​the second two-dimensional material insulating dielectric layer is provided with multiple upper plates of metal input electrodes; the upper plates of the multiple metal input electrodes are connected to the lower plates of the multiple metal input electrodes by flying wires.

[0012] A second aspect of the present invention provides a method for preparing a two-dimensional heterojunction floating gate device with a reconfigurable function, comprising:

[0013] Selecting a semiconductor substrate and cleaning the semiconductor substrate by a wet chemical cleaning method, wherein the semiconductor substrate is a doped substrate;

[0014] growing an insulating dielectric layer on the surface of the cleaned semiconductor substrate;

[0015] Etching is performed on the surface of the insulating dielectric layer, and a lower plate of a plurality of metal input electrodes is prepared;

[0016] Growing a first two-dimensional material insulating dielectric layer on the surface of the lower plate of the plurality of metal input electrodes;

[0017] Etching a first preset area on the surface of the first two-dimensional insulating dielectric layer to obtain a first pattern, and growing a plurality of preset two-dimensional material floating gate layers on the surface of the etched first two-dimensional insulating dielectric layer;

[0018] Growing a first two-dimensional material tunneling layer on the surface of the etched first two-dimensional material insulating dielectric layer;

[0019] Etching a second preset area on the surface of the first two-dimensional material tunneling layer to obtain a second pattern, and growing a plurality of preset two-dimensional material channel layers on the surface of the etched first two-dimensional material tunneling layer;

[0020] Etching a third preset area on the surface of the etched first two-dimensional material tunneling layer to obtain a third pattern, and growing a first two-dimensional material conductive dielectric layer on the surface of the newly etched first two-dimensional material tunneling layer;

[0021] Etching a fourth preset area on the surface of the newly etched first two-dimensional material tunneling layer to obtain a fourth pattern, and preparing a plurality of preset metal output electrodes on the surface of the newly etched first two-dimensional material tunneling layer, wherein the second preset area, the third preset area and the fourth preset area are all different;

[0022] Growing a second two-dimensional material tunneling layer on the surface of the first two-dimensional material tunneling layer after the latest etching;

[0023] Etching a fifth preset area on the surface of the second two-dimensional material tunneling layer to obtain a fifth pattern, and growing a plurality of target two-dimensional material channel layers on the surface of the etched second two-dimensional material tunneling layer;

[0024] Etching a sixth preset area on the surface of the etched second two-dimensional material tunneling layer to obtain a sixth pattern, and growing a second two-dimensional material conductive dielectric layer on the surface of the newly etched second two-dimensional material tunneling layer;

[0025] Etching is performed on a seventh preset area on the surface of the newly etched second two-dimensional material tunneling layer to obtain a seventh pattern, and a plurality of target metal output electrodes are prepared on the surface of the newly etched second two-dimensional material tunneling layer, wherein the fifth preset area, the sixth preset area and the seventh preset area are all different;

[0026] Growing a third two-dimensional material tunneling layer on the surface of the second two-dimensional material tunneling layer that has been etched most recently;

[0027] Etching an eighth preset area on the surface of the third two-dimensional material tunneling layer to obtain an eighth pattern, and growing a plurality of target two-dimensional material floating gate layers on the surface of the etched third two-dimensional material tunneling layer;

[0028] Growing an insulating dielectric layer of a second two-dimensional material on the surface of the etched third two-dimensional material tunneling layer;

[0029] Etching is performed on the surface of the second two-dimensional material insulating dielectric layer, and an upper plate of multiple metal input electrodes is prepared, and the upper plate of multiple metal input electrodes is connected to a lower plate of multiple metal input electrodes by using flying wires.

[0030] A third aspect of the present invention provides an electrical control method for a two-dimensional heterojunction floating gate device with a reconfigurable function, which is implemented based on the two-dimensional heterojunction floating gate device with a reconfigurable function, and includes:

[0031] Among a plurality of preset metal output electrodes and a plurality of target metal output electrodes, select any one or two metal output electrodes as source electrodes, and select any one or two metal output electrodes other than the source electrodes as drain electrodes;

[0032] The source electrode and the drain electrode are used as target metal output electrodes;

[0033] Inputting a positive voltage as an input level value 1 to a first metal input electrode and a second metal input electrode among the plurality of metal input electrodes, or inputting a negative voltage as an input level value 0 to the first metal input electrode and the second metal input electrode;

[0034] The source electrode in the target metal output electrode is grounded, and the drain electrode is connected to a positive voltage, and the current between the source electrode and the drain electrode is measured to obtain two current values;

[0035] The minimum current value and the maximum current value of the two current values ​​are determined, and the minimum current value is used as the output level value 0, and the maximum current value is used as the output level value 1, so as to realize the electrical control of the target logic function.

[0036] Compared with the prior art, the present invention provides a two-dimensional heterojunction floating gate device with reconfigurable function and a preparation method thereof. The two-dimensional heterojunction floating gate device with reconfigurable function includes a semiconductor substrate, an insulating dielectric layer, a first two-dimensional material insulating dielectric layer, a first two-dimensional material tunneling layer, a second two-dimensional material tunneling layer, a third two-dimensional material tunneling layer and a second two-dimensional material insulating dielectric layer arranged in sequence from bottom to top; a lower plate with multiple metal input electrodes is arranged in the top region of the insulating dielectric layer, a multiple preset two-dimensional material floating gate layers are arranged in the top region of the first two-dimensional material insulating dielectric layer; a multiple preset two-dimensional material channel layers are arranged in the top region of the first two-dimensional material tunneling layer, The first two-dimensional material conductive dielectric layer and multiple preset metal output electrodes, and the multiple preset two-dimensional material channel layers are in contact with the first two-dimensional material conductive dielectric layer; the top region of the second two-dimensional material tunneling layer is provided with multiple target two-dimensional material channel layers, the second two-dimensional material conductive dielectric layer and multiple target metal output electrodes, and the multiple target two-dimensional material channel layers are in contact with the second two-dimensional material conductive dielectric layer; the top region of the third two-dimensional material tunneling layer is provided with multiple target two-dimensional material floating gate layers; the top region of the second two-dimensional material insulating dielectric layer is provided with multiple upper plates of metal input electrodes; the upper plates of multiple metal input electrodes are connected to the lower plates of multiple metal input electrodes by flying wires. In this way, the upper plates of multiple metal input electrodes and the lower plates of multiple metal input electrodes after connection can be used as different inputs of electrical modulation, so that the two-dimensional heterojunction floating gate device with reconfigurable function can realize memory function, and can also realize complex logic function under the same device architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0038] Figure 1 The structure of a two-dimensional heterojunction floating gate device with reconfigurable function is schematically shown;

[0039] Figure 2 A flow chart of a method for preparing a two-dimensional heterojunction floating gate device with reconfigurable function is schematically shown;

[0040] Figure 3 A process flow chart for growing a first two-dimensional material tunneling layer is schematically shown;

[0041] Figure 4 A process flow chart for growing a second two-dimensional material conductive dielectric layer is schematically shown;

[0042] Figure 5 A process flow chart schematically illustrates connecting an upper plate of a plurality of metal input electrodes to a lower plate of a plurality of metal input electrodes;

[0043] Figure 6 A flow chart of an electrical control method for a two-dimensional heterojunction floating gate device with reconfigurable function is schematically shown;

[0044] Figure 7 A schematic top view of the first conductive layer polarity is shown;

[0045] Figure 8 A schematic top view of the second conductive layer polarity is shown;

[0046] Fig. 9 A schematic top view of a third conductive layer polarity is shown;

[0047] Fig.10 A top view of a fourth conductive layer polarity is schematically shown.

[0048] Description of Reference Numerals

[0049] 1. semiconductor substrate; 2. insulating dielectric layer; 3. first metal input electrode; 4. second metal input electrode; 5. first two-dimensional material insulating dielectric layer; 6. first two-dimensional material floating gate layer; 7. second two-dimensional material floating gate layer; 8. third two-dimensional material floating gate layer; 9. fourth two-dimensional material floating gate layer; 10. first two-dimensional material tunneling layer; 11. first two-dimensional material channel layer; 12. second two-dimensional material channel layer; 13. first two-dimensional material conductive dielectric layer; 14. first metal output electrode; 15. second metal output electrode; 16. third metal output electrode; 17 , fourth metal output electrode; 18, second two-dimensional material tunneling layer; 19, third two-dimensional material channel layer; 20, fourth two-dimensional material channel layer; 21, second two-dimensional material conductive dielectric layer; 22, fifth metal output electrode; 23, sixth metal output electrode; 24, seventh metal output electrode; 25, eighth metal output electrode; 26, third two-dimensional material tunneling layer; 27, fifth two-dimensional material floating gate layer; 28, sixth two-dimensional material floating gate layer; 29, seventh two-dimensional material floating gate layer; 30, eighth two-dimensional material floating gate layer; 31, second two-dimensional material insulating dielectric layer. DETAILED DESCRIPTION

[0050] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0051] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in the present invention should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0052] The method in the embodiment of the present invention is described in detail below.

[0053] Figure 1 The structure of a two-dimensional heterojunction floating gate device with a reconfigurable function is schematically shown, including a semiconductor substrate 1, an insulating dielectric layer 2, a first two-dimensional material insulating dielectric layer 5, a first two-dimensional material tunneling layer 10, a second two-dimensional material tunneling layer 18, a third two-dimensional material tunneling layer 26 and a second two-dimensional material insulating dielectric layer 31, which are arranged in sequence from bottom to top;

[0054] The top region of the insulating dielectric layer 2 is provided with a plurality of lower plates of metal input electrodes, and the top region of the first two-dimensional material insulating dielectric layer 5 is provided with a plurality of floating gate layers of preset two-dimensional materials;

[0055] The top region of the first two-dimensional material tunneling layer 10 is provided with a plurality of preset two-dimensional material channel layers, a first two-dimensional material conductive medium layer 13 and a plurality of preset metal output electrodes, and the plurality of preset two-dimensional material channel layers and the first two-dimensional material conductive medium layer 13 are in contact;

[0056] A top region of the second two-dimensional material tunneling layer 18 is provided with a plurality of target two-dimensional material channel layers, a second two-dimensional material conductive medium layer 21 and a plurality of target metal output electrodes, and the plurality of target two-dimensional material channel layers and the second two-dimensional material conductive medium layer 21 are in contact;

[0057] The top area of ​​the third two-dimensional material tunneling layer 26 is provided with multiple target two-dimensional material floating gate layers; the top area of ​​the second two-dimensional material insulating dielectric layer 31 is provided with multiple upper plates of metal input electrodes; the upper plates of the multiple metal input electrodes are connected to the lower plates of the multiple metal input electrodes by flying wires.

[0058] In this embodiment, multiple preset two-dimensional material floating gate layers are located directly above the lower plate of multiple metal input electrodes; multiple preset two-dimensional material channel layers are directly above the multiple preset two-dimensional material floating gate layers; multiple target two-dimensional material channel layers are directly above the multiple preset metal output electrodes; multiple target two-dimensional material floating gate layers are directly above the multiple target two-dimensional material channel layers; and the upper plate of multiple metal input electrodes is directly above the multiple preset two-dimensional material floating gate layers and the multiple target two-dimensional material floating gate layers.

[0059] In this embodiment, the lower plates of the plurality of metal input electrodes include the lower plates of the first metal input electrodes 3 and the lower plates of the second metal input electrodes 4 which are arranged at intervals;

[0060] The multiple preset two-dimensional material floating gate layers include a first two-dimensional material floating gate layer 6, a second two-dimensional material floating gate layer 7, a third two-dimensional material floating gate layer 8 and a fourth two-dimensional material floating gate layer 9 arranged at intervals. The second two-dimensional material floating gate layer 7 is directly above the lower plate of the second metal input electrode 4, and the third two-dimensional material floating gate layer 8 is directly above the lower plate of the first metal input electrode 3.

[0061] In this embodiment, the plurality of preset two-dimensional material channel layers include a first two-dimensional material channel layer 11 and a second two-dimensional material channel layer 12 arranged at intervals, and the first two-dimensional material channel layer 11 and the second two-dimensional material channel layer 12 are both in contact with the first two-dimensional material conductive medium layer 13; the plurality of preset metal output electrodes include a first metal output electrode 14, a second metal output electrode 15, a third metal output electrode 16 and a fourth metal output electrode 17 arranged at intervals, and the first metal output electrode 14 and the third metal output electrode 16 are symmetrically arranged, and the second metal output electrode 15 and the fourth metal output electrode 17 are symmetrically arranged;

[0062] The first two-dimensional material channel layer 11 is directly above the first two-dimensional material floating gate layer 6 and the second two-dimensional material floating gate layer 7 , and the second two-dimensional material channel layer 12 is directly above the third two-dimensional material floating gate layer 8 and the fourth two-dimensional material floating gate layer 9 .

[0063] In this embodiment, the multiple target two-dimensional material channel layers include a third two-dimensional material channel layer 19 and a fourth two-dimensional material channel layer 20 arranged at intervals, and the third two-dimensional material channel layer 19 and the fourth two-dimensional material channel layer 20 are both in contact with the second two-dimensional material conductive medium layer 21; the multiple target metal output electrodes include a fifth metal output electrode 22, a sixth metal output electrode 23, a seventh metal output electrode 24 and an eighth metal output electrode 25 arranged at intervals, and the fifth metal output electrode 22 is symmetrically arranged with the seventh metal output electrode 24, and the sixth metal output electrode 23 is symmetrically arranged with the eighth metal output electrode 25;

[0064] The third two-dimensional material channel layer 19 is directly above the first metal output electrode 14 and the second metal output electrode 15 , and the fourth two-dimensional material channel layer 20 is directly above the third metal output electrode 16 and the fourth metal output electrode 17 .

[0065] In this embodiment, the plurality of target two-dimensional material floating gate layers include a fifth two-dimensional material floating gate layer 27, a sixth two-dimensional material floating gate layer 28, a seventh two-dimensional material floating gate layer 29 and an eighth two-dimensional material floating gate layer 30 which are arranged at intervals; the fifth two-dimensional material floating gate layer 27 and the sixth two-dimensional material floating gate layer 28 are directly above the third two-dimensional material channel layer 19; the seventh two-dimensional material floating gate layer 29 and the eighth two-dimensional material floating gate layer 30 are directly above the fourth two-dimensional material channel layer 20; the fifth two-dimensional material floating gate layer 27 is directly above the second two-dimensional material floating gate layer 7; the eighth two-dimensional material floating gate layer 30 is directly above the third two-dimensional material floating gate layer 8;

[0066] The upper plates of the plurality of metal input electrodes include an upper plate of a first metal input electrode 3 and an upper plate of a second metal input electrode 4 arranged at intervals, the upper plate of the first metal input electrode 3 is directly above the first two-dimensional material floating gate layer 6 and the sixth two-dimensional material floating gate layer 28, and the upper plate of the second metal input electrode 4 is directly above the fourth two-dimensional material floating gate layer 9 and the seventh two-dimensional material floating gate layer 29;

[0067] The upper plate of the first metal input electrode 3 is connected to the lower plate of the first metal input electrode 3 by a flying wire, and the upper plate of the second metal input electrode 4 is connected to the lower plate of the second metal input electrode 4 by a flying wire.

[0068] In this embodiment, the materials of the first two-dimensional material channel layer 11 , the second two-dimensional material channel layer 12 , the third two-dimensional material channel layer 19 and the fourth two-dimensional material channel layer 20 are all selected from materials with less than 15 layers;

[0069] The materials of the first two-dimensional material floating gate layer 6, the second two-dimensional material floating gate layer 7, the third two-dimensional material floating gate layer 8, the fourth two-dimensional material floating gate layer 9, the fifth two-dimensional material floating gate layer 27, the sixth two-dimensional material floating gate layer 28, the seventh two-dimensional material floating gate layer 29 and the eighth two-dimensional material floating gate layer 30 are all multi-layer materials with 10 to 30 layers.

[0070] In this embodiment, the thicknesses of the insulating dielectric layer 2 , the first two-dimensional material insulating dielectric layer 5 , and the second two-dimensional material insulating dielectric layer 31 are all 10-20 nm.

[0071] Specifically, the semiconductor substrate 1 includes a silicon substrate with a certain doping concentration. The semiconductor substrate 1 can be selected from a silicon substrate with a doping concentration of 10 17 -10 19 / cm 3 , a silicon wafer with a resistivity of 1-3Ω*cm and a thickness of 300-600μm. Preferably, the semiconductor substrate 1 selected in this embodiment is P-type doped, with a doping concentration of 10 18 / cm 3 , silicon wafer with resistivity of 2Ω*cm and thickness of 500μm.

[0072] The first metal input electrode 3, the second metal input electrode 4, the first metal output electrode 14, the second metal output electrode 15, the third metal output electrode 16, the fourth metal output electrode 17, the fifth metal output electrode 22, the sixth metal output electrode 23, the seventh metal output electrode 24 and the eighth metal output electrode 25 all include a single metal or a stack of two metals such as titanium, chromium, tungsten, gold, silver, platinum, copper, etc. Preferably, the present embodiment selects a metal gold stack with a thickness of 10nm.

[0073] The first two-dimensional material floating gate layer 6, the second two-dimensional material floating gate layer 7, the third two-dimensional material floating gate layer 8, the fourth two-dimensional material floating gate layer 9, the fifth two-dimensional material floating gate layer 27, the sixth two-dimensional material floating gate layer 28, the seventh two-dimensional material floating gate layer 29 and the eighth two-dimensional material floating gate layer 30 can all be made of graphene and transition metal sulfides with more defects, and the transition metal sulfides include MoS2, WS2, ReS2, WSe2, MoSe2, PtS2, PtSe2, ReSe2, etc. Preferably, in this embodiment, graphene is selected as the first two-dimensional material floating gate layer 6, the second two-dimensional material floating gate layer 7, the third two-dimensional material floating gate layer 8, the fourth two-dimensional material floating gate layer 9, the fifth two-dimensional material floating gate layer 27, the sixth two-dimensional material floating gate layer 28, the seventh two-dimensional material floating gate layer 29 and the eighth two-dimensional material floating gate layer 30, and the thickness is 10nm.

[0074] The first two-dimensional material tunneling layer 10, the second two-dimensional material tunneling layer 18 and the third two-dimensional material tunneling layer 26 can all be made of two-dimensional insulating materials with a large bandgap, such as CuInP2S6, h-BN, etc. Preferably, in this embodiment, h-BN is selected as the first two-dimensional material tunneling layer 10 and the third two-dimensional material tunneling layer 26, and the thickness is 20nm. The second two-dimensional material tunneling layer 18 has a thickness of 10nm.

[0075] The first two-dimensional material channel layer 11, the second two-dimensional material channel layer 12, the third two-dimensional material channel layer 19 and the fourth two-dimensional material channel layer 20 can all be made of bipolar two-dimensional transition metal selenides and tellurides with high electron mobility, such as WSe2, MoSe2, PtSe2, ReSe2, MoTe2, etc. In order to improve the conductivity of the device, all of the above two-dimensional material channel layers are made of less than 15 layers of material. Preferably, in this embodiment, WSe2 is selected as the first two-dimensional material channel layer 11, the second two-dimensional material channel layer 12, the third two-dimensional material channel layer 19 and the fourth two-dimensional material channel layer 20, and the thickness is 10nm.

[0076] The first two-dimensional material conductive medium layer 13 and the second two-dimensional material conductive medium layer 21 can both be made of semi-metallic materials whose Fermi level is not easily regulated, including graphene and NbSe2. Preferably, in this embodiment, graphene is selected as the first two-dimensional material conductive medium layer 13 and the second two-dimensional material conductive medium layer 21, and the thickness of the first two-dimensional material conductive medium layer 13 and the second two-dimensional material conductive medium layer 21 are both 10nm. The first two-dimensional material conductive medium layer 13 and the second two-dimensional material conductive medium layer 21 are both made of less than 15 layers of material.

[0077] The insulating dielectric layer 2, the first two-dimensional insulating dielectric layer 5, and the second two-dimensional insulating dielectric layer 31 can all be made of high dielectric constant insulating materials, such as HfO2, Al2O3, ZrO2, Hf 0.5 Zr 0.5 O2, Hf 0.5 Al 0.5 O2, La 0.5 Al 0.5 O2, SiO2, La2O3, etc. In order to improve the gate control capability of the two-dimensional heterojunction floating gate device with reconfigurable function, the thickness of the insulating dielectric layer 2, the first two-dimensional material insulating dielectric layer 5, and the second two-dimensional material insulating dielectric layer 31 are all 10-20nm. Preferably, in this embodiment, Al2O3 is selected as the insulating dielectric layer 2, the first two-dimensional material insulating dielectric layer 5, and the second two-dimensional material insulating dielectric layer 31, and the thickness is 20nm.

[0078] The two-dimensional heterojunction floating gate device with reconfigurable function proposed in the present invention is used to simplify the structure of integrated circuits, reduce the number of integrated circuit devices, improve the computing speed, and reduce computing energy consumption.

[0079] Based on the above Figure 1 It can be seen from the implementation method that the two-dimensional heterojunction floating gate device with reconfigurable function in the embodiment of the present invention includes a semiconductor substrate 1, an insulating dielectric layer 2, a first two-dimensional material insulating dielectric layer 5, a first two-dimensional material tunneling layer 10, a second two-dimensional material tunneling layer 18, a third two-dimensional material tunneling layer 26 and a second two-dimensional material insulating dielectric layer 31 arranged in sequence from bottom to top; the top region of the insulating dielectric layer 2 is provided with a lower plate of multiple metal input electrodes, and the top region of the first two-dimensional material insulating dielectric layer 5 is provided with multiple preset two-dimensional material floating gate layers; the top region of the first two-dimensional material tunneling layer 10 is provided with multiple preset two-dimensional material channel layers, the first two-dimensional material conductive dielectric layer 13 and multiple preset metal output electrodes, and multiple preset two-dimensional material channel layers are in contact with the first two-dimensional material conductive dielectric layer 13; the top region of the second two-dimensional material tunneling layer 18 is provided with multiple target two-dimensional material channel layers, the second two-dimensional material conductive dielectric layer 21 and multiple target metal output electrodes, and the multiple target two-dimensional material channel layers are in contact with the second two-dimensional material conductive dielectric layer 21; the top region of the third two-dimensional material tunneling layer 26 is provided with multiple target two-dimensional material floating gate layers; the top region of the second two-dimensional material insulating dielectric layer 31 is provided with multiple upper plates of metal input electrodes; the upper plates of multiple metal input electrodes are connected to the lower plates of multiple metal input electrodes by flying wires. In this way, the upper plates of multiple metal input electrodes and the lower plates of multiple metal input electrodes after connection can be used as different inputs of electrical modulation, so that the two-dimensional heterojunction floating gate device with reconfigurable function can realize memory function, and can also realize complex logic function under the same device architecture.

[0080] Figure 2 The method for preparing a two-dimensional heterojunction floating gate device with reconfigurable function in an embodiment of the present invention is schematically shown. Figure 2 As shown, the method for preparing the two-dimensional heterojunction floating gate device with reconfigurable function may include:

[0081] S201 , selecting a semiconductor substrate 1 , and cleaning the semiconductor substrate 1 using a wet chemical cleaning method.

[0082] The semiconductor substrate 1 is a doped substrate.

[0083] The semiconductor substrate 1 may be a silicon substrate, the doping type of the silicon substrate includes P-type doping, and the doping concentration of the silicon substrate is 10 17 -10 19 / cm 3, resistivity is 1-3Ω*cm, thickness is 300~600μm.

[0084] S202 , growing an insulating dielectric layer 2 on the surface of the cleaned semiconductor substrate 1 .

[0085] Specifically, the method for growing the insulating dielectric layer 2 includes an atomic layer electrode method or a magnetron sputtering method.

[0086] The material of the insulating dielectric layer 2 includes insulating materials that meet the requirements of high dielectric constant, including HfO2, Al2O3, ZrO2, Hf 0.5 Zr 0.5 O2, Hf 0.5 Al 0.5 O2, La 0.5 Al 0.5 O2, SiO2, La2O3.

[0087] The thickness of the insulating dielectric layer 2 is 10-20 nm.

[0088] S203, etching is performed on the surface of the insulating dielectric layer 2, and a lower plate of a plurality of metal input electrodes is prepared.

[0089] Specifically, the number of the lower plates of the multiple metal input electrodes can be two, and the method of preparing the lower plates of the two metal input electrodes includes thermal evaporation and electron beam evaporation. The surface of the insulating dielectric layer 2 is etched, and the etching method used includes plasma etching.

[0090] The lower plate of the plurality of metal input electrodes includes any one of the preset single metals or a stack of any two of the preset single metals; wherein the preset single metals include titanium, chromium, tungsten, gold, silver, platinum and copper.

[0091] S204, growing a first two-dimensional material insulating dielectric layer 5 on the surface of the lower plate of the plurality of metal input electrodes.

[0092] Specifically, the method for growing the first two-dimensional material insulating dielectric layer 5 includes chemical vapor deposition. The material of the first two-dimensional material insulating dielectric layer 5 includes insulating materials that meet the requirements of high dielectric constants, including HfO2, Al2O3, ZrO2, Hf 0.5 Zr 0.5 O2, Hf 0.5 Al 0.5 O2, La 0.5 Al 0.5 O2, SiO2, La2O3.

[0093] The thickness of the first two-dimensional material insulating dielectric layer 5 is 10-20 nm.

[0094] S205 , etching is performed on a first preset area on the surface of the first two-dimensional insulating dielectric layer 5 to obtain a first pattern, and a plurality of preset two-dimensional material floating gate layers are grown on the surface of the etched first two-dimensional insulating dielectric layer 5 .

[0095] Specifically, the number of the plurality of preset two-dimensional material floating gate layers can be four, and etching is performed on the first preset area on the surface of the first two-dimensional material insulating dielectric layer 5, and the etching method adopted includes plasma etching. The method for growing the plurality of preset two-dimensional material floating gate layers includes chemical phase deposition.

[0096] The materials of the multiple preset two-dimensional material floating gate layers include graphene and transition metal sulfides; among them, the transition metal sulfides include MoS2, WS2, ReS2, WSe2, MoSe2, PtS2, PtSe2, and ReSe2.

[0097] The materials of the multiple preset two-dimensional material floating gate layers are all multi-layer materials with 10 to 30 layers.

[0098] S206 , growing a first two-dimensional material tunneling layer 10 on the surface of the etched first two-dimensional material insulating dielectric layer 5 .

[0099] Specifically, the method for growing the first two-dimensional material tunneling layer 10 includes chemical vapor deposition. The material of the first two-dimensional material tunneling layer 10 includes a two-dimensional insulating material that meets the requirement of a large bandgap width, including CuInP2S6 and h-BN.

[0100] S207 , etching is performed on a second preset area on the surface of the first two-dimensional material tunneling layer 10 to obtain a second pattern, and a plurality of preset two-dimensional material channel layers are grown on the surface of the first two-dimensional material tunneling layer 10 after etching.

[0101] Specifically, the number of the plurality of preset two-dimensional material channel layers may be two, and the method for growing the plurality of preset two-dimensional material channel layers includes chemical vapor deposition.

[0102] Etching is performed on a second preset region on the surface of the first two-dimensional material tunneling layer 10, and the etching method used includes a plasma etching method. The method for growing a plurality of preset two-dimensional material channel layers includes a chemical vapor deposition method.

[0103] The materials of multiple preset two-dimensional material channel layers include bipolar two-dimensional transition metal selenides and tellurides that meet the requirements of high electron mobility, including WSe2, MoSe2, PtSe2, ReSe 2、 MoTe2.

[0104] The materials of the multiple preset two-dimensional material channel layers are all selected to be less than 15 layers.

[0105] S208 , etching a third preset area on the surface of the etched first two-dimensional material tunneling layer 10 to obtain a third pattern, and growing a first two-dimensional material conductive dielectric layer 13 on the surface of the newly etched first two-dimensional material tunneling layer 10 .

[0106] Specifically, the third preset area on the surface of the etched first two-dimensional material tunneling layer 10 is etched, and the etching method used includes plasma etching. The method for growing the first two-dimensional material conductive dielectric layer 13 includes chemical vapor deposition.

[0107] The material of the first two-dimensional conductive medium layer 13 includes semi-metal materials whose Fermi level is not easily regulated, including graphene and NbSe2.

[0108] S209, etching the fourth preset area on the surface of the newly etched first two-dimensional material tunneling layer 10 to obtain a fourth pattern, and preparing a plurality of preset metal output electrodes on the surface of the newly etched first two-dimensional material tunneling layer 10.

[0109] Among them, the second preset area, the third preset area and the fourth preset area are all different.

[0110] Specifically, the number of the plurality of preset metal output electrodes can be four, and the method for preparing the four preset metal output electrodes includes thermal evaporation and electron beam evaporation. The fourth preset area on the surface of the newly etched first two-dimensional material tunneling layer 10 is etched, and the etching method used includes plasma etching.

[0111] S210 , growing a second two-dimensional material tunneling layer 18 on the surface of the first two-dimensional material tunneling layer 10 that has been recently etched.

[0112] Specifically, the method for growing the second two-dimensional material tunneling layer 18 includes chemical vapor deposition. The material of the second two-dimensional material tunneling layer 18 includes two-dimensional insulating materials that meet the requirement of a large bandgap width, including CuInP2S6 and h-BN.

[0113] S211 , etching is performed on a fifth preset area on the surface of the second two-dimensional material tunneling layer 18 to obtain a fifth pattern, and a plurality of target two-dimensional material channel layers are grown on the surface of the etched second two-dimensional material tunneling layer 18 .

[0114] Specifically, the number of the multiple target two-dimensional material channel layers can be two, and etching is performed on the fifth preset area on the surface of the second two-dimensional material tunneling layer 18, and the etching method used includes plasma etching. The method of growing multiple target two-dimensional material channel layers includes chemical vapor deposition.

[0115] The materials of the channel layer of multiple target two-dimensional materials include bipolar two-dimensional transition metal selenides and tellurides that meet the requirements of high electron mobility, including WSe2, MoSe2, PtSe2, ReSe 2、 MoTe2.

[0116] The materials of multiple target two-dimensional material channel layers are all selected to have less than 15 layers.

[0117] S212 , etching a sixth preset area on the surface of the etched second two-dimensional material tunneling layer 18 to obtain a sixth pattern, and growing a second two-dimensional material conductive dielectric layer 21 on the surface of the newly etched second two-dimensional material tunneling layer 18 .

[0118] Specifically, the sixth preset area on the surface of the etched second two-dimensional material tunneling layer 18 is etched, and the etching method used includes plasma etching. The method for growing the second two-dimensional material conductive dielectric layer 21 includes chemical vapor deposition.

[0119] The material of the second two-dimensional conductive medium layer 21 includes semi-metal materials whose Fermi level is not easily regulated, including graphene and NbSe2.

[0120] S213, etching the seventh preset area on the surface of the newly etched second two-dimensional material tunneling layer 18 to obtain a seventh pattern, and preparing a plurality of target metal output electrodes on the surface of the newly etched second two-dimensional material tunneling layer 18.

[0121] Among them, the fifth preset area, the sixth preset area and the seventh preset area are all different.

[0122] Specifically, the number of the plurality of target metal output electrodes can be four, and the method for preparing the four target metal output electrodes includes thermal evaporation and electron beam evaporation. Etching is performed on the seventh preset area on the surface of the newly etched second two-dimensional material tunneling layer 18, and the etching method used includes plasma etching.

[0123] S214 , growing a third two-dimensional material tunneling layer 26 on the surface of the second two-dimensional material tunneling layer 18 that has been etched most recently.

[0124] Specifically, the method for growing the third two-dimensional material tunneling layer 26 includes chemical vapor deposition. The material of the third two-dimensional material tunneling layer 26 includes a two-dimensional insulating material that meets the requirement of a larger bandgap width, including CuInP2S6 and h-BN.

[0125] S215 , etching is performed on an eighth preset area on the surface of the third two-dimensional material tunneling layer 26 to obtain an eighth pattern, and a plurality of target two-dimensional material floating gate layers are grown on the surface of the third two-dimensional material tunneling layer 26 after etching.

[0126] Specifically, the number of the plurality of target two-dimensional material floating gate layers can be four, and etching is performed in the eighth preset area on the surface of the third two-dimensional material tunneling layer 26, and the etching method used includes plasma etching. The method for growing the plurality of target two-dimensional material floating gate layers includes chemical phase deposition.

[0127] The materials of multiple target two-dimensional material floating gate layers include graphene and transition metal sulfides; among them, transition metal sulfides include MoS2, WS2, ReS2, WSe2, MoSe2, PtS2, PtSe2, and ReSe2.

[0128] The materials for the floating gate layers of multiple target two-dimensional materials are all multi-layer materials with 10 to 30 layers.

[0129] S216 , growing a second two-dimensional material insulating dielectric layer 31 on the surface of the etched third two-dimensional material tunneling layer 26 .

[0130] Specifically, the method for growing the second two-dimensional material insulating dielectric includes chemical vapor deposition. The material of the second two-dimensional material insulating dielectric layer 31 includes insulating materials that meet the requirements of high dielectric constants, including HfO2, Al2O3, ZrO2, Hf 0.5 Zr 0.5 O2, Hf 0.5 Al 0.5 O2, La 0.5 Al 0.5 O2, SiO2, La2O3.

[0131] The thickness of the second two-dimensional material insulating dielectric layer 31 is 10-20 nm.

[0132] S217, etching is performed on the surface of the second two-dimensional material insulating dielectric layer 31, and an upper plate of multiple metal input electrodes is prepared, and the upper plate of multiple metal input electrodes is connected to a lower plate of multiple metal input electrodes by using flying wires.

[0133] Specifically, the number of the upper plates of the plurality of metal input electrodes may be two, and the method for preparing the upper plates of the two metal input electrodes includes a thermal evaporation method and an electron beam evaporation method. The surface of the second two-dimensional material insulating dielectric layer 31 is etched, and the etching method used includes a plasma etching method. The connection method is an external flying wire connection.

[0134] The upper plate of the plurality of metal input electrodes includes any one of the preset single metals or a stack of any two of the preset single metals; wherein the preset single metals include titanium, chromium, tungsten, gold, silver, platinum and copper.

[0135] The present invention provides an optional implementation of a method for preparing a two-dimensional heterojunction floating gate device with a reconfigurable function, specifically:

[0136] Figure 3 The process flow chart of growing the first two-dimensional material tunneling layer 10 is schematically shown, see Figure 3 As shown, Figure 3 (a) is a process flow chart of a cleaned silicon substrate, step A1, selecting a P-type doping concentration of 10 18 / cm 3 Standard RCA cleaning was performed on a silicon substrate with a resistivity of 2Ω*cm and a thickness of 500μm.

[0137] The specific operations of step A1 are as follows:

[0138] Step A11, place the silicon substrate in an acetone solution for ultrasonic cleaning for 5 minutes, place the silicon substrate after acetone cleaning in an ethanol solution for ultrasonic cleaning for 5 minutes, and finally rinse with deionized water for 1 minute to remove organic matter on the silicon substrate.

[0139] Step A12: Clean the silicon substrate in a mixed solution of hydrochloric acid, hydrogen peroxide and deionized water in a ratio of 1:1:6 to remove impurities such as active metals, metal oxides and hydroxides on the silicon substrate.

[0140] Step A13, clean the silicon substrate in a mixed solution of hydrofluoric acid and deionized water in a ratio of 1:50 for 30 seconds, then place it in deionized water and let it stand for 1 minute. Repeat this step 5 times to remove the natural oxide and dangling bonds on the surface of the silicon substrate.

[0141] Step A14: Use a nitrogen gun to blow dry the cleaned silicon substrate.

[0142] Figure 3 The process flow chart of growing the first two-dimensional material tunneling layer 10 is schematically shown, see Figure 3 As shown, Figure 3 (b) is a process flow chart of a sample after growing an Al2O3 insulating dielectric layer 2, step A2, growing an Al2O3 insulating dielectric layer 2 with a thickness of 20 nm on the surface of a cleaned silicon substrate by an ALD method.

[0143] The specific steps of step A2 are as follows:

[0144] Step A21, select ozone as the oxygen source, and select trimethylaluminum (TMA) as the aluminum source.

[0145] Step A22, set the reaction chamber temperature of the ALD equipment to 300° C. and the aluminum source to 90° C., and after the temperatures of the reaction chamber and the aluminum source rise to the set values, evacuate the reaction chamber.

[0146] Step A23, evacuate the reaction chamber, and then fill it with nitrogen at an atmospheric pressure, and repeat this process 3 to 5 times to flush the reaction chamber.

[0147] Step A24, place the cleaned silicon substrate into the reaction chamber, close the chamber and evacuate the reaction chamber, open the gas valves of the oxygen source and the aluminum source, flush the aluminum precursor into the reaction chamber, the pulse time is 1 second, the carrier gas flow rate is 50sccm, after the reaction, fill the reaction chamber with nitrogen with a flow rate of 50sccm to flush the reaction chamber, and the flushing time is 10 seconds.

[0148] Step A25, flush the ozone precursor into the reaction chamber, the pulse time is 1 second, the carrier gas flow rate is 50 sccm, and after the reaction, the reaction chamber is flushed with nitrogen at a flow rate of 50 sccm, and the flushing time is 10 seconds.

[0149] Step A26: Form the Al2O3 medium grown in steps A24 and A25 into a single layer, and repeat steps A24 and A25 multiple times until the thickness of Al2O3 is 20 nm.

[0150] Step A27, after the thickness of the Al2O3 medium reaches a preset value through cyclic growth, nitrogen is filled into the reaction chamber, and when the pressure of the reaction chamber rises to atmospheric pressure, the sample is taken out.

[0151] Step A28, naturally cool the sample on which the Al2O3 dielectric layer is grown in a nitrogen atmosphere to obtain a sample on which the Al2O3 insulating dielectric layer 2 is grown.

[0152] Figure 3 The process flow chart of growing the first two-dimensional material tunneling layer 10 is schematically shown, see Figure 3 As shown, Figure 3 (c) is a process flow chart for the sample of the lower plate of the first metal input electrode 3 and the lower plate of the second metal input electrode 4 after the growth, step A3, preparing the lower plate of the first metal input electrode 3 and the lower plate of the second metal input electrode 4 on the surface of the Al2O3 insulating dielectric layer 2 by inductively coupled plasma etching (ICP etching) and thermal evaporation.

[0153] The specific steps of step A3 are as follows:

[0154] Step A31. Click Stop under the Pump icon on the ICP device interface, switch to Vent, and turn on Loadlock after 120 seconds.

[0155] Step A32: Apply an even layer of vacuum grease on the tray according to the size of the slices.

[0156] Step A33, gently clamp the sample with tweezers, stick one side of the sample on the grease, and slowly put down the other side. Press one end of the sample with tweezers, and move the sample slightly on the grease to drive away the bubbles between the sample and the grease, so that the sample and the grease are tightly attached.

[0157] Step A34, turn on the small mechanical pump and pre-pump the Loadlock until the vacuum degree reaches -2 before etching operation can be performed.

[0158] Step A35, select the required heating mode, select the required heating mode according to the sample, set the heating or cooling temperature, and enter the Chamber interface when the temperature and vacuum degree meet the requirements.

[0159] Step A36, set the program according to the requirements, determine the process parameters (gas flow, ICP power, RF power, pressure, temperature, time, etc.) and perform the etching, and appropriately correct the matching power.

[0160] Step A37. After etching is completed, click Stop, switch to Vent, open Loadlock and take out the sample.

[0161] Step A38, immerse the sample in a developer for 2 minutes to complete development, and then immerse the sample in isopropyl alcohol for 1 minute to complete fixing. After fixing, the PMMA on the upper plate of the metal input electrode 2 and the upper plate of the metal input electrode 3 is removed.

[0162] Step A39: Place the fixed sample in a vacuum thermal evaporation furnace for electrode evaporation. First, chromium metal is evaporated at a rate of The process stops when the thickness of the chromium metal reaches 10 nm.

[0163] Step A40, immerse the sample after gold vapor deposition in an acetone solution and heat it to 70°C. After 4 hours, the PMMA in the sample is melted by the acetone solution, so that the gold on the PMMA is stripped off, and the gold on the lower plate of the first metal input electrode 3 and the lower plate of the second metal input electrode 4 are retained as electrodes to obtain a sample on which the lower plate of the first metal input electrode 3 and the lower plate of the second metal input electrode 4 are grown.

[0164] Figure 3 The process flow chart of growing the first two-dimensional material tunneling layer 10 is schematically shown, see Figure 3 As shown, Figure 3 (d) is a process flow chart of a sample after growing an Al2O3 first two-dimensional material insulating dielectric layer 5, step A4, growing an Al2O3 first two-dimensional material insulating dielectric layer 5 with a thickness of 20 nm on the surface of the cleaned insulating dielectric layer 2 by an ALD method.

[0165] The specific steps of step A4 are as follows:

[0166] Step A41, select ozone as the oxygen source, and select trimethylaluminum (TMA) as the aluminum source.

[0167] Step A42, setting the reaction chamber temperature of the ALD equipment to 300° C. and the aluminum source to 90° C., and after the temperatures of the reaction chamber and the aluminum source rise to the set values, evacuating the reaction chamber.

[0168] Step A43, evacuate the reaction chamber, and then fill it with nitrogen at an atmospheric pressure, and repeat this process 3 to 5 times to flush the reaction chamber.

[0169] Step A44, place the cleaned silicon substrate into the reaction chamber, close the chamber and evacuate the reaction chamber, open the gas valves of the oxygen source and the aluminum source, flush the aluminum precursor into the reaction chamber, the pulse time is 1 second, the carrier gas flow rate is 50sccm, after the reaction, fill the reaction chamber with nitrogen with a flow rate of 50sccm to flush the reaction chamber, and the flushing time is 10 seconds.

[0170] Step A45, flush the ozone precursor into the reaction chamber, the pulse time is 1 second, the carrier gas flow rate is 50 sccm, and after the reaction, the reaction chamber is flushed with nitrogen gas with a flow rate of 50 sccm, and the flushing time is 10 seconds.

[0171] The Al2O3 medium grown in step A46, step A44 and step A45 is a single layer, and step A44 and step A45 are repeated multiple times until the thickness of Al2O3 is 20nm.

[0172] Step A47: After the thickness of the Al2O3 medium reaches a preset value through cyclic growth, nitrogen is filled into the reaction chamber. When the pressure of the reaction chamber rises to atmospheric pressure, the sample is taken out.

[0173] Step A48, naturally cool the sample on which the Al2O3 dielectric is grown in a nitrogen atmosphere to obtain a sample on which the Al2O3 first two-dimensional material insulating dielectric layer 5 is grown.

[0174] Figure 3 The process flow chart of growing the first two-dimensional material tunneling layer 10 is schematically shown, see Figure 3 As shown, Figure 3 (e) is a process flow chart for growing a first two-dimensional graphene material floating gate layer 6, a second two-dimensional graphene material floating gate layer 7, a third two-dimensional graphene material floating gate layer 8 and a fourth two-dimensional graphene material floating gate layer 9. Step A5: On the surface of the first two-dimensional graphene material insulating dielectric layer 5, grow a first two-dimensional graphene material floating gate layer 6, a second two-dimensional graphene material floating gate layer 7, a third two-dimensional graphene material floating gate layer 8 and a fourth two-dimensional graphene material floating gate layer 9 with a thickness of 10 nm by ICP etching and chemical vapor deposition (CVD).

[0175] The specific steps of step A5 are as follows:

[0176] Step A51. Click Stop under the Pump icon on the ICP device interface, switch to Vent, and turn on Loadlock after 120 seconds.

[0177] Step A52: Apply an even layer of vacuum grease on the tray according to the size of the wafer.

[0178] Step A53, gently clamp the sample with tweezers, stick one side of the sample on the grease, and slowly put down the other side. Press one end of the sample with tweezers, and move the sample slightly on the grease to drive away the bubbles between the sample and the grease, so that the sample and the grease are tightly attached.

[0179] Step A54, turn on the small mechanical pump and pre-pump the loadlock until the vacuum degree reaches -2 before etching operation can be performed.

[0180] Step A55, select the required heating mode, select the required heating mode according to the sample, set the heating or cooling temperature, and enter the Chamber interface when the temperature and vacuum degree meet the requirements.

[0181] Step A56, set the program according to the requirements, determine the process parameters (gas flow, ICP power, RF power, pressure, temperature, time, etc.) and perform the etching, and appropriately correct the matching power.

[0182] Step A57. After etching is completed, click Stop, switch to Vent, open Loadlock and take out the sample.

[0183] Step A58, immerse the sample in a developer for 2 minutes to complete development, and then immerse the sample in isopropyl alcohol for 1 minute to complete fixing. After fixing, the PMMA at the first two-dimensional material floating gate layer 6, the second two-dimensional material floating gate layer 7, the third two-dimensional material floating gate layer 8 and the fourth two-dimensional material floating gate layer 9 is removed.

[0184] Step A59: using CVD technology, grow a first two-dimensional graphene material floating gate layer 6, a second two-dimensional graphene material floating gate layer 7, a third two-dimensional graphene material floating gate layer 8 and a fourth two-dimensional graphene material floating gate layer 9 until the thickness reaches 10 nm.

[0185] Figure 3 The process flow chart of growing the first two-dimensional material tunneling layer 10 is schematically shown, see Figure 3 As shown, Figure 3 (f) is a process flow chart for growing an h-BN first two-dimensional material tunneling layer 10, step A6, growing an h-BN first two-dimensional material tunneling layer 10 with a thickness of 20 nm on the surface of the Al2O3 first two-dimensional material insulating dielectric layer 5 by CVD technology.

[0186] Figure 4 The process flow chart of growing the second two-dimensional conductive dielectric layer 21 is schematically shown, see Figure 4 As shown, Figure 4 (a) is a process flow chart for growing a WSe2 first two-dimensional material channel layer 11 and a second two-dimensional material channel layer 12, step A7, on the surface of the h-BN first two-dimensional material tunneling layer 10, grow a WSe2 first two-dimensional material channel layer 11 and a second two-dimensional material channel layer 12 with a thickness of 10 nm by ICP etching and CVD technology.

[0187] Figure 4 The process flow chart of growing the second two-dimensional conductive dielectric layer 21 is schematically shown, see Figure 4 As shown, Figure 4 (b) is a process flow chart for growing a graphene first two-dimensional material conductive dielectric layer 13, step A8, growing a graphene first two-dimensional material conductive dielectric layer 13 with a thickness of 10 nm on the surface of the h-BN first two-dimensional material tunneling layer 10 by ICP etching and CVD technology.

[0188] Figure 4 The process flow chart of growing the second two-dimensional conductive dielectric layer 21 is schematically shown, see Figure 4 As shown, Figure 4 (c) is a process flow chart for growing a first gold metal output electrode, a second metal output electrode 15, a third metal output electrode 16 and a fourth metal output electrode 17, step A9, on the surface of the h-BN first two-dimensional material tunneling layer 10, grow a first gold metal output electrode, a second metal output electrode 15, a third metal output electrode 16 and a fourth metal output electrode 17 with a thickness of 10 nm by ICP etching and thermal evaporation.

[0189] Figure 4 The process flow chart of growing the second two-dimensional conductive dielectric layer 21 is schematically shown, see Figure 4 As shown, Figure 4 (d) is a process flow chart for growing an h-BN second two-dimensional material tunneling layer 18, step A10, growing an h-BN second two-dimensional material tunneling layer 18 with a thickness of 10 nm on the surface of the h-BN first two-dimensional material tunneling layer 10 by CVD technology.

[0190] Figure 4 The process flow chart of growing the second two-dimensional conductive dielectric layer 21 is schematically shown, see Figure 4 As shown, Figure 4(e) is a process flow chart for growing a WSe2 third two-dimensional material channel layer 19 and a fourth two-dimensional material channel layer 20, step A11, on the surface of the h-BN second two-dimensional material tunneling layer 18, grow a WSe2 third two-dimensional material channel layer 19 and a fourth two-dimensional material channel layer 20 with a thickness of 10 nm by ICP etching and CVD technology.

[0191] Figure 4 The process flow chart of growing the second two-dimensional conductive dielectric layer 21 is schematically shown, see Figure 4 As shown, Figure 4 (f) is a process flow chart for growing a graphene second two-dimensional material conductive dielectric layer 21, step A12, growing a graphene second two-dimensional material conductive dielectric layer 21 with a thickness of 10 nm on the surface of the h-BN second two-dimensional material tunneling layer 18 by ICP etching and CVD technology.

[0192] Figure 5 A schematic diagram of a process flow chart for connecting an upper plate of a plurality of metal input electrodes to a lower plate of a plurality of metal input electrodes is shown, see Figure 5 As shown, Figure 5 (a) is a process flow chart for growing a fifth gold metal output electrode, a sixth metal output electrode 23, a seventh metal output electrode 24 and an eighth metal output electrode, step A13, on the surface of the h-BN two-dimensional material tunneling layer, grow a fifth gold metal output electrode, a sixth metal output electrode 23, a seventh metal output electrode 24 and an eighth metal output electrode with a thickness of 10 nm by ICP etching and thermal evaporation.

[0193] Figure 5 A schematic diagram of a process flow chart for connecting an upper plate of a plurality of metal input electrodes to a lower plate of a plurality of metal input electrodes is shown, see Figure 5 As shown, Figure 5 (b) is a process flow chart for growing a third two-dimensional material tunneling layer 26, step A14, growing a third two-dimensional material tunneling layer 26 with a thickness of 20 nm on the surface of the h-BN second two-dimensional material tunneling layer 18 by CVD technology.

[0194] Figure 5 A schematic diagram of a process flow chart for connecting an upper plate of a plurality of metal input electrodes to a lower plate of a plurality of metal input electrodes is shown, see Figure 5 As shown, Figure 5(c) is a process flow chart for growing a fifth two-dimensional graphene material floating gate layer 27, a sixth two-dimensional graphene material floating gate layer 28, a seventh two-dimensional graphene material floating gate layer 29 and an eighth two-dimensional graphene material floating gate layer 30, step A15, on the surface of the h-BN third two-dimensional material tunneling layer 26, grow a fifth two-dimensional graphene material floating gate layer 27, a sixth two-dimensional graphene material floating gate layer 28, a seventh two-dimensional graphene material floating gate layer 29 and an eighth two-dimensional graphene material floating gate layer 30 with a thickness of 10 nm by ICP etching and CVD technology.

[0195] Figure 5 A schematic diagram of a process flow chart for connecting an upper plate of a plurality of metal input electrodes to a lower plate of a plurality of metal input electrodes is shown, see Figure 5 As shown, Figure 5 (d) is a process flow chart for growing an h-BN second two-dimensional material insulating dielectric layer 31, step A16, growing an h-BN second two-dimensional material insulating dielectric layer 31 with a thickness of 20 nm on the surface of the h-BN third two-dimensional material tunneling layer 26 by CVD technology.

[0196] Figure 5 A schematic diagram of a process flow chart for connecting an upper plate of a plurality of metal input electrodes to a lower plate of a plurality of metal input electrodes is shown, see Figure 5 As shown, Figure 5 (e) is a process flow chart for preparing the lower plate of the first metal input electrode 3 and the lower plate of the second metal input electrode 4, step A17, on the surface of the h-BN second two-dimensional material insulating dielectric layer 31, prepare the lower plate of the first metal input electrode 3 and the lower plate of the second metal input electrode 4 with a thickness of 10 nm by ICP etching and thermal evaporation.

[0197] Figure 5 A schematic diagram of a process flow chart for connecting an upper plate of a plurality of metal input electrodes to a lower plate of a plurality of metal input electrodes is shown, see Figure 5 As shown, Figure 5 (f) is a process flow chart for connecting the first metal input electrode 3 and the second metal input electrode 4, step A18, using flying wires to connect the upper plate of the first metal input electrode 3 and the lower plate of the first metal input electrode 3, the upper plate of the second metal input electrode 4 and the lower plate of the second metal input electrode 4.

[0198] Figure 6 The flowchart of the electrical control method of the two-dimensional heterojunction floating gate device with reconfigurable function is schematically shown, see Figure 6 As shown, the electrical control method of the two-dimensional heterojunction floating gate device with reconfigurable function is implemented based on the two-dimensional heterojunction floating gate device with reconfigurable function, and may include:

[0199] S601 . Among a plurality of preset metal output electrodes and a plurality of target metal output electrodes, select any one or two metal output electrodes as source electrodes, and select any one or two metal output electrodes other than the source electrodes as drain electrodes.

[0200] The plurality of preset metal output electrodes include a first metal output electrode 14 , a second metal output electrode 15 , a third metal output electrode 16 and a fourth metal output electrode 17 , and the plurality of target metal output electrodes include a fifth metal output electrode 22 , a sixth metal output electrode 23 , a seventh metal output electrode 24 and an eighth metal output electrode 25 .

[0201] Specifically, among the first metal output electrode 14, the second metal output electrode 15, the third metal output electrode 16, the fourth metal output electrode 17, the fifth metal output electrode 22, the sixth metal output electrode 23, the seventh metal output electrode 24 and the eighth metal output electrode 25, a group is selected as a corresponding source electrode and a drain electrode to be selected in the target.

[0202] S602 , using the source electrode and the drain electrode as target metal output electrodes.

[0203] S603 , input a positive voltage as an input level value 1 to the first metal input electrode 3 and the second metal input electrode 4 among the plurality of metal input electrodes, or input a negative voltage as an input level value 0 to the first metal input electrode 3 and the second metal input electrode 4 .

[0204] S604, grounding the source electrode in the target metal output electrode, connecting the drain electrode to a positive voltage, and measuring the current between the source electrode and the drain electrode to obtain two current values.

[0205] After measuring the current between the source electrode and the drain electrode, two current values ​​are obtained as output.

[0206] S605 , determining a minimum current value and a maximum current value of the two current values, and using the minimum current value as an output level value of 0 and the maximum current value as an output level value of 1, so as to achieve electrical control of the target logic function.

[0207] The electrical control method of the two-dimensional heterojunction floating gate device with reconfigurable function, and the specific operation of realizing the electrical control of the target logic function are:

[0208] The first metal input electrode 3 and the second metal input electrode 4 are selected as logic input electrodes.

[0209] Figure 7 The first conductive layer polarity top view is schematically shown, see Figure 7As shown, a negative voltage is input to the first metal input electrode 3 , and a negative voltage is input to the second metal input electrode 4 .

[0210] Figure 8 The second conductive layer polarity top view is schematically shown, see Figure 8 As shown, a negative voltage is input to the first metal input electrode 3 , and a positive voltage is input to the second metal input electrode 4 .

[0211] Fig. 9 The third conductive layer polarity top view is schematically shown, see Fig. 9 As shown, a positive voltage is input to the first metal input electrode 3 , and a negative voltage is input to the second metal input electrode 4 .

[0212] Fig.10 The fourth conductive layer polarity top view is schematically shown, see Fig.10 As shown, a positive voltage is input to the first metal input electrode 3 , and a positive voltage is input to the second metal input electrode 4 .

[0213] The logic and functions are realized by electric control, specifically:

[0214] Select the first metal input electrode 3 and the second metal input electrode 4 as the input electrodes of the logic AND. Input an appropriate positive voltage to the first metal input electrode 3 and the second metal input electrode 4 as the input "1", and input an appropriate negative voltage to the first metal input electrode 3 and the second metal input electrode 4 as the input "0";

[0215] The current between the second metal output electrode 15 and the seventh metal output electrode 24 is selected as the output of the logic AND. The second metal output electrode 15 is used as the drain electrode, the seventh metal output electrode 24 is used as the source electrode, an appropriate positive voltage is input to the second metal output electrode 15, the seventh metal output electrode 24 is grounded, and the current between the drain electrode and the source electrode is measured as the output. The small current between the drain electrode and the source electrode is used as the output "0", and the large current is used as the output "1".

[0216] When a negative voltage is input to the first metal input electrode 3 and a negative voltage is input to the second metal input electrode 4, a small current will be output between the drain electrode and the source electrode, indicating the situation: input 00, output 0.

[0217] When a negative voltage is input to the first metal input electrode 3 and a positive voltage is input to the second metal input electrode 4, a small current will be output between the drain electrode and the source electrode, indicating the situation: input 01, output 0.

[0218] When a positive voltage is input to the first metal input electrode 3 and a negative voltage is input to the second metal input electrode 4, a small current will be output between the drain electrode and the source electrode, indicating the situation: input 10, output 0.

[0219] When a positive voltage is input to the first metal input electrode 3 and a positive voltage is input to the second metal input electrode 4, a large current will be output between the drain electrode and the source electrode, indicating the situation: input 11, output 1.

[0220] The logic or function is realized by electric control, specifically:

[0221] Select the first metal input electrode 3 and the second metal input electrode 4 as the input electrodes of the logic OR. Input an appropriate positive voltage to the first metal input electrode 3 and the second metal input electrode 4 as the input "1", and input an appropriate negative voltage to the first metal input electrode 3 and the second metal input electrode 4 as the input "0";

[0222] The second metal output electrode 15 and the sixth metal output electrode 23 are connected as the drain electrode; the third metal output electrode 16 and the seventh metal output electrode 24 are connected as the source electrode. The current between the drain electrode and the source electrode is selected as the output of the logic OR. An appropriate positive voltage is input to the drain electrode, the source electrode is grounded, and the current between the drain electrode and the source electrode is measured as the output. A small current is used as the output "0", and a large current is used as the output "1".

[0223] When a negative voltage is input to the first metal input electrode 3 and a negative voltage is input to the second metal input electrode 4, a small current will be output between the drain electrode and the source electrode, indicating the situation: input 00, output 0.

[0224] When a negative voltage is input to the first metal input electrode 3 and a positive voltage is input to the second metal input electrode 4, a large current will be output between the drain electrode and the source electrode, indicating the situation: input 01, output 1.

[0225] When a positive voltage is input to the first metal input electrode 3 and a negative voltage is input to the second metal input electrode 4, a large current will be output between the drain electrode and the source electrode, indicating the situation: input 10, output 1.

[0226] When a positive voltage is input to the first metal input electrode 3 and a positive voltage is input to the second metal input electrode 4, a large current will be output between the drain electrode and the source electrode, indicating the situation: input 11, output 1.

[0227] The electrical control is used to realize the logic and non-function, specifically:

[0228] Select the first metal input electrode 3 and the second metal input electrode 4 as the input electrodes of the logic NAND. Input an appropriate positive voltage to the first metal input electrode 3 and the second metal input electrode 4 as the input "1", and input an appropriate negative voltage to the first metal input electrode 3 and the second metal input electrode 4 as the input "0";

[0229] Connect the first metal output electrode 14 and the fifth metal output electrode 22 as the drain electrode; connect the fourth metal output electrode 17 and the eighth metal output electrode 25 as the source electrode. Select the current between the drain electrode and the source electrode as the output of the logic NAND. Input an appropriate positive voltage to the drain electrode, ground the source electrode, measure the current between the drain electrode and the source electrode as the output, and a small current is used as the output "0", and a large current is used as the output "1".

[0230] When a negative voltage is input to the first metal input electrode 3 and a negative voltage is input to the second metal input electrode 4, a large current will be output between the drain electrode and the source electrode, indicating the situation: input 00, output 1.

[0231] When a negative voltage is input to the first metal input electrode 3 and a positive voltage is input to the second metal input electrode 4, a large current will be output between the drain electrode and the source electrode, indicating the situation: input 01, output 1.

[0232] When a positive voltage is input to the first metal input electrode 3 and a negative voltage is input to the second metal input electrode 4, a large current will be output between the drain electrode and the source electrode, indicating the situation: input 10, output 1.

[0233] When a positive voltage is input to the first metal input electrode 3 and a positive voltage is input to the second metal input electrode 4, a small current will be output between the drain electrode and the source electrode, indicating the situation: input 11, output 0.

[0234] The logic or non-function is realized by electric control, specifically:

[0235] Select the first metal input electrode 3 and the second metal input electrode 4 as the input electrodes of the logic OR. Input an appropriate positive voltage to the first metal input electrode 3 and the second metal input electrode 4 as the input "1", and input an appropriate negative voltage to the first metal input electrode 3 and the second metal input electrode 4 as the input "0";

[0236] Select the current between the first metal output electrode 14 and the eighth metal output electrode 25 as the output of the logic NOR. Use the first metal output electrode 14 as the drain electrode and the eighth metal output electrode 25 as the source electrode. Input an appropriate positive voltage to the first metal output electrode 14, ground the eighth metal output electrode 25, measure the current between the drain electrode and the source electrode as the output, and the small current between the drain electrode and the source electrode is used as the output "0", and the large current is used as the output "1". Input a negative voltage to the first metal input electrode 3, and input a negative voltage to the second metal input electrode 4, and a large current will be output between the drain electrode and the source electrode, indicating the situation: input 00, output 1.

[0237] When a negative voltage is input to the first metal input electrode 3 and a positive voltage is input to the second metal input electrode 4, a small current will be output between the drain electrode and the source electrode, indicating the situation: input 01, output 0.

[0238] When a positive voltage is input to the first metal input electrode 3 and a negative voltage is input to the second metal input electrode 4, a small current will be output between the drain electrode and the source electrode, indicating the situation: input 10, output 0.

[0239] When a positive voltage is input to the first metal input electrode 3 and a positive voltage is input to the second metal input electrode 4, a small current will be output between the drain electrode and the source electrode, indicating the situation: input 11, output 0.

[0240] The electric control is used to realize the logical XOR function, specifically:

[0241] Select the first metal input electrode 3 and the second metal input electrode 4 as input electrodes of the logical XOR. Input an appropriate positive voltage to the first metal input electrode 3 and the second metal input electrode 4 as input "1", and input an appropriate negative voltage to the first metal input electrode 3 and the second metal input electrode 4 as input "0";

[0242] Connect the first metal output electrode 14 and the second metal output electrode 15 as the drain electrode; connect the seventh metal output electrode 24 and the eighth metal output electrode 25 as the source electrode. Select the current between the drain electrode and the source electrode as the output of the logical XOR. Input an appropriate positive voltage to the drain electrode, ground the source electrode, measure the current between the drain electrode and the source electrode as the output, and a small current is used as the output "0", and a large current is used as the output "1".

[0243] When a negative voltage is input to the first metal input electrode 3 and a negative voltage is input to the second metal input electrode 4, a large current will be output between the drain electrode and the source electrode, indicating the situation: input 00, output 1.

[0244] When a negative voltage is input to the first metal input electrode 3 and a positive voltage is input to the second metal input electrode 4, a small current will be output between the drain electrode and the source electrode, indicating the situation: input 01, output 0.

[0245] When a positive voltage is input to the first metal input electrode 3 and a negative voltage is input to the second metal input electrode 4, a small current will be output between the drain electrode and the source electrode, indicating the situation: input 10, output 0.

[0246] When a positive voltage is input to the first metal input electrode 3 and a positive voltage is input to the second metal input electrode 4, a large current will be output between the drain electrode and the source electrode, indicating the situation: input 11, output 1.

[0247] Using electrical control to realize logical XOR function:

[0248] Select the first metal input electrode 3 and the second metal input electrode 4 as input electrodes of logical exclusive OR. Input an appropriate positive voltage to the first metal input electrode 3 and the second metal input electrode 4 as input "1", and input an appropriate negative voltage to the first metal input electrode 3 and the second metal input electrode 4 as input "0";

[0249] The current between the first metal output electrode 14 and the third metal output electrode 16 is selected as the output of the logical XOR. The first metal output electrode 14 is used as the drain electrode, and the third metal output electrode 16 is used as the source electrode. An appropriate positive voltage is input to the drain electrode, the source electrode is grounded, and the current between the drain electrode and the source electrode is measured as the output. A small current is used as the output "0", and a large current is used as the output "1".

[0250] When a negative voltage is input to the first metal input electrode 3 and a negative voltage is input to the second metal input electrode 4, a small current will be output between the drain electrode and the source electrode, indicating the situation: input 00, output 0.

[0251] When a negative voltage is input to the first metal input electrode 3 and a positive voltage is input to the second metal input electrode 4, a large current will be output between the drain electrode and the source electrode, indicating the situation: input 01, output 1.

[0252] When a positive voltage is input to the first metal input electrode 3 and a negative voltage is input to the second metal input electrode 4, a large current will be output between the drain electrode and the source electrode, indicating the situation: input 10, output 1.

[0253] When a positive voltage is input to the first metal input electrode 3 and a positive voltage is input to the second metal input electrode 4, a small current will be output between the drain electrode and the source electrode, indicating the situation: input 11, output 0.

[0254] The present invention prepares a two-dimensional floating gate device with a new structure based on a two-dimensional material heterojunction. By selecting different signal input terminals and output terminals, a single device can realize six logic functions, namely, logical AND, logical OR, logical ANDN, logical ORN, logical XOR, logical XOR, and logical XOR, on the basis of realizing non-volatile storage characteristics. The present invention combines the logic operation function with the storage function, and expands the application of two-dimensional material floating gate memory in storage and computing integrated chips.

[0255] It should be pointed out here that: the description of the above embodiment of the method for preparing a two-dimensional heterojunction floating gate device with a reconfigurable function is similar to the description of the above embodiment of the two-dimensional heterojunction floating gate device with a reconfigurable function, and has similar beneficial effects as the embodiment of the two-dimensional heterojunction floating gate device with a reconfigurable function. For technical details not disclosed in the embodiment of the method for preparing a two-dimensional heterojunction floating gate device with a reconfigurable function of the embodiment of the present invention, please refer to the description of the embodiment of the two-dimensional heterojunction floating gate device with a reconfigurable function of the present invention for understanding.

[0256] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A two-dimensional heterojunction floating gate device with reconfigurable function, characterized in that: The invention comprises a semiconductor substrate, an insulating dielectric layer, a first two-dimensional material insulating dielectric layer, a first two-dimensional material tunneling layer, a second two-dimensional material tunneling layer, a third two-dimensional material tunneling layer and a second two-dimensional material insulating dielectric layer, which are arranged in sequence from bottom to top; A plurality of lower plates of metal input electrodes are arranged in the top region of the insulating dielectric layer, and a plurality of floating gate layers of preset two-dimensional materials are arranged in the top region of the first two-dimensional insulating dielectric layer; A top region of the first two-dimensional material tunneling layer is provided with a plurality of preset two-dimensional material channel layers, a first two-dimensional material conductive medium layer and a plurality of preset metal output electrodes, and the plurality of preset two-dimensional material channel layers and the first two-dimensional material conductive medium layer are in contact; A top region of the second two-dimensional material tunneling layer is provided with a plurality of target two-dimensional material channel layers, a second two-dimensional material conductive medium layer and a plurality of target metal output electrodes, and the plurality of target two-dimensional material channel layers and the second two-dimensional material conductive medium layer are in contact; A plurality of target two-dimensional material floating gate layers are arranged in the top region of the third two-dimensional material tunneling layer; An upper plate of multiple metal input electrodes is disposed in the top region of the second two-dimensional material insulating dielectric layer; the upper plate of the multiple metal input electrodes is connected to the lower plate of the multiple metal input electrodes by flying wires.

2. The two-dimensional heterojunction floating gate device with reconfigurable function according to claim 1, characterized in that: The plurality of preset two-dimensional material floating gate layers are located directly above the lower plate of the plurality of metal input electrodes; The plurality of preset two-dimensional material channel layers are directly above the plurality of preset two-dimensional material floating gate layers; The plurality of target two-dimensional material channel layers are directly above the plurality of preset metal output electrodes; The plurality of target two-dimensional material floating gate layers are directly above the plurality of target two-dimensional material channel layers; The upper plates of the plurality of metal input electrodes are directly above the plurality of preset two-dimensional material floating gate layers and the plurality of target two-dimensional material floating gate layers.

3. The two-dimensional heterojunction floating gate device with reconfigurable function according to claim 1, characterized in that: The lower plates of the plurality of metal input electrodes include a lower plate of a first metal input electrode and a lower plate of a second metal input electrode arranged at intervals; The multiple preset two-dimensional material floating gate layers include a first two-dimensional material floating gate layer, a second two-dimensional material floating gate layer, a third two-dimensional material floating gate layer and a fourth two-dimensional material floating gate layer arranged at intervals, the second two-dimensional material floating gate layer is directly above the lower plate of the second metal input electrode, and the third two-dimensional material floating gate layer is directly above the lower plate of the first metal input electrode.

4. The two-dimensional heterojunction floating gate device with reconfigurable function according to claim 3, characterized in that: The multiple preset two-dimensional material channel layers include a first two-dimensional material channel layer and a second two-dimensional material channel layer arranged at intervals, and the first two-dimensional material channel layer and the second two-dimensional material channel layer are both in contact with the first two-dimensional material conductive medium layer; the multiple preset metal output electrodes include a first metal output electrode, a second metal output electrode, a third metal output electrode and a fourth metal output electrode arranged at intervals, and the first metal output electrode and the third metal output electrode are symmetrically arranged, and the second metal output electrode and the fourth metal output electrode are symmetrically arranged; The first two-dimensional material channel layer is directly above the first two-dimensional material floating gate layer and the second two-dimensional material floating gate layer, and the second two-dimensional material channel layer is directly above the third two-dimensional material floating gate layer and the fourth two-dimensional material floating gate layer.

5. The two-dimensional heterojunction floating gate device with reconfigurable function according to claim 4, characterized in that: The multiple target two-dimensional material channel layers include a third two-dimensional material channel layer and a fourth two-dimensional material channel layer arranged at intervals, and the third two-dimensional material channel layer and the fourth two-dimensional material channel layer are both in contact with the second two-dimensional material conductive medium layer; the multiple target metal output electrodes include a fifth metal output electrode, a sixth metal output electrode, a seventh metal output electrode and an eighth metal output electrode arranged at intervals, and the fifth metal output electrode is symmetrically arranged with the seventh metal output electrode, and the sixth metal output electrode is symmetrically arranged with the eighth metal output electrode; The third two-dimensional material channel layer is directly above the first metal output electrode and the second metal output electrode, and the fourth two-dimensional material channel layer is directly above the third metal output electrode and the fourth metal output electrode.

6. The two-dimensional heterojunction floating gate device with reconfigurable function according to claim 5, characterized in that: The multiple target two-dimensional material floating gate layers include a fifth two-dimensional material floating gate layer, a sixth two-dimensional material floating gate layer, a seventh two-dimensional material floating gate layer and an eighth two-dimensional material floating gate layer which are arranged at intervals, the fifth two-dimensional material floating gate layer and the sixth two-dimensional material floating gate layer are directly above the third two-dimensional material channel layer, the seventh two-dimensional material floating gate layer and the eighth two-dimensional material floating gate layer are directly above the fourth two-dimensional material channel layer, the fifth two-dimensional material floating gate layer is directly above the second two-dimensional material floating gate layer, and the eighth two-dimensional material floating gate layer is directly above the third two-dimensional material floating gate layer; The upper plates of the plurality of metal input electrodes include an upper plate of a first metal input electrode and an upper plate of a second metal input electrode arranged at intervals, the upper plate of the first metal input electrode is directly above the first two-dimensional material floating gate layer and the sixth two-dimensional material floating gate layer, and the upper plate of the second metal input electrode is directly above the fourth two-dimensional material floating gate layer and the seventh two-dimensional material floating gate layer; The upper plate of the first metal input electrode is connected to the lower plate of the first metal input electrode by a flying wire, and the upper plate of the second metal input electrode is connected to the lower plate of the second metal input electrode by a flying wire.

7. The two-dimensional heterojunction floating gate device with reconfigurable function according to claim 6, characterized in that: The materials of the first two-dimensional material channel layer, the second two-dimensional material channel layer, the third two-dimensional material channel layer and the fourth two-dimensional material channel layer are all selected from materials with less than 15 layers; The materials of the first two-dimensional material floating gate layer, the second two-dimensional material floating gate layer, the third two-dimensional material floating gate layer, the fourth two-dimensional material floating gate layer, the fifth two-dimensional material floating gate layer, the sixth two-dimensional material floating gate layer, the seventh two-dimensional material floating gate layer and the eighth two-dimensional material floating gate layer are all multilayer materials with 10 to 30 layers.

8. The two-dimensional heterojunction floating gate device with reconfigurable function according to claim 1, characterized in that: The thickness of the insulating dielectric layer, the first two-dimensional material insulating dielectric layer, and the second two-dimensional material insulating dielectric layer are all 10 to 20 nm.

9. A method for preparing a two-dimensional heterojunction floating gate device with reconfigurable function, characterized in that: The two-dimensional heterojunction floating gate device with reconfigurable function according to any one of claims 1 to 8 comprises: Selecting a semiconductor substrate and cleaning the semiconductor substrate by a wet chemical cleaning method, wherein the semiconductor substrate is a doped substrate; growing an insulating dielectric layer on the surface of the cleaned semiconductor substrate; Etching the surface of the insulating dielectric layer and preparing a lower plate of a plurality of metal input electrodes; Growing a first two-dimensional material insulating dielectric layer on the surface of the lower plate of the plurality of metal input electrodes; Etching a first preset area on the surface of the first two-dimensional insulating dielectric layer to obtain a first pattern, and growing a plurality of preset two-dimensional floating gate layers on the surface of the first two-dimensional insulating dielectric layer after etching; Growing a first two-dimensional material tunneling layer on the surface of the etched first two-dimensional material insulating dielectric layer; Etching a second preset area on the surface of the first two-dimensional material tunneling layer to obtain a second pattern, and growing a plurality of preset two-dimensional material channel layers on the surface of the etched first two-dimensional material tunneling layer; Etching a third preset area on the surface of the etched first two-dimensional material tunneling layer to obtain a third pattern, and growing a first two-dimensional material conductive dielectric layer on the surface of the newly etched first two-dimensional material tunneling layer; Etching a fourth preset area on the surface of the newly etched first two-dimensional material tunneling layer to obtain a fourth pattern, and preparing a plurality of preset metal output electrodes on the surface of the newly etched first two-dimensional material tunneling layer, wherein the second preset area, the third preset area and the fourth preset area are all different; Growing a second two-dimensional material tunneling layer on the surface of the first two-dimensional material tunneling layer after the latest etching; Etching a fifth preset area on the surface of the second two-dimensional material tunneling layer to obtain a fifth pattern, and growing a plurality of target two-dimensional material channel layers on the surface of the etched second two-dimensional material tunneling layer; Etching a sixth preset area on the surface of the etched second two-dimensional material tunneling layer to obtain a sixth pattern, and growing a second two-dimensional material conductive dielectric layer on the surface of the newly etched second two-dimensional material tunneling layer; Etching a seventh preset area on the surface of the newly etched second two-dimensional material tunneling layer to obtain a seventh pattern, and preparing a plurality of target metal output electrodes on the surface of the newly etched second two-dimensional material tunneling layer, wherein the fifth preset area, the sixth preset area and the seventh preset area are all different; Growing a third two-dimensional material tunneling layer on the surface of the second two-dimensional material tunneling layer after the latest etching; Etching an eighth preset area on the surface of the third two-dimensional material tunneling layer to obtain an eighth pattern, and growing a plurality of target two-dimensional material floating gate layers on the surface of the etched third two-dimensional material tunneling layer; Growing an insulating dielectric layer of a second two-dimensional material on the surface of the etched third two-dimensional material tunneling layer; The surface of the insulating dielectric layer of the second two-dimensional material is etched, and an upper plate of a plurality of metal input electrodes is prepared, and the upper plate of the plurality of metal input electrodes is connected to a lower plate of the plurality of metal input electrodes by using flying wires.

10. An electrical control method for a two-dimensional heterojunction floating gate device with reconfigurable function, characterized in that: The two-dimensional heterojunction floating gate device with reconfigurable function according to claim 1 is implemented, comprising: Among a plurality of preset metal output electrodes and the plurality of target metal output electrodes, select any one or two metal output electrodes as source electrodes, and select any one or two metal output electrodes other than the source electrodes as drain electrodes; Using the source electrode and the drain electrode as target metal output electrodes; Inputting a positive voltage as an input level value 1 to a first metal input electrode and a second metal input electrode among the plurality of metal input electrodes, or inputting a negative voltage as an input level value 0 to the first metal input electrode and the second metal input electrode; The source electrode in the target metal output electrode is grounded, and the drain electrode is connected to a positive voltage, and the current between the source electrode and the drain electrode is measured to obtain two current values; The minimum current value and the maximum current value of the two current values ​​are determined, and the minimum current value is used as the output level value 0, and the maximum current value is used as the output level value 1, so as to realize the electrical control of the target logic function.

Images