Magnetic tunnel junction switching for spin current with parallel spin momentum locking

Abstract

Methods and apparatus are provided for an MRAM device utilizing spin transfer torque. A device includes: a substrate; an MTJ formed over the substrate, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; and a PSM layer formed over the free layer of the MTJ. In some embodiments, a PSM layer (i.e., a chiral material layer) may be formed adjacent to a free layer of the MTJ (or adjacent to a TBL, the TBL being adjacent to the free layer), providing an additional source of spin transfer torque and providing MTJ devices that can operate with lower switching currents.

Description

Technical Field

[0001] The present disclosure relates generally to the field of magnetic random access memory (MRAM), and more particularly, to MRAM devices utilizing spin transfer torque. Background Art

[0002] Magnetic memories such as MRAM use magnetic materials as information storage media to store information. For example, a magnetic tunnel junction (MTJ) can be used in MRAM, such as spin transfer torque MRAM (STT-MRAM). MTJs typically include a reference layer, a free layer, and a tunnel barrier layer between the reference layer and the free layer. The reference layer and the free layer are magnetic. The magnetic moment of the reference layer is typically fixed or pinned in a specific direction. The free layer has a variable magnetic moment and is used to store information. The bottom contact under the MTJ and the top contact on the MTJ are used to drive current through the MTJ in the current perpendicular to the plane (CPP) direction in the STT-MRAM. In the case of an MTJ with positive tunnel magnetoresistance (TMR), when sufficient current is driven in a direction perpendicular to the plane (e.g., top to bottom), the free layer magnetic moment switches to be parallel to the magnetic moment of the reference layer. When sufficient current is driven in the opposite direction (e.g., bottom to top), the free layer magnetic moment switches to be antiparallel to the magnetic moment of the reference layer. Different magnetic configurations correspond to different magnetic resistances, and therefore different logical states (eg, logical "0" and logical "1") of the MTJ.

[0003] More specifically, STT-MRAM changes the magnetic direction of the free layer by passing a spin-polarized current directly through the MTJ. This gives STT-MRAM scalability, which means that the threshold current for performing state reversal will decrease as the size of the MTJ becomes smaller. This feature also provides STT-MRAM with greater resistance to stray magnetic fields compared to Toggle MRAM.

[0004] Because STT-MRAM has the advantages of lower power consumption and better scalability than conventional MRAM, it can replace low-density dynamic random access memory (DRAM) and static random access memory (SRAM) in mobile and storage devices, for example. Another advantage of MRAM over DRAM and SRAM is its non-volatile nature, that is, MRAM retains written data even in a power-off state.

[0005] However, in the STT-MRAM, compared with the in-plane magnetization MTJ, if the magnetic layer has magnetization perpendicular to the film surface, that is, has perpendicular magnetic anisotropy (PMA), a smaller switching current is required.

[0006] Additionally, for low-power STT-MRAM products that can operate in the nanosecond regime (eg, 2-50 ns), lower switching currents are required.

[0007] Dual MTJ structures have been proposed to provide an additional source of spin-transfer torque, but require thicker MTJ stacks, which are challenging to manufacture, and require significant improvements in the stability of the top reference layer.

[0008] In addition, spin-orbit coupling torque (SOT)-assisted STT-MRAM has been proposed, in which an additional source of spin torque is provided by a SOT material adjacent to the free layer of the MTJ. However, in these conventional technologies, the SOT is generated by an in-plane current flowing through the SOT line, which extends laterally and also presents additional challenges regarding manufacturing. Summary of the invention

[0009] Accordingly, an aspect of the present disclosure is to provide an apparatus and method for obtaining lower switching current in an MTJ device.

[0010] Another aspect of the present disclosure is to provide an additional source of spin transfer torque for MTJ devices without the manufacturing challenges.

[0011] According to one aspect of the present disclosure, a device is provided, comprising: a substrate; an MTJ formed on the substrate, the MTJ comprising a reference layer, a tunnel barrier layer and a free layer; and a parallel spin-momentum (PSM) layer formed above the free layer of the MTJ, the PSM layer comprising a chiral material.

[0012] According to another aspect of the present disclosure, a device is provided, comprising: a substrate; a PSM layer formed on the substrate, the PSM layer comprising a chiral material; and an MTJ formed on the PSM layer, the MTJ comprising a free layer, a tunnel barrier layer and a reference layer.

[0013] According to another aspect of the present disclosure, a method is provided, comprising providing a substrate; and forming an MTJ and a PSM layer on the substrate. The MTJ comprises a reference layer, a tunnel barrier layer and a free layer, and the PSM layer is formed adjacent to the free layer of the MTJ and comprises a chiral material.

[0014] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory device including an MTJ, the MTJ including a reference layer, a tunnel barrier layer and a free layer, and a PSM layer formed over the free layer of the MTJ, the PSM layer including a chiral material. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other aspects, features and advantages of the present disclosure will become more apparent through the following detailed description in conjunction with the accompanying drawings, in which:

[0016] Figure 1A shows a left-handed PSM layer on a free layer of an MTJ according to an embodiment;

[0017] Figure 1B shows a right-hand PSM layer on a free layer of an MTJ according to an embodiment;

[0018] Figure 2A is a cross-sectional side view of a top free layer MTJ stack including a PSM layer according to an embodiment;

[0019] Figure 2B is a cross-sectional side view of a top free layer MTJ stack including a PSM layer according to another embodiment;

[0020] Figure 3A is a cross-sectional side view of a bottom free layer MTJ stack including a PSM layer according to an embodiment;

[0021] Figure 3B is a cross-sectional side view of a bottom free layer MTJ stack including a PSM layer according to another embodiment;

[0022] Figure 4 An electronic device according to an embodiment is shown;

[0023] Figure 5 is a flow chart illustrating a method of forming a top free layer MTJ stack including a PSM layer according to an embodiment; and

[0024] Figure 6 is a flow chart illustrating a method of forming a bottom free layer MTJ stack including a PSM layer according to an embodiment. DETAILED DESCRIPTION

[0025] In the following detailed description, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, those skilled in the art will appreciate that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits are not described in detail to avoid obscuring the subject matter disclosed herein.

[0026] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment disclosed herein. Therefore, the phrases "in one embodiment" or "in an embodiment" or "according to an embodiment" (or other phrases with similar meanings) appearing throughout this specification may not necessarily all refer to the same embodiment. In addition, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not to be construed as necessarily preferred or advantageous over other embodiments.

[0027] In addition, specific features, structures or characteristics can be combined in any suitable manner in one or more embodiments. In addition, depending on the context discussed herein, singular terms can include corresponding plural forms, and plural terms can include corresponding singular forms. Similarly, hyphenated terms (e.g., "two-dimensional", "predetermined", "pixel-specific", etc.) can occasionally be used interchangeably with corresponding non-hyphenated versions (e.g., "two-dimensional", "predetermined", "pixel-specific", etc.), and capitalized entries (e.g., "Counter Clock", "Row Select", "PIXOUT", etc.) can be used interchangeably with corresponding non-capitalized versions (e.g., "Counter Clock", "Row Select", "PIXOUT", etc.). This occasional interchangeable use should not be considered inconsistent with each other.

[0028] In addition, depending on the context of the discussion herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. It is also noted that the various drawings (including component drawings) shown and discussed herein are for illustrative purposes only and are not drawn to scale. For clarity, the size of some elements may be exaggerated relative to other elements. For example, the size of layers and regions may be exaggerated for clarity.

[0029] In addition, if deemed appropriate, reference numerals may be repeated in the drawings to indicate corresponding and / or similar elements. That is, the same reference numeral may be used across two or more drawings to refer to parts, components, blocks, circuits, units, or modules having the same or similar functions. However, such use is only for simplicity of illustration and ease of discussion; it does not mean that the construction or architectural details of such components or units are the same in all embodiments, or that such commonly referenced parts / modules are the only way to implement some example embodiments disclosed herein.

[0030] The terminology used herein is for the purpose of describing some example embodiments only and is not intended to limit the claimed subject matter.As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0031] As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0032] When an element or layer is referred to as being on, "connected to," or "coupled to" another element or layer, it may be directly on, connected to, or coupled to another element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] As used herein, the terms "first," "second," and the like are used as labels for the nouns that follow them, and do not imply any type of ordering (eg, spatial, temporal, logical, etc.) unless explicitly defined as such.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or excessive formal sense unless explicitly so defined herein.

[0035] As used herein, the term "module" refers to any combination of software, firmware, and / or hardware configured to provide the functionality described herein in conjunction with the module. For example, software may be embodied as a software package, code, and / or instruction set or instructions, and the term "hardware" as used in any embodiment described herein may include, for example, components, hardwired circuits, programmable circuits, state machine circuits, and / or firmware storing instructions executed by programmable circuits, either alone or in any combination. Modules may be collectively or individually embodied as circuits that form part of a larger system (e.g., but not limited to, an IC, a system on a chip (SoC), a component, etc.).

[0036] Embodiments of the present disclosure relate to MTJ devices and methods of manufacturing MTJ devices.

[0037] Embodiments relate to magnetic junctions that can be used in magnetic devices, such as magnetic memories, and devices using such magnetic junctions. Magnetic memories may include STT-MRAM, SOT memories, and may be used in electronic devices that employ non-volatile memory. Other devices that include magnetic junctions, particularly STT or SOT programmable magnetic junctions, include, but are not limited to, logic, neuromorphic computing units, and other devices. Electronic devices include, but are not limited to, cellular phones, smart phones, tablets, laptops, and other portable and non-portable computing devices.

[0038] For the purposes of the description below, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives shall refer to the described structures and methods as oriented in the accompanying drawings. The terms "overlying", "on top of", "on top of", "positioned on", or "positioned on top of" mean that a first element (such as a first structure) is present on a second element (such as a second structure), wherein an intermediate element (such as an interface structure) may be present between the first element and the second element. The term "direct contact" refers to a first element (such as a first structure) and a second element (such as a second structure) being connected without any intermediate conductive, insulating, or semiconducting layer at the interface of the two elements. It should be noted that the term "selective to", for example, "a first element selective to a second element", means that the first element can be etched and the second element can be used as an etch stop.

[0039] For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. In addition, the various tasks and process steps described herein may be incorporated into a more comprehensive process or technique having additional steps or functions not described in detail herein. In particular, the various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps will only be briefly mentioned herein or will be omitted entirely without providing well-known process details.

[0040] Typically, the various processes for forming a microchip to be packaged into an IC fall into four general categories, i.e., film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process of growing, coating, or otherwise transferring a material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD), etc. Removal / etching is any process of removing material from a wafer. Examples include etching processes (wet or dry) and chemical mechanical planarization (CMP), etc. Semiconductor doping is to change electrical properties by doping, for example, transistor source and drain, usually via diffusion and / or by ion implantation. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing is used to activate the implanted dopant. Films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various areas of a semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the formation of a three-dimensional relief image or pattern on a semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the pattern is formed from a photosensitive polymer called a photoresist. The lithography and etching pattern transfer steps are repeated many times in order to build the structures that make up an IC device. Each pattern printed on the wafer is aligned with the previously formed pattern, and conductors, insulators, and selectively doped regions are slowly built up to form the final device.

[0041] As described above, one aspect of the present disclosure is to provide an apparatus and method for obtaining lower switching current in an MTJ device. More specifically, the present disclosure provides an additional source of spin transfer torque for an MTJ device, thereby allowing lower switching current.

[0042] According to an embodiment, a PSM layer (i.e., a chiral material layer) can be formed adjacent to a free layer of an MTJ device, thereby providing an additional source of spin transfer torque. By utilizing a chiral layer, the spin current induced by the chiral material is non-reciprocal, and the spin and momentum are parallel locked, making the chiral layer compatible with a magnetic structure having perpendicular magnetic anisotropy.

[0043] Furthermore, the PSM layer can be placed adjacent to a perpendicularly magnetized magnetic free layer, consistent with conventional two-terminal MTJ devices, thereby alleviating fabrication issues associated with previous sources of additional spin transfer torque for MTJ devices.

[0044] In addition, compared to conventional double tunnel junctions, the MTJ including the PSM layer according to the embodiments provides more margin and less concern about the interface. There are also more materials available for fabrication.

[0045] Figure 1A A left-handed PSM layer on the free layer of an MTJ according to an embodiment is shown.

[0046] Reference Figure 1A , a left-handed PSM layer 101 is formed (eg, grown) on a free layer of an MTJ, the MTJ including a free layer, a reference layer, and a tunnel barrier layer between the reference layer and the free layer.

[0047] The spin currents 102 and 103 generated from the PSM layer 101 are non-reciprocal. The resulting torque from the spin currents 102 and 103 helps switch the free layer for both directions by simply reversing the direction of current flow. That is, the spin currents 102 and 103 induced by the PSM layer 101 and their associated torques can be added to the STT current from the reference layer, thereby amplifying the total torque. In addition, due to the handedness of the PSM layer 101 (e.g., Figure 1A ) is strong and fixed, so the spin currents 102 and 103 and the spin polarization are determined only by the current direction.

[0048] Figure 1B A right-hand PSM layer on the free layer of an MTJ according to an embodiment is shown.

[0049] refer to Figure 1B A right-hand PSM layer 104 is formed (eg, grown) on a free layer of an MTJ including a free layer, a reference layer, and a tunnel barrier layer between the reference layer and the free layer.

[0050] The spin currents 105 and 106 generated from the PSM layer 104 are non-reciprocal. Figure 1A, the resulting torque from the spin currents 105 and 106 helps switch the free layer for both directions by simply reversing the direction of current flow. That is, the spin currents 105 and 106 induced by the PSM layer 101 and their associated torques can be added to the STT current from the reference layer, thereby amplifying the total torque.

[0051] like Figure 1A and Figure 1B As shown, the spin transfer torques from the PSM layer and the reference layer add to each other, depending on the reference layer magnetization and the chirality of the PSM layer material. That is, by changing the direction of the current, the spin transfer torque from the PSM layer can be added to the spin transfer torque from the reference layer, allowing a lower switching current. The choice of chiral material with left-handed chirality or right-handed chirality in the PSM layer is based on (i.e., selected to match) the magnetization of the reference layer.

[0052] Figure 2A is a cross-sectional side view of a top free layer MTJ stack including a PSM layer according to an embodiment.

[0053] Reference Figure 2A , the top free layer MTJ stack includes a PSM layer 201, a PMA magnetic layer (ML) 202, a tunnel barrier layer 203, a PMA ML 204, a dusting layer 205, a synthetic antiferromagnetic (SAF) layer 206, and an underlayer (and / or substrate) 207. The PMA ML 202 is the free layer of the MTJ stack, and the PMA ML 204, the dusting layer 205, and the SAF layer 206 form a reference layer of the MTJ stack.

[0054] The PMA ML 202 as a free layer of the MTJ stack may be formed as a CoFeB layer. Herein, the CoFeB layer refers to an alloy of Co, Fe, and B, without referring to a specific stoichiometry.

[0055] PMA ML 202 can also be made of Heusler compounds (such as Mn 3 In one or more embodiments, the Heusler compound may be a tetragonal Heusler compound, such as Mn 3 Z, wherein Z is Ge, Sn or Sb. In one or more embodiments, the Heusler compound may be Mn 3 Sn、Mn 3 Sb、Mn 2 CoSn、Mn 2 FeSb、Mn 2 CoAl、Mn 2 CoGe、Mn2 CoSi、Mn 2 CuSi、Co 2 CrAl、Co 2 CrSi、Co 2 MnSb or Co 2 MnSi. All Heusler compounds are listed with their stoichiometric formula and these compounds can be grown with some variation depending on the stoichiometric composition.

[0056] The tunnel barrier layer 203 may include MgO. In addition, magnesium aluminum oxide may be a suitable substitute for MgO, wherein the magnesium aluminum oxide has the form Mg 1-z Al 2+(2 / 3)z O 4 , where -0.5 <z<0.5。

[0057] The dust layer 205 (eg, a Ta layer) is a thin layer (eg, 0.3 nm thick) of material that can be inserted into the structure to magnetically couple the magnetic layer 204 to the SAF 206. Alternatively, Ta can be replaced by Ir, Ru, or Mo.

[0058] The SAF layer 206 may include two magnetic layers separated by a spacer.

[0059] The bottom layer 207 may include TaN / IrMn 3 、TaN / IrMn 3 The bottom layer 207 may include Pt, Ru, Ir, Ta, CoFeB, CoFeBTa, TaB, TiN or TaN. The bottom layer 207 may include a combination of at least two of the above materials forming a double-layer structure or a multi-layer structure.

[0060] As described above, by changing the direction of the applied current, the spin transfer torque from the PSM layer 201 can be added to the spin transfer torque from the reference layer (i.e., PMA ML 204, dust layer 205, and SAF layer 206), thereby allowing a lower switching current. The choice of chiral material with left-handed chirality or right-handed chirality in the PSM layer 201 is selected to match the reference layer.

[0061] The PSM layer 201 may include a material selected from B20 or C40 structures or other chiral structures (cubic, trigonal, tetragonal, and hexagonal), and may have a thickness greater than 2 nm, for example, between 2-3 nm.

[0062] The B20 structure is a cubic crystal structure with low internal symmetry. It has neither 4-fold rotational symmetry nor inversion symmetry in the lattice. The B20 structure can be completely determined by three structural parameters: the lattice parameter a; and two internal parameters u and v. Examples of the B20 structure include PtAl, BeAu, CoGe, CoSi, FeGe, PdGa, MnGe, RhGe, HfSb, HfSn, ZrSb, MnSi, FeSi, PtGa, RhSi, RuSi, NiSi, MnGe, CrSi, CrGe, PtMg, ReSi, RhSn, ZrSb, PdAl, and PtAl.

[0063] C40 is part of the hexagonal space group #180, abbreviated as P6 2 22. Examples of C40 structures include TaGe 2 、TaSi 2 、VGe 2 、HfSn 2 、NbGe 2 、MoSi 2 、VSi 2 , WSi 2 ,CrSi 2 , WAl 2 、HfSn 2 and NiMg 2 .

[0064] Examples of other chiral structures with chiral symmetry groups that can be used include IrGe 4 , Hf 5 Ir 3 、NbGe 2 , WAl 2 ,β-RhSi,Mg 3 Ru 2 and YSb 2 .

[0065] The PSM layer 201 may also include a topological material having low symmetry.

[0066] The PSM layer 201 includes more than 50% of a chiral material having left-handed chirality or right-handed chirality. For example, the chiral material may be PtAl or PtGa.

[0067] Figure 2B is a cross-sectional side view of a top free layer MTJ stack including a PSM layer according to another embodiment.

[0068] Reference Figure 2BThe top free layer MTJ stack includes a PSM layer 201, a PMA ML 202, a tunnel barrier layer 203, a PMAML 204, a dust removal layer 205, a SAF layer 206, and a bottom layer 207, as shown in FIG. Figure 2A , but also includes a texture breaking layer (TBL) 208 inserted between the PSM layer 201 and the PMA ML 202. That is, the PSM layer 201 can be as Figure 2A Directly connect to the PMA ML 202 interface as shown, or Figure 2B Shown are separated by spacer layers such as TBL 208 .

[0069] The TBL 208 may be used to induce greater magnetic anisotropy in the CoFeB (ie, the PMA ML 202). Thus, the TBL 208 may include a high spin-conductance layer, such as NiO.

[0070] As mentioned above, the PSM layer is compatible with the top free layer MTJ, which has many advantages, such as the reference layer is highly thermally stable, has a relatively large magnetic exchange coupling to the PMA magnetic layer, H ex , current MRAM products often use a top free layer MTJ, etc. However, the PSM layer can also be incorporated into the bottom free layer in the MTJ.

[0071] Figure 3A is a cross-sectional side view of a bottom free layer MTJ stack including a PSM layer according to an embodiment.

[0072] Reference Figure 3A , the bottom free layer MTJ stack includes a SAF layer 306, a dust layer 305, a PMA ML 304, a tunnel barrier layer 303, a PMA ML 302, a PSM layer 301, and a bottom layer 307. PMA ML 302 is a free layer of the MTJ stack, and PMA ML 304, the dust layer 305, and the SAF layer 306 form a reference layer of the MTJ stack.

[0073] Except for the order of layers above the bottom layer 307, Figure 3A In addition to the inversion, the structure of the bottom free layer MTJ stack is similar to Figure 2A The structure of the top free layer MTJ stack shown in and described above. Therefore, repeated description of each layer is omitted here.

[0074] Figure 3B is a cross-sectional side view of a bottom free layer MTJ stack including a PSM layer according to another embodiment.

[0075] Reference Figure 3BThe bottom free layer MTJ stack includes a SAF layer 306, a dust removal layer 305, a PMA ML 304, a tunnel barrier layer 303, a PMA ML 302, a PSM layer 301 and a bottom layer 307, as shown in FIG. Figure 3A 302, but also includes a TBL 308 inserted between the PSM layer 301 and the PMAML 302. That is, the PSM layer 301 can be as Figure 3A Directly bonded to PMA ML 301 as shown, or as Figure 3B Shown are separated by spacer layers such as TBL 308 .

[0076] The cap layer can exist in Figure 2A , Figure 2B , Figure 3A and Figure 3B Above the MTJ stack shown in .

[0077] Figure 4 An electronic device according to an embodiment is shown.

[0078] refer to Figure 4 , an electronic device 400 (eg, a user equipment (UE) or a mobile terminal) includes a processor 401 and a memory 402. Although not shown in Figure 4 , but depending on the type of electronic device 400, electronic device 400 may include various additional components, such as an input device, a sound output device, a display device, an audio module, a sensor module, an interface, a tactile module, a camera module, a power management module, a battery, a communication module, a user identification module (SIM) and / or an antenna module.

[0079] The processor 401 may execute, for example, software (e.g., a program) to control at least one other component (e.g., a hardware or software component) of the electronic device 400, and may perform various data processing or calculations. As at least part of the data processing or calculation, the processor 401 may load a command or data received from another component into the volatile memory 403, process the command or data stored in the volatile memory 403, and store the resultant data in the non-volatile memory 404. The processor 401 may include a main processor (e.g., a central processing unit (CPU) or an application processor) and an auxiliary processor (e.g., a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)), and the auxiliary processor may operate independently of the main processor or in conjunction with the main processor.

[0080] The memory 402 may store various data used by at least one component (e.g., the processor 401) of the electronic device 400. The various data may include, for example, software (e.g., a program) and input data or output data for commands related thereto. The memory 402 may include a volatile memory 403 or a non-volatile memory 404. The non-volatile memory 404 includes an MTJ stack including a PSM layer, such as Figure 2A , Figure 2B , Figure 3A and Figure 3B shown.

[0081] Figure 5 is a flow chart illustrating a method of forming a top free layer MTJ stack including a PSM layer according to an embodiment.

[0082] refer to Figure 5 In step 501, a bottom layer is provided. The bottom layer may include TaN / IrMn 3 、TaN / IrMn 3 The bottom layer 207 may include Pt, Ru, Ir, Ta, CoFeB, CoFeBTa, TaB, TiN or TaN. The bottom layer 207 may include a combination of at least two of the above materials forming a double-layer structure or a multi-layer structure.

[0083] In step 503, a reference layer is formed over the bottom layer. The reference layer may include a SAF layer, a dust removal layer, and a PMA ML.

[0084] In step 505 , a tunnel barrier layer, such as MgO, is formed over the reference layer.

[0085] In step 507 , a free layer, such as another PMA ML, is formed over the tunnel barrier layer.

[0086] In step 509 , a TBL may be formed over the free layer.

[0087] In step 511 , a PSM layer is formed over the TBL.

[0088] As mentioned above, the PSM layer can be directly connected to the free layer interface, such as Figure 2A as shown, or separated by a spacer layer such as TBL, as Figure 2B Therefore, step 509 may be optional.

[0089] In case step 509 is not performed, a PSM layer is formed over the free layer in step 511 .

[0090] Figure 6is a flow chart showing a method of forming a bottom free layer MTJ stack including a PSM layer according to an embodiment. Basically, except for the initial bottom layer, Figure 6 The methods and Figure 5 The method in is the opposite.

[0091] refer to Figure 6 , in step 601, a bottom layer is provided.

[0092] In step 603, a PSM layer is formed over the bottom layer.

[0093] In step 605 , a TBL may be formed over the PSM layer.

[0094] In step 607, a free layer, such as a PSM ML, is formed over the TBL. As described above, the PSM layer may be directly connected to the free layer interface, such as Figure 3A as shown, or separated by a spacer layer such as TBL, as Figure 3B Therefore, step 605 may be optional.

[0095] In case step 605 is not performed, a free layer is formed over the PSM layer in step 607 .

[0096] In step 609 , a tunnel barrier layer (eg, MgO) is formed over the free layer.

[0097] In step 611, a reference layer is formed over the tunnel barrier layer. The reference layer may include a PMA ML, a dust removal layer, and a SAF layer.

[0098] According to the above embodiments, a PSM layer (i.e., a chiral material layer) may be formed adjacent to a free layer of an MTJ device (or adjacent to a TBL, which is adjacent to the free layer), thereby providing an additional source of spin transfer torque and providing an MTJ device operable with a lower switching current.

[0099] The embodiments of the subject matter and operations described in this specification may be implemented in digital electronic circuits, or in computer software, firmware or hardware, including the structures disclosed in this specification and their structural equivalents, or a combination of one or more of them. The embodiments of the subject matter described in this specification may be implemented as one or more computer programs, that is, one or more modules of computer program instructions, which are encoded on a computer storage medium for execution by a data processing device or for controlling the operation of a data processing device. Alternatively or additionally, program instructions may be encoded on an artificially generated propagation signal, such as a machine-generated electrical, optical or electromagnetic signal, which is generated to encode information for transmission to a suitable receiver device for execution by a data processing device. The computer storage medium may be a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination thereof, or be included therein. In addition, although a computer storage medium is not a propagation signal, a computer storage medium may be a source or destination of computer program instructions encoded in an artificially generated propagation signal. The computer storage medium may also be one or more separate physical components or media (e.g., multiple CDs, disks or other storage devices), or be included in one or more separate physical components or media (e.g., multiple CDs, disks or other storage devices). Additionally, the operations described in this specification may be implemented as operations performed by a data processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

[0100] Although this specification may contain many specific implementation details, the implementation details should not be interpreted as a limitation on the scope of any claimed subject matter, but rather as a description of features specific to a particular embodiment. Certain features described in the context of separate embodiments in this specification may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although the features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be omitted from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0101] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in sequence, or that all of the operations shown be performed, to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0102] Thus, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the appended claims. In some cases, the actions set forth in the claims can be performed in a different order and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing may be advantageous.

[0103] While the present disclosure has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents.

Claims

1. A memory device, comprising: substrate; A magnetic tunnel junction MTJ formed above the substrate, the MTJ comprising a reference layer, a tunnel barrier layer and a free layer; as well as A parallel spin momentum PSM layer is formed over the free layer of the MTJ, the PSM layer comprising a chiral material. 2 . The memory device of claim 1 , wherein the chiral material has left-handed chirality or right-handed chirality corresponding to a magnetization direction of the reference layer of the MTJ.

3. The memory device according to claim 1, wherein: The chiral material includes PtAl or PtGa.

4. The memory device according to claim 1, wherein: The PSM layer has a thickness greater than 2 nm.

5. The memory device according to claim 1, wherein: The PSM layer includes more than 50% of a chiral material having left-handed chirality or right-handed chirality. 6 . The memory device of claim 1 , further comprising a texture breaking layer (TBL) formed between the free layer and the PSM layer of the MTJ.

7. The memory device according to claim 1, wherein: The tunnel barrier layer of the MTJ includes MgO.

8. The memory device according to claim 1, wherein: The free layer of the MTJ includes an alloy of Co, Fe, and B.

9. The memory device according to claim 1, wherein: The free layer of the MTJ includes a Heusler compound.

10. The memory device according to claim 9, wherein: The Heusler compound includes Mn3Ge.

11. The memory device according to claim 1, wherein: The free layer of the MTJ includes a C38 compound.

12. The memory device according to claim 11, wherein: The C38 compound includes AlMnGe.

13. A memory device comprising: substrate; A parallel spin momentum PSM layer formed above the substrate, the PSM layer comprising a chiral material; as well as A magnetic tunnel junction MTJ is formed above the PSM layer, wherein the MTJ includes a free layer, a tunnel barrier layer, and a reference layer.

14. The memory device according to claim 13, wherein: The chiral material has left-handed chirality or right-handed chirality corresponding to a magnetization direction of the reference layer of the MTJ.

15. The memory device of claim 13, wherein the chiral material comprises PtAl or PtGa.

16. The memory device according to claim 13, wherein: The PSM layer has a thickness greater than 2 nm.

17. The memory device according to claim 13, wherein: The PSM layer includes more than 50% of a chiral material having left-handed chirality or right-handed chirality. 18 . The memory device of claim 13 , further comprising a texture destroying layer formed between the free layer and the PSM layer of the MTJ.

19. A method of forming a memory device, comprising: providing a substrate; as well as A magnetic tunnel junction MTJ and a parallel spin momentum PSM layer are formed above the substrate. The MTJ includes a reference layer, a tunnel barrier layer and a free layer, and The PSM layer is formed adjacent to the free layer of the MTJ and includes a chiral material.

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