Double-layer gate nMOSFET device and preparation method thereof

Abstract

The invention discloses a double-gate nMOSFET device and a preparation method thereof. The preparation method comprises the following steps: growing an HfO2 thin film layer and a TiO2 thin film layer on a p-type Si substrate as gate dielectric layers; manufacturing a TiN electrode on the gate dielectric layer to obtain a gate of the nMOSFET device; n + doping is carried out on the two sides of the grid electrode of the nMOSFET device respectively, and a source electrode and a drain electrode of the nMOSFET device are obtained; by changing the gate stack structure, the purposes of improving the saturation drain current and the maximum transconductance of the nMOSFET device, reducing the electrical characteristics such as threshold voltage and subthreshold swing factor, improving the reliability of the device, prolonging the service life of the device and the like are achieved, and the nMOSFET device has the characteristics of reducing the cost, being easy to implement and being easy to popularize to a pMOSFET (p Metal-Oxide-Semiconductor Field Effect Transistor) device.

Description

Technical Field

[0001] The invention belongs to the technical field of functional materials, relates to a MOSFET device, and in particular to a double-layer gate nMOSFET device and a preparation method thereof. Background Art

[0002] At present, the wave of informatization and digitalization is sweeping the world. The integrated circuit industry has become a globally recognized important industry that supports national economic and social development and ensures national security. It is the main driving force for the advancement of key technologies such as communication networks, data processing and artificial intelligence, and is also an important part of the country's core competitiveness. With the continuous evolution of CMOS technology, power MOSFET devices have established their cornerstone position in the field of power electronics and are widely used in power supply switches, photovoltaic inverters, rail transportation and remote sensing technology.

[0003] In 1965, Moore's Law revealed that the number of transistors (i.e., integration) on an integrated circuit will double approximately every 18 months, and the performance will also double, while at the same time the cost of the chip will be halved. The electrical performance of traditional Si-based MOSFET devices is gradually approaching the physical limit and can no longer meet the performance requirements of the modern information society. In the future, the integration and power consumption of Si-based chips will reach their limits during the scaling process. With the continuous reduction in size, the continuous improvement in integration, and the continuous reduction in power consumption, how to effectively suppress the short channel effect, thereby maintaining and improving the performance, reliability, and service life of the device has become one of the issues of common concern in the industry.

[0004] The performance and reliability of MOSFET devices are ultimately closely related to the stack structure at the gate interface. -9 When the gate dielectric material reaches the m) level, the physical and chemical properties of the gate dielectric material will undergo a qualitative change, and the short channel effect and quantum tunneling effect will be inevitable, making the behavior of electrons and holes increasingly difficult to control.

[0005] As the characteristic size of MOSFET devices gradually shrinks to the nanometer level and approaches its physical limit, a series of negative effects gradually become prominent, such as short channel effect, drain-induced barrier lowering effect, gate reverse saturation current increase effect and hot carrier effect, which seriously degrades the quality and reliability of MOSFET devices, manifested in that the electrical performance no longer increases proportionally with the proportional reduction of its size.

[0006] In order to improve electrical performance, MOSFET technology has undergone several key innovations, covering new manufacturing processes, structural designs, and gate oxide dielectrics. For example, from strained silicon technology to high-κ gate dielectric technology, to FinFET and GAA structure technology, these innovations have promoted the transformation of CMOS technology from traditional two-dimensional planar structure to three-dimensional structure. Although these improvements have significantly enhanced the integration, stability and reliability of MOSFET devices, they have also brought about increased costs and process complexity. At present, there is a lack of relevant technologies and applications on how to more efficiently use existing silicon process equipment and mature CMOS technology to improve the performance and reliability of MOSFET devices while reducing costs and simplifying processes. Summary of the invention

[0007] In view of the deficiencies in the prior art, the purpose of the present invention is to provide a double-layer gate nMOSFET device and a method for preparing the same, which can reduce costs, suppress short channel effects and quantum tunneling effects, increase the electron barrier, and enhance the performance and reliability of the device without increasing the physical thickness of the gate.

[0008] In order to achieve the above object, the present invention adopts the following technical solutions:

[0009] A method for preparing a double-layer gate nMOSFET device comprises the following steps:

[0010] Step 1: growing a HfO2 thin film layer and a TiO2 thin film layer on a p-type Si substrate as a gate dielectric layer;

[0011] Step 2: fabricating a TiN electrode on the gate dielectric layer to obtain a gate of an nMOSFET device;

[0012] Step 3: Perform n on both sides of the gate of the nMOSFET device. + Doping is performed to obtain the source and drain of the nMOSFET device.

[0013] The present invention also has the following technical features:

[0014] Preferably, the p-type Si substrate growth medium layer is immersed in acetone for 3 to 5 minutes, then immersed in HF acid solution with a mass concentration of 3 to 10% for 10 to 30 seconds, then rinsed with deionized water, and finally dried for use.

[0015] Preferably, the thickness of the HfO2 thin film layer is 3 to 9 nm.

[0016] Preferably, the thickness of the TiO2 thin film layer is 3 to 9 nm.

[0017] Preferably, the HfO2 thin film layer or the TiO2 thin film layer is grown on a p-type Si substrate by atomic layer deposition.

[0018] Preferably, the n + The doping method is ion implantation, and the doping position is 0.5μm on both sides of the gate, and the doping concentration is 1×10 16 / cm 3 ~1×10 20 / cm 3 .

[0019] The present invention also protects a double-layer gate nMOSFET device prepared by the method as described above, V DS When the voltage is 1V, the saturation drain current (IDSS) is 4×10 -4 A~8×10 -4 A;

[0020] Subthreshold swing is (SS) 62mV / dec~64mV / dec;

[0021] The maximum transconductance is (g m )4.0×10 -5 S~9.0×10 -5 S.

[0022] Compared with the prior art, the present invention has the following technical effects:

[0023] The present invention adopts atomic layer deposition technology to insert HfO2 and TiO2 thin film layers into the gate structure, thereby suppressing the short channel effect and quantum tunneling effect, increasing the electron barrier, and improving the capacitance characteristics in the gate stack structure of the device, thereby reducing the threshold voltage, subthreshold swing and gate leakage current of the nMOSFET device, and improving the electrical performance such as saturated drain current and maximum transconductance, and improving reliability;

[0024] Furthermore, before growing the HfO2 and TiO2 thin film layers on the p-type Si substrate, the p-type Si substrate is first cleaned for the purpose of reducing the impurities in the HfO2 and TiO2 thin film layers as much as possible to prevent the impurities from affecting the crystal quality and capacitance characteristics of the HfO2 and TiO2 inserted thin layers;

[0025] Furthermore, the thickness of the HfO2 and TiO2 thin film layers is 3 to 9 nm. The HfO2 and TiO2 thin film layers within this range can obtain the best capacitance characteristics of the gate, laying a physical foundation for improving the electrical characteristics of the device;

[0026] Furthermore, the gate stack structure of the HfO2 and TiO2 double-thin-layer nMOSFET device can effectively improve the electrical performance of the device. The thicker film layer and the larger number of film layers not only do not significantly improve the electrical performance of the device, but also cause carrier mobility attenuation due to scattering between interfaces, and also increase the process time and cost.

[0027] In summary, the present invention can effectively improve and optimize the electrical performance and reliability of traditional nMOSFET devices by using a double-thin layer gate stack structure of HfO2 and TiO2; it has the characteristics of reducing costs, being easy to implement, and being easy to extend to pMOSFET devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic structural diagram of an nMOSFET device of the present invention;

[0029] Figure 2 It is a schematic diagram of a nMOSFET device test circuit of the present invention;

[0030] Figure 3 Schematic diagram of input and output curves of the nMOSFET device of the present invention;

[0031] Figure 4 It is a schematic diagram of the transconductance curve of the nMOSFET device of the present invention. DETAILED DESCRIPTION

[0032] The specific contents of the present invention are further explained in detail below in conjunction with embodiments.

[0033] Example 1

[0034] This embodiment provides a method for preparing a double-layer gate nMOSFET device, comprising the following steps:

[0035] Step 1: The p-type Si substrate growth medium layer is immersed in acetone for 5 minutes, then immersed in a 10% HF acid solution for 10 seconds, then rinsed with deionized water, and finally dried for use;

[0036] A HfO2 thin film layer and a TiO2 thin film layer are sequentially grown on a p-type Si substrate by an atomic layer deposition method as a gate dielectric layer; wherein the thickness of the HfO2 thin film layer is 3 nm, and the thickness of the TiO2 thin film layer is 5 nm;

[0037] Step 2: Using a standard CMOS process to fabricate a TiN electrode on the gate dielectric layer to obtain a gate of an nMOSFET device;

[0038] Step 3: Perform n on both sides of the gate of the nMOSFET device. +Doping to obtain the source and drain of nMOSFET device; where n + The doping method is ion implantation, and the doping position is 0.5μm on both sides of the gate, and the doping concentration is 1×10 16 / cm 3 ; The double-layer gate nMOSFET device prepared in Example 1 is recorded as sample A.

[0039] Example 2

[0040] This embodiment provides a method for preparing a double-layer gate nMOSFET device, comprising the following steps:

[0041] Step 1: The p-type Si substrate growth medium layer is immersed in acetone for 5 minutes, then immersed in a 10% HF acid solution for 10 seconds, then rinsed with deionized water, and finally dried for use;

[0042] A HfO2 thin film layer and a TiO2 thin film layer are sequentially grown on a p-type Si substrate by an atomic layer deposition method as a gate dielectric layer; wherein the thickness of the HfO2 thin film layer is 8 nm, and the thickness of the TiO2 thin film layer is 5 nm;

[0043] Step 2: Using a standard CMOS process to fabricate a TiN electrode on the gate dielectric layer to obtain a gate of an nMOSFET device;

[0044] Step 3: Perform n on both sides of the gate of the nMOSFET device. + Doping to obtain the source and drain of nMOSFET; where n + The doping method is ion implantation, and the doping position is 0.5μm on both sides of the gate, and the doping concentration is 1×10 18 / cm 3 ; The double-layer gate nMOSFET device prepared in Example 2 is recorded as sample B.

[0045] Example 3

[0046] This embodiment provides a method for preparing a double-layer gate nMOSFET device, comprising the following steps:

[0047] Step 1: The p-type Si substrate growth medium layer is immersed in acetone for 5 minutes, then immersed in a 10% HF acid solution for 10 seconds, then rinsed with deionized water, and finally dried for use;

[0048] A HfO2 thin film layer and a TiO2 thin film layer are sequentially grown on a p-type Si substrate by an atomic layer deposition method as a gate dielectric layer; wherein the thickness of the HfO2 thin film layer is 9 nm, and the thickness of the TiO2 thin film layer is 8 nm;

[0049] Step 2: Using a standard CMOS process to fabricate a TiN electrode on the gate dielectric layer to obtain a gate of an nMOSFET device;

[0050] Step 3: Perform n on both sides of the gate of the nMOSFET device. + Doping to obtain the source and drain of nMOSFET; where n + The doping method is ion implantation, and the doping position is 0.5μm on both sides of the gate, and the doping concentration is 1×10 20 / cm 3 ; The double-layer gate nMOSFET device prepared in Example 3 is recorded as sample C.

[0051] The structure of the nMOSFET device of the present invention is as follows Figure 1 As shown, the nMOSFET device test circuit is shown as follows Figure 2 As shown;

[0052] The electrical properties of samples A, B and C were tested using a Keithley 4200A-SCS semiconductor parameter analyzer at room temperature;

[0053] The source was grounded, and the gate-source voltage was set to 0 V to 2 V with a step size of 0.04 V (51 data points); the source-drain voltage was 0 to 3 V with a step size of 0.05 V (61 data points);

[0054] Figure 3 Schematic diagram of input and output curves of the nMOSFET device of the present invention; Figure 3 As shown in the IV input-output curve, sample A has a DS When the voltage is 1V, the drain current is 5.5×10 -6 A increased to 7.5×10 -5 A; The subthreshold swing of sample A is lower than that of sample B and sample C, and is closer to the ideal subthreshold swing;

[0055] Figure 4 Schematic diagram of the transconductance curve of the nMOSFET device of the present invention, such as Figure 4 As shown, the maximum transconductance of sample A is from 4.5×10 -5 S increased to 8×10 -5 S.

[0056] Through Figure 3 , Figure 4 The analysis shows that by changing the gate stack structure, that is, introducing a double-layer stack structure of HfO2 and TiO2 at the gate, the saturated drain current and maximum transconductance of the nMOSFET device can be increased, and the electrical characteristics such as the threshold voltage, subthreshold swing factor, gate leakage current and reliability can be improved.

[0057] Example 4

[0058] This embodiment provides a method for preparing a double-layer gate nMOSFET device, comprising the following steps:

[0059] Step 1: The p-type Si substrate growth medium layer is immersed in acetone for 4 minutes, then immersed in a 5% HF acid solution for 15 seconds, then rinsed with deionized water, and finally dried for use;

[0060] A TiO2 thin film layer and a HfO2 thin film layer are sequentially grown on a p-type Si substrate by an atomic layer deposition method as a gate dielectric layer; wherein the thickness of the HfO2 thin film layer is 5 nm, and the thickness of the TiO2 thin film layer is 3 nm;

[0061] Step 2: Using a standard CMOS process to fabricate a TiN electrode on the gate dielectric layer to obtain a gate of an nMOSFET device;

[0062] Step 3: Perform n on both sides of the gate of the nMOSFET device. + Doping to obtain the source and drain of nMOSFET device; where n + The doping method is ion implantation, and the doping position is 0.5μm on both sides of the gate, and the doping concentration is 1×10 18 / cm 3 ; The double-layer gate nMOSFET device prepared in Example 4 is recorded as sample D.

[0063] The electrical properties of sample D were tested using a Keithley 4200A-SCS semiconductor parameter analyzer at room temperature;

[0064] The source was grounded, and the gate-source voltage was set to 0 V to 2 V with a step size of 0.04 V (51 data points); the source-drain voltage was 0 to 3 V with a step size of 0.05 V (61 data points);

[0065] The test results show that the saturation drain current (IDSS) of sample D is 4×10 -4 A~8×10 -4 A(V DS When the subthreshold swing (SS) is 62mV / dec~64mV / dec, the maximum transconductance (g m ) is 4.0×10 -5 S~9.0×10 -5 S.

[0066] Example 5

[0067] This embodiment provides a method for preparing a double-layer gate nMOSFET device, comprising the following steps:

[0068] Step 1: The p-type Si substrate growth medium layer is immersed in acetone for 4 minutes, then immersed in a 5% HF acid solution for 15 seconds, then rinsed with deionized water, and finally dried for use;

[0069] A TiO2 thin film layer and a HfO2 thin film layer are sequentially grown on a p-type Si substrate by an atomic layer deposition method as a gate dielectric layer; wherein the thickness of the HfO2 thin film layer is 9 nm, and the thickness of the TiO2 thin film layer is 9 nm;

[0070] Step 2: Using a standard CMOS process to fabricate a TiN electrode on the gate dielectric layer to obtain a gate of an nMOSFET device;

[0071] Step 3: Perform n on both sides of the gate of the nMOSFET device. + Doping to obtain the source and drain of nMOSFET device; where n + The doping method is ion implantation, and the doping position is 0.5μm on both sides of the gate, and the doping concentration is 1×10 20 / cm 3 ; The double-layer gate nMOSFET device prepared in Example 4 is recorded as sample E.

[0072] Example 6

[0073] This embodiment provides a method for preparing a double-layer gate nMOSFET device, comprising the following steps:

[0074] Step 1: The p-type Si substrate growth medium layer is immersed in acetone for 3 minutes, then immersed in a 3% HF acid solution for 30 seconds, then rinsed with deionized water, and finally dried for use;

[0075] A HfO2 thin film layer and a TiO2 thin film layer are sequentially grown on a p-type Si substrate by an atomic layer deposition method as a gate dielectric layer; wherein the thickness of the HfO2 thin film layer is 3 nm, and the thickness of the TiO2 thin film layer is 3 nm;

[0076] Step 2: Using standard CMOS process to make a TiN electrode on the gate dielectric layer to obtain the gate of nMOSFET;

[0077] Step 3: Perform n on both sides of the gate of the nMOSFET device. + Doping to obtain the source and drain of nMOSFET device; where n + The doping method is ion implantation, and the doping position is 0.5μm on both sides of the gate, and the doping concentration is 1×10 20 / cm 3 ; The double-layer gate nMOSFET device prepared in Example 5 is recorded as sample F.

[0078] In summary, the double-layer gate nMOSFET device of the present invention can effectively improve and optimize the electrical performance and reliability of the traditional nMOSFET device by changing the gate stack structure, that is, introducing a double-layer stack structure of HfO2 and TiO2 at the gate. The saturation drain current (IDSS) of the double-layer gate nMOSFET device of the present invention is 4×10 -4 A~8×10 -4 A(V DS When the subthreshold swing (SS) is 62mV / dec~64mV / dec, the maximum transconductance (g m ) is 4.0×10 -5 S~9.0×10 -5 S, and can reduce the cost of nMOSFET devices to a certain extent.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit them. Those skilled in the art should understand that modifying the technical solutions described in the above embodiments, or replacing some or all of the technical features therein by equivalents, does not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a double-gate nMOSFET device, characterized in that: The following steps are involved: Step 1: growing a HfO2 thin film layer and a TiO2 thin film layer on a p-type Si substrate as a gate dielectric layer; Step 2: fabricating a TiN electrode on the gate dielectric layer to obtain a gate of an nMOSFET device; Step 3: Perform n on both sides of the gate of the nMOSFET device. + Doping is performed to obtain the source and drain of the nMOSFET device.

2. The method for preparing a double-layer gate nMOSFET device according to claim 1, characterized in that: The p-type Si substrate growth medium layer is pre-immersed in acetone for 3-5 minutes, then immersed in HF acid solution with a mass concentration of 3-10% for 10-30 seconds, then rinsed with deionized water, and finally blown dry for standby use.

3. The method for preparing a double-layer gate nMOSFET device according to claim 1, characterized in that: The thickness of the HfO2 thin film layer is 3-9 nm.

4. The method for preparing a double-layer gate nMOSFET device according to claim 1, characterized in that: The thickness of the TiO2 film layer is 3-9nm.

5. The method for preparing a double-layer gate nMOSFET device according to claim 1, characterized in that: The HfO2 thin film layer or the TiO2 thin film layer is grown on the p-type Si substrate by using an atomic layer deposition method.

6. The method for preparing a double-layer gate nMOSFET device according to claim 1, characterized in that: The n + The doping method is ion implantation, and the doping position is 0.5μm on both sides of the gate, and the doping concentration is 1×10 16 / cm 3 ~1×10 20 / cm 3 .

7. A double-layer gate nMOSFET device prepared by the method according to any one of claims 1 to 6.

8. The double-gate nMOSFET device according to claim 7, characterized in that: V DS When the voltage is 1V, the saturated drain current is 4×10 -4 A~8×10 -4 A; Subthreshold swing is 62mV / dec~64mV / dec; The maximum transconductance is 4.0×10 -5 S~9.0×10 -5 S.

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