Semiconductor structure and manufacturing method thereof
By forming grooves in the semiconductor structure, the leakage current problem caused by the reduction of transistor size is solved, the width of the channel region and the control ability of the gate are improved, and the performance and efficiency of the transistor and chip are improved.
Patent Information
- Application Number
- CN202510156134.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-12
- Publication Date
- 2025-05-16
AI Technical Summary
With the decrease in transistor size, leakage currents become one of the key issues, and achieving higher transistor density, faster speeds and lower leakage currents in the post-Moor era has become challenging.
By forming the first and second sacrificial layers alternately stacked on the substrate, semiconductor pillars penetrate through these layers, and grooves are formed on the side walls of the semiconductor pillars to increase the contact area between the semiconductor pillars and the gate, thereby increasing the width of the channel region and improving the gate control ability of the channel region.
By increasing the width of the channel region, reducing leakage current, improving the performance and efficiency of the transistor, thereby improving the operating efficiency of the chip.
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Figure CN120018537A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art
[0002] Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is the basic component of silicon chips. Silicon chips have been developed in accordance with Moore's Law. As the size of devices continues to decrease, the size of transistors continues to shrink. However, the reduction in the size of transistors will deteriorate some of the performance of transistors. Therefore, in the post-Moore era, it is becoming increasingly challenging to achieve higher transistor density, faster speed and lower leakage current at the same time. Summary of the invention
[0003] In view of this, an embodiment of the present disclosure provides a semiconductor structure and a method for manufacturing the same.
[0004] According to a first aspect of the present disclosure, there is provided a method for manufacturing a semiconductor structure, comprising:
[0005] Forming a stacking structure on the first surface of the substrate; the stacking structure includes a first sacrificial layer and a second sacrificial layer alternately stacked;
[0006] forming a semiconductor column penetrating the stacked structure and contacting the substrate;
[0007] forming a groove in the stack structure, wherein the sidewall of the groove exposes each of the second sacrificial layers;
[0008] Etching each of the second sacrificial layers through the trenches until the sidewalls of the semiconductor pillars are exposed;
[0009] Etching the exposed sidewall of the semiconductor column to form a groove on the exposed sidewall surface of the semiconductor column;
[0010] removing the first sacrificial layer from the sidewall of the semiconductor column;
[0011] A gate dielectric layer and a gate are sequentially formed on the sidewalls of the semiconductor column.
[0012] In some embodiments, the forming of a semiconductor column penetrating the stacked structure and contacting the substrate includes:
[0013] forming a hole penetrating the stacked structure and exposing the substrate;
[0014] A single crystal semiconductor column is formed in the hole by using an epitaxial growth process.
[0015] In some embodiments, etching the sidewalls of the semiconductor pillars to be exposed includes:
[0016] The sidewall of the single crystal semiconductor column is etched by using an etching solution having different etching rates for multiple crystal planes of the single crystal semiconductor column; wherein the sidewall of the single crystal semiconductor column has different crystal orientations so that the cross-sectional shapes of the groove perpendicular to the substrate are different.
[0017] In some embodiments, the material of the single crystal semiconductor pillar is single crystal silicon, and the etching solution is an alkaline solution.
[0018] In some embodiments, a cross section of the groove perpendicular to the first surface is one of a triangle, a trapezoid, and an arcuate shape.
[0019] In some embodiments, the manufacturing method further comprises:
[0020] Doping is performed into the semiconductor column to form a first source-drain region and a second source-drain region that are spaced apart from each other; wherein the semiconductor column between the first source-drain region and the second source-drain region forms a channel region.
[0021] According to a second aspect of the present disclosure, there is provided a semiconductor structure, comprising:
[0022] substrate;
[0023] A semiconductor column, located on the first surface of the substrate and extending in a vertical direction, wherein a sidewall of the semiconductor column is formed with at least one groove parallel to the first surface of the substrate; the vertical direction is perpendicular to the first surface;
[0024] A gate dielectric layer, located on the sidewall surface of the semiconductor column where the groove is formed;
[0025] The gate is located on the surface of the gate dielectric layer.
[0026] In some embodiments, a cross section of the groove perpendicular to the first surface is one of a triangle, a trapezoid, and an arcuate shape.
[0027] In some embodiments, in a cross section of the semiconductor column perpendicular to the first surface, a sidewall of the semiconductor column is wavy.
[0028] In some embodiments, the semiconductor pillar is a single crystal semiconductor pillar. In some embodiments, the semiconductor pillar is a single crystal semiconductor pillar.
[0029] The manufacturing method of the semiconductor device provided in this embodiment first forms a first sacrificial layer and a second sacrificial layer alternately stacked on a substrate, then forms a semiconductor column that penetrates the first sacrificial layer and the second sacrificial layer, then removes the second sacrificial layer and etches the semiconductor column at the position where the second sacrificial layer is removed, thereby forming a groove parallel to the first surface of the substrate on the side wall of the semiconductor column. These grooves make the side wall of the semiconductor column appear wavy in a cross-sectional view perpendicular to the substrate. Compared with the side wall that is not formed with a groove and is straight in a cross-sectional view perpendicular to the substrate, the side wall with a groove can increase the contact area between the semiconductor column and the gate, thereby increasing the width of the channel region, so that the gate's control ability over the channel region can be enhanced, the efficiency of the transistor is improved, and then the chip operation efficiency is improved. In addition, the increase in the width of the channel region is conducive to reducing leakage current and improving the performance of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure.
[0031] Figures 2a to 2j A schematic diagram of a manufacturing process of a semiconductor structure provided in an embodiment of the present disclosure.
[0032] Figure 3 Schematic diagram of a semiconductor column provided in an embodiment of the present disclosure Figure 1 .
[0033] Figure 4 Schematic diagram 2 of a semiconductor column provided in an embodiment of the present disclosure.
[0034] Figure 5 Schematic diagram of a transistor provided in an embodiment of the present disclosure Figure 1 .
[0035] Figure 6 Schematic diagram 2 of a transistor provided in accordance with an embodiment of the present disclosure.
[0036] Figure 7 The embodiment of the present disclosure provides the etching rates of KOH on different crystal planes of the single crystal semiconductor pillar.
[0037] Figure 8a to Figure 8b A schematic diagram of another manufacturing process of a semiconductor column provided in an embodiment of the present disclosure.
[0038] Figure 9a to Figure 9b A schematic diagram of a manufacturing process of another semiconductor column provided in an embodiment of the present disclosure.
[0039] Figure 10a to Figure 10b A schematic diagram of a manufacturing process of another semiconductor column provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0040] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0041] Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. Obviously, the described aspects are only some of the aspects of the present disclosure, not all. Features in various aspects may be interchanged and / or combined.
[0042] In the description of the present disclosure, it is necessary to understand that the terms "length", "width", "depth", "up", "down", "outside", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.
[0043] As the size of transistors continues to decrease, leakage current becomes one of the key issues. One of the means to reduce transistor leakage current is to improve the control ability of the gate over the channel. The present disclosure provides a solution that can improve the control ability of the gate over the channel. Figure 1 The flowchart of the method for manufacturing the semiconductor structure provided by the embodiment of the present disclosure is as follows. Figure 1 As shown, the method for manufacturing the semiconductor structure includes:
[0044] S100: forming a stacking structure on a surface of a substrate; the stacking structure includes a first sacrificial layer and a second sacrificial layer alternately stacked;
[0045] S200: forming a semiconductor column penetrating the stacked structure and contacting the substrate;
[0046] S300: forming a trench in the stack structure, wherein the sidewall of the trench exposes each second sacrificial layer;
[0047] S400: etching each second sacrificial layer through the trenches until the sidewalls of the semiconductor pillars are exposed;
[0048] S500: etching the exposed sidewall of the semiconductor column to form a groove at the exposed sidewall of the semiconductor column;
[0049] S600: removing the first sacrificial layer on the sidewall of the semiconductor column;
[0050] S700: forming a gate dielectric layer and a gate in sequence on the sidewall of the semiconductor column.
[0051] The manufacturing method of the semiconductor device provided in this embodiment first forms a first sacrificial layer and a second sacrificial layer alternately stacked on a substrate, then forms a semiconductor column that penetrates the first sacrificial layer and the second sacrificial layer, then removes the second sacrificial layer and etches the semiconductor column at the position where the second sacrificial layer is removed, thereby forming a groove parallel to the first surface of the substrate on the side wall of the semiconductor column. These grooves make the side wall of the semiconductor column appear wavy in a cross-sectional view perpendicular to the substrate, which can also be called a sawtooth shape. Compared with the side wall that is not formed with a groove and is straight in a cross-sectional view perpendicular to the substrate, the side wall with a groove can increase the contact area between the active column and the gate, thereby increasing the width of the channel region, so that the gate's control ability over the channel region can be enhanced, the efficiency of the transistor is improved, and then the chip operation efficiency is improved. In addition, increasing the width of the channel region can also reduce leakage current and improve the performance of the transistor.
[0052] Figures 2a to 2j Schematic diagram of the structure of the semiconductor structure provided by the embodiment of the present disclosure during the manufacturing process. Figure 1 , Figures 2a to 2j The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure is described in detail.
[0053] See also Figure 2a , perform step S100, provide a substrate 100, and form a stacked structure 200 on the first surface 101 of the substrate 100, the stacked structure including a first sacrificial layer 210 and a second sacrificial layer 220 alternately stacked along a vertical direction. The vertical direction is, for example, Figure 2a The Z direction in .
[0054] By way of example, the substrate 100 may be made of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI), III-V compounds (e.g., GaN, GaAs, InAs, etc.), or any other suitable semiconductor material. The substrate 100 may also be made of other materials. In the present embodiment, the substrate 100 is a single crystal silicon substrate.
[0055] As shown in FIG2 , a first sacrificial layer 210 is first deposited on the substrate 100, a second sacrificial layer 220 is deposited on the first sacrificial layer 210, and another first sacrificial layer 210 is deposited on the second sacrificial layer 220, and the first sacrificial layer 210 and the second sacrificial layer 220 are alternately deposited to form a stacked structure 200. The top layer in the stacked structure 200 may be the first sacrificial layer 210 or the second sacrificial layer 220. In this embodiment, the top layer in the stacked structure is the second sacrificial layer 220.
[0056] The first sacrificial layer 210 and the second sacrificial layer 220 have a large etching selectivity ratio for the same etchant, so that the first sacrificial layer 210 will not be etched or the etching amount of the first sacrificial layer 210 is very small when the second sacrificial layer 220 is etched. For example, the materials of the first sacrificial layer 210 and the second sacrificial layer 220 can be selected from insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride, and can also be selected from metal oxides, metal nitrides, or conductive materials. In this embodiment, the material of the first sacrificial layer 210 is silicon nitride, and the material of the second sacrificial layer 220 is silicon oxide.
[0057] For example, the first sacrificial layer 210 and the second sacrificial layer 220 may be formed by using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).
[0058] See also Figure 2b and Figure 2c , step S200 is performed to form a semiconductor pillar 400 that penetrates the stack structure 200 and contacts the substrate 100 .
[0059] like Figure 2b As shown, a hole 310 penetrating the stacked structure 200 and exposing the substrate 100 is first formed.
[0060] By way of example, the hole 310 may be formed by a photolithography process and an etching process. Specifically, the step of forming the hole 310 includes: forming a first photoresist layer on the top surface of the stacked structure 200; exposing and developing the first photoresist layer to form a first pattern in the first photoresist layer, the first pattern revealing the stacked structure 200; etching the stacked structure 200 based on the first pattern until the substrate 100 is exposed, thereby forming the hole 310 in the stacked structure 200. After the hole 310 is formed, the first photoresist layer is removed to facilitate subsequent processes.
[0061] Then, if Figure 2c As shown, a semiconductor material is deposited in the hole 310 to form a semiconductor pillar 400 .
[0062] The material of the semiconductor pillar 400 can be selected from other semiconductor materials such as silicon, germanium, silicon germanium or metal oxide semiconductors. Metal oxide semiconductors include but are not limited to IGZO (indium gallium zinc oxide), ITZO (indium tin zinc oxide) or ZTO (zinc tin oxide). Silicon can be single crystal silicon or polycrystalline silicon.
[0063] In some embodiments, an epitaxial growth process may be used to form a single crystalline semiconductor pillar within the hole 310 .
[0064] By using an epitaxial growth process, a single crystal semiconductor pillar 400 that inherits the crystal orientation of the first surface 101 of the substrate can be formed on the single crystal substrate 100. In this embodiment, the substrate 100 is single crystal silicon, and the semiconductor pillar 400 is single crystal silicon that inherits the crystal orientation of the first surface 101 of the substrate. By way of example, a vapor phase epitaxy process, a low temperature epitaxy process, a liquid phase epitaxy process, a molecular beam epitaxy process, a reduced pressure epitaxy process, etc. can be used to form a single crystal silicon pillar on a silicon substrate.
[0065] The cross section of the single crystal semiconductor pillar 400 parallel to the substrate may be rectangular, square, circular, elliptical, etc., which is not limited in the present disclosure.
[0066] For example, the top surface of the semiconductor pillar 400 is flush with the top surface of the stacked structure 200. In the process of preparing the semiconductor pillar, the semiconductor material may be first deposited to fill the hole 310 and cover the top surface of the stacked structure 200, and then the semiconductor material may be processed by a planarization process to be flush with the top surface of the stacked structure 200, thereby obtaining the semiconductor pillar 400. The planarization process includes but is not limited to a chemical mechanical polishing (CMP) process.
[0067] In some embodiments, before performing step S300 , the manufacturing method further includes: forming a protection layer 260 covering the top surface of the stack structure 200 and the top surface of the semiconductor pillar 400 .
[0068] like Figure 2d As shown, a protective layer 260 is formed on the top surface of the stacked structure 200 and the semiconductor column 400. By way of example, the material of the protective layer 260 is different from the material of the sacrificial layer of the top layer in the stacked structure 200, but can be the same as the material of the sacrificial layer of the second top layer. For example, in the present embodiment, the top layer of the stacked structure 200 is the second sacrificial layer 220, then the material of the protective layer 260 can be the same as the material of the first sacrificial layer 210. Of course, the material of the protective layer 260 can also be different from both the first sacrificial layer 210 and the second sacrificial layer 220. By way of example, the material of the protective layer 260 can be an insulating material such as silicon oxide, silicon oxynitride, silicon nitride, or can also be an inorganic protective film. In the present embodiment, the material of the protective layer 260 is silicon nitride.
[0069] See also Figure 2e , step S300 is performed to form a trench 320 in the stack structure 200 , wherein the trench 320 extends along a vertical direction to a sidewall of the trench 320 to expose each second sacrificial layer 220 .
[0070] In some embodiments, step S300 may specifically include: alternately etching the second sacrificial layer 220 and the first sacrificial layer 210 until the first sacrificial layer 210 in contact with the substrate is exposed, and then stopping to form a groove 320. At this time, the bottom of the groove 320 stays in the first sacrificial layer 210 of the bottom layer and does not extend to the substrate 100. The retained first sacrificial layer 210 of the bottom layer can protect the first surface 101 of the substrate 100 in the subsequent etching step to prevent the first surface of the substrate from being etched, so that the first surface of the substrate maintains a good morphology and thus the device subsequently formed near the first surface of the substrate has good performance.
[0071] In this embodiment, since a protection layer 260 is formed on the stacked structure 200 , the groove 320 also penetrates the protection layer 260 .
[0072] The following is a detailed description of the formation process of the groove 320 by taking the embodiment in which the protective layer 260 is present on the stacked structure 200 as an example. For example, the groove can be formed by a photolithography process and an etching process. Specifically, the steps of forming the groove 320 include: forming a second photoresist layer on the top surface of the protective layer 260; exposing and developing the second photoresist layer to form a second pattern in the second photoresist layer, and the second pattern reveals the protective layer 260; etching the protective layer 260 and the stacked structure 200 in sequence based on the second pattern until the first sacrificial layer 210 of the bottom layer is exposed, thereby forming the groove 320 in the stacked structure 200. After the groove 320 is formed, the second photoresist layer is removed to facilitate subsequent processes.
[0073] Continue to see Figure 2e , the trench 320 is adjacent to the semiconductor pillar 400, that is, there is only a thin layer formed by a partial stacking structure between the trench 320 and the semiconductor pillar 400, and no other structure. In this way, the second sacrificial layer 220 on the side wall of the semiconductor pillar 400 can be removed more quickly through the trench 320, saving resources and shortening manufacturing time.
[0074] There may be more than one groove 320 adjacent to the semiconductor column 400. For example, in the present embodiment, there are two grooves 320 adjacent to each semiconductor column 400, and the two grooves 320 are arranged opposite to each other across the semiconductor column 400. The more grooves 320 there are, the faster the second sacrificial layer 220 is removed, and the removal rate is more uniform everywhere, which can reduce the occurrence of local etching of the semiconductor column, thereby making the depth of the groove formed in the next step more uniform.
[0075] See also Figure 2f , performing step S400 , etching each second sacrificial layer through the trench 320 until the sidewall of the semiconductor pillar 400 is exposed.
[0076] In some embodiments, if the cross section of the semiconductor pillar 400 parallel to the substrate is rectangular or square, the second sacrificial layer 220 may be etched in this step until two opposite sidewalls of the semiconductor pillar 400 are exposed.
[0077] In some other embodiments, all the second sacrificial layer 220 on the sidewalls of the semiconductor pillar 400 may be removed through the trench 320 to expose the sidewalls of the semiconductor pillar 400 .
[0078] For example, a wet etching process may be used to etch the second sacrificial layer 220. In this embodiment, the material of the second sacrificial layer 220 is silicon oxide, and a hydrofluoric acid (HF) solution may be used to remove the silicon oxide. The amount of etching of silicon nitride by hydrofluoric acid is very small, so the first sacrificial layer 210 on the side wall of the semiconductor pillar 400 is retained. In other embodiments, other wet etchants (such as etching solutions) may also be used to remove the second sacrificial layer 220 while retaining the first sacrificial layer 210.
[0079] See also Figure 2g , performing step S500 to etch the exposed sidewalls of the semiconductor pillar 400 to form a groove 410 at the exposed sidewalls of the semiconductor pillar 400 .
[0080] For example, a wet etching process may be used to etch the exposed sidewalls of the semiconductor pillar 400 .
[0081] Through the above step S400, the second sacrificial layer on the side wall of the semiconductor column is removed, and a channel from the groove 320 to the side wall of the semiconductor column 400 is formed. In this step, the etching liquid can contact the side wall of the semiconductor column 400 through the channel, and then etch the side wall of the semiconductor column 400, forming a groove 410 on the side wall surface of the semiconductor column 400. And if the second sacrificial layer 220 around the semiconductor column 400 is completely removed, then in this step, the etching liquid will surround the semiconductor column 400, and a circle of the semiconductor column side wall will be etched to form an annular groove. The annular groove is parallel to the first surface of the substrate.
[0082] like Figure 2g The first sacrificial layer 210 can prevent part of the sidewall of the semiconductor column 400 from contacting the etching solution, so that the semiconductor column 400 covered by the first sacrificial layer 210 is not etched, so that the sidewall surface of the semiconductor column 400 has multiple annular grooves 410 arranged at intervals along the vertical direction. In the cross-sectional view of the semiconductor column 400 perpendicular to the substrate, for example Figure 2g In the cross-sectional view shown, the sidewall of the semiconductor column is wavy, which can also be called sawtooth, wherein each depression of the wavy shape corresponds to an annular groove, and each straight line corresponds to the original sidewall covered by the first sacrificial layer 210 but not etched.
[0083] In different embodiments, the number of the annular grooves 410 on the sidewall of the semiconductor column may be different. Figure 2g In the embodiment shown, the sidewall of the semiconductor pillar 400 is formed with four annular grooves 410. In another embodiment, as shown in FIG. Figure 3 As shown, the number of the annular grooves 410 on the sidewall of the semiconductor column 400 may also be three. In some other embodiments, as Figure 4 As shown, the number of the annular groove 410 on the sidewall of the semiconductor pillar 400 may also be one. In practical applications, the number of the annular grooves 410 may be adjusted according to the required width of the channel region, etc.
[0084] In some embodiments, the thickness of the second sacrificial layer 220 along the vertical direction (eg, Z direction) is smaller than the thickness of the first sacrificial layer 210. Thus, in this step, the etching opening of the semiconductor pillar 400 is smaller, and the process control capability is stronger.
[0085] Return to see Figure 2g and Figure 2h , perform step S600 to remove all the first sacrificial layers 210 on the sidewalls of the semiconductor pillar 400 .
[0086] All first sacrificial layers 210 include: the first sacrificial layer 210 in the thin layer between the semiconductor pillar 400 and the trench 320, and the first sacrificial layer 210 on the substrate first surface 101. After all first sacrificial layers 210 are removed, the entire sidewall of the semiconductor pillar 400 may be exposed.
[0087] For example, a wet etching process may be used to remove all of the first sacrificial layer 210. It should be noted that, in the process of removing the first sacrificial layer 210, some sharp corners of the sidewall of the semiconductor column 400 may be etched to form rounded corners or etched away, so that the sidewall of the semiconductor column 400 is smoother. In this embodiment, phosphoric acid solution (H3PO4) or other etching solutions may be used to remove silicon nitride, that is, the first sacrificial layer.
[0088] See also Figure 2i and Figure 2j , step S700 is performed to sequentially form a gate dielectric layer 510 and a gate 520 on the sidewall of the semiconductor pillar 400 .
[0089] like Figure 2iAs shown, a gate dielectric layer 510 is formed on the side wall surface of the semiconductor column 400. It should be noted that the side wall surface of the semiconductor column 400 refers to the side wall surface of the semiconductor column 400 after the groove 410 is formed. The side wall surface includes not only the unetched side wall surface, but also the inner surface of the groove 410, that is, the side wall surface is wavy along the vertical direction. For example, the gate dielectric layer 510 covers the entire side wall surface of the semiconductor column 400, the top surface of the semiconductor column 400, and the exposed portion of the first surface 101 of the substrate.
[0090] The material of the gate dielectric layer 510 includes but is not limited to silicon oxide, transition metal oxide or other high-K dielectric materials.
[0091] like Figure 2j As shown, a gate 520 is formed on the surface of the gate dielectric layer 510 located on the sidewall of the semiconductor column 400. The gate 520 surrounds the semiconductor column 400 and is isolated from the semiconductor column 400 by the gate dielectric layer 510. The gate 520, the gate dielectric layer 510 and the semiconductor column 400 formed with the groove 410 constitute a vertical channel transistor.
[0092] The material of the gate includes but is not limited to metal, metal nitride, metal silicide or silicon, etc. Metal includes but is not limited to tungsten, copper, silver, gold, aluminum, nickel, tantalum, titanium, cobalt, platinum, etc. Metal nitride includes but is not limited to tungsten nitride, titanium nitride, etc. Metal silicide includes but is not limited to titanium silicide, tantalum silicide, tungsten silicide, etc.
[0093] The height of the gate 520 along the vertical direction (eg, Z direction) may be equal to or less than the height of the semiconductor pillar 400 along the vertical direction. In this embodiment, the height of the gate 520 along the vertical direction is equal to the height of the semiconductor pillar 400 along the vertical direction. In other embodiments, for example Figure 6 In the embodiment, the height of the gate 520 along the vertical direction may also be smaller than the height of the semiconductor pillar 400 .
[0094] In some embodiments, the semiconductor pillar 400 may not be doped to form a junctionless transistor. In other embodiments, the semiconductor pillar may also be doped. Figure 5 and Figure 6 shows the doped semiconductor column, reference Figure 5 and Figure 6 , the manufacturing method further comprises:
[0095] Doping is performed into the semiconductor column 400 to form a first source-drain region 401 and a second source-drain region 402 that are spaced apart from each other; wherein the semiconductor column between the first source-drain region 401 and the second source-drain region 402 forms a channel region 403 .
[0096] For example, the semiconductor pillar 400 may be doped after step S200 and before step S300, that is, after the semiconductor pillar 400 is formed. For example, the semiconductor pillar 400 may be doped before step S500 and before step S700, that is, before the semiconductor pillar 400 is etched to form the groove 410 but before the gate 520 is formed.
[0097] The doping ions of the first source and drain regions 401 and the second source and drain regions 402 are of the same type, both of which are N-type doping ions or both of which are P-type doping ions. The undoped region between the first source and drain regions 401 and the second source and drain regions 402 forms a channel region 403. Alternatively, doping ions of a different type from that of the first source and drain region 101 may be doped between the first source and drain regions 401 and the second source and drain regions 402 to form a channel region 403.
[0098] like Figure 6 As shown, the height of the gate 520 along the vertical direction may also be smaller than the height of the semiconductor pillar 400 , and the gate 520 and the channel region 403 are disposed opposite to each other via the gate dielectric layer 510 .
[0099] In some embodiments, etching the sidewalls of the semiconductor column exposed in step S500 may specifically include: etching the sidewalls of the single crystal semiconductor column using an etching solution having different etching rates for multiple crystal planes of the single crystal semiconductor column; wherein the sidewalls of the single crystal semiconductor column have different crystal orientations so that the cross-sectional shapes of the annular recess perpendicular to the substrate are different.
[0100] Some etching solutions have different etching rates for different crystal planes of a single crystal, that is, anisotropic wet etching can be performed on the single crystal. When the crystal orientations of the sidewalls of the semiconductor pillar 400 are different, the anisotropic etching characteristics of such etching solutions can be used to form grooves 410 with different cross-sectional shapes, so that the sidewalls have different morphologies.
[0101] In some embodiments, the material of the single crystal semiconductor column 400 is single crystal silicon, and the etching solution is an alkaline solution. The alkaline solution may include an inorganic alkaline solution such as a potassium hydroxide (KOH) solution and a sodium hydroxide (NaOH) solution, and may also include an organic alkaline solution. The present disclosure embodiment is described using KOH as an example.
[0102] Figure 7 The figure shows the etching rates of different crystal planes of single crystal silicon by KOH solutions of three concentrations, where the horizontal axis is the angle between each crystal plane and the (110) crystal plane, and the vertical axis is the etching rate. Figure 7As shown in the figure, the KOH solution with a concentration of 3 mol / L (3M) has different etching rates for the (110), (331), (111), (211), (311) and (100) crystal planes, and the etching rate for the (111) crystal plane is the smallest. The KOH solutions with concentrations of 5 mol / L (5M) and 10 mol / L (10M) also have similar characteristics, that is, Figure 7 The multiple crystal planes shown have different etch rates.
[0103] In addition, different concentrations of KOH solution have different etching rates for some crystal planes. For example, 3M, 5M and 10M KOH solutions have different etching rates for the (100) crystal plane. In this way, the etching rate can be adjusted by adjusting the concentration of the KOH solution, making the etching rate of the KOH solution more controllable. In addition, the KOH solution has a relatively large etching selectivity for silicon and silicon nitride, and silicon nitride is hardly etched in the KOH solution. These two characteristics are that when the KOH solution etches single crystal silicon, the process fluctuation is small and the stability is high.
[0104] Figure 8a and Figure 8b An embodiment of etching a semiconductor column using a KOH solution is shown. Figure 8a Steps and formation Figure 2f The steps are the same as those of the embodiment of the present invention, but the difference is that the crystal orientation of the first surface 101 of the substrate 100 is different. The single crystal semiconductor pillar 400 grown by epitaxial growth will inherit the crystal orientation of the first surface 101 of the substrate. In this embodiment, the sidewall of the semiconductor pillar 400 is a (100) crystal plane. Figure 8b The steps of forming the groove are Figure 2g The same, but due to the different crystal orientations of the sidewalls of the semiconductor pillars, grooves 410 with different cross-sectional shapes can be formed. In this embodiment, the cross section of the groove 410 perpendicular to the substrate is a trapezoid. The trapezoid is an isosceles trapezoid, and the bottom of the trapezoid is parallel to the unetched sidewalls of the semiconductor pillar 400.
[0105] Figure 9a and Figure 9b Another embodiment of etching the semiconductor pillar using KOH solution is shown. The difference from the previous embodiment is that the crystal orientation of the first surface 101 of the substrate 100 is different, so that the crystal orientation of the side wall of the semiconductor pillar 400 is different. In this embodiment, the side wall of the semiconductor pillar 400 is a (111) crystal plane, and after etching with KOH solution, the cross section of the groove 410 perpendicular to the substrate is a triangle.
[0106] In other embodiments, other etching solutions may be used to etch the single crystal semiconductor pillar 400 to form Fig.10a and Fig.10b The groove 410 shown in FIG. 4 has a triangular cross section perpendicular to the substrate. Figure 9b compared to, Figure 9b The apex of the triangle faces the substrate 100, and Fig.10b The vertex of the middle triangle faces the side of the semiconductor pillar 400 away from the substrate 100 .
[0107] In some embodiments, Figure 2f and Figure 2g As shown, the cross section of the groove 410 perpendicular to the substrate 100 may also be arcuate, and the inner surface of the groove 410 is an arc-shaped inner surface.
[0108] The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure adopts an epitaxial growth process to prepare a single crystal semiconductor column, and uses an etching solution with different etching rates for different crystal planes of the single crystal semiconductor column. According to the different crystal planes of the side wall of the single crystal semiconductor column, a variety of embodiments can be produced. In different embodiments, the grooves on the side wall of the semiconductor column have different cross-sectional shapes, so that the relative area between the side wall and the gate increases to different degrees, and different cross-sectional shapes may produce different electron migration behaviors, thereby increasing the control ability of the gate over the channel to different degrees. In practical applications, suitable grooves can be selected according to the etching difficulty, etching effect, required parameters of the transistor, etc.
[0109] The present disclosure also provides a semiconductor structure, such as Figure 5 and Figure 6 As shown, the semiconductor structure includes: a substrate 100, a semiconductor column 400, a gate dielectric layer 510 and a gate 520; wherein the semiconductor column 400 is located on the first surface 101 of the substrate 100 and extends along the vertical direction, and the side wall of the semiconductor column 400 is formed with at least one groove 410 parallel to the first surface 101 of the substrate 100, and the vertical direction (for example, the Z direction) is perpendicular to the first surface 101; the gate dielectric layer 510 is located on the side wall surface of the semiconductor column 400 where the groove 410 is formed; and the gate 520 is located on the surface of the gate dielectric layer 510.
[0110] In this disclosure, Figure 5 and Figure 6 As shown, the gate dielectric layer 510 is located on the sidewall surface of the semiconductor pillar 400 , including the inner surface of the groove 410 where the gate dielectric layer 510 is located on the sidewall.
[0111] In the semiconductor structure provided by the embodiment of the present disclosure, the sidewall of the semiconductor column is formed with a groove parallel to the first surface of the substrate, and the groove makes the sidewall of the semiconductor column appear wavy in a cross-sectional view perpendicular to the substrate. Compared with the sidewall without a groove and in a straight line in a cross-sectional view perpendicular to the substrate, the sidewall with a groove can increase the contact area between the semiconductor column and the gate, thereby increasing the width of the channel region, so that the control ability of the gate over the channel region can be enhanced, which is conducive to reducing leakage current, and improving the efficiency of the transistor, thereby improving the chip operation efficiency.
[0112] In some embodiments, the gate 520 surrounds the sidewall of the semiconductor pillar 400 and is separated from the sidewall of the semiconductor pillar 400 by the gate dielectric layer 510, forming a ring-shaped gate. The ring-shaped gate can increase the control capability of the gate 520 over the channel region.
[0113] In some embodiments, the groove 410 surrounds the sidewall of the semiconductor column 400 to form an annular groove. The gate dielectric layer 510 surrounds the sidewall of the semiconductor column and contacts the sidewall of the semiconductor column 400, and the gate 520 is located on the surface of the gate dielectric layer 510 and surrounds the sidewall of the semiconductor column 400. The annular groove can increase the contact area between the annular gate and the channel region, thereby increasing the control ability of the gate over the channel region.
[0114] In some embodiments, the semiconductor column 400 includes a first source and drain region 401 , a channel region 403 , and a second source and drain region 402 arranged in sequence along a vertical direction, the channel region 403 is located between the first source and drain region 401 and the second source and drain region 402 , wherein the groove 410 is at least located in the channel region 403 .
[0115] In some embodiments, there are multiple grooves 403, and the multiple grooves 403 are arranged side by side in the vertical direction, and each groove 410 extends in a direction parallel to the first surface; wherein at least part of the multiple grooves 410 are located in the channel region 403. For example, Figure 5 As shown, the plurality of grooves 410 may be distributed in the first source and drain region 401, the channel region 403 and the second source and drain region 402. Figure 6 As shown, the plurality of grooves 410 may also be distributed only in the channel region 403 .
[0116] In some embodiments, the cross section of the groove 410 perpendicular to the first surface is one of a triangle, a trapezoid, and an arcuate shape. In the above-mentioned method for manufacturing the semiconductor trench structure, according to the crystal phase of the side wall of the semiconductor column, the anisotropic characteristics of the etching solution etching the crystal plane can be used to obtain a groove with a cross-sectional shape of a triangle, a trapezoid, or an arcuate shape.
[0117] In some embodiments, when a plurality of grooves 410 are arranged side by side along the sidewall of the semiconductor column, in a cross section of the semiconductor column perpendicular to the first surface, the sidewall of the semiconductor column 400 is wavy. The wavy sidewall can increase the contact area between the gate and the semiconductor column 400, thereby enhancing the control capability of the gate 520 over the channel region.
[0118] In some embodiments, the semiconductor pillar 400 is a single crystal semiconductor pillar. For example, the semiconductor pillar 400 is single crystal silicon.
[0119] In some embodiments, since the semiconductor pillar 400 is formed on the substrate by an epitaxial process, the crystal orientation of the first surface 101 of the semiconductor pillar 400 close to the substrate is the same as that of the first surface 101 of the substrate, that is, the semiconductor pillar inherits the crystal orientation of the first surface 101 of the substrate.
[0120] The transistor provided by the embodiment of the present disclosure can be applied to any chip to form a device in the chip. For example, an amplifier, a buffer, a decoder, etc. can be formed. The leakage current of the transistor is small and the gate has a strong control ability over the channel, which can improve the performance and operating efficiency of the device, thereby improving the performance and operating efficiency of the chip. In addition, the transistor can also be applied to memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), etc., which can reduce the leakage current of the storage unit and improve storage performance. The semiconductor structure provided by the embodiment of the present disclosure can be any chip or other device including a transistor.
[0121] The above embodiments are merely illustrative of the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present disclosure shall still be covered by the claims of the present disclosure.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: Forming a stacking structure on the first surface of the substrate; the stacking structure includes a first sacrificial layer and a second sacrificial layer alternately stacked; forming a semiconductor column penetrating the stacked structure and contacting the substrate; forming a groove in the stack structure, wherein the sidewall of the groove exposes each of the second sacrificial layers; Etching each of the second sacrificial layers through the trenches until the sidewalls of the semiconductor pillars are exposed; Etching the exposed sidewall of the semiconductor column to form a groove on the exposed sidewall surface of the semiconductor column; removing the first sacrificial layer from the sidewall of the semiconductor column; A gate dielectric layer and a gate are sequentially formed on the sidewalls of the semiconductor column.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The forming of a semiconductor column penetrating the stacked structure and contacting the substrate comprises: forming a hole penetrating the stacked structure and exposing the substrate; A single crystal semiconductor column is formed in the hole by using an epitaxial growth process.
3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The etching of the semiconductor pillar to reveal the sidewalls includes: The sidewall of the single crystal semiconductor column is etched by using an etching solution having different etching rates for multiple crystal planes of the single crystal semiconductor column; wherein the sidewall of the single crystal semiconductor column has different crystal orientations so that the cross-sectional shapes of the groove perpendicular to the substrate are different.
4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: The material of the single crystal semiconductor column is single crystal silicon, and the etching solution is an alkaline solution.
5. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: A cross section of the groove perpendicular to the first surface is in the shape of a triangle, a trapezoid, or an arcuate shape.
6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The manufacturing method further comprises: Doping is performed into the semiconductor column to form a first source-drain region and a second source-drain region that are spaced apart from each other; wherein the semiconductor column between the first source-drain region and the second source-drain region forms a channel region.
7. A semiconductor structure, characterized in that: include: substrate; A semiconductor column, located on the first surface of the substrate and extending in a vertical direction, wherein a sidewall of the semiconductor column is formed with at least one groove parallel to the first surface of the substrate; the vertical direction is perpendicular to the first surface; A gate dielectric layer, located on the sidewall surface of the semiconductor column where the groove is formed; The gate is located on the surface of the gate dielectric layer.
8. The semiconductor structure according to claim 7, characterized in that: A cross section of the groove perpendicular to the first surface is in the shape of a triangle, a trapezoid, or an arcuate shape.
9. The semiconductor structure according to claim 7, characterized in that: In a cross section of the semiconductor column perpendicular to the first surface, a sidewall of the semiconductor column is wavy.
10. The semiconductor structure according to claim 7, characterized in that: The semiconductor column is a single crystal semiconductor column.