Method of fabricating an ldmos device

Abstract

The application discloses a manufacturing method of an LDMOS device, which comprises the following steps: providing a substrate, wherein a region of the substrate for forming a semiconductor device comprises a first region and a second region, the first region is used for forming a memory cell device, and the second region is used for forming an LDMOS device; forming a first dielectric layer on the substrate; forming a second dielectric layer on the first dielectric layer; forming a first groove in the first dielectric layer, the second dielectric layer and the substrate; forming a second groove in the first dielectric layer, the second dielectric layer and the substrate of the second region, the second groove comprises a first sub-region and a second sub-region, the second sub-region is communicated with the first groove in the second region, and the second sub-region and the communicated first groove form a field plate groove; filling a third dielectric layer in the first groove and the second groove, and the third dielectric layer filled in the field plate groove forms a field plate of the LDMOS device; removing the second dielectric layer; forming a doped region of the LDMOS device in the substrate below the field plate; and forming a gate of the LDMOS device above the field plate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and particularly relates to a manufacturing method of an LDMOS device. BACKGROUND

[0002] In non-volatile memory (NVM), or NOR flash, is developed based on the tunnel oxide programmable read-only memory (ETOX) structure proposed by Intel Corporation, which uses hot electron injection to write data and erases data based on tunneling effect. The significant feature is that the random read speed is very fast. As a kind of NVM memory, NOR flash has the characteristics of high device density, low power consumption and electrical re-writability, and is widely used in electronic products with storage function such as smart phones, tablet computers, digital cameras, universal serial bus flash disks (USB flash disks, referred to as "U disks") and the like.

[0003] Due to market demand, it is usually necessary to integrate memory cell devices, power devices and logic devices on the same wafer, so it is a common choice to integrate a lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET, referred to as "LDMOS" in the present application) device in the manufacturing process of NOR flash.

[0004] The LDMOS device usually sets a multi-layer field plate or a step-type field plate near the drain side of the gate, which can effectively reduce the bulk electric field peak value in the reverse blocking state, and can improve the doping concentration of the drift region as much as possible under the premise of ensuring that the breakdown voltage meets the requirements, thereby reducing the on-resistance of the device. However, the multi-layer field plate structure is often complex in manufacturing process, and additional processes are needed to form. SUMMARY

[0005] The present application provides a manufacturing method of an LDMOS device, which can solve the problem of high manufacturing cost caused by the need for additional mask plates to form a step-type field plate in the manufacturing method of the LDMOS provided in the related art. The method comprises:

[0006] A substrate is provided, wherein the regions on the substrate for forming semiconductor devices include a first region and a second region, the first region is used to form a memory cell device, the second region is used to form an LDMOS device, a first dielectric layer is formed on the substrate, and a second dielectric layer is formed on the first dielectric layer, wherein the first dielectric layer and the second dielectric layer are made of different materials.

[0007] A first trench is formed in the first dielectric layer, the second dielectric layer, and the substrate;

[0008] A second trench is formed in the first dielectric layer, the second dielectric layer, and the substrate in the second region. The depth of the second trench is different from the depth of the first trench. The second trench includes a first sub-region and a second sub-region. The second sub-region is connected to the first trench in the second region. The second sub-region and the first trench connected to it constitute a field plate trench.

[0009] A third dielectric layer is filled in the first trench and the second trench. The third dielectric layer filled in the first trench of the first region forms the STI structure of the memory cell device. The third dielectric layer filled in the field plate trench forms the field plate of the LDMOS device. The constituent material of the third dielectric layer is the same as that of the first dielectric layer.

[0010] Remove the second dielectric layer;

[0011] The doped region of the LDMOS device is formed in the substrate below the field plate, and the gate of the LDMOS device is formed above the field plate.

[0012] In some embodiments, forming a doped region for an LDMOS device in the substrate under the field plate and forming a gate for an LDMOS device on the field plate includes:

[0013] A first doped region is formed in the substrate beneath the field plate;

[0014] A second doped region is formed in the substrate below the field plate. The second doped region is laterally located on one side of the first doped region. The conductivity type of the impurities doped in the second doped region is different from that of the impurities doped in the first doped region.

[0015] The gate of an LDMOS device is formed on the field plate;

[0016] A first heavily doped region and a second heavily doped region are formed in the substrate on both sides of the gate. The first heavily doped region is located in the second doped region, and the second heavily doped region is located in the first doped region. The conductivity type of the impurities doped in the first heavily doped region is the same as that of the impurities doped in the second heavily doped region.

[0017] A third doped region is formed in the second doped region, wherein the conductivity type of the impurities doped in the third doped region is different from that of the impurities doped in the first doped region.

[0018] In some embodiments, the first doped region is a drift region, the second doped region is a well region, and the depth of the first doped region is greater than that of the second doped region.

[0019] In some embodiments, forming the gate of the LDMOS device on the field plate includes:

[0020] A polycrystalline silicon layer is formed on the first dielectric layer;

[0021] Remove the first dielectric layer and polysilicon layer from all regions except the first target region, and the remaining first dielectric layer forms the gate dielectric layer of the LDMOS device;

[0022] The polysilicon layer in all regions except the second target region is removed, and the remaining polysilicon layer forms the gate. The length of the gate in the lateral direction is less than the sum of the lengths of the gate dielectric layer and the field plate.

[0023] In some embodiments, the first dielectric layer and the third dielectric layer comprise a silicon dioxide layer.

[0024] In some embodiments, the second dielectric layer includes a silicon nitride layer.

[0025] The technical solution of this application has at least the following advantages:

[0026] In the fabrication process of LDMOS devices, a first trench and a second trench are formed sequentially in the substrate. The first trench and the second trench in the second region are connected to form a stepped field plate trench. Then, a dielectric layer is filled in the field plate trench to form the field plate of the LDMOS device. Since the first trench can be formed by a mask of the STI structure of the memory cell device and the second trench can be formed by a mask of the STI structure of the LDMOS device, it is not necessary to design an additional mask to form a stepped field plate. At the same time, the process is relatively simple, thereby reducing manufacturing costs and process complexity. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0028] Figure 1 This is a flowchart illustrating a method for fabricating an LDMOS device according to an exemplary embodiment of this application;

[0029] Figures 2 to 6 This is a schematic diagram illustrating the fabrication process of an LDMOS device provided in an exemplary embodiment of this application. Detailed Implementation

[0030] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0032] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0033] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0034] refer to Figure 1It illustrates a flowchart of a method for fabricating an LDMOS device according to an exemplary embodiment of this application, such as... Figure 1 As shown, the method includes:

[0035] Step S1: A substrate is provided. The substrate has a first region and a second region for forming semiconductor devices. The first region is used to form a memory cell device, and the second region is used to form an LDMOS device. A first dielectric layer is formed on the substrate, and a second dielectric layer is formed on the first dielectric layer. The first dielectric layer and the second dielectric layer are made of different materials.

[0036] Step S2: A first trench is formed in the first dielectric layer, the second dielectric layer, and the substrate.

[0037] refer to Figure 2 It shows a cross-sectional schematic diagram after a first trench is formed in the first dielectric layer, the second dielectric layer, and the substrate. For example... Figure 2 As shown, the regions on the substrate 210 used for forming semiconductor devices include a first region 201 and a second region 202. The first region 201 is used to form a memory cell device, and the second region 202 is used to form an LDMOS device. A first dielectric layer 221 is formed on the substrate 210, and a second dielectric layer 231 is formed on the first dielectric layer 221. The first dielectric layer 221 and the second dielectric layer 231 are made of different materials. The first dielectric layer 221 may include a silicon dioxide (SiO2) layer, and the second dielectric layer 231 includes a silicon nitride (Si3N4) layer.

[0038] For example, photoresist can be coated on the second dielectric layer 231. Figure 2 (Not shown in the image) After exposure through the first mask, development is performed to expose the target area (the area corresponding to the first trench). Etching is then performed to form the first trench in the first dielectric layer 221, the second dielectric layer 231, and the substrate 210. The first trench 3011 in the first region 201 is used to form the shallow trench isolation (STI) structure of the memory cell device, and the first trench 3012 in the second region 202 is used to form a portion of the field plate trench.

[0039] Step S3: A second trench is formed in the first dielectric layer, the second dielectric layer, and the substrate in the second region. The depth of the second trench is different from the depth of the first trench. The second trench includes a first sub-region and a second sub-region. The second sub-region is connected to the first trench in the second region. The second sub-region and the first trench connected to it constitute a field plate trench.

[0040] refer to Figure 3 The diagram shows a cross-sectional view after the second trench has been formed. For example, as shown... Figure 2As shown, photoresist can be coated on the second dielectric layer 231. Figure 3 (Not shown in the image) After exposure through a second mask, development is performed to expose the target area (the area corresponding to the second trench). Etching is then performed to form a second trench in the first dielectric layer 221, the second dielectric layer 231, and the substrate 210 of the second region 201. The second trench includes a first sub-region 3021 and a second sub-region 3022. The second sub-region 3022 is connected to the first trench 3012 in the second region 201. The second sub-region 3022 and the connected first trench 3012 constitute a field plate trench. The first trench and the second trench have different depths, resulting in a stepped cross-section for the field plate trench. It should be noted that... Figures 2 to 6 The example provided illustrates that the depth of the second trench is greater than the depth of the first trench. In practical applications, the depth of the second trench can also be set to be shallower than the depth of the first trench.

[0041] Step S4: A third dielectric layer is filled in the first trench and the second trench. The third dielectric layer filled in the first trench of the first region forms the STI structure of the memory cell device, and the third dielectric layer filled in the field plate trench forms the field plate of the LDMOS device. The constituent material of the third dielectric layer is the same as that of the first dielectric layer.

[0042] refer to Figure 4 The diagram illustrates a cross-sectional view after a third dielectric layer has been filled into the first and second trenches. Exemplarily, the third dielectric layer may include a silicon dioxide layer, such as... Figure 4 As shown, a silicon dioxide layer can be deposited to fill the first trench and the second trench using a chemical vapor deposition (CVD) process. The silicon dioxide layer outside the first trench and the second trench can be removed by a planarization process (e.g., chemical mechanical polishing (CMP) process). The silicon dioxide layer in the first trench 3011 in the first region 201 constitutes the STI structure 211 of the memory cell device. The silicon dioxide layer in the isolation trench constitutes the field plate 212 of the LDMOS device. The field plate 212 and the silicon dioxide layer 213 in the first sub-region 3021 constitute the isolation structure of the LDMOS device.

[0043] Step S5: Remove the second dielectric layer.

[0044] Step S6: A doped region of the LDMOS device is formed in the substrate below the field plate, and a gate of the LDMOS device is formed above the field plate.

[0045] For example, step S6 includes, but is not limited to: forming a first doped region in the substrate below the field plate; forming a second doped region in the substrate below the field plate, the second doped region being laterally located on one side of the first doped region, the conductivity type of the impurities doped in the second doped region being different from the conductivity type of the impurities doped in the first doped region; forming the gate of the LDMOS device on the field plate; forming a first heavily doped region and a second heavily doped region in the substrates on both sides of the gate, the first heavily doped region being located within the second doped region, the second heavily doped region being located within the first doped region, the conductivity type of the impurities doped in the first heavily doped region being the same as the conductivity type of the impurities doped in the second heavily doped region, and the conductivity type of the impurities doped in the first heavily doped region being the same as the conductivity type of the impurities doped in the first doped region; forming a third heavily doped region in the second doped region, the conductivity type of the impurities doped in the third heavily doped region being different from the conductivity type of the impurities doped in the first heavily doped region.

[0046] refer to Figure 5 It shows a schematic cross-sectional view after the formation of the first and second doped regions. For example, as shown... Figure 5 As shown, the second dielectric layer 231 can be removed by wet etching, and then ion implantation can be performed by photolithography to form a first doped region 216 in the substrate 210 below the field plate 212 and a second doped region 214 in the substrate 210 below the field plate 212. The first doped region 216 is a drift region and the second doped region 214 is a well region. The depth of the first doped region 216 is greater than that of the second doped region 214.

[0047] refer to Figure 6 This illustrates a schematic cross-sectional view after the formation of the heavily doped region and the gate. For example, such as... Figure 6 As shown, a polysilicon layer can be formed on the first dielectric layer 221; after removing the first dielectric layer 221 and the polysilicon layer in areas other than the first target area, the remaining first dielectric layer 221 forms the gate dielectric layer of the LDMOS device; after removing the polysilicon layer in areas other than the second target area, the remaining polysilicon layer forms the gate 233, and the length of the gate 233 in the lateral direction is less than the sum of the lengths of the gate dielectric layer and the field plate; ion implantation is performed by photolithography to form the first [unclear] in the substrate 210 on both sides of the gate 233. The first doped region 2151 and the second doped region 2152 are formed by photolithography-based ion implantation to create a third doped region 2153 in the second doped region 214. The impurity concentrations in the first doped region 2151, the second doped region 2152, and the third doped region 2153 are greater than those in other doped regions. The first doped region 2151 and the third doped region 2153 are located in the second doped region 214 and on both sides of the STI structure 213. The second doped region 2152 is located in the first doped region 216.

[0048] In this embodiment, if the impurities doped in the first doped region 216, the first heavily doped region 2151, and the second heavily doped region 2152 are N-type (negative) impurities, then the impurities doped in the second doped region 214 and the third heavily doped region 2153 are P-type (positive) impurities; if the impurities doped in the first doped region 216, the first heavily doped region 2151, and the second heavily doped region 2152 are P-type impurities, then the impurities doped in the second doped region 214 and the third heavily doped region 2153 are N-type impurities.

[0049] In summary, in the embodiments of this application, by forming a first trench and a second trench sequentially in the substrate during the fabrication of the LDMOS device, the first trench and the second trench in the second region are connected to form a stepped field plate trench, and then a dielectric layer is filled in the field plate trench to form the field plate of the LDMOS device. Since the first trench can be formed by a mask of the STI structure of the memory cell device, and the second trench can be formed by a mask of the STI structure of the LDMOS device, it is not necessary to design an additional mask to form a stepped field plate. At the same time, the process is relatively simple, thereby reducing manufacturing costs and process complexity.

[0050] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating an LDMOS device, characterized in that, include: A substrate is provided, wherein the regions on the substrate for forming semiconductor devices include a first region and a second region, the first region is used to form a memory cell device, the second region is used to form an LDMOS device, a first dielectric layer is formed on the substrate, and a second dielectric layer is formed on the first dielectric layer, wherein the first dielectric layer and the second dielectric layer are made of different materials. A first trench is formed in the first dielectric layer, the second dielectric layer, and the substrate; A second trench is formed in the first dielectric layer, the second dielectric layer, and the substrate in the second region. The depth of the second trench is different from the depth of the first trench. The second trench includes a first sub-region and a second sub-region. The second sub-region is connected to the first trench in the second region. The second sub-region and the first trench connected to it constitute a field plate trench. A third dielectric layer is filled in the first trench and the second trench. The third dielectric layer filled in the first trench of the first region forms the STI structure of the memory cell device. The third dielectric layer filled in the field plate trench forms the field plate of the LDMOS device. The constituent material of the third dielectric layer is the same as that of the first dielectric layer. Remove the second dielectric layer; The doped region of the LDMOS device is formed in the substrate below the field plate, and the gate of the LDMOS device is formed above the field plate.

2. The method according to claim 1, characterized in that, The process of forming a doped region for an LDMOS device in the substrate under the field plate and forming the gate of an LDMOS device on the field plate includes: A first doped region is formed in the substrate beneath the field plate; A second doped region is formed in the substrate below the field plate. The second doped region is laterally located on one side of the first doped region. The conductivity type of the impurities doped in the second doped region is different from that of the impurities doped in the first doped region. The gate of an LDMOS device is formed on the field plate; A first heavily doped region and a second heavily doped region are formed in the substrate on both sides of the gate. The first heavily doped region is located in the second doped region, and the second heavily doped region is located in the first doped region. The conductivity type of the impurities doped in the first heavily doped region is the same as that of the impurities doped in the second heavily doped region. A third doped region is formed in the second doped region, wherein the conductivity type of the impurities doped in the third doped region is different from that of the impurities doped in the first doped region.

3. The method according to claim 2, characterized in that, The first doped region is a drift region, and the second doped region is a well region. The depth of the first doped region is greater than that of the second doped region.

4. The method according to claim 2, characterized in that, The formation of the gate of the LDMOS device on the field plate includes: A polycrystalline silicon layer is formed on the first dielectric layer; Remove the first dielectric layer and polysilicon layer from all regions except the first target region, and the remaining first dielectric layer forms the gate dielectric layer of the LDMOS device; The polysilicon layer in all regions except the second target region is removed, and the remaining polysilicon layer forms the gate. The length of the gate in the lateral direction is less than the sum of the lengths of the gate dielectric layer and the field plate.

5. The method according to any one of claims 1 to 4, characterized in that, The first dielectric layer and the third dielectric layer comprise silicon dioxide layers.

6. The method according to claim 5, characterized in that, The second dielectric layer includes a silicon nitride layer.

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