High electron mobility transistor
By setting a conduction band step with different material at the interface between the source and channel layer of the GaN-based high electron mobility transistor and introducing a specific layer structure into the heterojunction structure layer, the problem of carrier density reduction is solved, and a GaN-based HEMT device with high frequency and high power performance is achieved.
Patent Information
- Application Number
- CN202510226369.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-27
- Publication Date
- 2025-05-16
AI Technical Summary
In the process of optimizing carrier mobility, existing GaN-based high electron mobility transistors lead to a decrease in carrier density, limiting the power characteristics of the device.
By providing different materials on both sides of the interface in which the source and the channel layer, a conduction band step is formed, providing additional kinetic energy, improving the injection efficiency of the two-dimensional electron gas, and introducing an insertion layer, a barrier layer and a cap layer into the heterojunction structure layer to optimize electron transport.
It effectively improves the channel carrier mobility, and has a small impact on the two-dimensional electron air density, achieving high-frequency and high-power performance GaN-based HEMT devices.
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Figure CN120018544A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of semiconductor transistors, and in particular to a high electron mobility transistor. Background Art
[0002] As a third-generation semiconductor, GaN-based materials have attracted widespread attention due to their adjustable wide bandgap, high breakdown electric field, and high saturation velocity. High Electron Mobility Transistor (HEMT) made from GaN-based materials has excellent high-frequency and high-power characteristics and is the core device of millimeter-wave low-noise amplifiers.
[0003] In order to cope with the influence of the intrinsic delay of the two-dimensional electron gas (2DEG) in the channel under the gate of GaN-based HEMT and the parasitic delay of the 2DEG in the channel access area on both sides of the gate, the current optimization is mainly carried out by changing the polarization effect, optimizing the epitaxial structure design, and improving the material crystal quality. However, this method will lead to a decrease in carrier density, thereby restricting the power characteristics of the device. Summary of the invention
[0004] In view of the above problems, an embodiment of the present disclosure provides a high electron mobility transistor.
[0005] One aspect of the present disclosure provides a high electron mobility transistor, comprising: a substrate. A heterojunction structure layer, arranged on one side of the substrate. A gate, arranged on a side of the heterojunction structure layer away from the substrate. A source, arranged on one side of the gate, and at least partially embedded in the heterojunction structure layer. A drain, arranged on a side of the gate away from the source, and at least partially embedded in the heterojunction structure layer. The heterojunction structure layer includes a channel layer, the channel layer is used to provide a transmission channel for a two-dimensional electron gas, the materials on both sides of the interface where the source electrode contacts the channel layer are different, and the bandgap width of the material on the side where the source electrode is located is greater than the bandgap width of the material on the side where the channel layer is located, forming a conduction band step.
[0006] According to an embodiment of the present disclosure, the source electrode includes: an auxiliary electron injection layer, which is arranged on a side of the heterojunction structure layer away from the substrate and at least partially embedded in the heterojunction structure layer. A first metal layer is arranged on a side of the auxiliary electron injection layer away from the substrate. The auxiliary electron injection layer is an n-type doped group III nitride material, and the group III nitride materials include: GaN, InN, AlN, InGaN, AlGaN, InAlN and AlGaInN. The materials of the channel layer include: GaN and InGaN.
[0007] According to an embodiment of the present disclosure, the heterojunction structure layer further includes: at least one of an insertion layer, a barrier layer and a cap layer arranged in sequence. The insertion layer is located on the side of the channel layer away from the substrate, the insertion layer is used to reduce interlayer stress and electron scattering, the barrier layer is used to provide a polarization effect to form a two-dimensional electron gas at the interface of the channel layer away from the substrate, and the cap layer is used to protect the barrier layer and provide a passivation effect.
[0008] According to an embodiment of the present disclosure, the drain includes: an ohmic contact layer, which is arranged on a side of the heterojunction structure layer away from the substrate and at least partially embedded in the heterojunction structure layer. A second metal layer is arranged on a side of the ohmic contact layer away from the substrate. The ohmic contact layer is an n-type doped GaN-based material, and the n-type doped GaN-based material includes: Si or Ge-doped GaN, InGaN and AlGaN. Or a third metal layer is arranged on a side of the heterojunction structure layer away from the substrate and at least partially embedded in the heterojunction structure layer.
[0009] According to an embodiment of the present disclosure, the high electron mobility transistor further includes: a buffer layer, which is disposed between the substrate and the heterojunction structure layer, and the thickness of the buffer layer is 0 nm to 500 μm.
[0010] According to an embodiment of the present disclosure, at least one of the source electrode and the drain electrode is not in contact with the buffer layer.
[0011] According to an embodiment of the present disclosure, a surface of at least one of the auxiliary electron injection layer and the ohmic contact layer that is away from the substrate is higher than a surface of the heterojunction structure layer that is away from the substrate.
[0012] According to an embodiment of the present disclosure, at least one of the auxiliary electron injection layer and the ohmic contact layer has a thickness of 0 nm to 100 μm.
[0013] According to an embodiment of the present disclosure, the thickness of the channel layer is 0 nm to 100 μm, and the thickness of at least one of the insertion layer, the barrier layer, and the cap layer is 0 nm to 50 nm.
[0014] According to an embodiment of the present disclosure, the gate includes: a first part and a second part, the second part is arranged on a side of the heterojunction structure layer away from the substrate, and the first part is arranged on a side of the second part away from the substrate. The projection area of the first part on the substrate is greater than or equal to the projection area of the second part on the substrate.
[0015] The present disclosure proposes a transistor that improves the carrier drift rate in a non-polarized manner, which effectively improves the channel carrier mobility while having little effect on the density of the two-dimensional electron gas. By arranging different materials on both sides of the interface where the source and the channel layer are in contact, and the bandgap width of the source side material is greater than the bandgap width of the channel layer side material, there is a conduction band step between the source and the channel layer, which can provide additional kinetic energy for the electrons of the source, and accelerate the injected electrons flowing from the source to the two-dimensional electron gas of the channel layer, so that the speed of the electrons is close to the saturation speed of the electrons, thereby reducing the intrinsic delay of the gallium nitride-based high electron mobility transistor when it is working, etc., so that a GaN-based HEMT device with high-frequency and high-power performance can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:
[0017] Figure 1 Schematically shows a cross-sectional structure diagram of a high electron mobility transistor according to an embodiment of the present disclosure;
[0018] Figure 2 The cross-sectional structure of a high electron mobility transistor according to another embodiment of the present disclosure is schematically shown.
[0019] [Description of Reference Numerals]
[0020] 1-substrate; 2-heterojunction structure layer; 21-channel layer; 22-insertion layer; 23-barrier layer; 24-cap layer; 3-gate; 31-first part; 32-second part; 4-source; 41-auxiliary electron injection layer; 42-first metal layer; 5-drain; 51-ohmic contact layer; 52-second metal layer; 6-buffer layer. DETAILED DESCRIPTION
[0021] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.
[0022] It should be noted that in the drawings or descriptions, similar or identical parts use the same figure numbers. The technical features in the various embodiments exemplified in the specification can be freely combined to form a new solution without conflict. In addition, each claim can be used as an embodiment alone or the technical features in each claim can be combined as a new embodiment. In the drawings, the shape or thickness of the embodiment can be expanded and simplified or conveniently indicated. Furthermore, the elements or implementations not shown or described in the drawings are in a form known to a person of ordinary skill in the art. In addition, although demonstrations of parameters containing specific values may be provided herein, it should be understood that the parameters do not need to be exactly equal to the corresponding values, but can be approximated to the corresponding values within an acceptable error tolerance or design constraint.
[0023] Unless there are technical obstacles or contradictions, the above-mentioned various embodiments of the present disclosure can be freely combined to form additional embodiments, and these additional embodiments are all within the protection scope of the present disclosure.
[0024] Although the present disclosure is described in conjunction with the accompanying drawings, the embodiments disclosed in the accompanying drawings are intended to exemplify the preferred embodiments of the present disclosure and should not be construed as limiting the present disclosure. The dimensional ratios in the accompanying drawings are merely illustrative and should not be construed as limiting the present disclosure.
[0025] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.
[0026] Figure 1 The cross-sectional structure of a high electron mobility transistor according to an embodiment of the present disclosure is schematically shown.
[0027] According to the embodiments of the present disclosure, Figure 1 As shown, the present disclosure provides a high electron mobility transistor, comprising: a substrate 1. A heterojunction structure layer 2, which is arranged on one side of the substrate 1. A gate 3, which is arranged on a side of the heterojunction structure layer 2 away from the substrate 1. A source 4, which is arranged on one side of the gate 3 and is at least partially embedded in the heterojunction structure layer 2. A drain 5, which is arranged on a side of the gate 3 away from the source 4 and is at least partially embedded in the heterojunction structure layer 2. The heterojunction structure layer 2 includes a channel layer 21, which is used to provide a transmission channel for a two-dimensional electron gas, and the materials on both sides of the interface where the source 4 contacts the channel layer 21 are different, and the bandgap width of the material on the side where the source 4 is located is greater than the bandgap width of the material on the side where the channel layer 21 is located, forming a conduction band step.
[0028] In some embodiments, the substrate serves as the basic support structure of the transistor, providing the necessary mechanical and thermal stability.
[0029] For example, the material type of the substrate includes but is not limited to one or more of SiC, sapphire, Si, and GaN. This provides more possibilities for the device, and a suitable substrate can be selected according to specific application requirements. The substrate can better control the growth of other layers, reduce defects and impurities, and improve quality. At the same time, the stress distribution of other layers can also be optimized, stress concentration can be reduced, and the stability and reliability of the device can be improved.
[0030] The heterojunction structure layer is arranged on one side of the substrate. This layer is the core part of the transistor and is used to form and control the transmission of the two-dimensional electron gas.
[0031] The gate is arranged on a side of the heterojunction structure layer away from the substrate, and controls the concentration and transmission characteristics of the two-dimensional electron gas in the channel layer by applying a voltage.
[0032] For example, the gate may be disposed in a groove on the upper surface of the heterojunction structure layer, or directly disposed on the upper surface of the heterojunction structure layer.
[0033] The source electrode is arranged on one side of the gate electrode and is at least partially embedded in the heterojunction structure layer. The materials on both sides of the interface where the source electrode contacts the channel layer are different. In particular, the bandgap width of the material on the side where the source electrode is located is higher than the bandgap width of the material on the side where the channel layer is located (that is, the conduction band energy of the material on the source electrode side is higher), so that a conduction band step is formed between the source electrode and the channel layer. This design helps to optimize the injection efficiency of the two-dimensional electron gas and the working performance of the transistor.
[0034] The drain electrode is arranged on a side of the gate electrode away from the source electrode and is also at least partially embedded in the heterojunction structure layer. The drain electrode and the channel layer form a conductive channel so that the two-dimensional electron gas can be transmitted between the source electrode and the drain electrode.
[0035] For example, the source electrode and the drain electrode may be respectively disposed at two side edges of the heterojunction structure layer away from the gate electrode and symmetrically relative to the gate electrode.
[0036] In this embodiment, the transistor provides a transmission channel for the two-dimensional electron gas through the channel layer in the heterojunction structure layer, and optimizes the injection efficiency of the two-dimensional electron gas and the working performance of the transistor by designing the bandgap width of different materials on both sides of the interface between the source and the channel layer. This design helps to improve the current driving capability and switching speed of the transistor, thereby meeting the needs of high-performance electronic devices.
[0037] According to the embodiments of the present disclosure, Figure 1As shown, the source 4 includes, for example: an auxiliary electron injection layer 41, which is arranged on the side of the heterojunction structure layer 2 away from the substrate 1 and at least partially embedded in the heterojunction structure layer 2. A first metal layer 42 is arranged on the side of the auxiliary electron injection layer 41 away from the substrate 1. The auxiliary electron injection layer 41 is an n-type doped group III nitride material, and the group III nitride material includes: GaN, InN, AlN, InGaN, AlGaN, InAlN and AlGaInN. The material of the channel layer 21 includes: GaN and InGaN.
[0038] In some embodiments, the substrate, the heterojunction structure layer, the gate and the drain may be the same as those in the above embodiments, for example.
[0039] The auxiliary electron injection layer is arranged on the side of the heterojunction structure layer away from the substrate and is at least partially embedded in the heterojunction structure layer. The main function of this layer is to promote the effective injection of two-dimensional electron gas from the heterojunction structure layer to the source electrode.
[0040] In this embodiment, the auxiliary electron injection layer is, for example, made of n-type doped group III nitride materials, such as GaN, InN, AlN, InGaN, AlGaN, InAlN or AlGaInN. These materials have good electron transport properties and chemical stability, and are suitable for building high-performance transistors. At the same time, the material of the channel layer can be, for example, GaN and InGaN.
[0041] It should be noted that in order to form a positive conduction band step difference at the interface where the source electrode contacts the channel layer, it is necessary to keep the materials on both sides of the interface different. For example, when the channel layer is made of InGaN, the auxiliary electron injection layer can be made of other materials except InGaN. When the channel layer is made of GaN, the auxiliary electron injection layer can be made of other materials except GaN and InGaN.
[0042] For example, the auxiliary electron injection layer is a regrown high-concentration n-type doped AlGaN material, the doping element of which can be Si or Ge, with a doping concentration of 1×10 12 cm -2 ~1×10 21 cm -2 In some embodiments, for example, it may be 1e15 cm -3 ~1e20cm -3 The selection of this concentration range provides greater flexibility for the auxiliary electron injection layer, and the appropriate concentration can be selected according to actual needs to optimize the specific or main performance of the device.
[0043] The first metal layer is arranged on the side of the auxiliary electron injection layer away from the substrate. This layer mainly serves to connect with the external circuit and transmit the electrical signal generated inside the transistor. The first metal layer can be made of metal materials such as copper, aluminum, gold or silver.
[0044] For example, a first metal layer is deposited on the auxiliary electron injection layer. The material type of the first metal layer includes but is not limited to alloys such as Ti / Au, Al / Au, Ti / Al / Ti / Au, and Ti / Al / Ni / Au. The first metal layer forms an ohmic contact with the auxiliary electron injection layer below.
[0045] As the main current output electrode of the transistor, the first metal layer can realize efficient and stable current transmission, and export electrons from the inside of the transistor and transmit them to the external circuit. At the same time, as the connection point between the transistor and the external circuit, the first metal layer can realize the effective integration of the transistor and the external circuit.
[0046] This embodiment optimizes the structure of the source electrode and introduces an auxiliary electron injection layer and a first metal layer. This layer uses n-type doped group III nitride material, which can effectively promote the injection of two-dimensional electron gas from the heterojunction structure layer to the source electrode, thereby improving the current driving capability and working performance of the transistor. The setting of the first metal layer ensures the effective connection between the transistor and the external circuit and realizes the transmission of electrical signals. This optimized transistor structure has broad application prospects in the field of high-performance electronic devices.
[0047] According to the embodiments of the present disclosure, Figure 1 As shown, the heterojunction structure layer 2 further includes: at least one of an insertion layer 22, a barrier layer 23 and a cap layer 24 which are arranged in sequence. The insertion layer 22 is located on the side of the channel layer 21 away from the substrate 1, and the insertion layer 22 is used to reduce interlayer stress and electron scattering. The barrier layer 23 is used to provide a polarization effect to form a two-dimensional electron gas at the interface of the channel layer 21 away from the substrate 1. The cap layer 24 is used to protect the barrier layer 23 and provide a passivation effect.
[0048] In some embodiments, the heterojunction structure layer can provide an effective electron transmission channel. In a gallium nitride high electron mobility transistor with a heterojunction structure layer, electrons are mainly transmitted in the channel layer. By optimizing the material and energy level structure of the channel layer, the electron transport behavior can be controlled to achieve efficient electron injection and collection. The barrier layer plays the role of modulating the electric field in the heterojunction structure layer. By adjusting the thickness of the barrier layer, the electric field distribution can be changed, further affecting the electron transmission behavior. The insertion layer can improve the interface quality between the channel layer and the barrier layer, reduce the interface state density, and reduce the impact of interface scattering on electron transmission, thereby improving the performance and stability of the transistor.
[0049] The channel layer is located at the core of the heterojunction structure layer and is used to provide a transmission channel for the two-dimensional electron gas. The material of the channel layer may include but is not limited to GaN and InGaN, etc. These materials have good electron mobility and chemical stability.
[0050] The insertion layer is located on the side of the channel layer away from the substrate. The main function of the insertion layer is to provide a part of the polarization effect, while reducing interlayer stress and electron scattering, improving mobility, and thus improving the performance and stability of the transistor. The insertion layer can be made of a semiconductor material that is similar to the channel layer material but has specific properties. The material types of the insertion layer include, but are not limited to, AlN, SiN, and InN.
[0051] The barrier layer is located on the side of the insertion layer (if present) or the channel layer (if no insertion layer) away from the substrate. The main function of the barrier layer is to provide piezoelectric polarization and spontaneous polarization effects, thereby forming one or more two-dimensional electron gas channels at the interface between the channel layer and the barrier layer. This layer of two-dimensional electron gas is very thin, with almost no thickness, but high surface density and mobility. The material of the barrier layer can include but is not limited to AlN, AlGaN, InAlN and InGaN, etc. These materials have high polarizability and band gap, and are suitable for building high-performance HEMTs.
[0052] The cap layer is located on the side of the barrier layer away from the substrate. The main function of the cap layer is to protect the barrier layer below from the influence of the external environment, such as oxidation and corrosion, and to provide passivation to reduce the density of surface defects and trap states, reduce surface leakage current, and help improve the reliability and stability of the transistor. The cap layer can be made of semiconductor materials or insulating materials that are similar to the barrier layer material but have better stability. The material types of the cap layer include, but are not limited to, GaN, AlN, and SiN.
[0053] It should be noted that at least one of the insertion layer, barrier layer and cap layer disposed in sequence means that the insertion layer and cap layer are optional layers. In some embodiments, the insertion layer and cap layer may not be disposed to achieve a simpler layer structure and save process steps.
[0054] This embodiment further improves the performance and stability of the transistor by introducing structures such as insertion layers, barrier layers and cap layers. The insertion layer reduces interlayer stress and electron scattering, the barrier layer provides a polarization effect to form a two-dimensional electron gas, and the cap layer protects the barrier layer and provides a passivation effect. This optimized transistor structure has a wider application prospect in the field of high-performance electronic devices and can meet the needs of more demanding electronic systems.
[0055] According to the embodiments of the present disclosure, Figure 1As shown, the drain 5 includes: an ohmic contact layer 51, which is arranged on the side of the heterojunction structure layer 2 away from the substrate 1 and at least partially embedded in the heterojunction structure layer 2. A second metal layer 52 is arranged on the side of the ohmic contact layer 51 away from the substrate 1. The ohmic contact layer 51 is an n-type doped GaN-based material, and the n-type doped GaN-based material includes: Si or Ge-doped GaN, InGaN and AlGaN. Or a third metal layer is arranged on the side of the heterojunction structure layer away from the substrate and at least partially embedded in the heterojunction structure layer.
[0056] In some embodiments, the source electrode is the same as the above embodiment, and includes an auxiliary electron injection layer and a first metal layer. The auxiliary electron injection layer uses an n-type doped group III nitride material to promote the effective injection of two-dimensional electron gas from the source electrode to the heterojunction structure layer. The first metal layer is connected to an external circuit to transmit electrical signals.
[0057] The ohmic contact layer is arranged on a side of the heterojunction structure layer away from the substrate and is at least partially embedded in the heterojunction structure layer. The main function of the ohmic contact layer is to provide a low resistance contact with the heterojunction structure layer to ensure that electrons can be smoothly transferred from the channel layer to the drain.
[0058] In this embodiment, the ohmic contact layer is made of, for example, n-type doped GaN-based materials, such as Si or Ge-doped GaN, InGaN, and AlGaN, etc. These materials have good electrical conductivity and chemical stability, and are suitable for constructing high-performance ohmic contacts.
[0059] For example, the doping concentration of the ohmic contact layer is 1×10 12 cm -2 ~1×10 21 cm -2 In some embodiments, for example, it may be 1e15 cm -3 ~1e20cm -3 The selection of this concentration range provides greater flexibility for the ohmic contact layer, and the appropriate concentration can be selected according to actual needs to optimize the specific or main performance of the device.
[0060] The second metal layer is arranged on the side of the ohmic contact layer away from the substrate. The main function of the second metal layer is to serve as a connection point with the external circuit to transmit the electrical signal generated inside the transistor. The second metal layer can be made of common metal materials, such as copper, aluminum, gold or silver.
[0061] For example, the second metal layer is deposited on the ohmic contact layer. The material type of the second metal layer includes but is not limited to alloys such as Ti / Au, Al / Au, Ti / Al / Ti / Au, and Ti / Al / Ni / Au. The second metal layer forms an ohmic contact with the ohmic contact layer below.
[0062] The second metal layer, as the main current collection electrode of the transistor, can achieve efficient and stable current transmission, extract electrons from the inside of the transistor and transport them to the external circuit. At the same time, as the connection point between the transistor and the external circuit, the second metal layer can achieve effective integration of the transistor and the external circuit.
[0063] It is understandable that a third metal layer may be directly disposed on the heterojunction structure layer as a drain electrode. The material of the third metal layer may refer to the material of the second metal layer.
[0064] This embodiment optimizes the structure of the drain electrode and introduces an ohmic contact layer and a second metal layer. The ohmic contact layer uses an n-type doped GaN-based material to provide a low-resistance contact with the heterojunction structure layer, ensuring smooth transmission of electrons. The second metal layer serves as a connection point with the external circuit to achieve transmission of electrical signals. This optimized transistor structure further improves the current driving capability and operating performance, and has a wider application prospect in the field of high-performance electronic devices.
[0065] Figure 2 The cross-sectional structure of a high electron mobility transistor according to another embodiment of the present disclosure is schematically shown.
[0066] According to the embodiments of the present disclosure, Figure 2 As shown, the high electron mobility transistor further includes: a buffer layer 6 disposed between the substrate 1 and the heterojunction structure layer 2, and the thickness of the buffer layer 6 is 0 nm to 500 μm.
[0067] In some embodiments, in addition to all the components mentioned in the above embodiments (i.e., substrate, heterojunction structure layer, two-dimensional electron gas channel layer, gate structure, source and drain), a buffer layer is added. The buffer layer is arranged between the substrate and the heterojunction structure layer, and plays a transition and supporting role.
[0068] For example, the thickness of the buffer layer can be 0nm to 500μm, such as 50μm, 100μm, etc. This design range is intended to optimize the performance of the transistor. When the buffer layer thickness is 0nm, it means that the substrate is in direct contact with the heterojunction structure layer, which is feasible under certain specific material combinations and process conditions, which helps to simplify the structure and may improve electron mobility. However, in most cases, the introduction of a buffer layer of a certain thickness (such as a few microns to tens of microns) can better match the lattice constant of the substrate and the heterojunction structure layer, reduce dislocations and defects, and thus improve the stability and reliability of the transistor. At the same time, the buffer layer can also effectively block the diffusion of impurities from the substrate and protect the purity of the two-dimensional electron gas channel layer.
[0069] By selecting a buffer layer material with a suitable energy level, the energy level matching between the heterojunction structure layer and the substrate can be adjusted, thereby optimizing the electron transport characteristics of the transistor. At the same time, by selecting an appropriate buffer layer material and thickness, the carrier concentration of the heterojunction can be adjusted, further optimizing the conductive characteristics of the transistor.
[0070] It should be noted that the material selection of the buffer layer is equally important. It should have good lattice matching, thermal stability and chemical stability to ensure the long-term stable operation of the transistor. The buffer layer material includes, but is not limited to, gallium nitride (GaN), aluminum nitride (AlN) or their alloys.
[0071] For another example, a nucleation layer may be added between the substrate layer and the buffer layer. The main function of the nucleation layer is to control the nucleation process of material growth and promote more uniform, orderly and consistent growth of the material on the substrate.
[0072] This embodiment further improves the performance and stability of the transistor by introducing a buffer layer. The presence of the buffer layer not only helps to reduce dislocations and defects and improve the quality of the crystal, but also effectively blocks the diffusion of impurities and protects the two-dimensional electron gas channel layer. In addition, by precisely controlling the thickness and material of the buffer layer, the electrical performance of the transistor can be further optimized to meet the needs of different application scenarios.
[0073] According to an embodiment of the present disclosure, at least one of the source electrode 4 and the drain electrode 5 is not in contact with the buffer layer 6 .
[0074] In some embodiments, the source and drain are partially embedded in the heterojunction structure layer, and further defined as not completely penetrating the heterojunction structure layer, and thus not in contact with the buffer layer. At least one (can be the source or the drain, or both, but at least one is not in contact in this embodiment) remains in a non-contact state with the buffer layer. Such a design helps to reduce the parasitic capacitance and resistance of the transistor, thereby improving its high-frequency response speed and overall performance.
[0075] In addition, since the source and drain are only partially embedded in the heterojunction structure layer, their contact area with the two-dimensional electron gas channel layer is also optimized. This optimization can ensure that while maintaining sufficient current driving capability, unnecessary energy loss and heat generation are reduced, further improving the energy efficiency of the transistor.
[0076] It should be noted that although at least one of the source and drain electrodes does not contact the buffer layer, they still need to form a good ohmic contact with the heterojunction structure layer to ensure that the current can pass smoothly through the transistor. This is usually achieved through relevant process steps, such as ion implantation, annealing, etc., to ensure the interface quality between the source and drain electrodes and the heterojunction structure layer.
[0077] This embodiment further improves the performance and energy efficiency of the transistor by adjusting the contact between the source and drain and the buffer layer. The design that the source and drain are only partially embedded in the heterojunction structure layer helps to reduce parasitic capacitance and resistance and improve high-frequency response speed; at the same time, the optimized contact area also helps to reduce energy loss and heat generation.
[0078] According to an embodiment of the present disclosure, a surface of at least one of the auxiliary electron injection layer 41 and the ohmic contact layer 51 away from the substrate 1 is higher than a surface of the heterojunction structure layer 2 away from the substrate 1 .
[0079] In some embodiments, the surface of at least one of the auxiliary electron injection layer and the ohmic contact layer (it can be the auxiliary electron injection layer, the ohmic contact layer, or both, but at least one satisfies the condition in this embodiment) away from the substrate is higher than the surface of the heterojunction structure layer away from the substrate. This means that these layers partially extend out of the heterojunction structure layer in the vertical direction, forming a "convex" structure.
[0080] Such a design has several potential benefits.
[0081] First, it may help improve the contact quality between the source and drain electrodes and the heterojunction structure layer, because the raised structure can provide a larger contact area and better interface matching, such as optimizing the vertical contact between the auxiliary electron injection layer and the ohmic contact layer and the lateral contact with the two-dimensional electron gas.
[0082] Secondly, by adjusting the height of these layers, the electrical performance of the transistor can be further optimized, such as reducing contact resistance and improving current driving capability.
[0083] Finally, this design may also provide more flexibility and tolerance space for subsequent process steps (such as metallization, packaging, etc.).
[0084] It should be noted that, although at least one of the auxiliary electron injection layer and the ohmic contact layer is protruding relative to the heterojunction structure layer, they still need to maintain an appropriate distance and relative position relationship with the gate structure to ensure that the transistor can work normally.
[0085] This embodiment further improves the performance and manufacturing flexibility of the transistor by adjusting the height relationship between the auxiliary electron injection layer and the ohmic contact layer relative to the heterojunction structure layer. The raised structure may help improve contact quality, optimize electrical performance, and provide more flexibility and tolerance space for subsequent process steps.
[0086] According to an embodiment of the present disclosure, at least one of the auxiliary electron injection layer 41 and the ohmic contact layer 51 has a thickness of 0 nm to 100 μm.
[0087] In some embodiments, the thickness of at least one of the auxiliary electron injection layer and the ohmic contact layer (which can be the auxiliary electron injection layer, the ohmic contact layer, or both satisfying the conditions) is controlled within the range of 0nm to 100μm. Such a thickness range design is based on comprehensive considerations of transistor performance, including current driving capability, contact resistance, thermal stability, and feasibility of manufacturing process.
[0088] When the thickness of the auxiliary electron injection layer and / or the ohmic contact layer is greater than 0 nm and less than or equal to 100 μm, these layers can effectively improve the contact quality between the source and drain electrodes and the heterojunction structure layer, reduce the contact resistance, and improve the current driving capability. At the same time, the appropriate thickness can also ensure the performance of these layers in terms of thermal stability and mechanical strength to meet the needs of transistors in different working environments.
[0089] It should be noted that the thickness of the auxiliary electron injection layer is not 0 nm, so as to provide a positive conduction band step difference with the channel layer. In practical applications, the optimal thickness of these layers may need to be further optimized and adjusted according to factors such as specific transistor design, material selection, and manufacturing process.
[0090] This embodiment further improves the performance of the transistor and the flexibility of the manufacturing process by controlling the thickness range of the auxiliary electron injection layer and the ohmic contact layer. Reasonable thickness design helps to improve contact quality, reduce contact resistance, increase current driving capability, and ensure the performance of the transistor in terms of thermal stability and mechanical strength.
[0091] According to an embodiment of the present disclosure, the thickness of the channel layer 21 is 0 nm to 100 μm, and the thickness of at least one of the insertion layer 22 , the barrier layer 23 , and the cap layer 24 is 0 nm to 50 nm.
[0092] In some embodiments, the thickness of the channel layer is controlled within a range of 0 nm to 100 μm. Such a design allows the channel layer to maintain sufficient electron mobility while also being able to adapt to different manufacturing processes and transistor performance requirements.
[0093] It should be noted that the thickness of the channel layer is not 0 nm, so that an interface for generating a two-dimensional electron gas can be provided.
[0094] At the same time, the thickness of at least one of the insertion layer, barrier layer and cap layer (it can be any one of the insertion layer, barrier layer and cap layer or a combination thereof, but in this embodiment at least one layer satisfies the conditions) is controlled within the range of 0nm to 50nm. Such a thickness range design helps to optimize the manufacturing process and reduce costs while ensuring the performance of the transistor.
[0095] When the thickness of the insertion layer is 0 nm, it means that no additional insertion layer is introduced, and the performance of the transistor will be directly determined by the channel layer and the barrier layer.
[0096] When the thickness of the barrier layer is in the range of 0nm~50nm, it can effectively regulate the electron concentration and mobility in the channel, thereby optimizing the switching speed and current driving capability of the transistor.
[0097] When the cap layer exists and its thickness is in the range of 0nm~50nm, it can provide additional protection and regulation functions, such as preventing gate oxidation and improving gate stability.
[0098] This embodiment further improves the performance of the transistor and the flexibility of the manufacturing process by precisely controlling the thickness range of the channel layer, the insertion layer, the barrier layer and the cap layer. Reasonable thickness design helps to optimize the key performance indicators of the transistor, such as electron mobility, switching speed, current driving capability, and meet different manufacturing process and cost requirements.
[0099] According to the embodiments of the present disclosure, Figure 2 As shown, the gate 3 includes: a first portion 31 and a second portion 32, the second portion 32 is arranged on a side of the heterojunction structure layer 2 away from the substrate 1, and the first portion 31 is arranged on a side of the second portion 32 away from the substrate 1. The projection area of the first portion 31 on the substrate 1 is greater than or equal to the projection area of the second portion 32 on the substrate 1.
[0100] In some embodiments, the gate structure can be divided into a first part and a second part. The second part is arranged on the side of the heterojunction structure layer away from the substrate, that is, the part directly in contact with the heterojunction structure layer, which is usually made of a material with a high dielectric constant and is used to form a gate electric field and regulate the electron concentration in the channel.
[0101] The first part is arranged on the side of the second part away from the substrate, that is, above the second part. This design allows the first part to use a different material or structure from the second part to meet specific performance requirements or manufacturing process requirements. For example, the first part can be a conductive layer made of metal or alloy to provide electrical connection to the gate electrode.
[0102] For example, the gate is a strip structure, and the cross-section includes but is not limited to T-shape, square and other polygons, and the material type includes but is not limited to alloys such as Ni / Au, Pt / Au, Mo / Au, Ni / Al / Ti / Au, etc. The gate and the top structure of the heterojunction structure layer form a Schottky barrier, which can control the injection and transmission behavior of electrons. By adjusting the height and width of the barrier, the switching characteristics of the transistor can be effectively controlled.
[0103] For another example, the projection area of the first part on the substrate is greater than or equal to the projection area of the second part on the substrate. This means that the first part can be relatively extended in the horizontal direction relative to the second part. This design helps to increase the electrical isolation between the gate electrode and the source and drain, reduce parasitic capacitance and leakage current, reduce the time for electrons to cross the gate, and reduce the resistance of the gate, thereby improving the stability and performance of the transistor.
[0104] In addition, the design of this gate structure can also provide more control freedom for the transistor. For example, by changing the size, shape and material of the first part and the second part, key performance indicators such as the switching speed, threshold voltage and current driving capability of the transistor can be further optimized.
[0105] This embodiment further improves the performance and stability of the transistor by introducing a gate structure with a special geometric relationship (including a first part and a second part, and the projection area of the first part on the substrate is larger than that of the second part). This gate structure design helps to reduce parasitic capacitance and leakage current, improve the switching speed and current driving capability of the transistor, and provide it with more control freedom.
[0106] Another aspect of the disclosed embodiment provides a method for preparing a gallium nitride high electron mobility transistor with an auxiliary electron injection function, for example, including operations S1 to S5.
[0107] In operation S1 , a buffer layer and a heterojunction structure layer are sequentially epitaxially grown on an upper surface of a substrate.
[0108] In operation S2 , the edge of the upper surface of the heterojunction structure layer is etched to form two symmetrical epitaxial grooves.
[0109] For example, the depth of the epitaxial groove is less than the thickness of the heterojunction structure layer, and the depth ranges from 0nm to 100μm. At the same time, all other areas outside the device area are etched as a whole to reduce the height by about 50nm, thereby preventing the device from leaking electricity to the surrounding area.
[0110] In operation S3, the surface of the epitaxial groove is cleaned, and an auxiliary electron injection layer and a first metal layer are deposited in the left epitaxial groove as a source electrode, wherein the thickness of the auxiliary electron injection layer is greater than the depth of the epitaxial groove.
[0111] In operation S4, an ohmic contact layer and a second metal layer are deposited in the right epitaxial trench as a drain electrode, wherein the thickness of the ohmic contact layer is greater than the depth of the epitaxial trench.
[0112] For example, the auxiliary electron injection layer and the ohmic contact layer may be grown by methods including but not limited to atomic layer deposition, MOCVD / MBE epitaxy, and the like.
[0113] In operation S5 , a gate electrode is deposited on the upper surface of the heterojunction structure layer and between the auxiliary electron injection layer and the ohmic contact layer, that is, the source electrode and the drain electrode.
[0114] In a related embodiment, a high drain bias can generate a higher electric field in the area below the gate and near the drain, which causes the electrons in this area to reach velocity saturation. However, in the area where the source and gate are close to the source, the high electric field from the drain is shielded by the gate, preventing the electrons in this area from reaching saturation velocity, limiting the current and electron velocity through the device.
[0115] The embodiments of the present disclosure provide a gallium nitride high electron mobility transistor with an auxiliary electron injection function and a preparation method thereof. By introducing an auxiliary electron injection layer in the source region of a GaN-based HEMT, the band step difference of the energy band is utilized to provide additional kinetic energy for the electrons in the source, thereby accelerating the injected electrons flowing from the source to the two-dimensional electron gas in the channel layer. While effectively improving the channel carrier mobility, the density of the channel two-dimensional electron gas will not be significantly reduced, thereby laying an epitaxial structure and material foundation for realizing a GaN-based HEMT device with high-frequency and high-power performance.
[0116] Any details not included in the method example section are similar to those in the product example section. Please refer to the product example section and will not be repeated here.
[0117] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of protection of the present disclosure. The attached method claims present the elements of the various steps in an exemplary order and are not intended to be limited to a specific order or hierarchy.
[0118] It should also be noted that the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only reference directions of the drawings and are not intended to limit the scope of protection of the present disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. In addition, the shapes, sizes, and positional relationships of the components in the drawings do not reflect the actual sizes, proportions, and actual positional relationships.
[0119] In the above detailed description, various features are grouped together in a single embodiment to simplify the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the embodiments of the claimed subject matter require more features than are clearly stated in each claim. On the contrary, as reflected in the attached claims, the disclosure is in a state of having less than all the features of the disclosed individual embodiments. Therefore, the attached claims are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment of the disclosure.
[0120] In addition, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. With respect to the term "comprising" used in the specification or claims, the word is covered in a manner similar to the term "including", as explained in terms of "including," used as a transitional word in the claims. Any term "or" used in the specification of the claims is intended to mean "non-exclusive or".
[0121] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.
Claims
1. A high electron mobility transistor, characterized in that: include: substrate; A heterojunction structure layer is disposed on one side of the substrate; A gate is arranged on a side of the heterojunction structure layer away from the substrate; A source electrode, disposed on one side of the gate and at least partially embedded in the heterojunction structure layer; A drain electrode, disposed on a side of the gate electrode away from the source electrode and at least partially embedded in the heterojunction structure layer; Among them, the heterojunction structure layer includes a channel layer, and the channel layer is used to provide a transmission channel for the two-dimensional electron gas. The materials on both sides of the interface where the source electrode contacts the channel layer are different, and the band gap width of the material on the side where the source electrode is located is greater than the band gap width of the material on the side where the channel layer is located, forming a conduction band step.
2. The high electron mobility transistor according to claim 1, characterized in that: The source comprises: an auxiliary electron injection layer, disposed on a side of the heterojunction structure layer away from the substrate and at least partially embedded in the heterojunction structure layer; A first metal layer is disposed on a side of the auxiliary electron injection layer away from the substrate; Wherein, the auxiliary electron injection layer is an n-type doped group III nitride material, and the group III nitride material includes: GaN, InN, AlN, InGaN, AlGaN, InAlN and AlGaInN; The material of the channel layer includes: GaN and InGaN.
3. The high electron mobility transistor according to claim 1, characterized in that: The heterojunction structure layer further includes: At least one of an insertion layer, a barrier layer, and a cap layer disposed in sequence; The insertion layer is located on a side of the channel layer away from the substrate, the insertion layer is used to reduce interlayer stress and electron scattering, the barrier layer is used to provide a polarization effect to form the two-dimensional electron gas at the interface of the channel layer away from the substrate, and the cap layer is used to protect the barrier layer and provide a passivation effect.
4. The high electron mobility transistor according to claim 2, characterized in that: The drain comprises: An ohmic contact layer, disposed on a side of the heterojunction structure layer away from the substrate and at least partially embedded in the heterojunction structure layer; A second metal layer is disposed on a side of the ohmic contact layer away from the substrate; Wherein, the ohmic contact layer is an n-type doped GaN-based material, and the n-type doped GaN-based material includes: Si or Ge doped GaN, InGaN and AlGaN; or The third metal layer is arranged on a side of the heterojunction structure layer away from the substrate and is at least partially embedded in the heterojunction structure layer.
5. The high electron mobility transistor according to claim 1, characterized in that: Also includes: A buffer layer is disposed between the substrate and the heterojunction structure layer, and the thickness of the buffer layer is 0 nm to 500 μm.
6. The high electron mobility transistor according to claim 5, characterized in that: At least one of the source electrode and the drain electrode does not contact the buffer layer.
7. The high electron mobility transistor according to claim 4, characterized in that: A surface of at least one of the auxiliary electron injection layer and the ohmic contact layer that is away from the substrate is higher than a surface of the heterojunction structure layer that is away from the substrate.
8. The high electron mobility transistor according to claim 4, characterized in that: At least one of the auxiliary electron injection layer and the ohmic contact layer has a thickness of 0 nm to 100 μm.
9. The high electron mobility transistor according to claim 3, characterized in that: The thickness of the channel layer is 0 nm to 100 μm, and the thickness of at least one of the insertion layer, the barrier layer and the cap layer is 0 nm to 50 nm.
10. The high electron mobility transistor according to claim 1, characterized in that: The gate comprises: A first portion and a second portion, wherein the second portion is disposed on a side of the heterojunction structure layer away from the substrate, and the first portion is disposed on a side of the second portion away from the substrate; The projection area of the first part on the substrate is greater than or equal to the projection area of the second part on the substrate.