Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof. The semiconductor device comprises a source electrode layer, a drain electrode layer, a channel layer and a grid electrode structure, the channel layer surrounds the gate structure; the gate structure comprises a gate layer, a ferroelectric material layer and a gate dielectric layer, wherein the ferroelectric material layer and the gate dielectric layer surround the gate layer; the source electrode layer and the drain electrode layer are located on the two sides of the channel layer respectively; a metal silicide layer is arranged between the source electrode layer and the channel layer, and a metal silicide layer is arranged between the drain electrode layer and the channel layer. According to the semiconductor device disclosed by the invention, the ferroelectric material is introduced, so that the obtained nonvolatile dynamic random access memory can solve the problems of storage density and energy consumption of the current dynamic random access memory, and high-density and high-energy-efficiency storage can be realized; besides, in the preparation process, a channel structure surrounding the grid electrode is formed through metal induction, wafer-level three-dimensional integration is achieved, and compared with a traditional semiconductor process, the integration density is high, the cost is low, and wide application prospects are achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof. Background Art

[0002] Currently, DRAM (dynamic random access memory) has problems with energy consumption and storage density. Combining DRAM and NVM (non-volatile memory) to form NVDRAM (non-volatile dynamic random access memory) and integrating it into the memory hierarchy can solve the current DRAM storage density and energy consumption problems. Ferroelectric materials can retain their polarization state for a long time after polarization, and have a wide range of applications in the field of non-volatile ferroelectric memory.

[0003] In addition, traditional semiconductor processes are dominated by silicon-based processes, represented by 3D V-cache, which are usually implemented based on advanced bonding technology, with limited integration density and high cost.

[0004] In view of this, the present invention is proposed. Summary of the invention

[0005] The object of the present invention is to provide a semiconductor device and a method for preparing the same, which can achieve high-density and high-energy-efficiency storage and adopt wafer-level three-dimensional integration with high integration density and low cost.

[0006] According to a first aspect of the present invention, a semiconductor device is provided, comprising: a source layer, a drain layer, a channel layer and a gate structure; the channel layer surrounds the gate structure; the gate structure comprises: a gate layer and a ferroelectric material layer and a gate dielectric layer surrounding the gate layer; the source layer and the drain layer are respectively located on both sides of the channel layer; a metal silicide layer is provided between the source layer and the channel layer, and a metal silicide layer is provided between the drain layer and the channel layer.

[0007] Preferably, the material of the channel layer is crystalline silicon formed by metal induction from amorphous silicon.

[0008] Preferably, the material of the metal silicide layer is NiSi2.

[0009] Preferably, the source layer, the drain layer and the gate layer are made of TiN / W, and the gate dielectric layer is made of HfO2.

[0010] Preferably, it further comprises: a plurality of conductive channels, wherein the conductive channels are respectively connected to the source layer, the drain layer and the gate layer.

[0011] A second aspect of the present invention provides a method for preparing a semiconductor device, comprising the following steps:

[0012] S1, depositing an OX / Si3N4 stack and forming an active trench in the stack;

[0013] S2, etching the Si3N4 layer adjacent to the active trench to form a channel region;

[0014] S3, forming a metal silicide layer in the channel region, and forming a channel layer by metal induction;

[0015] S4, removing the Si3N4 layer, and depositing to form a source layer and a drain layer;

[0016] S5. Forming a gate structure in the active trench.

[0017] Preferably, step S3 comprises:

[0018] S31, filling amorphous silicon in the channel region, the active trench and the top;

[0019] S32, etching the amorphous silicon to retain the amorphous silicon in the channel region;

[0020] S33, depositing a SiO2 layer and a metal layer in the active trench and on the top;

[0021] S34, forming a metal silicide layer through annealing treatment, and the amorphous silicon is induced by the metal silicide to form a channel layer of crystalline silicon material.

[0022] Preferably, in step S33, the thickness of the SiO2 layer is 2 nm, and the thickness of the metal layer is 5-10 nm.

[0023] Preferably, in step S34, the temperature range of the annealing treatment is 450-575°C.

[0024] Preferably, the method further comprises the following steps:

[0025] S6. Depositing an interlayer dielectric layer above the source layer, the drain layer and the gate structure, forming contact holes in the interlayer dielectric layer that are in contact with the source layer, the drain layer and the gate layer respectively, and forming a conductive channel in the contact holes.

[0026] The present invention has at least the following beneficial effects:

[0027] The semiconductor device 1T0C 3D NVDRAM of the present invention introduces ferroelectric materials to obtain a non-volatile dynamic random access memory that can solve the storage density and energy consumption problems of current dynamic random access memory and can achieve high-density and high-energy-efficiency storage; in addition, in the preparation process of the present invention, metal induction is used to form a channel structure surrounding the gate, which realizes wafer-level three-dimensional integration. Compared with traditional semiconductor processes, it has high integration density and low cost, and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 It is a cross-sectional view along the a-a' direction after the OX / Si3N4 stack is grown on the peripheral circuit of the present invention;

[0030] Figure 2 It is a cross-sectional view along the b-b' direction after the OX / Si3N4 stack is grown on the peripheral circuit of the present invention;

[0031] Figure 3 A cross-sectional view along the a-a' direction after an active trench is formed in the stack according to the present invention;

[0032] Figure 4 A cross-sectional view along the bb' direction after an active trench is formed in the stack according to the present invention;

[0033] Figure 5 A cross-sectional view along the a-a' direction after the channel region is formed in the present invention;

[0034] Figure 6 A cross-sectional view along the bb' direction after the channel region is formed according to the present invention;

[0035] Figure 7 It is a cross-sectional view along the a-a' direction after the amorphous silicon is filled and covered in the present invention;

[0036] Figure 8 It is a cross-sectional view along the direction bb' after the amorphous silicon is filled and covered in the present invention;

[0037] Fig. 9 A cross-sectional view along the a-a' direction of the amorphous silicon remaining in the channel region after etching the amorphous silicon according to the present invention;

[0038] Fig.10 A cross-sectional view along the bb' direction of the amorphous silicon remaining in the channel region after etching the amorphous silicon according to the present invention;

[0039] Fig.11 It is a cross-sectional view along the a-a' direction after the SiO2 layer and the metal layer are deposited on the active trench and the top of the stack according to the present invention;

[0040] Fig.12 It is a cross-sectional view along the direction b-b' after the SiO2 layer and the metal Ni layer are deposited on the active trench and the top of the stack according to the present invention;

[0041] Fig.13 A cross-sectional view along the a-a' direction after NiSi2 is formed by rapid thermal annealing of the present invention;

[0042] Fig.14 A cross-sectional view along the b-b' direction after NiSi2 is formed by rapid thermal annealing of the present invention;

[0043] Fig.15 It is a cross-sectional view along the a-a' direction after the amorphous silicon of the present invention is induced by metal to form a crystalline silicon material channel layer;

[0044] Fig.16 It is a cross-sectional view along the direction bb' of the amorphous silicon of the present invention after the amorphous silicon is induced by metal to form a crystalline silicon material channel layer;

[0045] Fig.17 It is a cross-sectional view along the a-a' direction after the insulating layer is deposited according to the present invention;

[0046] Fig.18 It is a cross-sectional view along the bb' direction after the insulating layer is deposited according to the present invention;

[0047] Fig.19 It is a cross-sectional view along the a-a' direction after etching to form the top BL of the present invention;

[0048] Fig. 20 It is a cross-sectional view along the bb' direction after etching to form the top BL of the present invention;

[0049] Fig.21 It is a cross-sectional view along the a-a' direction after the source and drain regions are formed in the present invention;

[0050] Fig. 22 It is a cross-sectional view along the bb' direction after the source and drain regions are formed in the present invention;

[0051] Fig.23 It is a cross-sectional view along the a-a' direction after TiN / W is deposited and covered according to the present invention;

[0052] Fig.24 It is a cross-sectional view along the b-b' direction after TiN / W is deposited and covered according to the present invention;

[0053] Fig.25 A cross-sectional view along the a-a' direction after the source electrode layer and the drain electrode layer are formed in the present invention;

[0054] Fig.26 A cross-sectional view along the bb' direction after the source electrode layer and the drain electrode layer are formed in the present invention;

[0055] Fig. 27 It is a cross-sectional view along the a-a' direction after the insulating layer is deposited according to the present invention;

[0056] Fig.28 It is a cross-sectional view along the bb' direction after the insulating layer is deposited according to the present invention;

[0057] Fig.29 A cross-sectional view along the a-a' direction after removing SiO2 in the active groove of the present invention;

[0058] Fig.30 A cross-sectional view along the bb' direction after removing SiO2 in the active groove of the present invention;

[0059] Fig.31 It is a cross-sectional view along the a-a' direction after the gate structure is formed in the present invention;

[0060] Fig.32 A cross-sectional view along the bb' direction after the gate structure is formed according to the present invention;

[0061] Fig.33 A cross-sectional view of a semiconductor device formed by the present invention along the a-a' direction;

[0062] Fig.34 A cross-sectional view of a semiconductor device formed according to the present invention along the bb' direction;

[0063] Fig.35 It is a schematic diagram of the a-a' and bb' directions of the present invention.

[0064] Explanation of the accompanying drawings: 1. peripheral circuit; 2. OX layer; 3. Si3N4 layer; 4. active trench; 5. channel region; 6. amorphous silicon; 7. SiO2 layer; 8. metal layer; 9. metal silicide layer; 10. channel layer; 11. TiN / W; 12. source layer; 13. drain layer; 14. gate dielectric layer; 15. ferroelectric material layer; 16. gate layer; 17. interlayer dielectric layer; 18. conductive channel. DETAILED DESCRIPTION

[0065] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0066] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form also includes the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0067] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0068] Example

[0069] The present embodiment provides a semiconductor device, specifically a 1T0C 3DNVDRAM based on a ferroelectric transistor, including: a source layer 12, a drain layer 13, a channel layer 10 and a gate structure; the channel layer 10 surrounds the gate structure; the gate structure includes: a gate layer 16 and a ferroelectric material layer 15 and a gate dielectric layer 14 surrounding the gate layer 16; the source layer 12 and the drain layer 13 are respectively located on both sides of the channel layer 10; a metal silicide layer 9 is provided between the source layer 12 and the channel layer 10, and a metal silicide layer 9 is provided between the drain layer 13 and the channel layer 10.

[0070] In this embodiment, the material of the channel layer 10 is crystalline silicon formed by metal induction using amorphous silicon 6 .

[0071] In this embodiment, the material of the metal silicide layer 9 is NiSi2.

[0072] In this embodiment, the source layer 12 , the drain layer 13 and the gate layer 16 are made of TiN / W 11 , and the gate dielectric layer 14 is made of HfO 2 .

[0073] In this embodiment, it also includes: a plurality of conductive channels 18 , and the conductive channels 18 are respectively connected to the source layer 12 , the drain layer 13 and the gate layer 16 .

[0074] This embodiment also provides a method for preparing a semiconductor device, comprising the following steps:

[0075] S1, depositing an OX / Si3N4 stack to form an active trench 4 in the stack;

[0076] S2, etching the Si3N4 layer 3 adjacent to the active trench 4 to form a channel region 5;

[0077] S3, forming a metal silicide layer 9 in the channel region 5, and forming a channel layer 10 by metal induction;

[0078] S4, removing the Si3N4 layer 3, and depositing to form a source electrode layer 12 and a drain electrode layer 13;

[0079] S5 . Form a gate structure in the active trench 4 .

[0080] S6. Deposit an interlayer dielectric layer 17 above the source layer 12, the drain layer 13 and the gate structure, form contact holes in the interlayer dielectric layer 17 that are in contact with the source layer 12, the drain layer 13 and the gate layer 16 respectively, and form a conductive channel 18 in the contact holes.

[0081] The preparation method of this embodiment is described in more detail below:

[0082] For step S1, Figure 1 and 2 As shown, an OX layer 2 and a Si3N4 layer 3 are sequentially grown on a CMOS peripheral circuit 1 by epitaxial growth, i.e., an OX / Si3N4 stack. The number of OX layers 2 and Si3N4 layers 3 can be set according to actual needs. In this embodiment, three layers of OX layers 2 and two layers of Si3N4 layers 3 are taken as an example, wherein the material of the OX layer 2 is SiO2.

[0083] like Figure 3 and 4 As shown, an active trench 4 is formed in the stack by etching.

[0084] For step S2, Figure 5 and 6 As shown, the channel region 5 is formed by laterally etching the Si3N4 layer 3 adjacent to the active trench 4 with phosphoric acid.

[0085] For step S3, Figure 7 and 8 As shown, the channel region 5, the active trench 4 and the top of the stack are filled with amorphous silicon 6 (α-Si).

[0086] like Fig. 9 and 10 As shown, the amorphous silicon 6 is etched in a self-aligned manner, and the amorphous silicon 6 in the channel region 5 is retained.

[0087] like Fig.11 and 12 As shown, an atomic layer deposition process (ALD) is used to deposit a 2nm thick SiO2 layer 7 and a 5-10nm thick Ni metal layer 8 on the active trench 4 and the top of the stack. The 2nm thick SiO2 layer can effectively control the reaction rate of nickel and silicon to prevent the reaction from being too fast, so as to better control the reaction. If the SiO2 layer is too thick, it is not conducive to the reaction. If the SiO2 layer is too thin, the effect of controlling the reaction rate is reduced. Therefore, a 2nm thick SiO2 layer is the best condition for controlling the reaction rate of nickel and silicon.

[0088] like Fig.13 and 14 As shown, rapid thermal annealing at 450-575°C for 5-10 min forms NiSi2 and removes unreacted Ni.

[0089] like Fig.15 and 16 As shown, annealing treatment is performed at 500-575℃ for 12-24h, and the SiO2 layer 7 is removed. During the annealing process, NiSi2 diffuses along the amorphous silicon 6 nanowires to the Si3N4 / α-Si interface. Under the induction of metal, the amorphous silicon 6 will crystallize into crystalline silicon (c-Si) with the NiSi2 crystal phase as the motherboard, and the impurities will be reactivated at the same time. Since NiSi2 has a face-centered cubic structure (FCC), which is very close to the single crystal silicon lattice structure, and the lattice mismatch is only 0.4%, it can be considered that the amorphous silicon 6 is crystallized into c-Si to form a channel layer 10.

[0090] For step S4, Fig.17 and 18 As shown, an insulating layer (SiO2) is deposited and chemically mechanically polished (CMP).

[0091] like Fig.19 and 20 As shown, a top BL is formed by etching.

[0092] like Fig.21 and 22 As shown, the remaining Si3N4 layer 3 is removed by phosphoric acid etching to form source and drain regions for preparing the source layer 12 and the drain layer 13.

[0093] like Fig.23 and 24 As shown, the deposition covers TiN / W11.

[0094] like Fig.25 and 26 As shown, W is laterally etched and NiSi2 is removed to form a source layer 12 and a drain layer 13.

[0095] For step S5, Fig. 27 and 28 As shown, an insulating layer SiO2 is deposited and planarized.

[0096] like Fig.29 and 30 As shown, SiO2 in the active trench 4 is removed by etching.

[0097] like Fig.31 and 32 As shown, a gate dielectric layer 14 (HfO2), a ferroelectric material layer 15, and a gate layer 16 (TiN / W) are grown in sequence, and the gate structure of the FeFET is formed by patterning.

[0098] For step S6, Fig.33 and 34As shown, an interlayer dielectric layer 17 is deposited on the top, and dielectric CMP is performed, and then contact hole lithography and etching are performed, and hole silicide is deposited to form contact holes that are respectively in contact with the source layer 12, the drain layer 13 and the gate layer 16, and a conductive channel 18 is formed in the contact hole to obtain the semiconductor device, namely 1T0C NVDRAM. Fig.35 It is a schematic diagram of the a-a' and bb' directions of the present invention.

[0099] In summary, in the 1T0C 3D NVDRAM and wafer-level three-dimensional integration solution based on ferroelectric transistors provided in this embodiment, the ferroelectric transistor is a horizontal channel all around structure, the gate is a metal-ferroelectric dielectric-insulating dielectric layer structure, the channel is metal-induced crystalline silicon, the storage cells in the same layer share the bit line, and the storage cells in the same column share the word line, which can achieve high-density and high-energy-efficiency storage.

[0100] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0101] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: include: Source layer, drain layer, channel layer and gate structure; The channel layer surrounds the gate structure; The gate structure includes: a gate layer and a ferroelectric material layer and a gate dielectric layer surrounding the gate layer; the source layer and the drain layer are respectively located on both sides of the channel layer; a metal silicide layer is provided between the source layer and the channel layer, and a metal silicide layer is provided between the drain layer and the channel layer.

2. The semiconductor device according to claim 1, wherein: The material of the channel layer is crystalline silicon formed by metal induction using amorphous silicon.

3. The semiconductor device according to claim 1, wherein: The material of the metal silicide layer is NiSi2.

4. The semiconductor device according to claim 1, wherein: The material of the source electrode layer, the drain electrode layer and the gate electrode layer is TiN / W, and the material of the gate dielectric layer is HfO2.

5. The semiconductor device according to claim 1, wherein: Also includes: A plurality of conductive channels are respectively connected to the source layer, the drain layer and the gate layer.

6. A method for preparing a semiconductor device, characterized in that: The steps include: S1, depositing an OX / Si3N4 stack and forming an active trench in the stack; S2, etching the Si3N4 layer adjacent to the active trench to form a channel region; S3, forming a metal silicide layer in the channel region, and forming a channel layer by metal induction; S4, removing the Si3N4 layer, and depositing to form a source layer and a drain layer; S5. Forming a gate structure in the active trench.

7. The method for preparing a semiconductor device according to claim 6, characterized in that: Step S3 includes: S31, filling amorphous silicon in the channel region, the active trench and the top; S32, etching the amorphous silicon to retain the amorphous silicon in the channel region; S33, depositing a SiO2 layer and a metal layer in the active trench and on the top; S34, forming a metal silicide layer through annealing treatment, and the amorphous silicon is induced by the metal silicide to form a channel layer of crystalline silicon material.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: In step S33, the thickness of the SiO2 layer is 2 nm, and the thickness of the metal layer is 5-10 nm.

9. The method for preparing a semiconductor device according to claim 7, characterized in that: In step S34, the temperature range of the annealing treatment is 450-575°C.

10. The method for preparing a semiconductor device according to claim 6, characterized in that: The following steps are also included: S6. Depositing an interlayer dielectric layer above the source layer, the drain layer and the gate structure, forming contact holes in the interlayer dielectric layer that are in contact with the source layer, the drain layer and the gate layer respectively, and forming a conductive channel in the contact holes.

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