Multi-nanowire channel indium gallium zinc oxide thin film transistor and preparation method thereof

Abstract

The invention discloses a multi-nanowire channel indium gallium zinc oxide thin film transistor and a preparation method thereof, and belongs to the technical field of semiconductor manufacturing. The multi-nanowire channel indium gallium zinc oxide thin film transistor comprises a substrate and a channel layer, wherein the channel layer is made of indium gallium zinc oxide; a source electrode, a top gate dielectric layer and a drain electrode are sequentially arranged on the channel layer in the transverse direction, and a top gate electrode is arranged on the top gate dielectric layer; the channel layer is provided with a plurality of transverse nanowire channels which are arranged at intervals in an area outside a contact area of the channel layer with the source electrode and the drain electrode, the width of the nanowire channels is 1-5 times of the thickness of the channel layer, and the distance between two adjacent nanowire channels is 1-3 times of the width of the nanowire channels. By means of the structure, multi-face surrounding of the grid electrode on the nanowire channel can be achieved, the control capacity of the grid electrode on the channel is enhanced, the short-channel effect can be restrained, and the equivalent mobility is higher than that of a single-layer continuous channel.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a multi-nanowire channel indium gallium zinc oxygen thin film transistor and a preparation method thereof. Background Art

[0002] The information disclosed in the background of the invention is only intended to enhance the understanding of the overall background of the invention and should not be necessarily regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art.

[0003] Indium gallium zinc oxide (In-Ga-Zn-O, IGZO) thin film transistor is a thin film transistor that uses indium gallium zinc oxide material as the semiconductor layer. The traditional indium gallium zinc oxide thin film transistor is a single-channel transistor with a complete indium gallium zinc oxide material thin film as the semiconductor layer. It has the advantages of high mobility, high uniformity, low power consumption and low cost. It has been widely used in the field of display technology and has great potential in the field of vertical integration and logic circuits. In the development of integrated circuits, in order to improve the resolution and frame rate of displays and the integration of integrated circuits, it is necessary to scale down the indium gallium zinc oxide thin film transistor in proportion, but too small a channel length will lead to a serious short channel effect, weaken the gate control ability of the device, and lead to performance degradation such as lower drain barrier, lower mobility, and larger subthreshold swing. This phenomenon seriously hinders the application of IGZO TFT in high integration. Summary of the invention

[0004] In view of this, the present invention provides a multi-nanowire channel InGaZnO thin film transistor and a preparation method thereof. The present invention adopts an InGaZnO thin film transistor with a multi-nanowire channel structure, which can form a channel structure with a gate surrounded on three sides, which is beneficial to suppressing the short channel effect and at the same time making the equivalent mobility higher than that of a continuous channel device.

[0005] In a first aspect, the present invention provides a multi-nanowire channel indium gallium zinc oxide thin film transistor, comprising:

[0006] substrate;

[0007] A channel layer is formed on the substrate and is made of indium gallium zinc oxide;

[0008] A source electrode, a top gate dielectric layer and a drain electrode are sequentially arranged on the channel layer in a lateral direction, and a top gate electrode is arranged on the top gate dielectric layer;

[0009] The channel layer is provided with a plurality of spaced-apart lateral nanowire channels in the area outside the contact area with the source electrode and the drain electrode. The width of the nanowire channel is 1 to 5 times the thickness of the channel layer, and the spacing between two adjacent nanowire channels is 1 to 3 times the width of the nanowire channel.

[0010] In a second aspect, the present invention provides a method for preparing the above-mentioned multi-nanowire channel InGaZnO thin film transistor, comprising the following steps:

[0011] providing a substrate;

[0012] forming a channel layer on the substrate;

[0013] A source electrode and a drain electrode are arranged on the surface of the channel layer; and then a plurality of lateral nanowire channels are etched in the area outside the contact area between the channel layer and the source electrode and the drain electrode;

[0014] Then, a top gate dielectric layer and a top gate electrode are sequentially formed on the surface of the channel layer between the source electrode and the drain electrode.

[0015] In a third aspect, the present invention provides a chip comprising the above-mentioned multi-nanowire channel indium gallium zinc oxide thin film transistor.

[0016] In a fourth aspect, the present invention provides an electronic device comprising the above-mentioned multi-nanowire channel indium gallium zinc oxide thin film transistor.

[0017] Compared with the prior art, the present invention has achieved the following beneficial effects:

[0018] The multi-nanowire channel indium gallium zinc oxide thin film transistor of the present invention can effectively improve the gate control capability and improve the mobility; the width of the multiple lateral nanowire channels of the present invention is 1 to 5 times of their thickness, and the spacing between adjacent nanowire channels is 1 to 3 times of their width. This design realizes the top gate electrode surrounding the three sides of the nanowire channel or the double gate electrode surrounding the four sides of the nanowire, thereby enhancing the control ability of the gate over the channel, which is beneficial to suppressing the short channel effect, and the equivalent mobility is higher than that of a single-layer continuous channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings constituting part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their description are used to explain the present invention and do not constitute an improper limitation of the present invention. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 is a schematic structural diagram of a multi-nanowire channel indium gallium zinc oxide thin film transistor provided in an embodiment of the present invention;

[0021] Figure 2 is a top view of a multi-nanowire channel indium gallium zinc oxide thin film transistor provided by an embodiment of the present invention;

[0022] Figure 3 It is a schematic diagram of the three-dimensional structure of a multi-nanowire channel InGaZnO thin film transistor provided by an embodiment of the present invention;

[0023] Figure 4 is a schematic diagram of the cross-sectional structure of a single nanowire provided by an embodiment of the present invention;

[0024] Figure 5 It is a schematic diagram of a cross section of a top gate electrode regulating three-sided channels of a multi-nanowire channel InGaZnO thin film transistor with a top gate structure provided by an embodiment of the present invention;

[0025] Figure 6 It is a schematic structural diagram of a multi-nanowire channel InGaZnO thin film transistor with a dual-gate structure provided by an embodiment of the present invention;

[0026] Figure 7 It is a schematic cross-sectional diagram of the top gate electrode and the bottom gate electrode regulating the four-sided channel of the multi-nanowire channel InGaZnO thin film transistor with a dual-gate structure provided by an embodiment of the present invention;

[0027] In the figure, 1, substrate; 2, channel layer; 3, source electrode; 4, top gate dielectric layer; 5, drain electrode; 6, top gate electrode; 7, nanowire channel; 8, bottom gate electrode; 9, bottom gate dielectric layer. DETAILED DESCRIPTION

[0028] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0029] Reference Figure 1 , Figure 2 and Figure 3 As shown, the present invention provides a multi-nanowire channel InGaZnO thin film transistor, comprising a substrate 1, a channel layer 2, a source electrode 3, a top gate dielectric layer 4, a top gate electrode 6 and a drain electrode 5; the channel layer 2 is formed on the substrate 1, and its material is InGaZnO; the source electrode 3, the top gate dielectric layer 4 and the drain electrode 5 are sequentially arranged on the channel layer 2 along the lateral direction, and the top gate dielectric layer 4 is provided with a top gate electrode 6.

[0030] In the present invention, a plurality of spaced-apart lateral nanowire channels 7 are arranged in the channel layer 2 outside the contact area with the source electrode 3 and the drain electrode 5, and each nanowire channel 7 can form a conductive channel; a top gate electrode 6 surrounds each nanowire channel 7 on the top and left and right sides. When a voltage is applied to the top gate electrode 6, the left and right sides of the nanowire channel 7 are regulated by the top gate to form an electron accumulation layer due to the electric field effect, thereby forming a conductive channel. Figure 4 and Figure 5 In addition, when the transistor device is a dual-gate structure, that is, when the substrate includes a bottom gate electrode 8 and a bottom gate dielectric layer 9, as shown in FIG. Figure 6As shown, the bottom gate dielectric layer 9 is formed on the bottom gate electrode 8, and the channel layer 2 is formed on the bottom gate dielectric layer 9; at this time, after the bottom gate electrode applies a voltage, a conductive channel can be formed under the nanowire channel 7, thereby realizing a four-sided channel structure, as shown in FIG. Figure 7 As shown, the carrier effect is further suppressed and the carrier mobility is improved.

[0031] In the present invention, the width of the nanowire channel 7 is 1 to 5 times the thickness of the channel layer 2, so that the top gate dielectric layer 4 and the top gate electrode 6 can cover the nanowire channel 7 on three sides. When the thickness of the channel layer 2 is relatively thin, the nanowire channel 7 needs to have sufficient width to provide sufficient coverage area so that the nanowire channel 7 presents a three-sided structure when regulated by the top gate. If it is too narrow, the surface of the nanowire regulated by the gate may be reduced, and the advantage of multi-sided regulation cannot be brought into play.

[0032] In the present invention, the spacing between two adjacent nanowire channels 7 is 1 to 3 times the width of the nanowire channel 7. Growing the top gate dielectric layer 4 and the top gate electrode 6 on the nanowire channel 7 will fill the groove between the two nanowire channels 7. If the spacing between the nanowire channels 7 is too small, the groove may be filled, so that the top gate can only cover the upper side of the nanowire but not the left and right sides. At the same time, if the spacing between the nanowire channels 7 is too large, the number of nanowire channels 7 will be reduced.

[0033] In some embodiments of the present invention, the top gate dielectric layer 4 is separated from the source electrode 3 and the drain electrode 5 by a set distance, that is, the source electrode 3 or the drain electrode 5 does not overlap with the top gate electrode 6, so there is no parasitic capacitance between the two. The source electrode 3 and the drain electrode 5 are arranged on both sides of the channel layer 2 in the lateral direction.

[0034] In some embodiments of the present invention, the lateral length of the nanowire channel 7 is 10 nm to 6 μm, more preferably 3 to 6 μm, which is also the distance between the source electrode 3 and the drain electrode 5 .

[0035] In some embodiments of the present invention, the thickness of the channel layer 2 is 4-30 nm; the width of the nanowire channel 7 is 10-50 nm; and the spacing between two adjacent nanowire channels 7 is 10-150 nm.

[0036] In some embodiments of the present invention, the source electrode 3 and the drain electrode 5 are made of indium tin oxide, tungsten or a composite material of the two; the material of the top gate dielectric layer 6 is SiO 2 or Al 2 O 3 ; The material of the top gate electrode 6 is tungsten or indium tin oxide.

[0037] In some embodiments of the present invention, the material of the substrate 1 is SiO 2 , the structural diagram is as follows Figure 1 As shown, this is a top gate device.

[0038] In some other embodiments of the present invention, the substrate 1 includes a bottom gate electrode 8 and a bottom gate dielectric layer 9. The material of the bottom gate electrode 8 is p-type lightly doped silicon; the material of the bottom gate dielectric layer 9 is SiO 2 or Al 2 O 3 ; This is a dual-gate device.

[0039] In some embodiments of the present invention, the thickness of the source electrode 3 and the drain electrode 5 is 10-100 nm, the thickness of the bottom gate dielectric layer 2 is 5-200 nm, the thickness of the top gate dielectric layer 4 is 5-200 nm; the thickness of the top gate electrode 6 is 10-100 nm.

[0040] The present invention also provides a method for preparing the multi-nanowire channel InGaZnO thin film transistor, comprising the following steps:

[0041] Providing a substrate 1;

[0042] forming a channel layer 2 on a substrate 1;

[0043] A source electrode 3 and a drain electrode 5 are arranged on the surface of the channel layer 2; and then a plurality of lateral nanowire channels 7 are etched in the area outside the contact area between the channel layer 2 and the source electrode 3 and the drain electrode 5;

[0044] Then, a top gate dielectric layer 4 and a top gate electrode 6 are sequentially formed on the surface of the channel layer 2 between the source electrode 3 and the drain electrode 5 .

[0045] In the present invention, after forming the top gate electrode 6, the surface of the channel layer 2 that is not in contact with the source electrode 3, the top gate dielectric layer 4 and the drain electrode 5 is further doped with B or P ion implantation to enhance the conductivity and reduce the contact resistance.

[0046] In some embodiments of the present invention, the method for preparing a multi-nanowire channel InGaZnO thin film transistor specifically comprises the following steps:

[0047] (1) Cleaning the substrate 1: Immerse the substrate 1 in a solvent (such as isopropanol, ethanol, water, etc.) and perform ultrasonic treatment, then take it out and blow dry it.

[0048] (2) Prepare a channel layer 2 on the sample obtained in step (1). Deposit IGZO material with a thickness of 4 to 30 nm by plasma enhanced atomic layer deposition (PEALD) at a temperature of 200°C.

[0049] (3) Annealing: The sample obtained in step (2) was placed in an oxygen environment and annealed at 400°C for 1 hour.

[0050] (4) preparing a source electrode 3 and a drain electrode 5 on the sample obtained in step (3): depositing 10 to 100 nm of metal tungsten by magnetron sputtering with a sputtering power of 50 W and a sputtering time of 2580 s;

[0051] (5) Define the channel region, and form the channel region on the sample obtained in step (4) by photolithography and etching. Specifically, place the sample on a 110°C heating table for pre-bake for 3 minutes, spin-coat the photoresist (AR-P-5350), and then perform photolithography with an exposure time of 6 to 7.5 seconds. Then place the sample in a solution of AR300-26 and deionized water mixed in a volume ratio of 1:6 for 20 to 27 seconds of development. Soak the sample in 15wt% hydrogen peroxide (H 2 O 2 ) solution for 1 to 1.5 minutes to remove the tungsten not covered by the photoresist. Inductively coupled plasma (ICP) etching was performed using methane (CH 4 ) and hydrogen (H 2 ), the methane flow rate is 30sccm, the hydrogen flow rate is 10sccm, the etching time is 1-2min, the ICP power is 350W, the RF power is 100W, and the indium gallium zinc oxide (IGZO) not covered by the photoresist is etched away. Finally, the sample is immersed in acetone for 2h to remove the photoresist.

[0052] (6) Preparing channels, source electrodes 3 and drain electrodes 5, forming a plurality of nanowire channels 7, source electrodes 3 and drain electrodes 5 on the sample obtained in step (5) by EBL process and ICP etching process. Specifically, the steps include:

[0053] (a) designing an electron beam exposure (EBL) lithography pattern to design a lithography pattern of multiple nanowire channels, wherein the length of each nanowire channel 7 is designed to be 10 nm to 6 μm, the width of the nanowire channel 7 is 10 to 50 nm, and the interval between two adjacent nanowire channels 7 is 10 to 150 nm;

[0054] (b) spin coating AR-P-5350 photoresist onto the surface of the sample obtained in step (5), and baking the sample at 110° C. for 3 min before and after spin coating;

[0055] (c) performing photolithography on the sample obtained in step (b), exposing the photoresist at the channel, with the exposure time being 6-7.5 s;

[0056] (d) immersing the sample obtained in step (c) in a solution of AR300-26 and deionized water mixed in a volume ratio of 1:6 for 20-27 seconds, and developing the solution to remove the photoresist above the channel;

[0057] (e) wet-etching the sample obtained in step (d) and immersing the sample in 15 wt % hydrogen peroxide (H 2 O 2) solution for 1 to 1.5 min to remove W on the indium gallium zinc oxide (IGZO) in the channel;

[0058] (f) soaking the sample obtained in step (e) in acetone for 2 h to remove the photoresist;

[0059] (g) spin coating PMMA photoresist on the sample obtained in step (f), and baking at 90° C. for 1 min before and after spin coating;

[0060] (h) placing the sample obtained in step (g) into the EBL equipment chamber and exposing the sample using the layout obtained in step (a) at an exposure dose of 150-180 μC / cm 2 ;

[0061] (i) developing the sample obtained in step (h), immersing the sample in a developer solution prepared by mixing isopropanol and water in a volume ratio of 1:3 for 1-2 minutes, and then immersing the sample in isopropanol for 10-15 seconds for fixing, so that the photoresist forms a multi-nanowire channel pattern;

[0062] (j) The sample obtained in step (d) is subjected to inductively coupled plasma (ICP) etching to form a multi-nanowire channel structure using methane (CH 4 ) and hydrogen (H 2 ), flow rates are 35 sccm and 10 sccm respectively, ICP power is 350 W, RF power is 100 W, and etching time is 1-2 min;

[0063] (k) Soak the sample obtained in step (j) in acetone for 2 hours to remove the photoresist. At this point, the channel layer 2 is etched into a multi-nanowire structure.

[0064] (7) A top gate dielectric layer 4 is prepared on the sample obtained in step (6). Atomic layer deposition (ALD) is used to deposit Al 2 O 3 , temperature is 200℃, thickness is 5~200nm.

[0065] (8) Annealing: The sample obtained in step (7) was placed in an oxygen environment and annealed at 400°C for 1 hour.

[0066] (9) Deposit a top gate electrode 6 on the sample obtained in step (8). Place the sample on a 110°C heating table and pre-bake for 3 minutes, spin-coat AR-P-5350 photoresist, and post-bake on a 110°C heating table for 3 minutes. Then perform photolithography with an exposure time of 6-7.5 seconds. Then place the sample in a solution of AR300-26 and deionized water mixed in a ratio of 1:6 for 20-27 seconds of development to form a top gate pattern. Grow 10-100nm indium tin oxide (ITO) by magnetron sputtering with a sputtering power of 60W for 14 minutes. Soak the sample in acetone for 2 hours for stripping to remove the photoresist and ITO except for the top gate area. At this point, the ITO top gate electrode 6 is completed.

[0067] (10) Al on the source electrode 3 and drain electrode 5 of the sample obtained in step (9) 2 O 3 Removed by photolithography and ICP etching. Place the sample on a 110℃ heating table for 3 minutes, spin-coat AR-P-5350 photoresist, and bake it on a 110℃ heating table for 3 minutes. Then perform photolithography with an exposure time of 6-7.5 seconds. Then place the sample in a solution of AR300-26 and deionized water mixed in a volume ratio of 1:6 for 20-27 seconds of development to remove the photoresist outside the top gate area. Perform ICP etching on the sample to remove the Al outside the top gate area. 2 O 3 , etching gas is BCl 3 , flow rate is 15sccm, ICP power is 50W, RF power is 100W, time is 2 to 3min, the sample is immersed in acetone for 2h to remove the photoresist.

[0068] (11) Annealing: The sample obtained in step (10) was placed in an oxygen environment and annealed at 400°C for 1 hour.

[0069] (12) The sample obtained in step (11) is doped with ions by ion implantation. B or P is used to dope the IGZO that does not overlap with the source electrode 3, the drain electrode 5, and the top gate electrode 6 with an ion implantation amount of 10 14 -10 15 ions / cm 2 , energy is 10-50keV.

[0070] In some embodiments of the present invention, a chip is further provided, the chip comprising the above-mentioned multi-nanowire channel InGaZnO thin film transistor. The structure and principle of the multi-nanowire channel InGaZnO thin film transistor can be referred to above, and this embodiment will not be repeated here.

[0071] In some embodiments of the present invention, an electronic device is also provided, comprising the multi-nanowire channel InGaZnO thin film transistor. The structure and principle of the multi-nanowire channel InGaZnO thin film transistor can be referred to above, and this embodiment will not be repeated here.

[0072] In some embodiments, the electronic device may be a system-level application such as a power supply, a power management unit, a smart meter, an IoT meter, a fusion terminal, a feeder unit, a fault indicator, etc. A plurality of multi-nanowire channel InGaZnO thin film transistors may be used in the electronic device.

[0073] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A multi-nanowire channel indium gallium zinc oxide thin film transistor, characterized in that: include: substrate; A channel layer is formed on the substrate and is made of indium gallium zinc oxide; A source electrode, a top gate dielectric layer and a drain electrode are sequentially arranged on the channel layer in a lateral direction, and a top gate electrode is arranged on the top gate dielectric layer; The channel layer is provided with a plurality of spaced-apart lateral nanowire channels in the area outside the contact area with the source electrode and the drain electrode. The width of the nanowire channel is 1 to 5 times the thickness of the channel layer, and the spacing between two adjacent nanowire channels is 1 to 3 times the width of the nanowire channel.

2. The multi-nanowire channel InGaZnO thin film transistor according to claim 1, characterized in that: The top gate dielectric layer is separated from the source electrode and the drain electrode by a set distance; the source electrode and the drain electrode are arranged on both sides of the channel layer in the lateral direction.

3. The multi-nanowire channel InGaZnO thin film transistor according to claim 1, characterized in that: The lateral length of the nanowire channel is 10 nm to 6 μm; the thickness of the channel layer is 4 to 30 nm; the width of the nanowire channel is 10 to 50 nm; and the spacing between two adjacent nanowire channels is 10 to 150 nm.

4. The multi-nanowire channel InGaZnO thin film transistor according to claim 1, characterized in that: The source electrode and the drain electrode are made of indium tin oxide, tungsten or a composite material of the two; the top gate dielectric layer is made of SiO2 or Al2O3; and the top gate electrode is made of tungsten or indium tin oxide.

5. The multi-nanowire channel InGaZnO thin film transistor according to claim 1, characterized in that: The material of the substrate is SiO2; Alternatively, the substrate comprises a bottom gate electrode and a bottom gate dielectric layer, wherein the bottom gate electrode is made of p-type lightly doped silicon, and the bottom gate dielectric layer is made of SiO2 or Al2O3.

6. The multi-nanowire channel InGaZnO thin film transistor according to claim 1, characterized in that: The thickness of the source electrode and the drain electrode is 10-100 nm, the thickness of the bottom gate dielectric layer is 5-200 nm, the thickness of the top gate dielectric layer is 5-200 nm; the thickness of the top gate electrode is 10-100 nm.

7. The method for preparing a multi-nanowire channel InGaZnO thin film transistor according to any one of claims 1 to 6, characterized in that: The steps include: providing a substrate; forming a channel layer on the substrate; A source electrode and a drain electrode are arranged on the surface of the channel layer; and then a plurality of lateral nanowire channels are etched in the area outside the contact area between the channel layer and the source electrode and the drain electrode; Then, a top gate dielectric layer and a top gate electrode are sequentially formed on the surface of the channel layer between the source electrode and the drain electrode.

8. The preparation method according to claim 7, characterized in that: After forming the top gate electrode, ion implantation with B or P is performed on the surface of the channel layer where the surface is not in contact with the source electrode, the top gate dielectric layer and the drain electrode.

9. A chip, characterized in that: The chip comprises the multi-nanowire channel indium gallium zinc oxide thin film transistor according to any one of claims 1 to 6.

10. An electronic device, characterized in that: The electronic device comprises the multi-nanowire channel InGaZnO thin film transistor according to any one of claims 1 to 6.

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