Gate dielectric layer preparation method and semiconductor device preparation method
By using multiple nitriding and annealing treatment methods in semiconductor devices, the nitrogen doping concentration and depth are finely controlled, and the problem of inaccurate nitrogen doping control in the prior art is solved, which significantly improves the NBTI effect and reliability of the device.
Patent Information
- Application Number
- CN202510213934.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2025-05-16
AI Technical Summary
The prior art is difficult to accurately control the nitrogen doping concentration, resulting in excessively high or low nitrogen doping, affecting the NBTI effect and reliability of semiconductor devices.
By using at least two nitriding treatments and two annealing treatments, the nitrogen doping concentration and depth in the gate oxide layer are finely controlled by controlling the number of treatments and the parameters during each treatment.
The uniform distribution of nitrogen doping concentration and depth is achieved, the NBTI effect is effectively improved, and the long-term stability and reliability of semiconductor devices are improved.
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Figure CN120018565A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a gate dielectric layer and a method for preparing a semiconductor device. Background Art
[0002] As integrated circuit technology continues to develop towards sub-micron and even nanometer scales, traditional silicon oxide (SiO2) as a gate dielectric can no longer meet the requirements of device miniaturization and high performance. As the thickness of the gate oxide layer continues to decrease, the gate leakage current in semiconductor devices increases significantly, which has an adverse effect on the life, power consumption and thermal stability of the device. On the other hand, due to the decline in the ability of traditional polysilicon gates to suppress boron penetration, the use of SiO2 as a gate dielectric in low-dimensional devices faces serious reliability issues.
[0003] In order to solve the above problems, the relevant technology began to introduce nitrogen doping technology, by introducing an appropriate amount of nitrogen atoms in the gate oxide layer to form a SiOxNy structure, in order to improve the NBTI (Negative Bias Temperature Instability) effect of the device while taking into account the high dielectric constant and inhibiting boron penetration. However, nitrogen doping is not simply the more the better. Excessive or deep nitrogen doping will introduce more interface defects, which will in turn aggravate the NBTI effect.
[0004] Therefore, how to accurately control the nitrogen doping concentration is a technical problem existing in the related art.
[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0006] In view of the problems in the prior art, the purpose of the present invention is to provide a gate dielectric layer method and a semiconductor device preparation method, which overcomes the difficulties of the prior art and can accurately control the nitrogen doping concentration in the gate dielectric layer.
[0007] A first aspect of the present disclosure provides a method for preparing a gate dielectric layer, comprising:
[0008] generating a gate oxide layer on the substrate;
[0009] The substrate having the gate oxide layer is subjected to at least two of the following cyclic treatment steps:
[0010] Nitriding and annealing treatment.
[0011] In some embodiments, the substrate having the gate oxide layer is subjected to the following cyclic treatment steps twice:
[0012] A first nitridation treatment is performed to deposit nitrogen atoms on the surface of the gate oxide layer to form a nitrogen-doped layer;
[0013] Performing a first annealing treatment after the first nitridation treatment to repair interface defects of the gate oxide layer and reduce the nitrogen concentration of the nitrogen-doped layer;
[0014] The substrate after the first annealing treatment is subjected to a second nitridation treatment and a second annealing treatment to prevent nitrogen in the nitrogen-doped layer from escaping, thereby obtaining a gate oxide layer having the nitrogen-doped layer as the gate dielectric layer.
[0015] In some embodiments, the first nitridation treatment and the second nitridation treatment both use a radio frequency plasma nitridation process, the radio frequency power used in the radio frequency plasma nitridation process is 800W to 1200W, and the proportion of time that the radio frequency power is turned on is 30% to 52%.
[0016] In some embodiments, after the second nitridation treatment, the nitrogen doping concentration in the gate oxide layer is 10% to 25% and the depth does not exceed 0.8 nm.
[0017] In some embodiments, the first annealing process is performed under low oxygen conditions, and the second annealing process is performed under high oxygen conditions.
[0018] In some embodiments, in the first annealing process, the annealing temperature is 950° C. to 1150° C., and the annealing time is 10 seconds to 20 seconds.
[0019] In some embodiments, in the second annealing process, the annealing temperature is 950° C. to 1150° C., and the annealing time is 20 seconds to 30 seconds.
[0020] In some embodiments, the gate oxide layer is formed by a rapid thermal oxidation process and has a thickness of 2 nm to 3 nm.
[0021] In some embodiments, the substrate is a P-type substrate.
[0022] A second aspect of the present disclosure provides a method for preparing a semiconductor device, which comprises forming a gate dielectric layer using the method for preparing a gate dielectric layer according to any of the above embodiments.
[0023] The gate dielectric layer preparation method and semiconductor device preparation provided by the embodiments of the present disclosure have the following advantages:
[0024] Compared with a single nitridation and annealing treatment, this embodiment adopts a batch nitridation and annealing treatment after generating the gate oxide layer, so that the nitrogen doping concentration and depth in the gate oxide layer can be more finely controlled by controlling the number of treatments and / or the parameters in each treatment process, so that the distribution of nitrogen in the gate oxide layer is more uniform, avoiding the problem of excessive or insufficient local nitrogen concentration caused by a single treatment in the traditional process, effectively improving the NBTI effect, and making the performance of the semiconductor device remain stable for a long time under the conditions of high integration and low power consumption.
[0025] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Other features, objectives and advantages of the present invention will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following accompanying drawings.
[0027] Figure 1 A flow chart showing a method for preparing a gate dielectric layer provided in an embodiment of the present disclosure.
[0028] Figure 2-Figure 6 exhibit Figure 1 Schematic diagram of device structure at various stages of the gate dielectric layer preparation method shown. DETAILED DESCRIPTION
[0029] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0030] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.
[0031] In a related technology, the gate oxide layer is treated with a nitridation treatment and then repaired by rapid annealing. The nitridation treatment can control the concentration of nitrogen, and the nitrogen doping layer is concentrated on the surface of the gate oxide layer, so the NBTI effect can be improved. However, this method is difficult to accurately control the depth and concentration of nitrogen, and is prone to nitrogen escape or excessive doping depth, which in turn affects the stability of the gate dielectric layer and the long-term reliability of the device.
[0032] Therefore, there is currently no technology that can achieve precise control of nitrogen doping depth and concentration while ensuring good dielectric properties of the SiOxNy gate dielectric layer and inhibiting boron penetration, thereby achieving the goal of improving the NBTI effect. Therefore, how to achieve precise control of nitrogen in the gate oxide layer by improving the process flow based on existing technologies has become a technical problem that needs to be solved urgently in the industry.
[0033] The gate dielectric layer preparation method proposed in the embodiment of the present disclosure accurately controls the nitrogen doping depth and concentration in the gate oxide layer through at least two nitridation treatments and two annealing methods to solve the above-mentioned technical problems and improve the performance of semiconductor devices.
[0034] like Figure 1 As shown, the gate dielectric layer preparation method provided in the embodiment of the present disclosure includes but is not limited to the following steps:
[0035] Step 110: generating a gate oxide layer on the substrate;
[0036] Step 120: performing at least two of the following cyclic processing steps on the substrate having the gate oxide layer:
[0037] Nitriding and annealing treatment.
[0038] Compared with a single nitridation treatment and annealing treatment, the present embodiment adopts a batch nitridation treatment and annealing treatment after generating the gate oxide layer, so that the nitrogen doping concentration and depth in the gate oxide layer can be more finely controlled by controlling the number of treatments and / or the parameters in each treatment process, so that the distribution of nitrogen in the gate oxide layer 2 is more uniform, avoiding the problem of excessive or insufficient local nitrogen concentration caused by a single treatment in the traditional process, effectively improving the NBTI effect, and making the performance of the semiconductor device remain stable for a long time under the conditions of high integration and low power consumption.
[0039] The method for preparing a gate dielectric layer according to the disclosed embodiment is described in detail below by taking the above two processing steps on a substrate having a gate oxide layer as an example.
[0040] like Figure 2 As shown, a substrate 1 is provided and a gate oxide layer 2 is formed on the substrate 1 .
[0041] In the embodiment of the present disclosure, the substrate 1 provides a process operation basis for subsequent processes.
[0042] Optionally, the substrate 1 may be a third generation wide bandgap semiconductor material such as silicon carbide or gallium nitride. In other embodiments, the material of the substrate 1 may also be other materials such as silicon, germanium, silicon germanium, gallium arsenide or indium gallium, and the substrate 1 may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate 1 may be a material suitable for process requirements or easy to integrate.
[0043] In this embodiment, the substrate 1 used is a high-purity P-type substrate, and after pre-cleaning and removal of organic and metal contamination, the surface enters the following process flow. The gate dielectric layer preparation method of this embodiment can take into account both high dielectric constant and inhibition of boron penetration in the substrate 1, while improving the NBTI effect.
[0044] In the embodiment of the present disclosure, the gate oxide layer 2 is formed by a rapid thermal oxidation process. Optionally, the gate oxide layer 2 is formed by the following rapid thermal oxidation process, including the following steps:
[0045] In a Regenerative Thermal Oxidizer (RTO) furnace with a precise gas flow control system, a substrate 1 is placed into the furnace chamber;
[0046] Oxygen (O2) is introduced into the furnace chamber, and the temperature is raised to the target temperature, and the target temperature is maintained for a certain period of time, so that a SiO2 film with a thickness of 2 to 3 nm is grown on the surface of the substrate 1 as the gate oxide layer 2. This process makes the thickness of the gate oxide layer 2 uniform, and at the same time requires the gate oxide layer 2 to have good density to ensure the stability of the nitridation and annealing treatments in the subsequent processes.
[0047] After the gate oxide layer 2 is grown, the substrate 1 is quickly cooled to room temperature to ensure that no additional stress and lattice defects are introduced during the cooling process.
[0048] like Figure 3 As shown, a first nitridation treatment is performed on a substrate 1 having a gate oxide layer 2 , so that nitrogen atoms are deposited on the surface of the gate oxide layer 2 to form a nitrogen-doped layer 3 .
[0049] Compared with the one-time nitridation treatment in the prior art, the depth of the nitrogen-doped layer 3 after the first nitridation treatment in this embodiment is shallower. Optionally, the first nitridation treatment specifically includes:
[0050] The substrate 1 with the gate oxide layer 2 grown thereon is transferred into a decoupled plasma nitridation (DPN) chamber, which is a radio frequency (RF) plasma processing system having uniform plasma distribution and fast gas switching functions.
[0051] Nitrogen (N2) and / or ammonia (NH3) are introduced into the DPN chamber, and the RF power is set to 1000W, and the duty cycle of the RF power is set to 30%, and the surface nitridation treatment is performed at a relatively low temperature in the room. At this time, nitrogen atoms are adsorbed on the surface of the thin gate oxide layer 2 through ion bombardment plasma chemical reaction to form a preliminary nitrogen doping layer 3.
[0052] Since the first nitridation process mainly acts on the surface of the gate oxide layer 2, the nitrogen doped layer 3 formed is shallow, and its depth can be controlled within the range of 1 to 2 nm. After this step, the nitrogen content formed on the substrate 1 is concentrated in the upper region of the gate oxide layer 2.
[0053] In the above embodiment, the RF power is set to 1000W and the duty cycle is set to 30%, which is an optional example. In actual application, the first nitridation treatment adopts a radio frequency plasma nitridation process, and the radio frequency power used is 800W to 1200W, wherein the proportion of the time when the radio frequency power is turned on is 30% to 52%, which can be selected according to needs.
[0054] The above RF power range can ensure that the nitrogen plasma has sufficient energy to effectively excite and ionize the nitrogen source, thereby depositing an appropriate amount of nitrogen atoms on the surface of the gate oxide layer 2. The duty cycle controls the ratio of the RF power on time to the off time, while ensuring sufficient nitridation, avoiding excessive ion bombardment caused by long-term continuous exposure, thereby reducing damage to the gate oxide layer 2.
[0055] In the DPN process of the embodiment of the present disclosure, in addition to fixing the RF power and duty cycle, the flow rate of nitrogen (or ammonia) and the chamber pressure may also be adjusted to further improve the uniformity of the nitrogen-doped layer 3 .
[0056] like Figure 4 As shown, a first annealing treatment is performed after the first nitridation treatment to repair the interface defects of the gate oxide layer 2 and reduce the nitrogen concentration of the nitrogen-doped layer 3. Exemplarily, the first annealing treatment includes the following steps:
[0057] After the first nitridation treatment is completed, the substrate 1 is transferred to a PNA (Postnitridation Annealing) chamber to avoid the non-uniformity of nitrogen diffusion. The PNA chamber is a rapid annealing system with high temperature uniformity and rapid response capability of atmosphere switching.
[0058] In the PNA chamber, the substrate 1 is heated to 1100° C., and O 2 gas is introduced simultaneously to repair the lattice defects and surface defects in the thin gate oxide layer caused by ion bombardment during the first nitridation treatment.
[0059] The first annealing treatment in this step may cause partial dissipation of nitrogen in the nitrogen-doped layer 3 on the surface of the gate oxide layer 2, but it also plays a role in repairing SiO2 defects and improving the interface state density. After the first annealing treatment, although the nitrogen concentration in the nitrogen-doped layer 3 is reduced, the overall defect density is effectively improved, which is conducive to the further adjustment of the subsequent nitrogen doping depth and concentration.
[0060] In the embodiment of the present disclosure, the first annealing treatment is performed under low oxygen conditions, which is a low oxygen environment relative to the high oxygen conditions in the subsequent second annealing treatment process. The first annealing treatment adopts a low oxygen process, which can appropriately reduce the nitrogen concentration on the surface of the gate oxide layer 2, thereby avoiding the introduction of additional interface defects due to excessive nitrogen evaporation.
[0061] In an optional manner, during the first annealing process, the annealing temperature is 950° C. to 1150° C., and the annealing time is 10 seconds to 20 seconds. By controlling the annealing time and annealing temperature, atomic migration and interface defect repair are stimulated, and at the same time, the nitrogen concentration on the surface of the gate oxide layer 2 is appropriately reduced to avoid excessive nitrogen dissipation caused by high temperature or long-term annealing.
[0062] In actual testing, through rapid thermal annealing (RTA) experiments, combined with electrical performance and interface defect tests, the annealing conditions were optimized to determine that good defect repair effects and nitrogen concentration adjustment can be achieved within this temperature and time range.
[0063] like Figure 5 and Figure 6 As shown, the substrate 1 after the first annealing treatment is subjected to a second nitridation treatment and a second annealing treatment to prevent nitrogen in the nitrogen-doped layer 3 from escaping, thereby obtaining a gate oxide layer 2 having the nitrogen-doped layer 3 as the gate dielectric layer.
[0064] After the second nitridation treatment and the second annealing treatment, the nitrogen doping in the nitrogen-doped layer 3 on the surface of the gate oxide layer 2 is finely regulated.
[0065] For example, Figure 5 As shown, the second nitriding treatment includes the following steps:
[0066] After the first annealing treatment, the substrate 1 is quickly taken out of the PNA cavity and placed in the DPN cavity again. Since part of the nitrogen in the nitrogen-doped layer 3 has been dissipated in the first annealing treatment, the purpose of the second nitridation process is to replenish the surface nitrogen doping and make the nitrogen distribution reach the ideal concentration.
[0067] During the second nitridation process, the process parameters of RF power 1000W and duty cycle 30% are used to ensure that the nitridation treatment is roughly consistent with the first nitridation treatment. However, since the previous annealing has changed the surface state of the gate oxide layer 2, the second nitridation treatment can more evenly supplement the required nitrogen amount.
[0068] In this embodiment, by adjusting the second nitridation treatment time and the nitrogen flow rate, the increase in the overall nitrogen content in the nitrogen-doped layer 3 after the second nitridation treatment can be precisely controlled. The goal is to make the final SiOxNy layer in an ideal state in terms of nitrogen content distribution, without introducing excessive defects or losing the effect of suppressing the NBTI effect due to insufficient nitrogen.
[0069] In this embodiment, the second nitridation treatment adopts a radio frequency plasma nitridation process, and the radio frequency power used in the radio frequency plasma nitridation process is 800W to 1200W, wherein the proportion of time when the radio frequency power is turned on is 30% to 52%.
[0070] For example, Figure 6 As shown, the second annealing treatment includes the following steps:
[0071] After the second nitridation treatment, the substrate 1 is transferred to the PNA chamber again. In order to prevent the lattice defects newly introduced during the second nitridation treatment and the possible local uneven accumulation of nitrogen atoms, a second annealing treatment is performed for repair.
[0072] In the second annealing process, the substrate 1 is heated to 1100°C. Unlike the first annealing process, this annealing is performed under high oxygen conditions, and the oxygen flow rate is higher than that of the first annealing process. The higher oxygen content not only helps to more effectively repair the lattice damage caused by the second nitridation process, but also can inhibit the diffusion and escape of nitrogen atoms at high temperatures, ensuring that the depth and concentration of nitrogen in the gate oxide layer 2 are stably controlled.
[0073] In the second annealing process, the annealing temperature is 950° C. to 1150° C., and the annealing time is 20 seconds to 30 seconds. The annealing temperature in the second annealing process can be higher than that in the first annealing process, and the annealing time is longer than that in the first annealing process, so as to ensure that the gate oxide layer 2 structure achieves a sufficient repair effect in a high temperature, oxygen-rich atmosphere, promote the densification of the gate oxide layer 2, improve the quality of the oxide layer, reduce residual stress, reduce the interface state density, and improve the reliability of the STI structure.
[0074] In this embodiment, a higher annealing temperature and a shorter annealing time can quickly fix the nitrogen added in the second nitridation process in the gate oxide layer 2, and further repair local lattice defects to prevent nitrogen from escaping again. This can be achieved by comparing the nitrogen distribution after annealing and device stability testing under different annealing temperatures and annealing times, and selecting the best conditions for maintaining nitrogen concentration while minimizing negative diffusion effects.
[0075] In this embodiment, two nitridation treatments and two annealing treatments are performed to achieve fine control of nitrogen doping in the gate oxide layer 2. Experiments show that, compared with the conventional process of directly performing an annealing treatment after a single nitridation treatment, the present process can make the depth distribution of nitrogen in the final gate oxide layer 2 more concentrated in the surface 1-2 nm region under the same annealing temperature and overall treatment time, and the overall nitrogen concentration is also within the expected range.
[0076] Optionally, experimental data show that after the second nitridation treatment, the nitrogen doping concentration in the gate oxide layer 2 is 10% to 25% and the depth does not exceed 0.8nm, which is in line with expectations. This ensures that a sufficiently thin and uniform nitrogen doping layer 3 is formed on the surface of the gate oxide layer 2, which helps to improve interface passivation and suppress the NBTI effect, while avoiding excessive nitrogen doping or excessive diffusion, thereby maintaining the dielectric properties and stability of the SiOxNy layer.
[0077] In actual testing, characterization tests (such as SIMS, CV, DLTS, etc.) and device reliability tests are performed to find the optimal balance point of device performance under the above nitrogen doping concentration and depth.
[0078] In the embodiments of the present disclosure, for different types of semiconductor devices, the required gate dielectric layer thickness and nitrogen doping requirements may be different. The method of the present invention can flexibly control the depth and concentration of the nitrogen-doped layer 3 by adjusting the parameters of each step according to the actual process requirements. For example, in the case of requiring a higher dielectric constant, the processing time of the second nitridation treatment can be appropriately increased. In devices with higher requirements for the interface state, the annealing time can be extended in the annealing process to fully repair the defects.
[0079] The disclosed embodiment adopts at least two nitridation processes and two annealing processes with different oxygen contents, so that the distribution of nitrogen in the gate oxide layer 2 is more uniform, avoiding the problem of excessive or insufficient local nitrogen concentration caused by a single treatment in the traditional process. By rationally designing the annealing process, the lattice defects introduced by the nitridation process can be repaired, and the excessively fast dissipation of nitrogen can be suppressed, ensuring that the final nitrogen content reaches the ideal control level.
[0080] In addition, while ensuring the dielectric properties of the SiOxNy layer and inhibiting boron penetration, the process of this embodiment also significantly reduces the NBTI effect, improves the service life and reliability of the device, and at the same time, the rapid conversion and parameter optimization between the above steps achieve high repeatability and stability in mass production, and has good prospects for industrial application.
[0081] The above-mentioned gate dielectric layer preparation method of the embodiment of the present disclosure can be used for the preparation method of a semiconductor device, and the semiconductor device includes a gate dielectric layer prepared by the above-mentioned method. Wherein, the semiconductor device can be a metal oxide semiconductor field effect transistor (MOSFET), and the gate dielectric layer is located between the substrate and the gate.
[0082] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.
Claims
1. A method for preparing a gate dielectric layer, characterized in that: include: generating a gate oxide layer on the substrate; The substrate having the gate oxide layer is subjected to at least two of the following cyclic treatment steps: Nitriding and annealing treatment.
2. The method for preparing a gate dielectric layer according to claim 1, characterized in that: The substrate having the gate oxide layer is subjected to the following cyclic treatment steps twice: A first nitridation treatment is performed to deposit nitrogen atoms on the surface of the gate oxide layer to form a nitrogen-doped layer; Performing a first annealing treatment after the first nitridation treatment to repair interface defects of the gate oxide layer and reduce the nitrogen concentration of the nitrogen-doped layer; The substrate after the first annealing treatment is subjected to a second nitridation treatment and a second annealing treatment to prevent nitrogen in the nitrogen-doped layer from escaping, thereby obtaining a gate oxide layer having the nitrogen-doped layer as the gate dielectric layer.
3. The method for preparing a gate dielectric layer according to claim 2, characterized in that: The first nitridation treatment and the second nitridation treatment both adopt a radio frequency plasma nitridation process, the radio frequency power used in the radio frequency plasma nitridation process is 800W to 1200W, and the proportion of time that the radio frequency power is turned on is 30% to 52%.
4. The method for preparing a gate dielectric layer according to claim 3, characterized in that: After the second nitridation treatment, the nitrogen doping concentration in the gate oxide layer is 10% to 25% and the depth does not exceed 0.8 nm.
5. The method for preparing a gate dielectric layer according to claim 2, characterized in that: The first annealing treatment is performed under low oxygen conditions, and the second annealing treatment is performed under high oxygen conditions.
6. The method for preparing a gate dielectric layer according to claim 5, characterized in that: In the first annealing process, the annealing temperature is 950° C. to 1150° C., and the annealing time is 10 seconds to 20 seconds.
7. The method for preparing a gate dielectric layer according to claim 5, characterized in that: In the second annealing process, the annealing temperature is 950° C. to 1150° C., and the annealing time is 20 seconds to 30 seconds.
8. The method for preparing a gate dielectric layer according to claim 1, characterized in that: The gate oxide layer is formed by a rapid thermal oxidation process and has a thickness of 2nm to 3nm.
9. The method for preparing a gate dielectric layer according to claim 1, characterized in that: The substrate is a P-type substrate.
10. A method for preparing a semiconductor device, characterized in that: The method comprises forming the gate dielectric layer by using the gate dielectric layer preparation method according to any one of claims 1 to 9.