Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a forming method thereof, and the forming method comprises the steps: providing a substrate which comprises a first region and a second region which is connected with the first region in a surrounding manner; sequentially forming a first source electrode layer, a first source channel layer, a first channel layer and a first channel drain layer which are stacked in the first region; forming a first gate dielectric layer surrounding and covering the side walls of the first source channel layer, the first channel layer and the first channel drain layer in the second region; forming a first gate structure layer surrounding and covering the first gate dielectric layer; sequentially forming a first drain layer, a sacrificial layer, a second source layer, a second source channel layer, a second channel layer and a second channel drain layer which are stacked on the first channel drain layer; forming a second gate dielectric layer surrounding and covering the side walls of the second source channel layer, the second channel layer and the second channel drain layer in the second region; forming a second gate structure layer surrounding and covering the second gate dielectric layer; and forming a second drain layer covering the second trench drain layer. By adopting the forming method, the on-state current of the semiconductor transistor can be further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Semiconductor transistors are one of the most important components in modern integrated circuits. The basic structure of a transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, wherein the gate structure includes a gate dielectric layer located on the surface of the semiconductor substrate and a gate layer located on the surface of the gate dielectric layer; source and drain doped regions in the semiconductor substrate on both sides of the gate structure; and a semiconductor channel located between the source and drain doped regions.

[0003] However, the existing transistor structure has a limitation in improving the on-state current of the transistor and cannot further improve the on-state current of the semiconductor transistor. Summary of the invention

[0004] The technical problem solved by the present invention is to further improve the on-state current of a semiconductor transistor by providing a semiconductor structure and a forming method thereof.

[0005] In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, including a first region, and a second region surrounding and connected to the first region; forming a stacked first source layer, a first source trench layer, a first channel layer and a first trench drain layer in the first region; forming a first gate dielectric layer surrounding and covering the side walls of the first source trench layer, the first channel layer and the first trench drain layer in the second region; forming a first gate structure layer surrounding and covering the first gate dielectric layer; forming a stacked first drain layer, a sacrificial layer, a second source layer, a second source trench layer, a second channel layer and a second trench drain layer in the first trench drain layer; forming a second gate dielectric layer surrounding and covering the side walls of the second source trench layer, the second channel layer and the second trench drain layer in the second region; forming a second gate structure layer surrounding and covering the second gate dielectric layer; forming a second drain layer covering the second trench drain layer.

[0006] Optionally, along a direction perpendicular to the surface of the substrate, the side walls of the first source layer, the first source trench layer, the first channel layer, the first trench drain layer, the first drain layer, the sacrificial layer, the second source layer, the second source trench layer, the second channel layer, the second trench drain layer and the second drain layer are flush.

[0007] Optionally, the material of the first source trench layer includes silicon germanium, the material of the first trench drain layer includes silicon germanium, the material of the second source trench layer includes silicon carbide, the material of the second trench drain layer includes silicon carbide, and the material of the sacrificial layer includes silicon germanium.

[0008] Optionally, after forming the first drain layer and before forming the first gate dielectric layer, the formation method further includes: forming a first filling layer on the substrate of the second region, the first filling layer covering the side walls of the first source layer, the first source trench layer, the first channel layer and the first drain layer; removing a portion of the first filling layer to expose the side walls of the first source trench layer, the first channel layer and the first drain layer to form a first filling layer trench; the first filling layer trench includes: first filling layer trench side walls opposite to the side walls of the first source trench layer, the first channel layer and the first drain layer, and first filling layer trench bottom.

[0009] Optionally, a first gate dielectric layer is formed in the first filling layer trench to surround and cover the sidewalls of the first source trench layer, the first channel layer, and the first drain layer; the first gate dielectric layer also covers the bottom and sidewalls of the first filling layer trench.

[0010] Optionally, after forming the first filling layer trench and before forming the first gate dielectric layer, the forming method further includes: forming a first metal layer covering the surface of the first filling layer and the first drain layer outside the first filling layer trench.

[0011] Optionally, the first gate structure layer is filled in the first filling layer trench, and the first gate structure layer surrounds and covers the first gate dielectric layer.

[0012] Optionally, the formation method further includes: forming a first thin layer covering the surface of the first gate structure layer; the first thin layer also covers the first filling layer.

[0013] Optionally, after forming the second drain layer and before forming the second gate dielectric layer, the formation method further includes: forming a second filling layer on the first thin layer, the second filling layer covering the side walls of the first drain layer, the sacrificial layer, the second source layer, the second source trench layer, the second channel layer and the second drain layer; removing a portion of the second filling layer to expose the side walls of the sacrificial layer, the second source layer, the second source trench layer, the second channel layer and the second drain layer to form a second filling layer groove, and removing the sacrificial layer to form a first spacer between the first drain layer and the second source layer.

[0014] Optionally, a third filling layer is filled in the second filling layer groove and the first interval; a portion of the third filling layer is removed to expose the side walls of the second source trench layer, the second channel layer, and the second trench drain layer to form a third filling layer groove; the third filling layer groove includes: third filling layer groove side walls opposite to the side walls of the second source trench layer, the second channel layer, and the second trench drain layer, and a third filling layer groove bottom.

[0015] Optionally, a second gate dielectric layer is formed in the third filling layer trench to surround and cover the side walls of the second source trench layer, the second channel layer, and the second drain layer; the second gate dielectric layer also covers the bottom and side walls of the third filling layer trench.

[0016] Optionally, after forming the third filling layer trench and before forming the second gate dielectric layer, the forming method further includes: forming a second metal layer covering surfaces of the second filling layer and the second drain layer outside the third filling layer trench.

[0017] Optionally, the second gate structure layer is filled in the third filling layer trench, and the second gate structure layer surrounds and covers the second gate dielectric layer.

[0018] Optionally, the formation method further includes: after forming the second gate structure layer and before forming the second drain layer, forming a second thin layer on the surface of the second gate structure layer, wherein the second thin layer also covers the second filling layer.

[0019] Optionally, an interlayer dielectric layer covering the second thin layer and the second drain layer is formed; a first source layer via hole is formed that penetrates the interlayer dielectric layer, the second drain layer, the second drain layer, the second channel layer, the second source layer, the second source layer, the third filling layer, the first drain layer, the first drain layer, the first channel layer and the first source layer; a first channel layer via hole is formed that penetrates the interlayer dielectric layer, the second drain layer, the second channel layer, the second source layer, the second source layer, the third filling layer, the first drain layer and the first drain layer; a first drain layer via hole is formed that penetrates the interlayer dielectric layer, the second drain layer, the second channel layer, the second source layer, the second source layer and the third filling layer; a second source layer via hole is formed that penetrates the interlayer dielectric layer, the second drain layer, the second channel layer, the second source layer and the second source layer; a second channel layer via hole is formed that penetrates the interlayer dielectric layer, the second drain layer, the second drain layer and the second channel layer; a second channel layer via hole is formed that penetrates the interlayer dielectric layer, the second drain layer and the second drain layer; a second drain layer via in the dielectric layer; forming a first gate structure layer via penetrating the interlayer dielectric layer, the second thin layer, the second filling layer and the first thin layer; forming a second gate structure layer via penetrating the interlayer dielectric layer and the second thin layer; forming a via isolation layer covering the side walls of the first source layer via, the first channel layer via, the first drain layer via, the second source layer via, the second channel layer via and the second drain layer via; forming a first source layer plug filling the first source layer via; forming a first channel layer plug filling the first channel layer via; forming a first drain layer plug filling the first drain layer via; forming a second source layer plug filling the second source layer via; forming a second channel layer plug filling the second channel layer via; forming a second drain layer plug filling the second drain layer via; forming a first gate structure layer plug filling the first gate structure layer via; forming a second gate structure layer plug filling the second gate structure layer via.

[0020] Optionally, the formation methods all adopt an epitaxial process to form the first source layer, the first source trench layer, the first channel layer, the first trench drain layer, the first drain layer, the second source layer, the second source trench layer, the second channel layer and the second trench drain layer.

[0021] Optionally, the parameters of the epitaxial process include: a temperature between 600 degrees Celsius and 800 degrees Celsius.

[0022] Optionally, the parameters of the epitaxial process include at least one of the following: pressure of 70 Torr to 90 Torr; flow rate of Purge MainH2 of 3200 sccm to 3800 sccm; flow rate of Purge SlitH2 of 80 sccm to 120 sccm; flow rate of silicon source gas of 120 sccm to 180 sccm; and epitaxial rate of 200 angstroms / minute to 300 angstroms / minute.

[0023] Correspondingly, the present application also provides a semiconductor structure, including: a substrate, including a first region, a second region connected to the first region in a surrounding manner; a first source layer, a first source trench layer, a first channel layer and a first trench drain layer stacked in sequence in the first region; a first gate dielectric layer, located in the second region and surrounding and covering the side walls of the first source trench layer, the first channel layer and the first trench drain layer; a first gate structure layer, surrounding and covering the first gate dielectric layer; a first drain layer, a second source layer, a second source trench layer, a second channel layer and a second trench drain layer stacked in sequence on the first trench drain layer; a second gate dielectric layer, located in the second region and surrounding and covering the side walls of the second source trench layer, the second channel layer and the second trench drain layer; a second gate structure layer, surrounding and covering the second gate dielectric layer; and a second drain layer, located on the second trench drain layer.

[0024] Optionally, along a direction perpendicular to the surface of the substrate, the side walls of the first source layer, the first source trench layer, the first channel layer, the first trench drain layer, the first drain layer, the second source layer, the second source trench layer, the second channel layer, the second trench drain layer and the second drain layer are flush.

[0025] Optionally, the semiconductor structure further includes: a first filling layer, located in the second region, and along a surface direction parallel to the substrate, the first filling layer is flush with the surface of the first trench and drain layer; a first filling layer groove, located in the first filling layer, the first filling layer groove exposing the side walls of the first source trench layer, the first channel layer, and the first trench and drain layer; the first filling layer groove includes: the side walls of the first filling layer groove opposite to the side walls of the first source trench layer, the first channel layer, and the first trench and drain layer, and the bottom of the first filling layer groove; the first gate dielectric layer is located in the first filling layer groove, surrounding and covering the side walls of the first source trench layer, the first channel layer, and the first trench and drain layer; the first gate dielectric layer also covers the side walls of the first filling layer groove and the bottom of the first filling layer groove; a first gate structure layer is filled in the first filling layer groove, and surrounding and covering the first gate dielectric layer.

[0026] Optionally, the semiconductor structure further includes: a first thin layer covering the surface of the first filling layer and the first gate structure layer; a second filling layer located in the second region, and along a surface direction parallel to the substrate, the second filling layer is flush with the surface of the second drain layer in the first region; a first spacer located between the first drain layer and the second source layer; a second filling layer groove located in the second filling layer, the second filling layer groove exposing the sidewalls of the second source layer, the second source groove layer, the second channel layer, the second drain layer and the first spacer; a third filling layer filled in the first spacer and also filled in a portion of the second filling layer groove to form a first Three filling layer grooves, the third filling layer groove exposes the side walls of the second source groove layer, the second channel layer and the second drain layer; the third filling layer groove includes: the side walls of the third filling layer groove opposite to the side walls of the second source groove layer, the second channel layer and the second drain layer, and the bottom of the third filling layer groove; the second gate dielectric layer is located in the third filling layer groove, surrounding and covering the side walls of the second source groove layer, the second channel layer and the second drain layer; the second gate dielectric layer also covers the side walls of the third filling layer groove and the bottom of the third filling layer groove; the second gate structure layer is filled in the third filling layer groove, and surrounding and covering the second gate dielectric layer.

[0027] Optionally, the semiconductor structure further includes: a second thin layer covering the surfaces of the second filling layer and the second gate structure layer; and an interlayer dielectric layer covering the surfaces of the second thin layer and the second drain layer.

[0028] Optionally, the semiconductor structure further includes: a first source layer via hole: penetrating the interlayer dielectric layer, the second drain layer, the second drain trench layer, the second channel layer, the second source trench layer, the second source layer, the third filling layer, the first drain layer, the first drain trench layer, the first channel layer and the first source trench layer; a first channel layer via hole penetrating the interlayer dielectric layer, the second drain layer, the second drain trench layer, the second channel layer, the second source trench layer, the second source layer, the third filling layer, the first drain layer, the first drain trench layer; a first drain layer via hole penetrating the interlayer dielectric layer, the second drain layer, the second drain trench layer, the second channel layer, the second source trench layer, the second source layer, the third filling layer, the first drain layer, the first drain trench layer; The interlayer dielectric layer, the second drain layer, the second trench layer, the second channel layer, the second source trench layer, the second source layer, and the third filling layer; the second source layer via hole penetrates the interlayer dielectric layer, the second drain layer, the second trench layer, the second channel layer, and the second source trench layer; the second channel layer via hole penetrates the interlayer dielectric layer, the second drain layer, and the second trench layer; the second drain layer via hole penetrates the interlayer dielectric layer; the via isolation layer covers the first source layer via hole, the first channel layer via hole, the first drain layer via hole, the second source layer via hole, and the second source layer. The first gate structure layer via hole penetrates the interlayer dielectric layer, the second thin layer, the second filling layer and the first thin layer; the second gate structure layer via hole penetrates the interlayer dielectric layer and the second thin layer; the first source layer plug is filled in the first source layer via hole and contacts the first source layer; the first channel layer plug is filled in the first channel layer via hole and contacts the first channel layer; the first drain layer plug is filled in the first drain layer via hole and contacts the first drain layer A drain layer is in contact; a second source layer plug is filled in the second source layer via hole and in contact with the second source layer; a second channel layer plug is filled in the second channel layer via hole and in contact with the second channel layer; a second drain layer plug is filled in the second drain layer via hole and in contact with the second drain layer; a first gate structure layer plug is filled in the first gate structure layer via hole and in contact with the first gate structure layer; a second gate structure layer plug is filled in the second gate structure layer via hole and in contact with the second gate structure layer.

[0029] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages: A method for forming a semiconductor structure provided by an embodiment of the present invention comprises: providing a substrate, the substrate comprising a first region; sequentially forming a stacked first source layer, a first source trench layer, a first channel layer and a first trench drain layer in the first region, and sequentially forming a stacked first drain layer, a second source layer, a second source trench layer, a second channel layer and a second trench drain layer on the first trench drain layer; one type of carrier of the semiconductor structure flows from the first source layer through the first source trench layer, the first channel layer and the first trench drain layer to the first drain layer in a direction perpendicular to the surface of the substrate, and another type of carrier of the semiconductor structure flows from the second source layer through the second source trench layer, the second channel layer and the second trench drain layer to the second drain layer; in a direction perpendicular to the surface of the substrate, the thickness of the first channel layer corresponds to the channel length of one type of carrier, and the thickness of the second channel layer corresponds to the channel length of another type of carrier, and the thickness of the first channel layer and the second channel layer can be reduced by a film forming process to reduce the channel length of the carrier, thereby further improving the on-state current of the semiconductor transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0031] Figure 1 It is a schematic diagram of the structure of a semiconductor transistor; Figures 2 to 22 It is a structural schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] As described in the background technology, the existing transistor structure has the problem of limited increase in transistor on-state current. Figure 1 The transistor structure is shown, and the reasons why the on-state current increase of the transistor is limited are analyzed.

[0034] refer to Figure 1 , is a schematic diagram of the structure of a semiconductor transistor.

[0035] The structure of the semiconductor transistor comprises: Semiconductor substrate 100 .

[0036] The gate structure is located on the surface of the semiconductor substrate 100 , and the gate structure includes a gate dielectric layer 101 located on the surface of the semiconductor substrate 100 and a gate layer 102 located on the surface of the gate dielectric layer.

[0037] A source doped region 103 and a drain doped region 104 are located on the semiconductor substrate at both sides of the gate structure.

[0038] A semiconductor channel 105 is located between the source doping region 103 and the drain doping region 104 .

[0039] Continue to refer Figure 1 The carriers of the semiconductor structure flow from the source doping region 103 to the drain doping region 104 along a direction F parallel to the surface of the semiconductor substrate 100. The displacement of the carriers is L, and the length of the semiconductor channel 105 is L. The length L determines the on-state current of the semiconductor transistor.

[0040] In order to increase the on-state current of the semiconductor transistor, the usual practice is to reduce the semiconductor channel length L through an exposure process along a direction parallel to the surface of the semiconductor substrate 100. However, the resolution (minimum resolvable feature size) of the lithography machine is limited, and the reduction of the semiconductor channel length L is limited, so that the increase in the on-state current of the transistor is limited, that is, the on-state current of the semiconductor transistor cannot be further increased.

[0041] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, the formation method comprising: providing a substrate, including a first region, and a second region surrounding and connected to the first region, sequentially forming a stacked first source layer, a first source trench layer, a first channel layer and a first trench drain layer in the first region, forming a first gate dielectric layer surrounding and covering the side walls of the first source trench layer, the first channel layer and the first trench drain layer in the second region, forming a first gate structure layer surrounding and covering the first gate dielectric layer, sequentially forming a stacked first drain layer, a sacrificial layer, a second source layer, a second source trench layer, a second channel layer and a second trench drain layer on the first trench drain layer, forming a second gate dielectric layer surrounding and covering the side walls of the second source trench layer, the second channel layer and the second trench drain layer in the second region; forming a second gate structure layer surrounding and covering the second gate dielectric layer, and forming a second drain layer covering the second trench drain layer, thereby further improving the on-state current of the semiconductor transistor.

[0042] By adopting the semiconductor structure formation method provided by the embodiment of the present invention, one type of carrier of the semiconductor structure flows from the first source layer through the first source trench layer, the first channel layer and the first trench drain layer to the first drain layer in a direction perpendicular to the surface of the substrate, and another type of carrier of the semiconductor structure flows from the second source layer through the second source trench layer, the second channel layer and the second trench drain layer to the second drain layer; in a direction perpendicular to the surface of the substrate, the thickness of the first channel layer corresponds to the channel length of one type of carrier, and the thickness of the second channel layer corresponds to the channel length of another type of carrier, and the thickness of the first channel layer and the second channel layer can be reduced by a film forming process to reduce the channel length of the carriers, thereby further improving the on-state current of the semiconductor transistor.

[0043] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0044] refer to Figures 2 to 22 , is a schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present invention, wherein: Figure 2 is a schematic top view of a semiconductor structure according to an embodiment of the present invention, Fig. 20 for Figure 2 The cross-sectional view along the A1A2 direction, Fig.21 for Figure 2 The cross-sectional view along the B1B2 direction, Fig. 22 for Figure 2 Cross-sectional view along C1C2 direction.

[0045] refer to Figure 3 , providing a substrate 200 , wherein the substrate 200 includes a first area 201 and a second area 202 surrounding and connected to the first area 201 .

[0046] The first area 201 includes a first area outer edge (not shown), the second area 202 includes a second area inner edge (not shown), the second area inner edge is connected to the first area outer edge, the second area 202 surrounds the first area 201, so that the second area 202 is surrounded and adjacent to the first area 201. In some embodiments, the second area 202 is surrounded and adjacent to the first area 201 to form a "U" shape. In other embodiments, the second area 202 is surrounded and adjacent to the first area 201 to form a "U" shape, but this is not intended to limit the present application.

[0047] The substrate 200 is used to provide a process platform for the formation of a semiconductor structure, that is, the substrate 200 is used to form a first semiconductor device and a second semiconductor device stacked on the first semiconductor device. The types of the first semiconductor device include: PMOS transistor or NMOS transistor, and the types of the second semiconductor device include: PMOS transistor or NMOS transistor. In this embodiment, the first semiconductor device is a PMOS transistor, and the second semiconductor device is an NMOS transistor. The transistor types of the first semiconductor device and the second semiconductor device stacked on the substrate 200 can be selected according to actual needs and are not limited to this application. In some embodiments, the first semiconductor device is an NMOS transistor and the second semiconductor device is a PMOS transistor, or the first semiconductor device is a PMOS transistor and the second semiconductor device is a PMOS transistor, or the first semiconductor device is an NMOS transistor and the second semiconductor device is an NMOS transistor.

[0048] In this embodiment, the substrate 200 is a silicon substrate 200, and the material of the substrate 200 is single crystal silicon. In other embodiments, the material of the substrate 200 can also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium, and the substrate 200 can also be a silicon substrate 200 on an insulator or a germanium substrate 200 on an insulator, and other types of substrates 200. In other embodiments, an epitaxial layer (not shown) having the same crystal structure as the substrate 200 can also be formed on the surface of the substrate 200 to improve the quality of pattern transfer.

[0049] refer to Figure 4 A first source layer 300 , a first source trench layer 301 , a first channel layer 302 and a first drain trench layer 303 are sequentially stacked in the first region 201 .

[0050] The first source layer 300 is used as a source of the first semiconductor device.

[0051] The first channel layer 302 is used as a channel of the first semiconductor device.

[0052] The first source trench layer 301 is used as a barrier layer (also referred to as a first barrier layer) between the first source layer 300 and the first channel layer 302, and can effectively prevent the mutual diffusion of doped ions in the first channel layer 302 and the doped ions in the first source layer 300, thereby improving the reliability and stability of the semiconductor device.

[0053] The first drain layer 303 is used as the first channel layer 302 and the first drain layer 310 (see Fig. 9) between the first drain layer 310 and the first channel layer 302, can effectively prevent the doped ions in the first drain layer 310 and the doped ions in the first channel layer 302 from diffusing with each other, thereby improving the reliability and stability of the semiconductor device.

[0054] In this embodiment, along a direction perpendicular to the surface of the substrate 200, the carriers of the first semiconductor device flow from the first source layer 300 to the first drain layer 310 through the first source trench layer 301, the first channel layer 302 and the first trench drain layer 303. That is, the channel length of the first semiconductor device is the thickness of the first channel layer 302. Compared with the exposure process of the lithography machine, a first channel layer 302 with a smaller thickness can be formed through a chemical vapor deposition process or an epitaxial process, thereby reducing the flow path of the carriers of the first semiconductor device and further improving the on-state current of the semiconductor transistor.

[0055] In this embodiment, the first source layer 300, the first source trench layer 301, the first channel layer 302, and the first drain trench layer 303 are formed by an epitaxial process, and doping treatment is performed during the epitaxial growth process, wherein each layer has its own doping type and doping concentration.

[0056] In this embodiment, the main process steps of sequentially forming the stacked first source layer 300, the first source trench layer 301, the first channel layer 302 and the first drain trench layer 303 on the first region 201 of the substrate 200 along a direction perpendicular to the surface of the substrate 200 are as follows: A material layer (not shown) of the first source layer 300 is formed on the substrate 200 by epitaxy and phosphorus ion doping processes, wherein the material of the first source layer 300 is silicon, and the doping concentration of the first source layer 300 can be 1E 14 atom / cm 3 To 1E 15 atom / cm 3 , the thickness of the first source layer 300 may be 500 angstroms to 1000 angstroms.

[0057] By epitaxial process, a material layer (not shown) of the first source trench layer 301 is formed on the first source layer 300, wherein the material of the first source trench layer 301 is silicon germanium (SiGe), and the thickness of the first source trench layer 301 may be 500 angstroms to 1000 angstroms. In other embodiments, the material of the first source trench layer 301 may be one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0058] A material layer (not shown) of the first channel layer 302 is formed on the first source channel layer 301 by epitaxy and boron ion doping processes, wherein the material of the first channel layer 302 is silicon, and the doping concentration of the first channel layer 302 can be 1E 12 atom / cm 3 To 1E 13 atom / cm 3 , the thickness of the first channel layer 302 may be greater than or equal to 20 angstroms.

[0059] By epitaxial process, a material layer (not shown) of the first channel layer 303 is formed on the first channel layer 302, wherein the material of the first channel layer 303 is silicon germanium (SiGe), and the thickness of the first channel layer 303 may be 500 angstroms to 1000 angstroms. In other embodiments, the material of the first channel layer 303 may be one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0060] In this embodiment, the epitaxial process may include an atomic layer deposition process or a molecular beam epitaxy process.

[0061] In this embodiment, the materials, doping concentrations, doping ion types and thicknesses of the first source layer 300 , the first source trench layer 301 , the first channel layer 302 and the first drain trench layer 303 can be selected according to actual needs, and the present application is not limited thereto.

[0062] The parameters of the epitaxial process include: a temperature between 600 degrees Celsius and 800 degrees Celsius. In this embodiment, the formation temperature of the first source layer 300, the first source trench layer 301, the first channel layer 302 and the first trench drain layer 303 is between 600 degrees Celsius and 800 degrees Celsius, which can reduce or avoid the mutual diffusion phenomenon between the carriers in the first source layer 300, the first source trench layer 301, the first channel layer 302 and the first trench drain layer 303, so that each layer maintains its own characteristics and improves the performance of the semiconductor structure.

[0063] The parameters of the epitaxial process include at least one of the following: Pressure is 70 Torr to 90 Torr; The flow rate of Purge MainH2 is 3200sccm to 3800sccm; The flow rate of Purge SlitH2 is 80 sccm to 120 sccm; The flow rate of the silicon source gas is 120 sccm to 180 sccm; The epitaxial growth rate is 200 angstroms / minute to 300 angstroms / minute.

[0064] In this embodiment, the parameters of the epitaxial process for forming the first source layer 300, the first source trench layer 301, the first channel layer 302 and the first trench drain layer 303 also include: a pressure of 70 Torr to 90 Torr (the pressure in the epitaxial reaction chamber); a flow rate of Purge MainH2 of 3200 sccm to 3800 sccm; a flow rate of Purge SlitH2 of 80 sccm to 120 sccm; a flow rate of the silicon source gas of 120 sccm to 180 sccm; and an epitaxial rate of 200 angstroms / minute to 300 angstroms / minute, so as to achieve high quality (e.g., fewer film pores, higher density, purer film quality, better film thickness uniformity, etc.) of the first source layer 300, the first source trench layer 301, the first channel layer 302 and the first trench drain layer 303.

[0065] The Purge MainH2 (Purge Main Hydrogen: Purge MainH2) is to purge the main hydrogen, and the purge of the main hydrogen has the following beneficial effects: First, as a diluent.

[0066] Hydrogen can also be used as a diluent to reduce the concentration of reactive gases (such as silicon source gas), control the reaction rate and the growth rate of the film layer, and thus control the thickness and doping concentration of the film.

[0067] Second, protect the atmosphere.

[0068] Hydrogen can prevent the epitaxial film from being oxidized or contaminated by other gases during the growth process.

[0069] The Purge SlitH2 (Purge Slit Hydrogen: Purge SlitH2) is a hydrogen purge for slits, which has the following beneficial effects: First, clean the reaction chamber.

[0070] By flushing the gaps in the reaction chamber with hydrogen, particulate matter, byproducts and residues that may be produced during the growth process can be removed, helping to maintain the cleanliness of the reaction chamber and preventing these impurities from affecting the subsequent epitaxial film growth quality.

[0071] Second, prevent cross contamination.

[0072] Flushing the gaps in the reaction chamber between different batches of epitaxial growth can avoid cross-contamination between different materials or dopants and ensure the purity and consistency of each batch of epitaxial films.

[0073] Third, extend the life of equipment.

[0074] Regular crevice flushing can reduce corrosion and wear inside the epitaxial reactor, thereby extending the life of the equipment and reducing maintenance costs.

[0075] By exposure, development, etching and other processes or laser cutting process, the material layer of the first source layer 300, the material layer of the first source trench layer 301, the material layer of the first channel layer 302, and the material layer of the first trench drain layer 303 of the second area 202 are removed to form a stacked first source layer 300, a first source trench layer 301, a first channel layer 302 and a first trench drain layer 303 in the first area 201 in sequence.

[0076] Continue to refer Figure 4 After forming the first drain layer 303 and before forming the first gate dielectric layer 307, the formation method further includes: forming a first filling layer 304 on the substrate 200 of the second region 202, wherein the first filling layer 304 covers the side walls of the first source layer 300, the first source drain layer 301, the first channel layer 302 and the first drain layer 303.

[0077] The first filling layer 304 has the following beneficial effects: First, to form the first gate dielectric layer 307 (see Figure 7 ) and the first gate structure layer 308 (see Figure 7 ) provides process space.

[0078] Second, it is used to electrically isolate semiconductor devices and prevent electrical interference between different regions. The material of the first filling layer 304 includes one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the first filling layer 304 is silicon oxide.

[0079] In this embodiment, a chemical vapor deposition process is used to form a first filling material layer (also referred to as a first filling layer 304 ) on the substrate 200 . The first filling material layer covers the second region 202 and the surface of the first drain layer 303 .

[0080] The first drain layer 303 is used as a stop layer, and the first filling material layer is subjected to a first planarization treatment to form a first filling layer 304 on the substrate 200 of the second region 202 , wherein the first filling layer 304 covers the side walls of the first source layer 300 , the first source drain layer 301 , the first channel layer 302 and the first drain layer 303 .

[0081] refer to Figure 5 , a portion of the first filling layer 304 is removed to expose the sidewalls of the first source trench layer 301 , the first channel layer 302 , and the first drain layer 303 to form a first filling layer trench 305 .

[0082] The first filling layer trench 305 is used to subsequently form a first gate dielectric layer 307 (see Figure 7 ) and the first gate structure layer 308 (see Figure 7 ) provides the process basis.

[0083] In this embodiment, a portion of the first filling layer 304 is removed by processes such as exposure, development, and etching to expose the sidewalls of the first source trench layer 301, the first channel layer 302, and the first drain layer 303 to form a first filling layer trench 305; a portion of the sidewalls of the first source layer 300 is also exposed. The first filling layer trench 305 includes: first filling layer trench sidewalls opposite to the sidewalls of the first source trench layer 301, the first channel layer 302, and the first drain layer 303, and the first filling layer trench bottom.

[0084] refer to Figure 6 After forming the first filling layer trench 305 and before forming the first gate dielectric layer 307 , the formation method further includes: forming a first metal layer 306 covering the surface of the first filling layer 304 and the first drain layer 303 outside the first filling layer trench 305 .

[0085] The first metal layer 306 has the following beneficial effects: First, as a barrier layer (also called the third barrier layer).

[0086] The first metal layer 306 can block the material of the subsequently formed first gate structure layer 308 from diffusing into the first drain layer 303 in a direction perpendicular to the substrate surface, affecting the performance of the first drain layer 303 and thus affecting the stability and reliability of the first semiconductor device.

[0087] Second, reduce stress.

[0088] The first metal layer 306 , as a buffer layer, can reduce the stress between the first gate structure layer 308 and the first drain layer 303 to be formed subsequently, thereby improving the reliability of the first semiconductor device.

[0089] The material of the first metal layer 306 includes titanium nitride (TiN) and tantalum nitride (TaN). In this embodiment, the material of the first metal layer 306 is titanium nitride (TiN).

[0090] The process for forming the first metal layer 306 includes: one or more of physical vapor deposition, chemical vapor deposition and atomic layer deposition processes. In this embodiment, a first metal material layer (also referred to as the first metal layer 306) (not shown) covering the substrate 200 is formed by a physical vapor deposition process. The first metal material layer covers the side walls of the first source trench layer 301, the first channel layer 302 and the first drain layer 303, and also covers the side walls of the first filling layer trench, the bottom of the first filling layer trench and the surface of the first filling layer 304.

[0091] For the first metal material layer, through exposure, development, etching and other processes, a first metal layer 306 covering the surface of the first filling layer 304 and the first trench leakage layer 303 is formed outside the first filling layer groove 305, that is, the first metal layer 306 covers the surface of the first filling layer 304 and the surface of the first trench leakage layer 303.

[0092] It should be noted that the first metal layer 306 cannot be used as a limitation of the present application, and whether the first metal layer 306 is needed can be selected according to actual needs. In other embodiments, the first metal layer 306 may not be formed.

[0093] Continue to refer Figure 6 A first gate dielectric layer 307 is formed in the second region 202 to surround and cover the side walls of the first source trench layer 301 , the first channel layer 302 and the first drain trench layer 303 .

[0094] The first gate dielectric layer 307 , as an electrical insulating material, electrically isolates the subsequently formed first gate structure layer 308 from the first source layer 300 , the first source trench layer 301 , the first channel layer 302 , the first trench drain layer 303 and the first drain layer 310 of the first semiconductor device.

[0095] The material of the first gate dielectric layer 307 includes: one or more of silicon oxide and a high dielectric constant gate dielectric layer material. The silicon oxide has good insulation, coverage and stability. In this embodiment, the material of the first gate dielectric layer 307 is silicon oxide.

[0096] The first gate dielectric layer 307 is made of silicon oxide and has a thickness in a range of greater than or equal to 50 nanometers and less than or equal to 200 nanometers.

[0097] By making the film thickness of silicon oxide greater than or equal to 50 nanometers, a good electrical insulation and isolation effect can be achieved; by making the film thickness of silicon oxide less than or equal to 200 nanometers, the process manufacturing cycle can be reduced and the characteristics of the semiconductor device can be guaranteed.

[0098] It should be noted that the high dielectric constant gate dielectric layer material includes a dielectric material having a dielectric constant greater than the dielectric constant of silicon oxide (3.9); the high dielectric constant gate dielectric layer material includes one or more of hafnium oxide, zirconium oxide, hafnium silicon oxide, hafnium oxynitride, hafnium silicon oxynitride, hafnium tantalum oxynitride, zirconium oxynitride, zirconium silicon oxynitride, zirconium silicon oxide, lanthanum oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, and strontium titanium oxide. Preferably, the dielectric constant of the high dielectric constant gate dielectric layer material is greater than 8, so as to reduce the thickness of the first gate dielectric layer 307 and improve the performance of the transistor.

[0099] The process of forming the first gate dielectric layer 307 includes: one or more of a chemical vapor deposition process, a furnace process and an atomic layer deposition process.

[0100] In this embodiment, the main process steps for forming the first gate dielectric layer 307 surrounding and covering the sidewalls of the first source trench layer 301 , the first channel layer 302 , and the first drain trench layer 303 in the second region 202 are as follows: A first gate dielectric material layer (also referred to as the first gate dielectric layer 307 ) (not shown) is formed on the substrate 200 by a chemical vapor deposition process, and the first gate dielectric material layer covers the first metal layer 306 and the first filling layer trench.

[0101] The first gate dielectric material layer is subjected to exposure, development, etching and other processes to form a first gate dielectric layer 307 in the first filling layer groove 305, which surrounds and covers the side walls of the first source trench layer 301, the first channel layer 302 and the first drain layer 303. The first gate dielectric layer 307 also covers the bottom of the first filling layer groove and the side walls of the first filling layer groove.

[0102] refer to Figure 7 , forming a first gate structure layer 308 surrounding and covering the first gate dielectric layer 307 .

[0103] The first gate structure layer 308 is used to control the on and off of the first semiconductor device.

[0104] The material of the first gate structure layer 308 includes: one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC).

[0105] In this embodiment, the material of the first gate structure layer 308 is titanium nitride (TiN).

[0106] The process of forming the first gate structure layer 308 includes: one or more of physical vapor deposition, chemical vapor deposition and atomic layer deposition. In this embodiment, the first gate structure layer 308 surrounding and covering the first gate dielectric layer 307 is formed by a physical vapor deposition process.

[0107] In this embodiment, the main process steps for forming the first gate structure layer 308 surrounding and covering the first gate dielectric layer 307 include: A first gate structure material layer (also referred to as the first gate structure layer 308 ) (not shown) is formed on the substrate 200 by a physical vapor deposition process, and the first gate structure material layer covers the first metal layer 306 and fills the first filling layer trench.

[0108] With the first drain layer 303 as a stop layer, the first gate structure material layer is subjected to a second planarization treatment to remove the first metal layer 306, a portion of the first gate dielectric layer 307 in the first filling layer groove 305, and a portion of the first gate structure material layer, so as to fill the first filling layer groove 305 to form the first gate structure layer 308, thereby forming a first gate structure layer 308 surrounding and covering the first gate dielectric layer 307, and at the same time making the first gate structure layer 308, the first drain layer 303, the top of the first gate dielectric layer 307 and the surface of the first filling layer 304 located at the same level.

[0109] refer to Figure 8 , forming a first thin layer 309 covering the surface of the first gate structure layer 308 .

[0110] The first thin layer 309 is used to protect the first gate structure layer 308 .

[0111] The material of the first thin layer 309 includes: one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the first thin layer 309 is silicon oxide.

[0112] In this embodiment, the main process steps for forming the first thin layer 309 covering the surface of the first gate structure layer 308 include: A first thin layer 309 material layer (also referred to as the first thin layer 309 ) is formed on the substrate 200 by chemical vapor deposition process, and the first thin layer 309 material layer covers the surfaces of the first drain layer 303 , the first gate structure layer 308 , the first gate dielectric layer 307 and the first filling layer 304 .

[0113] The material layer of the first thin layer 309 is subjected to processes such as exposure, development, and etching to form the first thin layer 309 covering the surface of the first gate structure layer 308 . The first thin layer 309 also covers the first filling layer 304 .

[0114] It should be noted that the first thin layer 309 cannot be used as a limitation of the present application. Whether the first thin layer 309 is required can be selected according to actual needs. In some embodiments, the first thin layer 309 is not formed, and the second filling layer 404 (see Fig. 9 ) is directly formed to cover the first filling layer 304, the surface of the first gate structure layer 308 and the top end surface of the first gate dielectric layer 307.

[0115] refer to Fig. 9 A first drain layer 310 , a sacrificial layer 311 , a second source layer 400 , a second source trench layer 401 , a second channel layer 402 and a second drain layer 403 are sequentially stacked on the first drain trench layer 303 .

[0116] The first drain electrode layer 310 is used as a drain electrode of the first semiconductor device.

[0117] The sacrificial layer 311 is used to subsequently form a third filling layer 407 between the first drain layer 310 and the second source layer 400 (see Fig.11 ) provide space.

[0118] The second source layer 400 is used as a source of the second semiconductor device.

[0119] The second channel layer 402 is used as a channel of the second semiconductor device.

[0120] The second source trench layer 401 is used as a barrier layer (also referred to as a fourth barrier layer) between the second source layer 400 and the second channel layer 402, and can effectively prevent the mutual diffusion of doped ions in the second channel layer 402 and the doped ions in the second source layer 400, thereby improving the reliability and stability of the semiconductor device.

[0121] The second drain layer 403 is used as the second channel layer 402 and the second drain layer 413 (see Fig.15 ) between the second drain layer 413 and the second channel layer 402 can effectively prevent the mutual diffusion of doped ions in the second drain layer 413 and the doped ions in the second channel layer 402, thereby improving the reliability and stability of the semiconductor device.

[0122] In this embodiment, along a direction perpendicular to the surface of the substrate 200, the carriers of the second semiconductor device flow from the second source layer 400 through the second source trench layer 401, the second channel layer 402 and the second trench drain layer 403 to the second drain layer 413, that is, the channel length of the second semiconductor device is the thickness of the second channel layer 402. Compared with the exposure process of the lithography machine, a second channel layer 402 with a smaller thickness can be formed through a chemical vapor deposition process or an epitaxial process, thereby reducing the flow path of the carriers of the second semiconductor device and further improving the on-state current of the semiconductor transistor.

[0123] In this embodiment, an epitaxial process is used to form the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source trench layer 401, the second channel layer 402 and the second trench drain layer 403, and during the epitaxial growth process, doping treatment is performed, wherein each layer has its own doping type and doping concentration.

[0124] In this embodiment, the main process steps of sequentially forming the stacked first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source trench layer 401, the second channel layer 402 and the second trench drain layer 403 in the first region 201 are as follows: A material layer (not shown) of the first drain electrode layer 310 is formed on the first drain layer 303 by epitaxy and phosphorus ion doping process, wherein the material of the first drain electrode layer 310 is silicon, and the doping concentration of the first drain electrode layer 310 can be 1E 14 atom / cm 3 To 1E 15 atom / cm 3 , the thickness of the first drain layer 310 may be 500 angstroms to 1000 angstroms.

[0125] By epitaxial process, a material layer (not shown) of the sacrificial layer 311 is formed on the first drain layer 310, wherein the material of the sacrificial layer 311 is silicon germanium (SiGe), and the thickness of the sacrificial layer 311 may be 500 angstroms to 1000 angstroms. In other embodiments, the material of the sacrificial layer 311 may be one or more of silicon nitride, silicon oxide, and silicon oxynitride, and the sacrificial layer is formed by chemical vapor deposition process.

[0126] A material layer (not shown) of the second source layer 400 is formed on the sacrificial layer 311 by epitaxy and boron ion doping processes, wherein the material of the second source layer 400 is silicon, and the doping concentration of the second source layer 400 may be 1E 14 atom / cm 3 To 1E 15 atom / cm 3, the thickness of the second source layer 400 can be 500 angstroms to 1000 angstroms.

[0127] By epitaxial process, a material layer (not shown) of the second source trench layer 401 is formed on the second source layer 400, wherein the material of the second source trench layer 401 is silicon carbide (SiC), and the thickness of the second source trench layer 401 may be 500 angstroms to 1000 angstroms. In other embodiments, the material of the second source trench layer 401 may be one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0128] A material layer (not shown) of the second channel layer 402 is formed on the second source channel layer 401 by epitaxy and phosphorus ion doping processes, wherein the material of the second channel layer 402 is silicon, and the doping concentration of the second channel layer 402 can be 1E 12 atom / cm 3 To 1E 13 atom / cm 3 , the thickness of the second channel layer 402 may be greater than or equal to 20 angstroms.

[0129] By epitaxial process, a material layer (not shown) of the second drain layer 403 is formed on the second channel layer 402, wherein the material of the second drain layer 403 is silicon carbide (SiC), and the thickness of the second drain layer 403 may be 500 angstroms to 1000 angstroms. In other embodiments, the material of the second source trench layer 401 may be one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0130] In this embodiment, the epitaxial process may include an atomic layer deposition process or a molecular beam epitaxy process.

[0131] In this embodiment, the materials, doping concentrations, doping ion types and thicknesses of the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source trench layer 401, the second channel layer 402 and the second trench drain layer 403 can be selected according to actual needs, and the present application is not limited thereto.

[0132] The parameters of the epitaxial process include: a temperature between 600 degrees Celsius and 800 degrees Celsius. In this embodiment, the formation temperature of the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source trench layer 401, the second channel layer 402 and the second trench drain layer 403 is between 600 degrees Celsius and 800 degrees Celsius, which can reduce or avoid the mutual diffusion phenomenon between the carriers in the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source trench layer 401, the second channel layer 402 and the second trench drain layer 403, so that each layer maintains its own characteristics and improves the performance of the semiconductor structure.

[0133] The parameters of the epitaxial process include at least one of the following: Pressure is 70 Torr to 90 Torr; The flow rate of Purge MainH2 is 3200sccm to 3800sccm; The flow rate of Purge SlitH2 is 80 sccm to 120 sccm; The flow rate of the silicon source gas is 120 sccm to 180 sccm; The epitaxial growth rate is 200 angstroms / minute to 300 angstroms / minute.

[0134] In this embodiment, the parameters of the epitaxial process for forming the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source trench layer 401, the second channel layer 402 and the second trench drain layer 403 also include: a pressure of 70 Torr to 90 Torr (the pressure in the epitaxial reaction chamber); a flow rate of Purge MainH2 of 3200 sccm to 3800 sccm; a flow rate of Purge SlitH2 of 80 sccm to 120 sccm; a flow rate of the silicon source gas of 120 sccm to 180 sccm; and an epitaxial rate of 200 angstroms / minute to 300 angstroms / minute, so as to achieve high quality (e.g., fewer film pores, higher density, purer film quality, better film thickness uniformity, etc.) of the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source trench layer 401, the second channel layer 402 and the second trench drain layer 403.

[0135] The Purge MainH2 (Purge Main Hydrogen: Purge MainH2) is to purge the main hydrogen, and the purge of the main hydrogen has the following beneficial effects: First, as a diluent.

[0136] Hydrogen can also be used as a diluent to reduce the concentration of reactive gases (such as silicon source gas), control the reaction rate and the growth rate of the film layer, and thus control the thickness and doping concentration of the film.

[0137] Second, protect the atmosphere.

[0138] Hydrogen can prevent the epitaxial film from being oxidized or contaminated by other gases during the growth process.

[0139] The Purge SlitH2 (Purge Slit Hydrogen: Purge SlitH2) is a hydrogen purge for slits, which has the following beneficial effects: Second, clean the reaction chamber.

[0140] By flushing the gaps in the reaction chamber with hydrogen, particulate matter, byproducts and residues that may be produced during the growth process can be removed, helping to maintain the cleanliness of the reaction chamber and preventing these impurities from affecting the subsequent epitaxial film growth quality.

[0141] Second, prevent cross contamination.

[0142] Flushing the gaps in the reaction chamber between different batches of epitaxial growth can avoid cross-contamination between different materials or dopants and ensure the purity and consistency of each batch of epitaxial films.

[0143] Third, extend the life of equipment.

[0144] Regular crevice flushing can reduce corrosion and wear inside the epitaxial reactor, thereby extending the life of the equipment and reducing maintenance costs.

[0145] By exposure, development, etching and other processes or laser cutting process, the material layer of the first drain layer 310, the material layer of the sacrificial layer 311, the material layer of the second source layer 400, the material layer of the second source trench layer 401, the material layer of the second channel layer 402 and the material layer of the second trench drain layer 403 of the second area 202 are removed to form a stacked first drain layer 310, a sacrificial layer 311, a second source layer 400, a second source trench layer 401, a second channel layer 402 and a second trench drain layer 403 in the first area 201 in sequence.

[0146] Continue to refer Fig. 9 After forming the second drain layer 403 and before forming the second gate dielectric layer 410, the formation method further includes: forming a second filling layer 404 on the first thin layer 309, and the second filling layer 404 covers the side walls of the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source drain layer 401, the second channel layer 402 and the second drain layer 403.

[0147] The second filling layer 404 has the following beneficial effects: First, to form the second gate dielectric layer 410 (see Fig.14 ) and the second gate structure layer 411 (see Fig.14 ) provides process space.

[0148] Second, it is used to isolate semiconductor devices and prevent electrical interference between different areas.

[0149] The material of the second filling layer 404 includes: one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the second filling layer 404 is silicon oxide.

[0150] In this embodiment, the main process steps of forming the second filling layer 404 on the first thin layer 309 include: A second filling material layer (also referred to as a second filling layer 404 ) is formed on the substrate 200 by a chemical vapor deposition process, and the second filling material layer covers the first thin layer 309 , the second drain layer 403 , the first drain layer 310 , the sacrificial layer 311 , the second source layer 400 , the second source trench layer 401 , the second channel layer 402 , and the sidewalls of the second drain layer 403 .

[0151] With the second drain layer 403 as a stop layer, the second filling material layer is subjected to a third planarization treatment to form a second filling layer 404 on the first thin layer 309, wherein the second filling layer 404 covers the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source drain layer 401, the second channel layer 402 and the side walls of the second drain layer 403, and the second filling layer 404 and the surface of the second drain layer 403 are located on the same horizontal plane.

[0152] refer to Fig.10 , a portion of the second filling layer 404 is removed to expose the side walls of the sacrificial layer 311, the second source layer 400, the second source trench layer 401, the second channel layer 402 and the second drain layer 403 to form a second filling layer trench 405, and the sacrificial layer 311 is removed to form a first spacer 406 located between the first drain layer 310 and the second source layer 400.

[0153] The second filling layer groove 405 is used to form a third filling layer 407 (see Fig.11 ) provides location space.

[0154] The first spacer 406 is used to provide a space for forming a third filling layer 407 between the first semiconductor device and the second semiconductor device.

[0155] In this embodiment, a portion of the second filling layer 404 is removed through processes such as exposure, development, and etching to expose the side walls of the sacrificial layer 311, the second source layer 400, the second source trench layer 401, the second channel layer 402, and the second drain layer 403 to form a second filling layer trench 405.

[0156] The sacrificial layer 311 is removed by a dry etching process to form a first spacer 406 between the first drain layer 310 and the second source layer 400 .

[0157] refer to Fig.11 , a third filling layer 407 is filled in the second filling layer groove 405 and the first space 406 .

[0158] The third filling layer 407 in the first spacer 406 is used to electrically isolate the first semiconductor device from the second semiconductor device.

[0159] The third filling layer 407 in the second filling layer trench 405 is used to cover the sidewalls of the second source layer 400 , the second source trench layer 401 , the second channel layer 402 and the second drain layer 403 .

[0160] The material of the third filling layer 407 includes: one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the first filling layer 304 is silicon oxide.

[0161] In this embodiment, a chemical vapor deposition process is used to form a third filling material layer (also referred to as a third filling layer 407 ) on the substrate 200 . The third filling material layer fills the second filling layer groove 405 and the first spacer 406 , and also covers the first thin layer 309 and the second drain layer 403 .

[0162] The third filling material layer is subjected to a fourth planarization process using the second drain layer 403 as a stop layer, so as to fill the second filling layer trench 405 and the first space 406 with a third filling layer 407 .

[0163] refer to Fig.12 , a portion of the third filling layer 407 is removed to expose the sidewalls of the second source trench layer 401 , the second channel layer 402 , and the second drain layer 403 to form a third filling layer trench 408 .

[0164] The third filling layer trench 408 is used to provide a process basis for subsequently forming a second gate dielectric layer 410 and a second gate structure layer 411 .

[0165] In this embodiment, a portion of the third filling layer 407 is removed by exposure, development, etching and other processes to expose the sidewalls of the second source trench layer 401 , the second channel layer 402 , and the second drain layer 403 to form a third filling layer trench 408 .

[0166] In this embodiment, the third filling layer trench 408 includes: a third filling layer trench sidewall opposite to the sidewalls of the second source trench layer 401 , the second channel layer 402 , and the second drain layer 403 , and a third filling layer trench bottom.

[0167] refer to Fig.13 After forming the third filling layer trench 408 and before forming the second gate dielectric layer 410 , the formation method further includes: forming a second metal layer 409 covering the surfaces of the second filling layer 404 and the second drain layer 403 outside the third filling layer trench 408 .

[0168] The second metal layer 409 has the following beneficial effects: First, as a barrier layer (also called the sixth barrier layer).

[0169] The second metal layer 409 can prevent the material of the subsequently formed second gate structure layer 411 from diffusing into the second drain layer 403 in a direction perpendicular to the substrate surface, thereby affecting the performance of the second drain layer 403 and thus affecting the stability and reliability of the second semiconductor device.

[0170] Second, reduce stress.

[0171] The second metal layer 409 , as a buffer layer, can reduce the stress between the second gate structure layer 411 and the second drain layer 403 to be formed subsequently, thereby improving the reliability of the second semiconductor device.

[0172] The material of the second metal layer 409 includes titanium nitride (TiN) and tantalum nitride (TaN). In this embodiment, the material of the second metal layer 409 is titanium nitride (TiN).

[0173] The process for forming the second metal layer 409 includes: one or more of physical vapor deposition, chemical vapor deposition and atomic layer deposition processes. In this embodiment, a second metal material layer (also referred to as the second metal layer 409) (not shown) covering the substrate 200 is formed by a physical vapor deposition process. The second metal material layer covers the side walls of the second source trench layer 401, the second channel layer 402 and the second trench drain layer 403, and also covers the side walls and bottom of the third filling layer trench and the surface of the second filling layer 404.

[0174] The second metal material layer is subjected to processes such as exposure, development, and etching to form a second metal layer 409 outside the third filling layer trench 408 to cover the surfaces of the second filling layer 404 and the second drain layer 403 .

[0175] It should be noted that the second metal layer 409 cannot be used as a limitation of the present application, and whether the second metal layer 409 is needed can be selected according to actual needs. In other embodiments, the second metal layer 409 may not be formed.

[0176] Continue to refer Fig.13 A second gate dielectric layer 410 is formed in the second region 202 to surround and cover the side walls of the second source trench layer 401 , the second channel layer 402 and the second drain trench layer 403 .

[0177] The second gate dielectric layer 410, as an electrical insulating material, is formed by the second gate structure layer 411 (see Fig.16) and the second source layer 400, the second source trench layer 401, the second channel layer 402, the second trench drain layer 403 and the second drain layer 413 of the second semiconductor device (see Fig.16 ) for electrical isolation.

[0178] The material of the second gate dielectric layer 410 includes: one or more of silicon oxide and a high dielectric constant gate dielectric layer material. The silicon oxide has good insulation, coverage and stability. In this embodiment, the material of the second gate dielectric layer 410 is silicon oxide.

[0179] The second gate dielectric layer 410 is silicon oxide and has a thickness in a range of greater than or equal to 50 nanometers and less than or equal to 200 nanometers.

[0180] By making the film thickness of silicon oxide greater than or equal to 50 nanometers, a good electrical insulation and isolation effect can be achieved; by making the film thickness of silicon oxide less than or equal to 200 nanometers, the process manufacturing cycle can be reduced and the characteristics of the semiconductor device can be guaranteed.

[0181] It should be noted that the high dielectric constant gate dielectric layer material includes a dielectric material having a dielectric constant greater than the dielectric constant of silicon oxide (3.9); the high dielectric constant gate dielectric layer material includes one or more of hafnium oxide, zirconium oxide, hafnium silicon oxide, hafnium oxynitride, hafnium silicon oxynitride, hafnium tantalum oxynitride, zirconium oxynitride, zirconium silicon oxynitride, zirconium silicon oxide, lanthanum oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, and strontium titanium oxide. Preferably, the dielectric constant of the high dielectric constant gate dielectric layer material is greater than 8, so as to reduce the thickness of the second gate dielectric layer 410 and improve the performance of the transistor.

[0182] The process of forming the second gate dielectric layer 410 includes: one or more of a chemical vapor deposition process, a furnace process and an atomic layer deposition process.

[0183] In this embodiment, the main process steps for forming the second gate dielectric layer 410 surrounding and covering the sidewalls of the second source trench layer 401 , the second channel layer 402 , and the second drain trench layer 403 in the second region 202 are as follows: A second gate dielectric material layer (also referred to as the second gate dielectric layer 410 ) is formed on the substrate 200 by a chemical vapor deposition process, and the second gate dielectric material layer covers the second metal layer 409 and the third filling layer trench 408 .

[0184] For the second gate dielectric material layer, exposure, development, etching and other processes are used to form a second gate dielectric layer 410 in the third filling layer groove 408, which surrounds and covers the side walls of the second source trench layer 401, the second channel layer 402, and the second drain layer 403. The second gate dielectric layer 410 also covers the bottom and side walls of the third filling layer trench.

[0185] refer to Fig.14 , forming a second gate structure layer 411 surrounding and covering the second gate dielectric layer 410 .

[0186] The second gate structure layer 411 is used to control the turning on and off of the second semiconductor device.

[0187] The material of the second gate structure layer 411 includes: one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC).

[0188] In this embodiment, the material of the second gate structure layer 411 is titanium nitride (TiN).

[0189] The process of forming the second gate structure layer 411 includes: one or more of physical vapor deposition, chemical vapor deposition and atomic layer deposition. In this embodiment, the second gate structure layer 411 surrounding and covering the second gate dielectric layer 410 is formed by a physical vapor deposition process.

[0190] In this embodiment, the main process steps for forming the second gate structure layer 411 surrounding and covering the second gate dielectric layer 410 include: A second gate structure material layer (also referred to as the second gate structure layer 411 ) (not shown) is formed on the substrate 200 by a physical vapor deposition process, and the second gate structure material layer covers the second metal layer 409 and fills the third filling layer trench 408 .

[0191] With the second drain layer 403 as a stop layer, the second gate structure material layer is subjected to a fifth planarization treatment to remove the second metal layer 409, a portion of the second gate structure material layer in the third filling layer groove 408, and a portion of the second gate dielectric layer 410 to form the second gate structure layer 411 in the third filling layer groove 408, thereby forming a second gate structure layer 411 surrounding and covering the second gate dielectric layer 410, and at the same time making the second gate structure layer 411, the second drain layer 403, the top of the second gate dielectric layer 410 and the surface of the second filling layer 404 at the same level.

[0192] refer to Fig.15 The formation method further includes: after forming the second gate structure layer 411 and before forming the second drain layer 413 , forming a second thin layer 412 on the surface of the second gate structure layer 411 .

[0193] The second thin layer 412 is used to protect the second gate structure layer 411 .

[0194] The material of the second thin layer 412 includes: one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the second thin layer 412 is silicon oxide.

[0195] In this embodiment, the main process steps for forming the second thin layer 412 covering the surface of the second gate structure layer 411 include: A second thin layer 412 of material is formed on the substrate 200 by chemical vapor deposition, and the second thin layer 412 of material covers the second drain layer 403 , the second gate structure layer 411 , the second gate dielectric layer 410 and the second filling layer 404 .

[0196] The material layer of the second thin layer 412 is subjected to processes such as exposure, development, and etching to form a second thin layer 412 covering the surface of the second gate structure layer 411 . The second thin layer 412 also covers the second filling layer 404 .

[0197] It should be noted that the second thin layer 412 cannot be used as a limitation of the present application. Whether the second thin layer 412 is required can be selected according to actual needs. In some embodiments, the second thin layer 412 is not formed, and the interlayer dielectric layer 414 (see Fig.16 ) is directly formed to cover the second filling layer 404, the surface of the second gate structure layer 411 and the top end surface of the second gate dielectric layer 410.

[0198] Continue to refer Fig.15 , forming a second drain layer 413 covering the second drain layer 403 .

[0199] The second drain electrode layer 413 is used as a drain electrode of the second semiconductor device.

[0200] The second drain layer 413 may be processed according to the epitaxial growth and doping process parameters of the second source layer 400 , which will not be elaborated here.

[0201] It should be noted that, in some embodiments, along the direction perpendicular to the surface of the substrate 200, the side walls of the first source layer 300, the first source trench layer 301, the first channel layer 302, the first trench drain layer 303, the first drain layer 310, the sacrificial layer 311, the second source layer 400, the second source trench layer 401, the second channel layer 402, the second trench drain layer 403 and the second drain layer 413 are flush, and each of the above-mentioned film layers has four side walls, namely, a front side wall, a rear side wall, a left side wall and a right side wall. The front side wall of each film layer is located on the front side, the rear side wall of each film layer is located on the rear side, the left side wall of each film layer is located on the left side, and the right side wall of each film layer is located on the right side.

[0202] The first gate dielectric layer 307 is formed in the second region 202 to surround and cover the front side walls, rear side walls and left side walls of the first source trench layer 301, the first channel layer 302 and the first trench drain layer 303. The second gate dielectric layer 410 is formed in the second region 202 to surround and cover the front side walls, rear side walls and left side walls of the second source trench layer 401, the second channel layer 402 and the second trench drain layer 403.

[0203] It should be noted that the reference Fig.10 When forming the first spacer 406, a second filling layer 404 is formed on the right side walls of each film layer of the first drain layer 310, the second source layer 400, the second source trench layer 401, the second channel layer 402, and the second trench drain layer 403 to support the above-mentioned film layers.

[0204] In other embodiments, the number of sidewalls of each film layer can be designed according to actual needs, and this is not intended to limit the present application.

[0205] refer to Fig.16 , forming an interlayer dielectric layer 414 covering the second thin layer 412 and the second drain layer 413 .

[0206] The interlayer dielectric layer 414 has the following beneficial effects: First, electrical isolation: The interlayer dielectric layer 414 isolates different metal layers (such as interconnects) to avoid short circuits caused by direct contact between metal layers, thereby reducing electromagnetic interference (crosstalk) between signal lines and improving signal transmission quality.

[0207] Second, parasitic capacitance is reduced. By using low dielectric constant materials, the interlayer dielectric layer 414 can reduce the parasitic capacitance between metal layers.

[0208] Third, planarization: The interlayer dielectric layer 414 is planarized by chemical mechanical polishing and other processes, providing a good foundation for the subsequent deposition and photolithography of metal layers.

[0209] The material of the interlayer dielectric layer 414 includes: one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 414 is silicon oxide.

[0210] In this embodiment, the main process steps for forming the interlayer dielectric layer 414 covering the second thin layer 412 and the second drain electrode layer 413 include: An interlayer dielectric material layer (also referred to as an interlayer dielectric layer 414 ) is formed on the substrate 200 by a chemical vapor deposition process. The interlayer dielectric material layer covers the surfaces of the second thin layer 412 and the second drain electrode layer 413 to form the interlayer dielectric layer 414 .

[0211] refer to Figures 17 to 19 , forming a first source layer via hole 500 (see FIG. 5 ) penetrating the interlayer dielectric layer 414, the second drain layer 413, the second drain layer 403, the second channel layer 402, the second source layer 401, the second source layer 400, the third filling layer 407, the first drain layer 310, the first drain layer 303, the first channel layer 302 and the first source layer 301 Fig.19 ); forming a first channel layer via hole 501 penetrating through the interlayer dielectric layer 414, the second drain layer 413, the second drain layer 403, the second channel layer 402, the second source trench layer 401, the second source layer 400, the third filling layer 407, the first drain layer 310, and the first drain layer 303 (see Fig.17 ); forming a first drain layer via hole 502 penetrating the interlayer dielectric layer 414, the second drain layer 413, the second drain layer 403, the second channel layer 402, the second source trench layer 401, the second source layer 400, and the third filling layer 407 (see Fig.18 ); forming a second source layer via hole 503 penetrating the interlayer dielectric layer 414, the second drain layer 413, the second drain layer 403, the second channel layer 402, and the second source trench layer 401 (see Fig.19 ); forming a second channel layer via hole 504 penetrating the interlayer dielectric layer 414, the second drain layer 413, and the second drain layer 403 (see Fig.17 ); forming a second drain layer via hole 505 penetrating the interlayer dielectric layer 414 ( Fig.18 ); forming a first gate structure layer via hole 506 (see FIG. 5 ) penetrating the interlayer dielectric layer 414, the second thin layer 412, the second filling layer 404 and the first thin layer 309 Fig.17 ); forming a second gate structure layer via hole 507 penetrating the interlayer dielectric layer 414 and the second thin layer 412 (see Fig.17 ).

[0212] Combined with reference Figure 20 to Figure 22 The first source layer via 500 is used to provide a position space for the first source layer plug 600; the first channel layer via 501 is used to provide a position space for the first channel layer plug 601; the first drain layer via 502 is used to provide a position space for the first drain layer plug 602; the second source layer via 503 is used to provide a position space for the second source layer plug 603; the second channel layer via 504 is used to provide a position space for the second channel layer plug 604; the second drain layer via 505 is used to provide a position space for the second drain layer plug 605; the first gate structure layer via 506 is used to provide a position space for the first gate structure layer plug 606; the second gate structure layer via 507 is used to provide a position space for the second gate structure layer plug 607.

[0213] The first source layer via 500, the first channel layer via 501, the first drain layer via 502, the second source layer via 503, the second channel layer via 504, the second drain layer via 505, the first gate structure layer via 506, and the second gate structure layer via 507 can be formed respectively through independent exposure, development, etching and other processes, that is, 8 independent exposure, development, etching and other processes are required.

[0214] The first source layer via 500, the first channel layer via 501, the first drain layer via 502, the second source layer via 503, the second channel layer via 504, the second drain layer via 505, the first gate structure layer via 506, and the second gate structure layer via 507 can also be formed at one time through a single exposure, development, and etching process. By designing 8 different transmittances on the mask corresponding to the above 8 vias, the deeper the via, the greater the transmittance, the thinner the photoresist thickness at the via, and the photoresist thickness at the deepest via is 0.

[0215] Continue to refer Figures 17 to 19 , forming a via isolation layer 508 covering the side walls of the first source layer via 500 , the first channel layer via 501 , the first drain layer via 502 , the second source layer via 503 , the second channel layer via 504 and the second drain layer via 505 .

[0216] The via isolation layer 508 has the following beneficial effects: Used for electrical isolation between the first source layer plug 600 and the second drain layer 413, the second drain layer 403, the second channel layer 402, the second source trench layer 401, the second source layer 400, the first drain layer 310, the first drain layer 303, the first channel layer 302 and the first source trench layer 301; Used for electrical isolation between the first channel layer plug 601 and the second drain layer 413, the second drain layer 403, the second channel layer 402, the second source trench layer 401, the second source layer 400, the first drain layer 310, and the first drain layer 303; Used for electrical isolation between the first drain layer plug 602 and the second drain layer 413, the second drain layer 403, the second channel layer 402, the second source trench layer 401, and the second source layer 400; Used for electrical isolation between the second source layer plug 603 and the second drain layer 413, the second drain layer 403, the second channel layer 402, and the second source channel layer 401; It is used for electrical isolation between the second channel layer plug 604 and the second drain layer 413 and the second drain layer 403 .

[0217] The material of the via isolation layer 508 includes: one or more of silicon nitride, silicon oxide, silicon carbide, and silicon carbonitride. In this embodiment, the material of the via isolation layer 508 is silicon nitride.

[0218] In this embodiment, a conformal covering process is adopted to form the via isolation material layer on the inner walls and bottom of the first source layer via 500 , the first channel layer via 501 , the first drain layer via 502 , the second source layer via 503 , the second channel layer via 504 , and the second drain layer via 505 .

[0219] A back etching process is adopted to remove the via isolation material layer located at the bottom of the first source layer via 500, the first channel layer via 501, the first drain layer via 502, the second source layer via 503, the second channel layer via 504 and the second drain layer via 505 to form a via isolation layer 508 covering the side walls of the first source layer via 500, the first channel layer via 501, the first drain layer via 502, the second source layer via 503, the second channel layer via 504 and the second drain layer via 505.

[0220] refer to Figure 20 to Figure 22 , forming a first source layer plug 600 filling the first source layer via hole 500 (see Fig. 22 ), forming a first channel layer plug 601 filling the first channel layer via hole 501 (see Fig. 20 ), forming a first drain layer plug 602 filling the first drain layer via hole 502 (see Fig.21 ), forming a second source layer plug 603 filling the second source layer via hole 503 (see Fig. 22 ), forming a second channel layer plug 604 filling the second channel layer via hole 504 (see Fig. 20 ), forming a second drain layer plug 605 filling the second drain layer via hole 505 (see Fig.21 ), forming a first gate structure layer plug 606 filling the first gate structure layer via hole 506 (see Fig. 20 ), forming a second gate structure layer plug 607 filling the second gate structure layer via hole 507 (see Fig. 20 ).

[0221] The materials of the first source layer plug 600, the first channel layer plug 601, the first drain layer plug 602, the second source layer plug 603, the second channel layer plug 604, the second drain layer plug 605, the first gate structure layer plug 606, and the second gate structure layer plug 607 include: one or more of cobalt, copper, aluminum and tungsten. In this embodiment, the materials of the first source layer plug 600, the first channel layer plug 601, the first drain layer plug 602, the second source layer plug 603, the second channel layer plug 604, the second drain layer plug 605, the first gate structure layer plug 606, and the second gate structure layer plug 607 are all tungsten.

[0222] In this embodiment, the main process steps for forming the above plug include: A plug material layer is formed on the substrate 200 through a chemical vapor deposition process, and the plug material layer covers the surface of the interlayer dielectric layer 414, as well as the first source layer via 500, the first channel layer via 501, the first drain layer via 502, the second source layer via 503, the second channel layer via 504, the second drain layer via 505, the first gate structure layer via 506 and the second gate structure layer via 507.

[0223] With the interlayer dielectric layer 414 as a stop layer, the plug material layer is subjected to a sixth planarization treatment to form the first source layer plug 600, the first channel layer plug 601, the first drain layer plug 602, the second source layer plug 603, the second channel layer plug 604, the second drain layer plug 605, the first gate structure layer plug 606, and the second gate structure layer plug 607.

[0224] It should be noted that, in some embodiments, when forming each via hole, a portion of the thickness of the film layer at the bottom of each via hole may be removed so that the plug in each via hole is in electrical contact with the corresponding film layer.

[0225] It should be noted that one type of carriers of the semiconductor structure corresponds to the carriers of the first semiconductor device, and another type of carriers of the semiconductor structure corresponds to the carriers of the second semiconductor device.

[0226] In order to solve the technical problem, the present invention also provides a semiconductor structure accordingly. Figure 2 It is a schematic top view of a semiconductor structure according to an embodiment of the present invention, corresponding to a method for forming a semiconductor structure according to the present invention.

[0227] It should be noted that Figure 2 Need to combine Figures 3 to 22 , so as to more clearly demonstrate and explain a semiconductor structure of an embodiment of the present invention.

[0228] The semiconductor structure of the present embodiment includes: a substrate 200, including a first region 201, a second region 202 surrounding and connected to the first region 201; a first source layer 300, a first source trench layer 301, a first channel layer 302 and a first drain trench layer 303 stacked in sequence in the first region 201; a first gate dielectric layer 307, located in the second region 202 and surrounding and covering the sidewalls of the first source trench layer 301, the first channel layer 302 and the first drain trench layer 303; a first gate structure layer 308, surrounding and covering the first gate A dielectric layer 307; a first drain layer 310, a second source layer 400, a second source trench layer 401, a second channel layer 402, and a second trench drain layer 403 stacked in sequence on the first trench drain layer 303; a second gate dielectric layer 410, located in the second region 202 and surrounding and covering the side walls of the second source trench layer 401, the second channel layer 402, and the second trench drain layer 403; a second gate structure layer 411, surrounding and covering the second gate dielectric layer 410; and a second drain layer 413, located on the second trench drain layer 403.

[0229] Using the semiconductor structure provided by the embodiment of the present invention, one type of carrier of the semiconductor structure flows from the first source layer through the first source channel layer, the first channel layer and the first channel drain layer to the first drain layer in a direction perpendicular to the surface of the substrate, and another type of carrier of the semiconductor structure flows from the second source layer through the second source channel layer, the second channel layer and the second channel drain layer to the second drain layer; along the direction perpendicular to the surface of the substrate, the thickness of the first channel layer corresponds to the channel length of one type of carrier, and the thickness of the second channel layer corresponds to the channel length of another type of carrier, and the thickness of the first channel layer and the second channel layer can be reduced by a film forming process to reduce the channel length of the carriers, thereby further improving the on-state current of the semiconductor transistor.

[0230] refer to Fig. 20 , the semiconductor structure includes: a substrate 200.

[0231] The substrate 200 is used to provide a process platform for forming a semiconductor structure.

[0232] It should be noted that the substrate 200 is used to form a first semiconductor device and a second semiconductor device stacked on the first semiconductor device. The types of the first semiconductor device include: PMOS transistor or NMOS transistor, and the types of the second semiconductor device include: PMOS transistor or NMOS transistor. In this embodiment, the first semiconductor device is a PMOS transistor, and the second semiconductor device is an NMOS transistor. The transistor types of the first semiconductor device and the second semiconductor device stacked in the first region 201 can be selected according to actual needs and are not limited to this application. In some embodiments, the first semiconductor device is an NMOS transistor and the second semiconductor device is a PMOS transistor, or the first semiconductor device is a PMOS transistor and the second semiconductor device is a PMOS transistor, or the first semiconductor device is an NMOS transistor and the second semiconductor device is an NMOS transistor.

[0233] In this embodiment, the substrate 200 is a silicon substrate 200, and the material of the substrate 200 is single crystal silicon. In other embodiments, the material of the substrate 200 can also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium, and the substrate 200 can also be a silicon substrate 200 on an insulator or a germanium substrate 200 on an insulator. Other types of substrates 200. In other embodiments, an epitaxial layer (not shown) having the same crystal structure as the substrate 200 can also be formed on the surface of the substrate 200 to improve the quality of pattern transfer.

[0234] The substrate 200 includes a first area 201 and a second area 202 surrounding and connected to the first area 201 .

[0235] The first area 201 includes a first area outer edge (not shown), the second area 202 includes a second area inner edge (not shown), the second area inner edge is connected to the first area outer edge, the second area 202 surrounds the first area 201, so that the second area 202 is surrounded and adjacent to the first area 201. In some embodiments, the second area 202 is surrounded and adjacent to the first area 201 to form a "U" shape. In other embodiments, the second area 202 is surrounded and adjacent to the first area 201 to form a "U" shape, but this is not intended to limit the present application.

[0236] refer to Fig. 20 The semiconductor structure comprises: a first source layer 300, a first source trench layer 301, a first channel layer 302 and a first trench drain layer 303 stacked in sequence in the first region 201; a first drain layer 310, a second source layer 400, a second source trench layer 401, a second channel layer 402 and a second trench drain layer 403 stacked in sequence on the first trench drain layer 303; The first source layer 300 is used as a source of the first semiconductor device.

[0237] The first channel layer 302 is used as a channel of the first semiconductor device.

[0238] The first source trench layer 301 is used as a barrier layer between the first source layer 300 and the first channel layer 302, and can effectively prevent the mutual diffusion between the doped ions in the first channel layer 302 and the doped ions in the first source layer 300, thereby improving the reliability and stability of the semiconductor device.

[0239] The first drain layer 303 is used as a barrier layer between the first channel layer 302 and the first drain layer 310, and can effectively prevent the mutual diffusion between the doped ions in the first drain layer 310 and the doped ions in the first channel layer 302, thereby improving the reliability and stability of the semiconductor device.

[0240] In this embodiment, along a direction perpendicular to the surface of the substrate 200, the carriers of the first semiconductor device flow from the first source layer 300 to the first drain layer 310 through the first source trench layer 301, the first channel layer 302 and the first trench drain layer 303. That is, the channel length of the first semiconductor device is the thickness of the first channel layer 302. Compared with the exposure process of the lithography machine, a first channel layer 302 with a smaller thickness can be formed through a chemical vapor deposition process or an epitaxial process, thereby reducing the flow path of the carriers of the first semiconductor device and further improving the on-state current of the semiconductor transistor.

[0241] In this embodiment, along a direction perpendicular to the surface of the substrate 200, the carriers of the second semiconductor device flow from the second source layer 400 through the second source trench layer 401, the second channel layer 402 and the second trench drain layer 403 to the second drain layer 413, that is, the channel length of the second semiconductor device is the thickness of the second channel layer 402. Compared with the exposure process of the lithography machine, a second channel layer 402 with a smaller thickness can be formed through a chemical vapor deposition process or an epitaxial process, thereby reducing the flow path of the carriers of the second semiconductor device and further improving the on-state current of the semiconductor transistor.

[0242] Regarding the materials, thicknesses, doping concentrations, doping ion types, etc. of the first source layer 300, the first source trench layer 301, the first channel layer 302, the first trench drain layer 303, the first drain layer 310, the second source layer 400, the second source trench layer 401, the second channel layer 402, and the second trench drain layer 403, reference may be made to the aforementioned method for forming the semiconductor structure and will not be elaborated herein.

[0243] Continue to refer Fig. 20The semiconductor structure includes: a first filling layer 304 located in the second region 202 , and along a direction parallel to the surface of the substrate 200 , the first filling layer 304 is flush with the surface of the first drain layer 303 .

[0244] The first filling layer 304 is used to isolate semiconductor devices and prevent electrical interference between different regions.

[0245] The material of the first filling layer 304 includes: one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the first filling layer 304 is silicon oxide.

[0246] Continue to refer Fig. 20 , combined with Figure 5 The semiconductor structure includes: a first filling layer trench 305 located in the first filling layer 304 , and the first filling layer trench 305 exposes the side walls of the first source trench layer 301 , the first channel layer 302 , and the first drain layer 303 .

[0247] The first filling layer trench 305 includes: first filling layer trench sidewalls opposite to the sidewalls of the first source trench layer 301 , the first channel layer 302 , and the first drain layer 303 , and a first filling layer trench bottom.

[0248] The first filling layer trench 305 is used to accommodate the first gate dielectric layer 307 and the first gate structure layer 308 .

[0249] Continue to refer Fig. 20 The semiconductor structure includes: a first gate dielectric layer 307 located in the second region 202 and surrounding and covering the sidewalls of the first source trench layer 301 , the first channel layer 302 and the first drain trench layer 303 .

[0250] The first gate dielectric layer 307 , as an electrical insulating material, is used to electrically isolate the first gate structure layer 308 from the first source layer 300 , the first source trench layer 301 , the first channel layer 302 , the first drain trench layer 303 and the first drain layer 310 of the first semiconductor device.

[0251] The material of the first gate dielectric layer 307 includes: one or more of silicon oxide and a high dielectric constant gate dielectric layer material. The silicon oxide has good insulation, coverage and stability. In this embodiment, the material of the first gate dielectric layer 307 is silicon oxide.

[0252] The first gate dielectric layer 307 is made of silicon oxide and has a thickness in a range of greater than or equal to 50 nanometers and less than or equal to 200 nanometers.

[0253] By making the film thickness of silicon oxide greater than or equal to 50 nanometers, a good electrical insulation and isolation effect can be achieved; by making the film thickness of silicon oxide less than or equal to 200 nanometers, the process manufacturing cycle can be reduced and the characteristics of the semiconductor device can be guaranteed.

[0254] It should be noted that the high dielectric constant gate dielectric layer material includes a dielectric material having a dielectric constant greater than the dielectric constant of silicon oxide (3.9); the high dielectric constant gate dielectric layer material includes one or more of hafnium oxide, zirconium oxide, hafnium silicon oxide, hafnium oxynitride, hafnium silicon oxynitride, hafnium tantalum oxynitride, zirconium oxynitride, zirconium silicon oxynitride, zirconium silicon oxide, lanthanum oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, and strontium titanium oxide. Preferably, the dielectric constant of the high dielectric constant gate dielectric layer material is greater than 8, so as to reduce the thickness of the first gate dielectric layer 307 and improve the performance of the transistor.

[0255] In this embodiment, the first gate dielectric layer 307 is located in the first filling layer groove 305, that is, the first gate dielectric layer 307 is located in the second region 202 and surrounds and covers the side walls of the first source trench layer 301, the first channel layer 302 and the first drain layer 303, and the first gate dielectric layer 307 also covers the side walls of the first filling layer groove and the bottom of the first filling layer groove.

[0256] Continue to refer Fig. 20 The semiconductor structure includes: a first gate structure layer 308 surrounding and covering the first gate dielectric layer 307 .

[0257] The first gate structure layer 308 is used to control the on and off of the first semiconductor device.

[0258] The material of the first gate structure layer 308 includes: one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC).

[0259] In this embodiment, the material of the first gate structure layer 308 is titanium nitride (TiN).

[0260] In this embodiment, the first gate structure layer 308 is filled in the first filling layer groove 305 and surrounds and covers the first gate dielectric layer 307. That is, the first gate structure layer 308 surrounds and covers the surface of the first gate dielectric layer 307 at the side walls of the first source trench layer 301, the first channel layer 302 and the first drain layer 303, and also surrounds and covers the surface of the first gate dielectric layer 307 at the side walls of the first filling layer groove 305, and covers the surface of the first gate dielectric layer 307 at the bottom of the first filling layer groove 305.

[0261] Continue to refer Fig. 20 The semiconductor structure includes: a first thin layer 309 covering the surface of the first filling layer 304 and the first gate structure layer 308 .

[0262] The first thin layer 309 is used to protect the first gate structure layer 308 .

[0263] The material of the first thin layer 309 includes: one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the first thin layer 309 is silicon oxide.

[0264] Continue to refer Fig. 20 The semiconductor structure includes: a second filling layer 404 located in the second region 202 , and along a surface direction parallel to the substrate 200 , the second filling layer 404 is flush with the surface of the second drain layer 403 in the first region 201 .

[0265] The second filling layer 404 is used to isolate semiconductor devices and prevent electrical interference between different regions.

[0266] The material of the second filling layer 404 includes: one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the first filling layer 304 is silicon oxide.

[0267] In this embodiment, the second filling layer 404 covers the surface of the first thin layer 309 in the second region 202 , and along a direction parallel to the surface of the substrate 200 , the second filling layer 404 is flush with the surface of the second drain layer 403 in the first region 201 .

[0268] Continue to refer Fig. 20 , combined with Fig.10 The semiconductor structure includes: a first spacer 406 located between the first drain layer 310 and the second source layer 400 .

[0269] The first spacer 406 is used to accommodate a third filling layer 407 located between the first drain electrode layer 310 and the second source electrode layer 400 .

[0270] Continue to refer Fig. 20 , combined with Fig.10 The semiconductor structure includes: a second filling layer groove 405, which is located in the second filling layer 404, and the second filling layer groove 405 exposes the side walls of the second source layer 400, the second source trench layer 401, the second channel layer 402, the second trench drain layer 403 and the first spacer 406.

[0271] Continue to refer Fig. 20 , combined with Fig.12The semiconductor structure includes: a third filling layer 407, which is filled in the first spacer 406 and also fills a part of the second filling layer trench 405 to form a third filling layer trench 408, and the third filling layer trench 408 exposes the side walls of the second source trench layer 401, the second channel layer 402 and the second drain layer 403.

[0272] The third filling layer trench 408 includes: the third filling layer trench sidewalls opposite to the sidewalls of the second source trench layer 401 , the second channel layer 402 , and the second drain layer 403 , and the third filling layer trench bottom.

[0273] The third filling layer 407 in the first spacer 406 is used to electrically isolate the first semiconductor device from the second semiconductor device. That is, the third filling layer 407 is located in the first spacer 406 between the first drain layer 310 and the second source layer 400 .

[0274] Continue to refer Fig. 20 The semiconductor structure includes: a second gate dielectric layer 410 located in the second region 202 and surrounding and covering the sidewalls of the second source trench layer 401 , the second channel layer 402 and the second drain trench layer 403 .

[0275] The second gate dielectric layer 410 , as an electrical insulating material, electrically isolates the subsequently formed second gate structure layer 411 from the second source layer 400 , the second source trench layer 401 , the second channel layer 402 , the second trench layer 403 and the second drain layer 413 of the second semiconductor device.

[0276] The material of the second gate dielectric layer 410 includes: one or more of silicon oxide and a high dielectric constant gate dielectric layer material. The silicon oxide has good insulation, coverage and stability. In this embodiment, the material of the second gate dielectric layer 410 is silicon oxide.

[0277] The second gate dielectric layer 410 is silicon oxide and has a thickness in a range of greater than or equal to 50 nanometers and less than or equal to 200 nanometers.

[0278] By making the film thickness of silicon oxide greater than or equal to 50 nanometers, a good electrical insulation and isolation effect can be achieved; by making the film thickness of silicon oxide less than or equal to 200 nanometers, the process manufacturing cycle can be reduced and the characteristics of the semiconductor device can be guaranteed.

[0279] It should be noted that the high dielectric constant gate dielectric layer material includes a dielectric material having a dielectric constant greater than the dielectric constant of silicon oxide (3.9); the high dielectric constant gate dielectric layer material includes one or more of hafnium oxide, zirconium oxide, hafnium silicon oxide, hafnium oxynitride, hafnium silicon oxynitride, hafnium tantalum oxynitride, zirconium oxynitride, zirconium silicon oxynitride, zirconium silicon oxide, lanthanum oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, and strontium titanium oxide. Preferably, the dielectric constant of the high dielectric constant gate dielectric layer material is greater than 8, so as to reduce the thickness of the second gate dielectric layer 410 and improve the performance of the transistor.

[0280] In this embodiment, the second gate dielectric layer 410 is located in the third filling layer trench 408, that is, the second gate dielectric layer 410 is located in the second region 202 and surrounds and covers the side walls of the second source trench layer 401, the second channel layer 402 and the second drain layer 403, and the second gate dielectric layer 410 also covers the side walls of the third filling layer trench and the bottom of the third filling layer trench.

[0281] Continue to refer Fig. 20 The semiconductor structure includes: a second gate structure layer 411 surrounding and covering the second gate dielectric layer 410 .

[0282] The second gate structure layer 411 is used to control the on and off of the second semiconductor device.

[0283] The material of the second gate structure layer 411 includes: one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC).

[0284] In this embodiment, the material of the second gate structure layer 411 is titanium nitride (TiN).

[0285] In this embodiment, the second gate structure layer 411 is filled in the third filling layer groove 408 and surrounds and covers the second gate dielectric layer 410, that is, the second gate structure layer 411 surrounds and covers the surface of the second gate dielectric layer 410 at the side walls of the second source trench layer 401, the second channel layer 402 and the second drain layer 403, and also surrounds and covers the surface of the second gate dielectric layer 410 at the side walls of the third filling layer groove, and covers the surface of the second gate dielectric layer 410 at the bottom of the third filling layer groove.

[0286] Continue to refer Fig. 20 The semiconductor structure includes: a second thin layer 412 covering the surface of the second filling layer 404 and the second gate structure layer 411.

[0287] The second thin layer 412 is used to protect the second gate structure layer 411 .

[0288] The material of the second thin layer 412 includes: one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the second thin layer 412 is silicon oxide.

[0289] Continue to refer Fig. 20 The semiconductor structure includes: a second drain layer 413 located on the second drain layer 403 .

[0290] The second drain electrode layer 413 is used as a drain electrode of the second semiconductor device.

[0291] Continue to refer Fig. 20 The semiconductor structure includes: an interlayer dielectric layer 414 covering the surface of the second thin layer 412 and the second drain layer 413.

[0292] The interlayer dielectric layer 414 has the following beneficial effects: First, electrical isolation: The interlayer dielectric layer 414 isolates different metal layers (such as interconnects) to avoid short circuits caused by direct contact between metal layers, thereby reducing electromagnetic interference (crosstalk) between signal lines and improving signal transmission quality.

[0293] Second, parasitic capacitance is reduced. By using low dielectric constant materials, the interlayer dielectric layer 414 can reduce the parasitic capacitance between metal layers.

[0294] The material of the interlayer dielectric layer 414 includes: one or more of silicon oxide, silicon nitride, silicon carbide, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 414 is silicon oxide.

[0295] In the semiconductor structure, along a direction perpendicular to the surface of the substrate 200, the side walls of the first source layer 300, the first source trench layer 301, the first channel layer 302, the first trench drain layer 303, the first drain layer 310, the third filling layer 407 in the first spacer 406, the second source layer 400, the second source trench layer 401, the second channel layer 402, the second trench drain layer 403 and the second drain layer 413 are flush.

[0296] Continue to refer Figures 17 to 22 , combined with Figure 2 , the semiconductor structure comprises: The first source layer via hole 500 penetrates the interlayer dielectric layer 414, the second drain layer 413, the second drain layer 403, the second channel layer 402, the second source trench layer 401, the second source layer 400, the third filling layer 407, the first drain layer 310, the first drain layer 303, the first channel layer 302 and the first source trench layer 301; The first channel layer via hole 501 penetrates the interlayer dielectric layer 414, the second drain layer 413, the second drain layer 403, the second channel layer 402, the second source trench layer 401, the second source layer 400, the third filling layer 407, the first drain layer 310, and the first drain layer 303; The first drain layer via hole 502 penetrates the interlayer dielectric layer 414, the second drain layer 413, the second drain layer 403, the second channel layer 402, the second source layer 401, the second source layer 400, and the third filling layer 407; The second source layer via hole 503 penetrates the interlayer dielectric layer 414, the second drain layer 413, the second drain layer 403, the second channel layer 402, and the second source channel layer 401; A second channel layer via hole 504 is formed to penetrate the interlayer dielectric layer 414, the second drain layer 413, and the second channel drain layer 403; A second drain layer via hole 505 penetrating the interlayer dielectric layer 414; A via isolation layer 508 covering the side walls of the first source layer via 500, the first channel layer via 501, the first drain layer via 502, the second source layer via 503, the second channel layer via 504 and the second drain layer via 505; The first gate structure layer via hole 506 penetrates the interlayer dielectric layer 414, the second thin layer 412, the second filling layer 404 and the first thin layer 309; The second gate structure layer via hole 507 penetrates the interlayer dielectric layer 414 and the second thin layer 412; The first source layer plug 600 is filled in the first source layer via hole 500 and is in contact with the first source layer 300 , that is, in electrical contact.

[0297] The first channel layer plug 601 is filled in the first channel layer via hole 501 and is in contact with the first channel layer 302 , ie, in electrical contact.

[0298] The first drain layer plug 602 is filled in the first drain layer via hole 502 and is in contact with the first drain layer 310 , ie, in electrical contact.

[0299] The second source layer plug 603 is filled in the second source layer via hole 503 and is in contact with the second source layer 400 , that is, in electrical contact.

[0300] The second channel layer plug 604 is filled in the second channel layer via hole 504 and is in contact with the second channel layer 402 , ie, in electrical contact.

[0301] The second drain layer plug 605 is filled in the second drain layer via hole 505 and is in contact with the second drain layer 413 , ie, in electrical contact.

[0302] The first gate structure layer plug 606 is filled in the first gate structure layer via hole 506 and is in contact with the first gate structure layer 308 , ie, in electrical contact.

[0303] The second gate structure layer plug 607 is filled in the second gate structure layer via hole 507 and is in contact with the second gate structure layer 411 , ie, in electrical contact.

[0304] Regarding the via isolation layer 508 , the various vias and the various plugs mentioned above, reference may be made to the description of the semiconductor structure forming method, which will not be described in detail here.

[0305] The first semiconductor body device at least includes: a first source layer 300, a first source trench layer 301, a first channel layer 302 and a first trench drain layer 303, a first drain layer 310, a first gate dielectric layer 307, a first gate structure layer 308, a first source layer plug 600, a first channel layer plug 601, a first drain layer plug 602, a first gate structure layer plug 606, a first source layer plug 600, a first channel layer plug 601, a first drain layer plug 602, and a first gate structure layer plug 606.

[0306] The second semiconductor body device at least includes: a second source layer 400, a second source trench layer 401, a second channel layer 402 and a second trench drain layer 403, a second drain layer 413, a second gate dielectric layer 410, a second gate structure layer 411, a second source layer plug 603, a second channel layer plug 604, a second drain layer plug 605, a second gate structure layer plug 607, a second source layer plug 603, a second channel layer plug 604, a second drain layer plug 605, and a second gate structure layer plug 607.

[0307] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, comprising a first region, and a second region surrounding and connected to the first region; Sequentially forming a first source layer, a first source trench layer, a first channel layer and a first drain trench layer stacked in the first region; Forming a first gate dielectric layer in the second region, surrounding and covering the first source trench layer, the first channel layer and the sidewalls of the first drain trench layer; forming a first gate structure layer surrounding and covering the first gate dielectric layer; Sequentially forming a first drain layer, a sacrificial layer, a second source layer, a second source trench layer, a second channel layer, and a second drain layer stacked on the first drain trench layer; forming a second gate dielectric layer in the second region, surrounding and covering the sidewalls of the second source trench layer, the second channel layer and the second drain trench layer; forming a second gate structure layer surrounding and covering the second gate dielectric layer; A second drain layer is formed covering the second drain layer.

2. The forming method according to claim 1, characterized in that: Along the direction perpendicular to the substrate surface, the side walls of the first source layer, the first source trench layer, the first channel layer, the first trench drain layer, the first drain layer, the sacrificial layer, the second source layer, the second source trench layer, the second channel layer, the second trench drain layer and the second drain layer are flush.

3. The forming method according to claim 1, characterized in that: The material of the first source trench layer includes silicon germanium, the material of the first trench drain layer includes silicon germanium, the material of the second source trench layer includes silicon carbide, the material of the second trench drain layer includes silicon carbide, and the material of the sacrificial layer includes silicon germanium.

4. The forming method according to claim 1, characterized in that: After forming the first drain layer and before forming the first gate dielectric layer, the forming method further includes: forming a first filling layer on the substrate of the second region, wherein the first filling layer covers the sidewalls of the first source electrode layer, the first source trench layer, the first channel layer and the first trench drain layer; Removing a portion of the first filling layer to expose the sidewalls of the first source trench layer, the first channel layer, and the first drain trench layer to form a first filling layer trench; The first filling layer trench comprises: first filling layer trench sidewalls opposite to the sidewalls of the first source trench layer, the first channel layer and the first drain trench layer, and a first filling layer trench bottom.

5. The forming method according to claim 4, characterized in that: In the first filling layer trench, a first gate dielectric layer is formed surrounding and covering the sidewalls of the first source trench layer, the first channel layer, and the first drain trench layer; The first gate dielectric layer also covers the bottom of the first filling layer trench and the sidewalls of the first filling layer trench.

6. The forming method according to claim 4, characterized in that: After forming the first filling layer trench and before forming the first gate dielectric layer, the forming method further includes: A first metal layer is formed outside the first filling layer trench to cover the surface of the first filling layer and the first drain layer.

7. The forming method according to claim 4, characterized in that: The first gate structure layer is filled in the first filling layer trench, and the first gate structure layer surrounds and covers the first gate dielectric layer.

8. The forming method according to claim 5, characterized in that: The forming method further includes: forming a first thin layer covering a surface of the first gate structure layer; The first thin layer also covers the first filling layer.

9. The forming method according to claim 8, characterized in that: After forming the second drain layer and before forming the second gate dielectric layer, the forming method further includes: forming a second filling layer on the first thin layer, wherein the second filling layer covers the sidewalls of the first drain layer, the sacrificial layer, the second source layer, the second source trench layer, the second channel layer and the second trench drain layer; A portion of the second filling layer is removed to expose the side walls of the sacrificial layer, the second source layer, the second source trench layer, the second channel layer and the second drain layer to form a second filling layer trench, and the sacrificial layer is removed to form a first spacer located between the first drain layer and the second source layer.

10. The forming method according to claim 9, characterized in that: Filling a third filling layer in the second filling layer groove and the first space; Removing a portion of the third filling layer to expose the sidewalls of the second source trench layer, the second channel layer, and the second drain trench layer to form a third filling layer trench; The third filling layer trench comprises: a third filling layer trench sidewall opposite to the sidewalls of the second source trench layer, the second channel layer and the second drain trench layer, and a third filling layer trench bottom.

11. The forming method according to claim 10, characterized in that: In the third filling layer trench, a second gate dielectric layer is formed to surround and cover the sidewalls of the second source trench layer, the second channel layer, and the second drain trench layer; The second gate dielectric layer also covers the bottom of the third filling layer trench and the sidewalls of the third filling layer trench.

12. The forming method according to claim 11, characterized in that: After forming the third filling layer trench and before forming the second gate dielectric layer, the forming method further includes: A second metal layer is formed outside the third filling layer trench to cover the surfaces of the second filling layer and the second drain layer.

13. The forming method according to claim 11, characterized in that: The second gate structure layer is filled in the third filling layer trench, and the second gate structure layer surrounds and covers the second gate dielectric layer.

14. The forming method according to claim 13, characterized in that: The forming method further comprises: After forming the second gate structure layer and before forming the second drain electrode layer, a second thin layer is formed on the surface of the second gate structure layer, and the second thin layer also covers the second filling layer.

15. The forming method according to claim 14, characterized in that: forming an interlayer dielectric layer covering the second thin layer and the second drain electrode layer; Forming a first source layer via hole penetrating the interlayer dielectric layer, the second drain layer, the second drain layer, the second channel layer, the second source layer, the second source layer, the third filling layer, the first drain layer, the first drain layer, the first channel layer and the first source layer; Forming a first channel layer via hole penetrating the interlayer dielectric layer, the second drain layer, the second drain layer, the second channel layer, the second source trench layer, the second source layer, the third filling layer, the first drain layer, and the first drain layer; Forming a first drain layer via hole penetrating the interlayer dielectric layer, the second drain layer, the second drain layer, the second channel layer, the second source layer, the second source layer, and the third filling layer; Forming a second source layer via hole penetrating the interlayer dielectric layer, the second drain layer, the second drain layer, the second channel layer, and the second source channel layer; forming a second channel layer via hole penetrating the interlayer dielectric layer, the second drain layer, and the second channel drain layer; forming a second drain layer via hole penetrating the interlayer dielectric layer; Forming a first gate structure layer via hole penetrating the interlayer dielectric layer, the second thin layer, the second filling layer and the first thin layer; Forming a second gate structure layer via hole penetrating the interlayer dielectric layer and the second thin layer; forming a via isolation layer covering the sidewalls of the first source layer via, the first channel layer via, the first drain layer via, the second source layer via, the second channel layer via, and the second drain layer via; forming a first source layer plug filling the first source layer via hole; forming a first channel layer plug filling the first channel layer via hole; forming a first drain layer plug filling the first drain layer via hole; forming a second source layer plug filling the second source layer via hole; forming a second channel layer plug filling the second channel layer via hole; forming a second drain layer plug filling the second drain layer via hole; Forming a first gate structure layer plug filling the first gate structure layer via hole; A second gate structure layer plug is formed to fill the second gate structure layer via hole.

16. The forming method according to claim 1, characterized in that: The first source layer, the first source trench layer, the first channel layer, the first drain trench layer, the first drain layer, the second source layer, the second source trench layer, the second channel layer and the second drain trench layer are all formed by epitaxial process.

17. The forming method according to claim 16, characterized in that: The parameters of the epitaxial process include: a temperature between 600 degrees Celsius and 800 degrees Celsius.

18. The forming method according to claim 17, characterized in that: The parameters of the epitaxial process include at least one of the following: Pressure is 70 Torr to 90 Torr; The flow rate of Purge MainH2 is 3200sccm to 3800sccm; The flow rate of Purge SlitH2 is 80 sccm to 120 sccm; The flow rate of the silicon source gas is 120 sccm to 180 sccm; The epitaxial growth rate is 200 angstroms / minute to 300 angstroms / minute.

19. A semiconductor structure, characterized in that: include: A substrate, comprising a first region, and a second region surrounding and connected to the first region; A first source layer, a first source trench layer, a first channel layer and a first drain trench layer stacked in sequence in the first region; A first gate dielectric layer, located in the second region, surrounds and covers the sidewalls of the first source trench layer, the first channel layer and the first drain trench layer; A first gate structure layer surrounding and covering the first gate dielectric layer; A first drain layer, a second source layer, a second source trench layer, a second channel layer, and a second drain layer are sequentially stacked on the first drain trench layer; A second gate dielectric layer is located in the second region and surrounds and covers the sidewalls of the second source trench layer, the second channel layer, and the second drain trench layer; A second gate structure layer surrounding and covering the second gate dielectric layer; The second drain electrode layer is located on the second drain electrode layer.

20. The semiconductor structure according to claim 19, wherein: Along a direction perpendicular to the substrate surface, side walls of the first source layer, the first source trench layer, the first channel layer, the first trench drain layer, the first drain layer, the second source layer, the second source trench layer, the second channel layer, the second trench drain layer and the second drain layer are flush.

21. The semiconductor structure according to claim 19, wherein: Also includes: A first filling layer, located in the second region, along a direction parallel to the surface of the substrate, the first filling layer is flush with the surface of the first drain layer; A first filling layer trench, located in the first filling layer, wherein the first filling layer trench exposes side walls of the first source trench layer, the first channel layer, and the first drain trench layer; The first filling layer trench comprises: first filling layer trench sidewalls opposite to the sidewalls of the first source trench layer, the first channel layer, and the first drain trench layer, and a first filling layer trench bottom; The first gate dielectric layer is located in the first filling layer trench, surrounding and covering the first source trench layer, the first channel layer and the sidewalls of the first drain layer; The first gate dielectric layer also covers the sidewalls of the first filling layer trench and the bottom of the first filling layer trench; The first gate structure layer is filled in the first filling layer trench and surrounds and covers the first gate dielectric layer.

22. The semiconductor structure according to claim 21, wherein: Also includes: A first thin layer, covering the surface of the first filling layer and the first gate structure layer; A second filling layer is located in the second region, and along a direction parallel to the surface of the substrate, the second filling layer is flush with a surface of the second drain layer in the first region; a first spacer, located between the first drain electrode layer and the second source electrode layer; A second filling layer trench, located in the second filling layer, wherein the second filling layer trench exposes the second source layer, the second source trench layer, the second channel layer, the sidewalls of the second drain and trench layer and the first spacer; A third filling layer is filled in the first space and also filled in a part of the second filling layer trench to form a third filling layer trench, wherein the third filling layer trench exposes the sidewalls of the second source trench layer, the second channel layer and the second drain layer; The third filling layer trench comprises: the third filling layer trench sidewalls opposite to the sidewalls of the second source trench layer, the second channel layer, and the second drain trench layer, and the third filling layer trench bottom; The second gate dielectric layer is located in the third filling layer trench, surrounding and covering the sidewalls of the second source trench layer, the second channel layer and the second drain layer; The second gate dielectric layer also covers the sidewalls of the third filling layer trench and the bottom of the third filling layer trench; The second gate structure layer is filled in the third filling layer trench and surrounds and covers the second gate dielectric layer.

23. The semiconductor structure according to claim 22, wherein: Also includes: A second thin layer, covering the surfaces of the second filling layer and the second gate structure layer; The interlayer dielectric layer covers the surface of the second thin layer and the second drain electrode layer.

24. The semiconductor structure according to claim 23, wherein: Also includes: The first source layer via hole penetrates the interlayer dielectric layer, the second drain layer, the second drain layer, the second channel layer, the second source trench layer, the second source layer, the third filling layer, the first drain layer, the first drain layer, the first channel layer and the first source trench layer; The first channel layer via hole penetrates the interlayer dielectric layer, the second drain layer, the second drain layer, the second channel layer, the second source layer, the second source layer, the third filling layer, the first drain layer, and the first drain layer; the first drain layer via hole penetrates the interlayer dielectric layer, the second drain layer, the second drain layer, the second channel layer, the second source layer, the second source layer, and the third filling layer; A second source layer via hole, penetrating the interlayer dielectric layer, the second drain layer, the second drain layer, the second channel layer, and the second source channel layer; A second channel layer via hole is formed to penetrate the interlayer dielectric layer, the second drain layer, and the second channel drain layer; A second drain layer via hole penetrating the interlayer dielectric layer; A via isolation layer covering the side walls of the first source layer via, the first channel layer via, the first drain layer via, the second source layer via, the second channel layer via and the second drain layer via; A first gate structure layer via hole passes through the interlayer dielectric layer, the second thin layer, the second filling layer and the first thin layer; A second gate structure layer via hole penetrates the interlayer dielectric layer and the second thin layer; A first source layer plug is filled in the first source layer via hole and contacts the first source layer; A first channel layer plug is filled in the first channel layer via hole and contacts the first channel layer; A first drain layer plug is filled in the first drain layer via hole and contacts the first drain layer; A second source layer plug is filled in the second source layer via hole and contacts the second source layer; A second channel layer plug is filled in the second channel layer via hole and contacts the second channel layer; A second drain layer plug is filled in the second drain layer via hole and contacts the second drain layer; A first gate structure layer plug is filled in the first gate structure layer via hole and contacts the first gate structure layer; The second gate structure layer plug is filled in the second gate structure layer via hole and is in contact with the second gate structure layer.

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