Thin film transistor, driving method thereof, pixel driving circuit and display device

Abstract

The invention provides a thin film transistor, a driving method thereof, a pixel driving circuit and a display device, and the thin film transistor comprises a substrate; the active layer is located on the substrate; the active layer comprises a PIN junction, and the PIN junction comprises a P region, an intrinsic region and an N region which are arranged in sequence in the plane direction parallel to the substrate; the type of ions doped in the P region is different from that of ions doped in the N region; wherein the active layer is made of low-temperature polycrystalline silicon, the P region and the N region are used for constructing a tunneling effect, and the intrinsic region is used for disconnecting a current channel when the minority carrier concentration in the P region and the N region is lower than a first preset threshold value. And when the electron concentration in the corresponding region is increased to a second preset threshold value, the current channel is formed through the tunneling effect.

Description

Technical Field

[0001] The present invention relates to the technical field of thin film transistors, and in particular to a thin film transistor, a driving method thereof, a pixel driving circuit and a display device. Background Art

[0002] At present, with the improvement of the resolution of flat panel displays and sensor arrays, higher requirements are placed on the size and mobility of thin film transistors of active drive elements. At the same time, the requirement of low power consumption requires that the leakage current level of TFT is low enough to achieve low refresh rate and long-term charge retention.

[0003] In the prior art, indium gallium zinc oxide thin film transistors (IGZO TFTs) can provide a lower leakage current level, but their mobility is insufficient and it is difficult to drive current-type displays. For this reason, a low-temperature polycrystalline silicon oxide (LTPO) technical solution can be adopted. Specifically, low-temperature polycrystalline silicon (LTPS) is used as a driving tube, and IGZO TFT is used as a switching tube. However, the LTPO technical solution needs to consider the compatibility of both LTPS and IGZO processes, especially the effect of H on the stability of IGZO, which becomes a bottleneck for improving the yield. And in actual preparation, IGZO needs to be prepared above LTPS, the film layer is complex, and the cost is high. Summary of the invention

[0004] The present invention provides a thin film transistor, a driving method thereof, a pixel driving circuit and a display device, which are used to realize a low leakage current design while taking into account the low cost production of the thin film transistor.

[0005] In a first aspect, an embodiment of the present invention provides a thin film transistor, including:

[0006] substrate;

[0007] An active layer is located on the substrate; the active layer includes a PIN junction, and along a plane direction parallel to the substrate, the PIN junction includes a P region, an intrinsic region and an N region arranged in sequence; the type of ions doped in the P region is different from the type of ions doped in the N region;

[0008] Among them, the material of the active layer is low-temperature polysilicon, the P region and the N region are used to construct a tunneling effect, the intrinsic region is used to disconnect the current channel when the minority carrier concentration in the P region and the N region is lower than a first preset threshold value, and to form the current channel through the tunneling effect when the electron concentration in the corresponding region increases to a second preset threshold value.

[0009] In a possible implementation manner, the P region, the intrinsic region, and the N region are arranged flush with each other on a side facing away from the substrate.

[0010] In a possible implementation manner, the ions doped in the P region are B and elements of the same group corresponding to B.

[0011] In a possible implementation manner, the ions doped in the N region are P and elements of the same group corresponding to P.

[0012] In a possible implementation, it further includes a gate insulating layer and a gate layer located on the active layer, wherein the orthographic projection of the intrinsic region on the substrate completely falls within the area of ​​the orthographic projection of the gate layer on the substrate.

[0013] In a possible implementation manner, the thin film transistor is an N-type transistor or a P-type transistor.

[0014] In a possible implementation, it also includes a passivation layer and a source-drain layer located on the gate layer, the source in the source-drain layer is electrically connected to the P region, and the drain in the source-drain layer is electrically connected to the N region; when the thin film transistor is an N-type tube and the drain receives a positive voltage, and the positive voltage applied to the gate layer is less than a third preset threshold, the current channel is disconnected, and the thin film transistor is in an off state; when the positive voltage received by the gate layer is greater than or equal to the third preset threshold, the electron concentration in the intrinsic region tends to increase, the current channel is turned on, and the thin film transistor is in an on state.

[0015] In a second aspect, an embodiment of the present invention further provides a display device, including:

[0016] A display substrate, an opposite substrate arranged opposite to the display substrate, and a liquid crystal layer located between the display substrate and the opposite substrate;

[0017] Wherein, the display substrate comprises a plurality of switch units arranged in an array, each of the switch units is configured to drive the deflection of the liquid crystal layer, and each of the switch units is a thin film transistor as described in any one of the above items.

[0018] In a possible implementation, it further includes a gate layer located between the active layer and the substrate, and the orthographic projection of the intrinsic region on the substrate completely falls within the area of ​​the orthographic projection of the gate layer on the substrate.

[0019] In a third aspect, an embodiment of the present invention further provides a pixel driving circuit, including:

[0020] a driving transistor, and a switching transistor coupled to a gate of the driving transistor;

[0021] The switch transistor is a thin film transistor as described in any one of the above items.

[0022] In a possible implementation manner, the material of the active layer of the driving transistor is low-temperature polysilicon, and the active layer of the driving transistor and the active layer of the switch transistor are provided in the same layer and with the same material.

[0023] In a fourth aspect, an embodiment of the present invention further provides a display device, including:

[0024] A pixel driving circuit as described above, and a light emitting device electrically connected to the pixel driving circuit.

[0025] In a fifth aspect, an embodiment of the present invention further provides a driving method of a thin film transistor, wherein the thin film transistor comprises a substrate and an active layer located on the substrate; the active layer comprises a PIN junction, and along a plane parallel to the substrate, the PIN junction comprises a P region, an intrinsic region and an N region arranged in sequence; the type of ions doped in the P region is different from the type of ions doped in the N region; the material of the active layer is low temperature polysilicon, and the P region and the N region are used to construct a tunneling effect; the driving method comprises:

[0026] If the minority carrier concentration in the P region and the N region is lower than a first preset threshold, the current channel is disconnected to control the thin film transistor to be in an off state;

[0027] If the electron concentration in the intrinsic region increases to a second preset threshold, the current channel is formed in the intrinsic region through the tunneling effect.

[0028] In a possible implementation, if the thin film transistor is an N-type transistor and further includes a source electrode electrically connected to the P region, a drain electrode electrically connected to the N region, and a gate insulating layer and a gate layer located on the active layer, the step of controlling the thin film transistor to be in an off state includes:

[0029] Under the effect of the reverse characteristic of the PIN junction, the minority carrier concentrations of the P region and the N region are lower than a first preset threshold value;

[0030] If the drain receives a positive voltage and the positive voltage applied to the gate layer is less than a third preset threshold, the thin film transistor is controlled to be in an off state.

[0031] In a possible implementation manner, forming the current channel in the intrinsic region by using the tunneling effect includes:

[0032] If the positive voltage received by the gate layer is greater than or equal to the third preset threshold, the electron concentration of the intrinsic region is gradually increased, and the energy bands of the P region and the intrinsic region are bent so that the conduction band bottom of the intrinsic region is lower than the valence band top of the P region;

[0033] The electrons in the valence band of the P region are controlled to undergo trap-assisted tunneling to the conduction band of the intrinsic region via the deep energy level and band tail state formed in the band gap at the grain boundary, so that the current channel is formed in the intrinsic region and the thin film transistor is in an on state.

[0034] The beneficial effects of the present invention are as follows:

[0035] The embodiment of the present invention provides a thin film transistor, a driving method thereof, a pixel driving circuit and a display device, wherein the thin film transistor includes a substrate and an active layer located on the substrate; the active layer includes a PIN junction, and along a plane direction parallel to the substrate, the PIN junction includes a P region, an intrinsic region and an N region arranged in sequence; the ion type doped in the P region is different from the ion type doped in the N region. For example, the ions doped in the P region are P, and the ions doped in the N region are B. In this way, a tunneling effect can be formed through the PIN structure; moreover, the material of the active layer is low-temperature polycrystalline silicon, and the thin film transistor can be compatible with conventional LTPS processes, reducing the process manufacturing cost. In addition, the intrinsic region is used to disconnect the current channel when the minority carrier concentration in the P region and the N region is lower than the first preset threshold value, and accordingly, the thin film transistor is in an off state; and when the electron concentration in the intrinsic region increases to a second preset threshold value, a current channel is formed through the tunneling effect, and accordingly, the thin film transistor is in an on state. In this way, the low current design of the thin film transistor is guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of a structure of a thin film transistor provided by an embodiment of the present invention;

[0037] Figure 2 Another structural schematic diagram of a thin film transistor provided by an embodiment of the present invention;

[0038] Figure 3 A schematic diagram of the working principle of a thin film transistor provided by an embodiment of the present invention;

[0039] Figure 4 A schematic diagram of a structure of a display device provided by an embodiment of the present invention;

[0040] Figure 5 A schematic diagram of a pixel circuit corresponding to a display device using a 1T1C architecture provided by an embodiment of the present invention;

[0041] Figure 6A schematic diagram of a structure of a pixel driving circuit provided in an embodiment of the present invention;

[0042] Figure 7 A schematic diagram of a structure of a display device provided by an embodiment of the present invention;

[0043] Figure 8 A method flow chart of a thin film transistor driving method provided by an embodiment of the present invention;

[0044] Fig. 9 for Figure 8 A method flow chart of step S101 in FIG.

[0045] Fig.10 for Figure 8 A method flow chart of step S102;

[0046] Description of reference numerals:

[0047] 10-substrate; 20-active layer; 21-PIN junction; 211-P region; 212-intrinsic region; 213-N region; 30-buffer layer; 40-gate insulating layer; 50-gate layer; 60-passivation layer; 70-source-drain layer; 71-source; 72-drain; 100-display substrate; 200-opposite substrate; 300-liquid crystal layer; 400-switching unit; 201-color resistance; 202-shielding part; 101-pixel electrode layer; 203-common electrode layer; T2-driving transistor; T3-switching transistor; 1000-pixel driving circuit; 2000-light-emitting device. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. And in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.

[0049] Unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0050] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, but are only intended to illustrate the content of the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0051] In related technologies, in order to achieve low power consumption design at low refresh rate and long-term charge retention, the leakage current level of TFT needs to be low enough. To this end, LTPO technology can be used to take into account both low leakage current and high mobility design. However, not only the compatibility of LTPS and IGZO processes needs to be considered, but also because IGZO needs to be prepared on LTPS in actual preparation, the film layer is complex and the cost is high.

[0052] In view of this, the embodiments of the present invention provide a thin film transistor, a driving method thereof, a pixel driving circuit and a display device, which are used to achieve a low leakage current design while taking into account the low cost production of the thin film transistor.

[0053] like Figure 1 As shown, an embodiment of the present invention provides a thin film transistor, including:

[0054] Substrate 10;

[0055] An active layer 20 is located on the substrate 10; the active layer 20 includes a PIN junction 21, and along a plane direction parallel to the substrate 10, the PIN junction 21 includes a P region 211, an intrinsic region 212 and an N region 213 arranged in sequence; the type of ions doped in the P region 211 is different from the type of ions doped in the N region 213;

[0056] Among them, the material of the active layer 20 is low-temperature polycrystalline silicon, the P region 211 and the N region 213 are used to construct a tunneling effect, and the intrinsic region 212 is used to disconnect the current channel when the minority carrier concentration in the P region 211 and the N region 213 is lower than a first preset threshold value, and to form the current channel through the tunneling effect when the electron concentration in the corresponding region increases to a second preset threshold value.

[0057] In the specific implementation process, the thin film transistor provided by the embodiment of the present invention includes a substrate 10 and an active layer 20 located on the substrate 10; wherein the substrate 10 can be a flexible substrate or a rigid substrate, which is not limited here. The material of the active layer 20 is a low-temperature polycrystalline silicon material, so that the manufacturing process of the thin film transistor can be directly compatible with the manufacturing process of the conventional LTPS TFT, and the manufacturing cost of the entire process is low. Moreover, the active layer 20 includes a PIN junction 21, and along the plane direction parallel to the substrate 10, the PIN junction 21 includes a P region 211, an intrinsic region 212 and an N region 213 arranged in sequence, wherein the ion type doped in the P region 211 is different from the ion type doped in the N region 213, for example, the ion doped in the P region 211 is P, and the ion doped in the N region 213 is B. In this way, a tunneling effect can be constructed through the P region 211 and the N region 213, thereby providing a possibility for the subsequent open state of the thin film transistor.

[0058] In addition, the intrinsic region 212 is used to disconnect the current channel when the minority carrier concentration in the P region 211 and the N region 213 is lower than the first preset threshold value. Exemplarily, the first preset threshold value can be an extremely low value; in this case, it is difficult for the thin film transistor to obtain current through the drift process. Accordingly, the device exhibits an extremely low off-state current level, and the thin film transistor is in the off state. Among them, the specific value of the first preset threshold value can be set according to the actual application needs, and is not limited here. Moreover, when the electron concentration in the intrinsic region 212 increases to the second preset threshold value, a current channel can be formed through the tunneling effect, so that the thin film transistor is in the on state. In this way, the on and off functions of the thin film transistor are guaranteed. Among them, the specific value of the second preset threshold value can be set according to the actual application needs, and is not limited here.

[0059] In the embodiment of the present invention, the P region 211 , the intrinsic region 212 , and the N region 213 are arranged flush with each other on a side facing away from the substrate 10 .

[0060] Still combined Figure 1In the exemplary embodiment shown, the P region 211, the intrinsic region 212, and the N region 213 are arranged flush with each other on the side facing away from the substrate 10, so that the flatness of the subsequent film layer preparation is guaranteed and the structural stability of the thin film transistor is guaranteed. In addition, it should be noted that the area and position distribution of the P region 211, the intrinsic region 212, and the N region 213 in the active layer 20 can be set according to the actual application needs and are not limited here.

[0061] In the embodiment of the present invention, the ions doped in the P region 211 are B and elements of the same group as B.

[0062] For example, the ions doped in the P region 211 are B, the dosage is 5e15 / cm2, and the energy is 30 KeV. Of course, the ions doped in the P region 211 can also be set according to actual application needs, which is not limited here.

[0063] In the embodiment of the present invention, the ions doped in the N region 213 are P and elements of the same group corresponding to P.

[0064] For example, the ions doped in the N region 213 are P, the dosage is 5e15 / cm2, and the energy is 70 KeV. Of course, the ions doped in the N region 213 can also be set according to actual application needs, which is not limited here.

[0065] In an embodiment of the present invention, the thin film transistor further includes a gate insulating layer 40 and a gate layer 50 located on the active layer 20 , wherein the orthographic projection of the intrinsic region 212 on the substrate 10 completely falls within the region of the orthographic projection of the gate layer 50 on the substrate 10 .

[0066] In one exemplary embodiment, Figure 2 As shown, the thin film transistor further includes a gate insulating layer 40 and a gate layer 50 located on the active layer 20; illustratively, the gate insulating layer 40 is SiOx / SiNx, wherein the thickness of SiOx ranges from 800 angstroms to 1000 angstroms, and the thickness of SiNx ranges from 400 angstroms to 500 angstroms; illustratively, the gate layer 50 is Mo / Al / Mo, and the corresponding thickness ranges from 3000 angstroms to 5000 angstroms. Of course, the specific materials and specific thickness values ​​of the gate insulating layer 40 and the gate layer 50 can also be set according to actual application conditions, and are not limited here.

[0067] In the embodiment of the present invention, the thin film transistor is an N-type transistor or a P-type transistor.

[0068] In an embodiment of the present invention, the thin film transistor also includes a passivation layer 60 and a source-drain layer 70 located on the gate layer 50, the source 71 in the source-drain layer 70 is electrically connected to the P region 211, and the drain 72 in the source-drain layer 70 is electrically connected to the N region 213; when the thin film transistor is an N-type transistor and the drain 72 receives a positive voltage, and the positive voltage applied to the gate layer 50 is less than a third preset threshold, the current channel is disconnected, and the thin film transistor is in an off state; when the positive voltage received by the gate layer 50 is greater than or equal to the third preset threshold, the electron concentration in the intrinsic region 212 shows an increasing trend, the current channel is turned on, and the thin film transistor is in an on state.

[0069] Still combined Figure 2 In the exemplary embodiment shown, the thin film transistor further includes a passivation layer 60 and a source-drain layer 70 located on the gate layer 50 . A source 71 in the source-drain layer 70 is electrically connected to the P region 211 , and a drain 72 in the source-drain layer 70 is electrically connected to the N region 213 .

[0070] Combine the following Figure 3 The working principle schematic diagram shown in the figure provides a corresponding explanation of the working principle of the thin film transistor in the embodiment of the present invention.

[0071] In one exemplary embodiment, if the thin film transistor is an N-type transistor, when a positive voltage is applied to the drain 72, due to the reverse characteristics of the PIN junction 21, the minority carrier concentrations of the P region 211 and the N region 213 reach the first preset value threshold. At this time, the minority carrier concentrations of the P region 211 and the N region 213 are extremely low, and it is difficult to obtain current through the drift process. The device exhibits an extremely low off-state current level. Accordingly, if the positive voltage applied to the gate layer 50 is less than the third preset threshold, the thin film transistor is in the off state. When the positive voltage applied to the gate layer 50 exceeds the third preset threshold, the electron concentration in the intrinsic region 212 gradually increases. When the electron concentration in the intrinsic region 212 increases to the second preset threshold, the energy bands of the P region 211 and the intrinsic region 212 are bent so that the bottom of the conduction band of the intrinsic region 212 is lower than the top of the valence band of the P region 211. At the same time, because the grain boundaries in the LTPS form a certain number of deep energy levels and band tail states in the band gap. In this case, the electrons in the valence band of the P region 211 (such as Figure 3 The deep energy levels and band tail states in the band gap will undergo trap-assisted tunneling to the conduction band of region I, thus placing the device in the on state. Figure 3 The direction indicated by the middle arrow is the tunneling direction, and region I represents the intrinsic region. In this way, flexible control of the off state and the on state of the thin film transistor is achieved. Accordingly, the thin film transistor provided in the embodiment of the present invention is essentially a tunneling LTPS thin film transistor. Among them, the specific value of the third preset threshold value can be set according to the actual application needs and is not limited here.

[0072] It should be noted that the thin film transistor provided in the embodiment of the present invention, in addition to the film layers mentioned above, also includes, for example, a buffer layer 30 located between the active layer 20 and the substrate 10. For example, the buffer layer 30 is SiOx. Of course, other film layer structures can be provided according to actual application needs, which are not limited here.

[0073] In the embodiment of the present invention, for Figure 2 The thin film transistor shown can be prepared by using one of the following process flows:

[0074] S1: Cleaning the glass substrate according to the standard process;

[0075] S2: using a plasma enhanced chemical vapor deposition (PECVD) process to deposit SiOx as a buffer layer 30, the thickness of which ranges from 2000 angstroms to 5000 angstroms;

[0076] S3: depositing a-Si by PECVD process, and reducing H content by annealing process, annealing condition is 400° C. to 500° C., time is 90 min to 180 min, to obtain active layer 20;

[0077] S4: using an excimer laser annealing (ELA) process to obtain an LTPS polysilicon layer; performing photolithography and ICP etching to pattern the polysilicon layer to obtain a patterned polysilicon layer;

[0078] S5: depositing a gate insulating layer 40 by a PECVD process, wherein the film layer is SiOx / SiNx, wherein the thickness of the SiOx film layer is in a range of 800 angstroms to 1000 angstroms, and the thickness of the SiNx film layer is in a range of 400 angstroms to 500 angstroms;

[0079] S6: depositing Mo by magnetron sputtering to a thickness of 3000 angstroms to 5000 angstroms, and performing patterning by photolithography and wet etching to obtain a patterned Mo layer;

[0080] S7: Using the patterned metal layer as a mask, ion implantation is performed on the left region of the active layer 20 to obtain a P region 211, wherein the implanted ions are B, the dose is 5e15 / cm2, and the energy is 30KeV; after the implantation is completed, the patterned Mo layer is removed by wet method;

[0081] S8: depositing Mo by magnetron sputtering to a thickness of 3000 angstroms to 5000 angstroms, and performing patterning by photolithography and wet etching to obtain a patterned Mo layer;

[0082] S9: Using the patterned metal layer as a mask, ion implantation is performed on the right region of the active layer 20 to obtain an N region 213, wherein the implanted ions are P, the dose is 5e15 / cm2, and the energy is 70KeV;

[0083] S10: After the implantation is completed, the patterned Mo layer is removed by wet method;

[0084] S11: depositing Mo by magnetron sputtering to a thickness of 3000 angstroms to 5000 angstroms, and obtaining a patterned gate by photolithography and wet etching;

[0085] S12: depositing a gate insulating layer 40 by a PECVD process, wherein the film layer is SiOx / SiNx and has a thickness ranging from 4000 angstroms to 6000 angstroms, and performing photolithography and dry etching to form contact holes;

[0086] S13: depositing Mo / Al / Mo by magnetron sputtering with a thickness ranging from 3000 angstroms to 5000 angstroms, and obtaining patterned source and drain electrodes by photolithography and wet etching;

[0087] S14: preparing another passivation layer 60 on the source and drain electrodes.

[0088] Of course, in the specific implementation process, other process flows may also be used to prepare the thin film transistor of the embodiment of the present invention, which will not be described in detail here.

[0089] Based on the same inventive concept, Figure 4 and Figure 5 As shown, Figure 4 A schematic diagram of a structure of a display device provided by an embodiment of the present invention is shown in FIG. Figure 5 The display device adopts a pixel circuit corresponding to the 1T1C architecture. Specifically, the display device includes:

[0090] A display substrate 100, an opposite substrate 200 disposed opposite to the display substrate 100, and a liquid crystal layer 300 located between the display substrate 100 and the opposite substrate 200;

[0091] The display substrate 100 includes a plurality of switch units 400 arranged in an array, each of the switch units 400 is configured to drive the deflection of the liquid crystal layer 300 , and each of the switch units 400 is a thin film transistor as described in any one of the above items.

[0092] In the specific implementation process, the thin film transistor provided by the embodiment of the present invention can be applied to a liquid crystal display device, and accordingly, the display device provided by the embodiment of the present invention can be a liquid crystal display device. Specifically, the display device includes a display substrate 100, an opposing substrate 200 arranged opposite to the display substrate 100, and a liquid crystal layer 300 located between the display substrate 100 and the opposing substrate 200. Exemplarily, the opposing substrate 200 is a color film (CF) substrate. Among them, the display substrate 100 includes a plurality of switch units 400 arranged in an array, each switch unit 400 is configured to drive the deflection of the liquid crystal layer 300, and each switch unit 400 adopts the relevant structure of the thin film transistor described above. The specific number and specific arrangement of the plurality of switch units 400 can be set according to the actual application needs, and are not limited here.

[0093] In the embodiment of the present invention, still combined with Figure 4 As shown, the display device further includes a gate layer 50 located between the active layer 20 and the substrate 10 , and the orthographic projection of the intrinsic region 212 on the substrate 10 completely falls within the region of the orthographic projection of the gate layer 50 on the substrate 10 .

[0094] In the specific implementation process, since the switch unit 400 can use the aforementioned tunneling LTPS thin film transistor, the tunneling LTPS thin film transistor can provide a much smaller off-state current than the traditional a-Si TFT, so that an extremely low frame refresh rate can be achieved compared to the traditional a-Si TFT LCD. In addition, since the off-state current of the tunneling LTPS thin film transistor is low, the capacitance value of the required storage capacitor can be reduced, thereby reducing the area of ​​the storage capacitor, improving the pixel aperture ratio, and ensuring the light transmittance of the display device.

[0095] It should be noted that, Figure 4 In the exemplary embodiment shown, the counter substrate 200 includes color resists 201 arranged in an array and a shielding portion 202 surrounding the color resists 201; the display device further includes a pixel electrode layer 101 located on the side of the passivation layer 60 away from the substrate 10, and a common electrode layer 203 located on the side of the color resists 201 and the shielding portion 202 close to the liquid crystal layer 300; Figure 5In the pixel circuit shown, Cs represents a storage capacitor formed by the gate layer 50, the pixel electrode layer 101, and the dielectric layer between the gate layer 50 and the pixel electrode layer 101; Clc represents a capacitor formed by the common electrode layer 203, the pixel electrode layer 101, and the liquid crystal layer 300 therebetween; CE represents a common electrode, and PE represents a pixel electrode. The specific driving principle corresponding to the pixel circuit can refer to the implementation in the relevant technology, which will not be described in detail here. The display device also includes a shading layer LS located between the gate layer 50 and the substrate 10, a data line coupled to the source 71 of the switch unit 400, and a gate line coupled to the gate of the switch unit 400, wherein D represents a data line and G represents a gate line. Of course, the display device provided in the embodiment of the present invention, in addition to the above-mentioned film layers, can also be provided with other film layer structures according to actual application needs, which are not limited here.

[0096] In addition, in the specific implementation process, the same thin film transistor can be used as a P-type transistor or an N-type transistor according to different bias settings. Figure 2 In the exemplary embodiment shown, the current thin film transistor can be switched from an N-type transistor to a P-type transistor by simply grounding the drain 72 electrically connected to the N-region 213 and connecting the source 71 electrically connected to the P-region 211 to a negative voltage.

[0097] Based on the same inventive concept, Figure 6 As shown, the embodiment of the present invention further provides a pixel driving circuit 1000, and the pixel driving circuit 1000 includes:

[0098] A driving transistor T2, and a switch transistor T3 coupled to a gate of the driving transistor T2;

[0099] The switch transistor T3 is a thin film transistor as described in any one of the above.

[0100] In the specific implementation process, the aforementioned thin film transistor can be applied to the current-driven pixel driving circuit 1000. Specifically, the switch transistor T3 coupled to the gate of the driving transistor T2 adopts the aforementioned tunneling LTPS thin film transistor. Figure 6 The pixel driving circuit 1000 of the 6T1C architecture shown in FIG. 1 is taken as an example, wherein V DD Indicates the high potential signal terminal, V SS Indicates the low potential signal terminal, V DATA Indicates the data signal terminal, V INI Indicates the initialization signal terminal, V EM1 Represents the first light-emitting control signal terminal, V EM2 Represents the second light-emitting control signal terminal, V SCAN1 Represents the first scanning control signal terminal, V SCAN2Indicates the second scanning control signal terminal, C st represents the storage capacitor; T2 is the driving transistor T2, T3 is the tunneling LTPS thin film transistor, and the gate of the T2 transistor that controls the data signal is coupled to T3, so that the signal voltage input on the gate can be better maintained after T3 is turned off, that is, it is guaranteed. Figure 6 The stability of the potential of the N2 node. Except for T3, T1, T2, T4, T5 and T6 are all conventional LTPS transistors. Since the tunneling thin-film transistor in the embodiment of the present invention can also be manufactured using the LTPS process, the use of the same semiconductor material can effectively avoid the interference between the LTPS process and the IGZO process used in the LTPO pixel architecture compared to the traditional LTPO pixel architecture, and there is no need to consider the compatibility between the two processes. In addition, the process film layer corresponding to the pixel driving circuit 1000 provided in the embodiment of the present invention is simpler, and there is no need to prepare the corresponding film layer of IGZO above the corresponding film layer of LTPS as in the LTPO process, thereby reducing the number of overall process masks (masks), greatly reducing the production cost.

[0101] In the embodiment of the present invention, the material of the active layer 20 of the driving transistor T2 is low temperature polysilicon, and the active layer 20 of the driving transistor T2 and the active layer 20 of the switch transistor T3 are provided in the same layer and with the same material.

[0102] In the specific implementation process, the process for preparing the switch transistor T3 is highly compatible with the LTPS process used by other transistors. Moreover, the active layer 20 of the driving transistor T2 and the active layer 20 of the switch transistor T3 are arranged in the same layer and material, which greatly reduces the process manufacturing cost.

[0103] It should be noted that the thin film transistor provided in the embodiment of the present invention can be used in addition to Figure 6 The pixel driving circuit 1000 shown can also be applied to pixel driving circuits 1000 of other pixel architectures according to actual needs. In addition, the thin film transistor provided by the embodiment of the present invention can also be used to prepare a low-power complementary metal oxide semiconductor (CMOS) circuit, and can also be applied to a peripheral array substrate row driver (Gate Driver on Array, GOA) circuit, etc., which is not limited here.

[0104] The embodiment of the present invention further provides a display device, such as Figure 7 As shown, the display device includes:

[0105] As described above, the pixel driving circuit 1000 and the light emitting device 2000 electrically connected to the pixel driving circuit 1000.

[0106] In the specific implementation process, the light-emitting device 2000 can be an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro light-emitting diode (Micro LED), or a mini-LED. Of course, the light-emitting device 2000 can also be set according to the actual application needs, which is not limited here. In addition, the specific number and specific arrangement of the light-emitting devices 2000 can be set according to the actual application needs, which is not limited here.

[0107] Since the principle of solving the problem of the display device is similar to that of the aforementioned thin film transistor, the implementation of the display device can refer to the implementation of the aforementioned thin film transistor, and the repeated parts will not be repeated.

[0108] It should be noted that the display device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by those skilled in the art, and will not be described in detail here, nor should they be used as limitations on the present invention.

[0109] Based on the same inventive concept, Figure 8 As shown, an embodiment of the present invention further provides a driving method of a thin film transistor. Specifically, the thin film transistor includes a substrate 10 and an active layer 20 located on the substrate 10; the active layer 20 includes a PIN junction 21, and along a plane direction parallel to the substrate 10, the PIN junction 21 includes a P region 211, an intrinsic region 212 and an N region 213 arranged in sequence; the type of ions doped in the P region 211 is different from the type of ions doped in the N region 213; the material of the active layer 20 is low-temperature polysilicon, and the P region 211 and the N region 213 are used to construct a tunneling effect; accordingly, the driving method includes:

[0110] S101: if the minority carrier concentration in the P region and the N region is lower than a first preset threshold, disconnecting the current channel and controlling the thin film transistor to be in an off state;

[0111] S102: If the electron concentration in the intrinsic region increases to a second preset threshold, the current channel is formed in the intrinsic region through the tunneling effect.

[0112] In the specific implementation process, there is no execution order between step S101 and step S102. For the specific implementation process of step S101 to step S102, reference can be made to the description of the above-mentioned relevant parts, and no further description is given here.

[0113] In the embodiment of the present invention, if the thin film transistor is an N-type transistor and further includes a source electrode 71 electrically connected to the P region 211, a drain electrode 72 electrically connected to the N region 213, and a gate insulating layer 40 and a gate layer 50 located on the active layer 20, Fig. 9 As shown, in step S101, controlling the thin film transistor to be in an off state includes:

[0114] S201: Under the effect of the reverse characteristic of the PIN junction, the minority carrier concentrations of the P region and the N region are lower than a first preset threshold value;

[0115] S202: If the drain receives a positive voltage and the positive voltage applied to the gate layer is less than a third preset threshold, control the thin film transistor to be in an off state.

[0116] In the specific implementation process, the specific implementation process of step S201 to step S202 can refer to the description of the aforementioned relevant parts and will not be repeated here.

[0117] In the embodiment of the present invention, Fig.10 As shown, in step S102, forming the current channel in the intrinsic region 212 by the tunneling effect includes:

[0118] S301: if the positive voltage received by the gate layer is greater than or equal to the third preset threshold, gradually increasing the electron concentration of the intrinsic region, and bending the energy bands of the P region and the intrinsic region so that the conduction band bottom of the intrinsic region is lower than the valence band top of the P region;

[0119] S302: Controlling the electrons in the valence band of the P region to undergo trap-assisted tunneling to the conduction band of the intrinsic region via the deep energy levels and band tail states formed in the band gap at the grain boundary, thereby forming the current channel in the intrinsic region and the thin film transistor is in an on state.

[0120] In the specific implementation process, the specific implementation process of step S301 to step S302 can refer to the description of the aforementioned relevant parts and will not be repeated here.

[0121] The embodiment of the present invention provides a thin film transistor, a driving method thereof, a pixel driving circuit 1000 and a display device, wherein the thin film transistor includes a substrate 10 and an active layer 20 located on the substrate 10; the active layer 20 includes a PIN junction 21, and along a plane direction parallel to the substrate 10, the PIN junction 21 includes a P region 211, an intrinsic region 212 and an N region 213 arranged in sequence; the ion type doped in the P region 211 is different from the ion type doped in the N region 213. For example, the ions doped in the P region 211 are P, and the ions doped in the N region 213 are B. In this way, a tunneling effect can be constructed through the PIN junction 21; moreover, the material of the active layer 20 is low temperature polysilicon, and the thin film transistor can be compatible with the conventional LTPS process, reducing the process manufacturing cost. In addition, the intrinsic region 212 is used to disconnect the current channel when the minority carrier concentration in the P region 211 and the N region 213 is lower than the first preset threshold value, and accordingly, the thin film transistor is in the off state; and when the electron concentration in the intrinsic region 212 increases to the second preset threshold value, a current channel is formed through the tunneling effect, and accordingly, the thin film transistor is in the on state. In this way, the low current design of the thin film transistor is guaranteed.

[0122] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0123] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A thin film transistor, characterized in that: include: substrate; An active layer is located on the substrate; the active layer includes a PIN junction, and along a plane direction parallel to the substrate, the PIN junction includes a P region, an intrinsic region and an N region arranged in sequence; the type of ions doped in the P region is different from the type of ions doped in the N region; Among them, the material of the active layer is low-temperature polysilicon, the P region and the N region are used to construct a tunneling effect, the intrinsic region is used to disconnect the current channel when the minority carrier concentration in the P region and the N region is lower than a first preset threshold value, and to form the current channel through the tunneling effect when the electron concentration in the corresponding region increases to a second preset threshold value.

2. The thin film transistor according to claim 1, wherein: The P region, the intrinsic region and the N region are arranged flush with each other on a side facing away from the substrate.

3. The thin film transistor according to claim 1, wherein: The ions doped in the P region are B and elements of the same group as B.

4. The thin film transistor according to claim 1, wherein: The ions doped in the N region are P and elements of the same group corresponding to P.

5. The thin film transistor according to any one of claims 1 to 4, characterized in that: It also includes a gate insulating layer and a gate layer located on the active layer, wherein the orthographic projection of the intrinsic region on the substrate completely falls within the area of ​​the orthographic projection of the gate layer on the substrate.

6. The thin film transistor according to claim 5, characterized in that: The thin film transistor is an N-type transistor or a P-type transistor.

7. The thin film transistor according to claim 6, wherein: It also includes a passivation layer and a source-drain layer located on the gate layer, wherein the source electrode in the source-drain layer is electrically connected to the P region, and the drain electrode in the source-drain layer is electrically connected to the N region; when the thin film transistor is an N-type transistor and the drain electrode receives a positive voltage, and the positive voltage applied to the gate layer is less than a third preset threshold value, the current channel is disconnected, and the thin film transistor is in an off state; When the positive voltage received by the gate layer is greater than or equal to the third preset threshold, the electron concentration in the intrinsic region tends to increase, the current channel is turned on, and the thin film transistor is in an on state.

8. A display device, characterized in that: include: A display substrate, an opposite substrate arranged opposite to the display substrate, and a liquid crystal layer located between the display substrate and the opposite substrate; Wherein, the display substrate comprises a plurality of switch units arranged in an array, each of the switch units is configured to drive the deflection of the liquid crystal layer, and each of the switch units is a thin film transistor as described in any one of claims 1-7.

9. The display device according to claim 8, wherein: It also includes a gate layer located between the active layer and the substrate, and the orthographic projection of the intrinsic region on the substrate completely falls within the area of ​​the orthographic projection of the gate layer on the substrate.

10. A pixel driving circuit, characterized in that: include: a driving transistor, and a switching transistor coupled to a gate of the driving transistor; The switch transistor is a thin film transistor as described in any one of claims 1 to 7.

11. The pixel driving circuit according to claim 10, wherein: The material of the active layer of the driving transistor is low-temperature polysilicon, and the active layer of the driving transistor and the active layer of the switch transistor are arranged in the same layer and with the same material.

12. A display device, characterized in that: include: The pixel driving circuit as claimed in claim 10, and a light emitting device electrically connected to the pixel driving circuit.

13. A method for driving a thin film transistor, characterized in that: The thin film transistor comprises a substrate and an active layer on the substrate; the active layer comprises a PIN junction, and along a plane direction parallel to the substrate, the PIN junction comprises a P region, an intrinsic region and an N region arranged in sequence; the type of ions doped in the P region is different from the type of ions doped in the N region; The material of the active layer is low temperature polysilicon, and the P region and the N region are used to construct a tunneling effect; The driving method comprises: If the minority carrier concentration in the P region and the N region is lower than a first preset threshold, the current channel is disconnected to control the thin film transistor to be in an off state; If the electron concentration in the intrinsic region increases to a second preset threshold, the current channel is formed in the intrinsic region through the tunneling effect.

14. The driving method according to claim 13, characterized in that: If the thin film transistor is an N-type transistor and further includes a source electrode electrically connected to the P region, a drain electrode electrically connected to the N region, and a gate insulating layer and a gate layer located on the active layer, the step of controlling the thin film transistor to be in an off state includes: Under the effect of the reverse characteristic of the PIN junction, the minority carrier concentrations of the P region and the N region are lower than a first preset threshold value; If the drain receives a positive voltage and the positive voltage applied to the gate layer is less than a third preset threshold, the thin film transistor is controlled to be in an off state.

15. The driving method according to claim 14, characterized in that: The forming the current channel in the intrinsic region by the tunneling effect comprises: If the positive voltage received by the gate layer is greater than or equal to the third preset threshold, the electron concentration of the intrinsic region is gradually increased, and the energy bands of the P region and the intrinsic region are bent so that the conduction band bottom of the intrinsic region is lower than the valence band top of the P region; The electrons in the valence band of the P region are controlled to undergo trap-assisted tunneling to the conduction band of the intrinsic region via the deep energy level and band tail state formed in the band gap at the grain boundary, so that the current channel is formed in the intrinsic region and the thin film transistor is in an on state.

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