LED chip and manufacturing method thereof
By designing the epitaxial unit and dam structure on the first substrate of the LED chip, the problem of the epitaxial unit being crushed due to lateral force in the film compression process is solved, and the effect of reducing the problem of edge collapse and angle collapse is achieved.
Patent Information
- Application Number
- CN202510396133.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2025-05-16
AI Technical Summary
During the production process of LED chips, epitaxial units are easily crushed due to lateral forces in the film compression process, resulting in problems such as edge collapse and angle collapse.
An LED chip is designed that includes an epitaxial unit and a dam structure on the first substrate, which is located at least part of the outside of the epitaxial unit and has a gap with the epitaxial unit to share the lateral force.
The lateral force is shared by the dam structure, the probability of epitaxial unit being crushed is reduced, the problems of edge collapse and angle collapse are alleviated, and the appearance is abnormal.
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Figure CN120018653A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of LED technology, and in particular to an LED chip and a manufacturing method thereof. Background Art
[0002] As a new generation of lighting source, light emitting diode (LED) has many advantages such as high efficiency and energy saving, green environmental protection, and long service life. It is widely used in lighting, display, backlight and other fields. With the continuous advancement of science and technology and the continuous growth of market demand, the LED industry has developed rapidly, and its manufacturing process and technology are also constantly innovating and improving. However, in the production process of LED, there are still many technical challenges, and the edge collapse problem is one of them. Summary of the invention
[0003] In view of the above problems, the present application provides an LED chip and a method for manufacturing the same, so as to reduce the edge collapse phenomenon during the manufacturing process of the LED chip. The specific solution is as follows:
[0004] An LED chip, comprising:
[0005] A first substrate, wherein a surface of the first substrate has a first area and a second area surrounding the first area;
[0006] An epitaxial unit located in a first region of the first substrate and a dam structure located in a second region of the first substrate, the epitaxial unit comprising a stacked P-type semiconductor layer, a quantum well active layer and an N-type semiconductor layer, the dam structure being located at least in a portion of an outer side of the epitaxial unit in a first direction, and a gap being provided between the dam structure and the epitaxial unit, and the first direction being parallel to a plane where the first substrate is located;
[0007] A P electrode is located on a side of the first substrate away from the epitaxial unit.
[0008] Optionally, the dam structure is arranged around the epitaxial unit.
[0009] Optionally, the dam structure is composed of a plurality of columnar units, and the distance between adjacent columnar units is not less than 3 microns.
[0010] Optionally, in the first direction, a distance of a gap between the dam structure and the epitaxial unit is not less than 3 micrometers and not greater than a width of the second region.
[0011] Optionally, in the first direction, the width of the dam structure is greater than 5 microns.
[0012] Optionally, the P-type semiconductor layer includes a P-type confinement layer located on a side of the quantum well active layer away from the N-type semiconductor layer; the LED chip also includes a P-type window layer located on a side of the P-type semiconductor layer away from the quantum well active layer.
[0013] Optionally, it also includes: an omnidirectional reflection layer located between the P-type window layer and the first substrate.
[0014] Optionally, the omnidirectional reflective layer includes:
[0015] a first ohmic contact layer located on a surface of the P-type window layer facing the first substrate, wherein the first ohmic contact layer covers the third region of the P-type window layer and exposes the fourth region of the P-type window layer;
[0016] a dielectric layer located on a surface of the first ohmic contact layer facing the first substrate, wherein the dielectric layer has a plurality of through holes, and the through holes expose a partial area of the first ohmic contact layer;
[0017] a conductive filling member located in the through hole;
[0018] a mirror layer located on the side of the dielectric layer facing the first substrate, the mirror layer being a conductive layer and electrically connected to the conductive filling member;
[0019] The P electrode is electrically connected to the P-type semiconductor layer through the first substrate, the mirror layer, the conductive filler, and the first ohmic contact layer.
[0020] Optionally, the dielectric layer includes a stacked first component layer, a second component layer and a third component layer, wherein the first component layer is an ITO layer or an IZO layer or an Al2O3 layer, the second component layer is a SiO2 layer, and the third component layer is an Al2O3 layer or an ITO layer or an IZO layer;
[0021] The conductive filler comprises a stacked Au layer, a Zn layer and an Au layer, or a stacked Au layer, a Be layer and an Au layer;
[0022] The mirror layer includes a stacked Ag layer, a TiW layer, a Ti layer, a Pt layer, and an Au layer.
[0023] Optionally, the N-type semiconductor layer includes an N-type confinement layer located on a side of the quantum well active layer away from the P-type semiconductor layer, and an N-type roughening layer located on a side of the N-type confinement layer away from the quantum well active layer.
[0024] A method for manufacturing an LED chip, comprising:
[0025] Forming an epitaxial layer on the surface of a semiconductor substrate, wherein the epitaxial layer includes a stacked N-type semiconductor layer, a quantum well active layer, and a P-type semiconductor layer;
[0026] Fixing the side of the epitaxial layer away from the semiconductor substrate to a first substrate, and removing the semiconductor substrate;
[0027] The epitaxial layer is cut from a side of the epitaxial layer away from the first substrate to form a plurality of epitaxial units and a plurality of dam structures, wherein the dam structures correspond to the epitaxial units one by one, and in a first direction, the dam structures are at least located in at least a portion of the outer side of the epitaxial units, and there is a gap between the dam structures and the epitaxial units, and the first direction is parallel to the plane where the first substrate is located;
[0028] forming a P electrode on a side of the first substrate away from the epitaxial unit;
[0029] A second carrier film is fixed on a side of the P electrode away from the first substrate;
[0030] Splitting the first substrate from the side of the second carrier film away from the P electrode to form a plurality of LED grains;
[0031] The second carrier film on the surface of the first substrate away from the epitaxial layer is removed by using a film turning process, and the first carrier film is fixed on the surface of the first substrate away from the epitaxial layer.
[0032] Optionally, before fixing the side of the epitaxial layer away from the semiconductor substrate to the first substrate, the method further comprises:
[0033] An omnidirectional reflection layer is formed on a side of the P-type semiconductor layer away from the quantum well active layer, and the P electrode is electrically connected to the P-type semiconductor layer through the omnidirectional reflection layer and the first substrate.
[0034] The LED chip provided in the embodiment of the present application, in addition to including an epitaxial unit located in the first area of the first substrate, also includes a dam structure located in the second area of the first substrate, and in a plane parallel to the first substrate, the dam structure is located at least in at least a portion of the area outside the epitaxial unit. Therefore, in the process of replacing the carrier film at the bottom of the LED chip using a film pressing process, the dam structure can be used to share the lateral force applied to the edge of the epitaxial unit, thereby reducing the possibility of the epitaxial unit being crushed due to pressure, alleviating problems such as edge collapse and corner collapse generated during the production process of the LED chip, and reducing abnormal appearance. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.
[0036] Figure 1 A schematic diagram of the structure of an LED chip provided in this application;
[0037] Figure 2 A schematic diagram of the structure of another LED chip provided in this application;
[0038] Figure 3 A top view of an LED chip provided in this application;
[0039] Figure 4 A top view of an LED chip provided in this application;
[0040] Figure 5 A flowchart of a method for manufacturing an LED chip provided in this application;
[0041] Figure 6 for- Fig.15 A schematic diagram of some structures involved in the manufacturing process of an LED chip provided in this application. DETAILED DESCRIPTION
[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0043] It is obvious to those skilled in the art that various modifications and changes can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and changes of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.
[0044] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.
[0045] As described in the background technology section, there are still many technical challenges in the production process of LEDs, and the edge collapse problem is one of them.
[0046] This is because when making LEDs, it involves cutting a LED structure including multiple LED grains into multiple independent LED grains. During the cutting process, cutting marks will be generated on the carrier film on the back of the LED grain used to carry the LED grains. Therefore, it is necessary to replace the carrier film on the back of the LED grain with a new carrier film through a film turning process. Specifically, the film turning process of the LED grain includes: pasting a carrier film on the front of the LED grain using a film pressing process, the LED grain includes a substrate and an epitaxial structure, the epitaxial structure is located in a partial area on the front of the substrate, and there is a height difference between the surface of the epitaxial structure and the surface of the substrate; flipping the LED grain, removing the carrier film on the back of the LED grain, and pasting another carrier film on the back of the LED grain using a film pressing process; removing the carrier film on the front of the LED grain to complete the replacement of the carrier film on the back of the LED grain.
[0047] Due to the height difference between the surface of the epitaxial structure and the surface of the substrate, when the carrier film is pasted on the front or back of the LED chip using the lamination process, the edge area of the epitaxial structure may be crushed due to the pressure, resulting in problems such as edge collapse and corner collapse.
[0048] In view of this, the present application embodiment provides an LED chip, such as Figure 1 As shown, the LED chip includes:
[0049] A first substrate 10, wherein a surface of the first substrate 10 has a first area and a second area surrounding the first area;
[0050] The epitaxial unit 21 located in the first region of the first substrate 10 and the dam structure 22 located in the second region of the first substrate 10 are as follows: Figure 2 As shown, the epitaxial unit 21 includes a stacked P-type semiconductor layer 211, a quantum well active layer 212 and an N-type semiconductor layer 213. In a first direction X, the dam structure 22 is at least located in a partial area outside the epitaxial unit 21, and there is a gap between the dam structure 22 and the epitaxial unit 21. The first direction X is parallel to the plane where the first substrate 10 is located;
[0051] A P electrode 30 is located on a side of the first substrate 10 away from the epitaxial unit 21 .
[0052] Optionally, in one embodiment of the present application, the LED chip also includes: a first carrier film 40 located on the side of the P electrode 30 away from the first substrate 10. Optionally, the first carrier film can be a blue film, a white film, or other types of carrier films. The present application does not limit this, and it depends on the specific circumstances.
[0053] The LED chip provided in the embodiment of the present application, in addition to including an epitaxial unit located in the first area of the first substrate, also includes a dam structure located in the second area of the first substrate, and in a plane parallel to the first substrate, the dam structure is located at least in a partial area outside the epitaxial unit. Therefore, in the process of replacing the carrier film at the bottom of the LED chip using a film pressing process, the dam structure can be used to share the lateral force applied to the edge of the epitaxial unit, thereby reducing the possibility of the epitaxial unit being crushed due to pressure, alleviating problems such as edge collapse and corner collapse generated during the production process of the LED chip, and reducing abnormal appearance.
[0054] Optionally, in one embodiment of the present application, Figure 3 As shown, in a plane parallel to the plane where the first substrate 10 is located, the dam structure 22 is arranged around the epitaxial unit 21, so that in the process of replacing the carrier film at the bottom of the LED chip by the lamination process, the dam structure 22 can be used to share the lateral force applied to the edge of the epitaxial unit 21, and the dam structure 22 is used to protect the side edges of the epitaxial unit 21, further reducing the situation where the epitaxial unit 21 is crushed due to the pressure, and alleviating the problems of edge collapse and corner collapse generated during the production process of the LED chip. Among them, the lateral force applied to the edge of the epitaxial unit refers to the force applied to the edge of the epitaxial unit and at a certain angle with the direction perpendicular to the plane where the first substrate is located, and the angle is greater than 0° and less than 90°.
[0055] In another embodiment of the present application, Figure 4 As shown, the dam structure 22 is composed of a plurality of columnar units 221, and the distance between adjacent columnar units 221 is not less than 3 microns, so that in the process of replacing the carrier film at the bottom of the LED chip by the lamination process, the plurality of columnar units 221 can be used to share the lateral force applied to the edge of the epitaxial unit 21. Optionally, the columnar units 221 can be arranged around the epitaxial unit 21, and the plurality of columnar units 221 can be used to protect the sides of the epitaxial unit 21, further reducing the possibility that the epitaxial unit 21 is crushed due to the pressure, and alleviating the problems of edge collapse, corner collapse, etc. generated during the production process of the LED chip.
[0056] On the basis of any of the above embodiments, in one embodiment of the present application, in the first direction, the gap between the dam structure and the epitaxial unit is not less than 3 microns and not greater than the width of the second region, so as to avoid the gap between the dam structure and the epitaxial unit being too small, thereby increasing the difficulty of manufacturing. It should be noted that, in the present embodiment, the second region of the first substrate is the region where the cutting path in the traditional LED chip is located, and the width of the second region is the width of the cutting path in the traditional LED chip, so that the addition of the dam structure does not increase the size of the LED chip in the first direction, but the present application does not limit this, and it depends on the specific situation.
[0057] On the basis of any of the above embodiments, in one embodiment of the present application, in the first direction, the width of the dam structure is greater than 5 microns, so that in the process of replacing the carrier film at the bottom of the LED chip using the lamination process, the dam structure can provide sufficient support for the force applied to the epitaxial unit, and better share the lateral force applied to the edge of the epitaxial unit 21, so that the dam structure can be used to effectively protect the side edges of the epitaxial unit, further reduce the possibility of the epitaxial unit being crushed due to pressure, and alleviate the problems of edge collapse, corner collapse, etc. generated in the process of manufacturing the LED chip, but the present application does not limit this, and it depends on the specific situation.
[0058] Based on any of the above embodiments, in one embodiment of the present application, continue as follows Figure 2 As shown, the P-type semiconductor layer 211 includes a P-type confinement layer located on the side of the quantum well active layer 212 away from the N-type semiconductor layer 213; the N-type semiconductor layer 213 includes an N-type confinement layer 2131 located on the side of the quantum well active layer 212 away from the P-type semiconductor layer 211 and an N-type roughening layer 2132 located on the side of the N-type confinement layer 2131 away from the quantum well active layer 212. The P-type confinement layer, the quantum well active layer and the N-type confinement layer constitute the light-emitting layer of the LED chip, which is used to generate light, and the N-type roughening layer is used to change the angle of the light emitted by the light-emitting layer to the surface of the N-type roughening layer, thereby increasing the light emission efficiency of the epitaxial unit, thereby improving the light extraction efficiency of the LED chip.
[0059] Optionally, based on the above embodiment, in one embodiment of the present application, continue as follows Figure 2As shown, the LED chip further includes: a P-type window layer 50 located on the side of the P-type semiconductor layer 211 away from the quantum well active layer 212, so as to form a low-resistance path on the side of the P-type semiconductor layer 211 away from the quantum well active layer 212, and to diffuse the current provided by the P electrode 30 laterally to the entire P-type semiconductor layer 211 at the interface between the P-type window layer 50 and the P-type semiconductor layer 211, thereby reducing the current density gradient. Optionally, in one embodiment of the present application, the P-type window layer may be a P-type doped GaP layer, and the doping concentration may be 2×10 18 cm -3 , but this application does not limit this and it depends on the specific circumstances.
[0060] Based on the above embodiment, in one embodiment of the present application, continue as follows Figure 2 As shown, the LED chip also includes: an omnidirectional reflection layer 60 located between the P-type window layer 50 and the first substrate 10, so as to at least partially reflect the light emitted from the P-type window layer 50 away from the quantum well active layer 212 back to the side of the N-type confinement layer 2131 away from the quantum well active layer 212, that is, to at least partially reflect the light on the non-light-emitting side of the LED chip back to the light-emitting side of the LED chip, thereby improving the light extraction efficiency of the LED chip.
[0061] Optionally, in one embodiment of the present application, the omnidirectional reflection layer 60 includes:
[0062] a first ohmic contact layer 61 located on a surface of the P-type window layer 50 facing the first substrate 10 , wherein the first ohmic contact layer 61 covers the third region of the P-type window layer 50 and exposes the fourth region of the P-type window layer 50 ;
[0063] A dielectric layer 62 located on a surface of the first ohmic contact layer 61 facing the first substrate 10, wherein the dielectric layer 62 has a plurality of through holes, and the through holes expose a portion of the first ohmic contact layer 61;
[0064] A conductive filler 63 located in the through hole;
[0065] The mirror layer 64 is located on the side of the dielectric layer 62 facing the first substrate 10 . The mirror layer 64 is a conductive layer and is electrically connected to the conductive filler 63 .
[0066] It should be noted that, in this embodiment, the P electrode 30 is electrically connected to the P-type semiconductor layer 211 through the first substrate 10 , the mirror layer 64 , the conductive filler 63 and the first ohmic contact layer 61 in sequence.
[0067] Specifically, in one embodiment of the present application, the first ohmic contact layer may be a P-type doped GaP layer. When the first ohmic contact layer and the P-type window layer are both P-type doped GaP layers, the doping concentration of the first ohmic contact layer is greater than the doping concentration of the P-type window layer to reduce the resistance of the first ohmic contact layer.
[0068] It should be noted that the P-type GaP layer has a certain light absorption effect. In this embodiment, the first ohmic contact layer covers the third area of the P-type window layer and exposes the fourth area of the P-type window layer. On the basis of utilizing the first ohmic contact layer to electrically connect the conductive filler and the P-type window layer, the light absorption of the first ohmic contact layer can be reduced, thereby reducing the influence of the first ohmic contact layer on the light extraction efficiency of the LED chip.
[0069] Optionally, in one embodiment of the present application, the third area includes multiple sub-areas, the fourth area includes multiple sub-areas, and the sub-areas of the third area and the sub-areas of the fourth area are arranged at intervals, but the present application does not limit this and it depends on the specific circumstances.
[0070] On the basis of any of the above embodiments, in one embodiment of the present application, the dielectric layer includes a stacked first component layer, a second component layer and a third component layer, wherein the first component layer is an ITO layer or an IZO layer or an Al2O3 layer, the second component layer is a SiO2 layer, and the third component layer is an Al2O3 layer or an ITO layer or an IZO layer; the conductive filler may include a stacked Au layer, a Zn layer and an Au layer, or may include a stacked Au layer, a Be layer and an Au layer; the mirror layer includes a stacked Ag layer, a TiW layer, a Ti layer, a Pt layer and an Au layer. However, the present application does not limit this, and it depends on the specific situation.
[0071] Optionally, in an embodiment of the present application, the first substrate 10 is bonded to the mirror layer 64 via a metal bonding layer 70 to achieve a fixed connection between the first substrate 10 and the omnidirectional reflective layer 60 .
[0072] Based on any of the above embodiments, in one embodiment of the present application, the LED chip further includes: a second ohmic contact layer 80 located in a partial area of the epitaxial unit 21 away from the first substrate 10 , and an N electrode 90 electrically connected to the second ohmic contact layer 80 and the N-type semiconductor layer 213 .
[0073] In summary, in the LED chip provided in the embodiment of the present application, a dam structure is formed on at least part of the outer side of the epitaxial unit, so that in the process of replacing the carrier film at the bottom of the LED chip using the lamination process, the dam structure can be used to share the lateral force applied to the edge of the epitaxial unit, thereby reducing the possibility of the epitaxial unit being crushed due to pressure, alleviating problems such as edge collapse and corner collapse generated during the production process of the LED chip, and reducing abnormal appearance.
[0074] Moreover, in the LED chip provided in the embodiment of the present application, a dam structure is formed on at least part of the outer side of the epitaxial unit. In the process of splitting the first substrate from the side of the first carrier film away from the P electrode to form a plurality of LED grains, the cutting position can be defined by the position of the dam structure, so that the cutting position is located on the side of the dam structure away from the epitaxial unit. Therefore, when the first substrate is split from the side of the first carrier film away from the P electrode, the dam structure can be used to block metal sputtering generated by laser cutting, so as to effectively reduce the leakage ratio of the LED chip caused by metal sputtering generated by laser cutting.
[0075] Accordingly, the present application also provides a method for manufacturing an LED chip, such as Figure 5 As shown, the production method includes:
[0076] S1: forming an epitaxial layer on a surface of a semiconductor substrate, wherein the epitaxial layer comprises a stacked N-type semiconductor layer, a quantum well active layer and a P-type semiconductor layer.
[0077] Optionally, in one embodiment of the present application, the P-type semiconductor layer includes a P-type confinement layer, and the N-type semiconductor layer includes an N-type roughening layer and an N-type confinement layer. In this embodiment, Figure 6 As shown, forming an epitaxial layer on the surface of the semiconductor substrate 100 includes:
[0078] A buffer layer 101 is formed on the surface of the semiconductor substrate 100. Optionally, the semiconductor substrate 100 is a GaAs substrate, and the buffer layer 101 is a GaAs buffer layer;
[0079] Forming an etching stop layer 102 on the surface of the buffer layer 101 away from the semiconductor substrate 100;
[0080] A second ohmic contact layer 80 is formed on a side of the etching stop layer 102 away from the buffer layer 101. Optionally, the second ohmic contact layer 80 is a GaAs ohmic contact layer.
[0081] Forming an N-type roughening layer 2132 on a side of the second ohmic contact layer 80 away from the etching stop layer 102;
[0082] Forming an N-type confinement layer 2131 on a side of the N-type roughening layer 2132 away from the second ohmic contact layer 80;
[0083] A quantum well active layer 212 is formed on a side of the N-type confinement layer 2131 away from the N-type roughening layer 2132;
[0084] A P-type semiconductor layer 211 is formed on a side of the quantum well active layer 212 away from the N-type confinement layer 2131 , and the P-type semiconductor layer includes the P-type confinement layer 211 .
[0085] Optionally, in one embodiment of the present application, the process for forming the epitaxial layer is a deposition process, but the present application does not limit this and it depends on the specific circumstances.
[0086] Based on the above embodiments, in one embodiment of the present application, Figure 7 As shown, the method further includes: forming a P-type window layer 50 on a side of the epitaxial layer away from the semiconductor substrate 100. Optionally, the P-type window layer 50 is a P-type doped GaP layer, and the doping concentration may be 2×10 18 cm -3 , but this application does not limit this and it depends on the specific circumstances.
[0087] Based on any of the above embodiments, in one embodiment of the present application, before fixing the side of the epitaxial layer away from the semiconductor substrate to the first substrate, Figure 8 As shown, the method also includes: forming an omnidirectional reflection layer 60 on the side of the P-type semiconductor layer 211 away from the quantum well active layer 212, so as to at least partially reflect the light emitted from the P-type window layer 50 or the P-type semiconductor layer 211 away from the quantum well active layer 212 back to the side of the N-type confinement layer 2131 away from the quantum well active layer 212, that is, to at least partially reflect the light on the non-light-emitting side of the LED chip back to the light-emitting side of the LED chip, thereby improving the light extraction efficiency of the LED chip.
[0088] Optionally, in one embodiment of the present application, continue as Figure 8 As shown, forming an omnidirectional reflection layer 60 on a side of the P-type semiconductor layer 211 away from the quantum well active layer 212 includes:
[0089] A first ohmic contact layer 61 is formed on a surface of the P-type window layer 50 away from the semiconductor substrate 100, wherein the first ohmic contact layer 61 covers the third region of the P-type window layer 50 and exposes the fourth region of the P-type window layer 50;
[0090] A dielectric layer 62 is formed on a surface of the first ohmic contact layer 61 away from the semiconductor substrate 100, wherein the dielectric layer 62 has a plurality of through holes, and the through holes expose a portion of the first ohmic contact layer 61;
[0091] forming a conductive filling member 63 in the through hole;
[0092] A mirror layer 64 is formed on a side of the dielectric layer 62 away from the semiconductor substrate 100 . The mirror layer 64 is a conductive layer and is electrically connected to the conductive filler 63 .
[0093] Optionally, based on the above embodiment, in one embodiment of the present application, the first ohmic contact layer may be a P-type doped GaP layer, and the doping concentration of the first ohmic contact layer is greater than the doping concentration of the P-type window layer; in this embodiment, the first ohmic contact layer is formed on a surface of the P-type window layer away from the semiconductor substrate, the first ohmic contact layer covers the third region of the P-type window layer, and the fourth region of the P-type window layer is exposed, including:
[0094] Forming a first ohmic contact layer covering a surface of the P-type window layer on a side of the P-type window layer away from the epitaxial layer;
[0095] The first ohmic contact layer is etched so that the first ohmic contact layer covers the third region of the P-type window layer and exposes the fourth region of the P-type window layer.
[0096] Specifically, in one embodiment of the present application, etching the first ohmic contact layer so that the first ohmic contact layer covers the third region of the P-type window layer and exposes the fourth region of the P-type window layer comprises:
[0097] Cleaning the surface of the first ohmic contact layer by using acetone, isopropyl alcohol, deionized water, etc.;
[0098] forming a first photoresist pattern on the surface of the first ohmic contact layer;
[0099] Using the first photoresist pattern as a mask, using a wet or dry etching method, remove the portion of the first ohmic contact layer covering the fourth region of the P-type window layer, so that the first ohmic contact layer only covers the third region of the P-type window layer, and the fourth region of the P-type window layer is exposed;
[0100] The first photoresist pattern is removed.
[0101] Optionally, in one embodiment of the present application, the dielectric layer includes a stacked first component layer, a second component layer and a third component layer, wherein the first component layer is an ITO layer or an IZO layer or an Al2O3 layer, the second component layer is a SiO2 layer, and the third component layer is an Al2O3 layer or an ITO layer or an IZO layer. In this embodiment, a dielectric layer is formed on a surface of the first ohmic contact layer away from the semiconductor substrate, and the dielectric layer has a plurality of through holes, and the through holes expose a partial area of the first ohmic contact layer:
[0102] Sequentially vapor-depositing a first component layer, a second component layer, and a third component layer on the entire surface of the first ohmic contact layer away from the semiconductor substrate to form a stacked first component layer, a second component layer, and a third component layer;
[0103] The stacked first component layer, the second component layer and the third component layer are etched to form a plurality of through holes penetrating the first component layer, the second component layer and the third component layer, thereby obtaining a dielectric layer located on a surface of the first ohmic contact layer away from the semiconductor substrate, wherein the dielectric layer has a plurality of through holes, and the through holes expose a partial area of the first ohmic contact layer.
[0104] Optionally, in one embodiment of the present application, the conductive filler may include a stacked Au layer, a Zn layer and an Au layer, or may include a stacked Au layer, a Be layer and an Au layer. In this embodiment, forming the conductive filler in the through hole includes:
[0105] Forming a second photoresist pattern on a surface of the dielectric layer away from the P-type window layer;
[0106] A conductive filling layer is evaporated on the side of the second photoresist pattern away from the P-type window layer and on the entire surface of the through hole, wherein the conductive filling layer may include a stacked Au layer, a Zn layer and an Au layer, or may include a stacked Au layer, a Be layer and an Au layer;
[0107] Using a stripping process, a portion of the conductive filling layer located on the surface of the second photoresist pattern is removed, and a portion of the conductive filling layer located in the through hole is retained to form a conductive filling member in the through hole;
[0108] The second photoresist pattern is removed, and the surface of the dielectric layer away from the P-type window layer is cleaned.
[0109] Optionally, in one embodiment of the present application, the mirror layer includes a stacked Ag layer, a TiW layer, a Ti layer, a Pt layer and an Au layer. In this embodiment, forming a mirror layer on the side of the dielectric layer away from the semiconductor substrate may include: using a sputtering process to sputter the mirror layer on the side of the dielectric layer away from the semiconductor substrate, and the mirror layer is a metal mirror layer.
[0110] S2: Fixing the side of the epitaxial layer away from the semiconductor substrate to a first base plate, and removing the semiconductor substrate.
[0111] Optionally, in one embodiment of the present application, fixing the side of the epitaxial layer away from the semiconductor substrate to the first substrate, and removing the semiconductor substrate comprises:
[0112] like Fig. 9 As shown, a bonding process is used to fix the surface of the epitaxial layer away from the semiconductor substrate 100 to the first substrate 10. Optionally, in one embodiment of the present application, a metal mirror layer is formed on the surface of the epitaxial layer away from the semiconductor substrate 100, and a metal bonding layer 70 is formed on the first substrate 10. The metal mirror layer and the metal bonding layer are bonded by a bonding process to fix the surface of the epitaxial layer away from the semiconductor substrate to the first substrate.
[0113] like Fig.10 As shown, the semiconductor substrate is removed.
[0114] It should be noted that, in this embodiment, if a buffer layer and an etching stop layer are formed between the semiconductor substrate and the epitaxial layer, in this embodiment, the method further includes removing the buffer layer and the etching stop layer after removing the semiconductor substrate.
[0115] It should also be noted that, in this embodiment, the P electrode is electrically connected to the P-type semiconductor layer through the omnidirectional reflective layer and the first substrate. Optionally, the first substrate is a highly doped silicon substrate, but this application does not limit this, depending on the specific situation.
[0116] Optionally, in one embodiment of the present application, after removing the semiconductor substrate to expose the surface of the second ohmic contact layer away from the N-type roughened layer, Fig.11 As shown, the method also includes: etching the second ohmic contact layer 80 to retain the portion of the second ohmic contact layer 80 located in the central area of the N-type roughening layer 2132; forming an N-electrode 90 covering the second ohmic contact layer 80, and the N-electrode 90 is electrically connected to the second ohmic contact layer 80 and the N-type roughening layer 2132.
[0117] S3: Fig.12 As shown, the epitaxial layer is cut from a side of the epitaxial layer away from the first substrate to form a plurality of epitaxial units 21 and a plurality of dam structures 22, the dam structures 22 corresponding to the epitaxial units 21 one by one, in a first direction, the dam structure 22 is at least located in a partial area outside the epitaxial unit 21, and there is a gap between the dam structure 22 and the epitaxial unit 21, and the first direction is parallel to the plane where the first substrate is located, so that in the subsequent process of replacing the supporting film at the bottom of the LED chip by a film pressing process, the dam structure 22 can be used to share the lateral force applied to the edge of the epitaxial unit 21, thereby reducing the situation where the epitaxial unit 21 is crushed due to the action of pressure, and alleviating the problems of edge collapse, corner collapse, etc. generated during the production process of the LED chip.
[0118] Optionally, in one embodiment of the present application, in a plane parallel to the plane where the first substrate is located, the dam structure is arranged around the epitaxial unit, so that in the process of replacing the carrier film at the bottom of the LED chip by the lamination process, the dam structure can be used to share the lateral force applied to the edge of the epitaxial unit, and the dam structure is used to protect the side edges of the epitaxial unit, thereby further reducing the possibility of the epitaxial unit being crushed due to pressure, and alleviating the problems of edge collapse, corner collapse, etc. generated during the production process of the LED chip.
[0119] In another embodiment of the present application, the dam structure 22 is composed of a plurality of columnar units 221, and the distance between adjacent columnar units 221 is not less than 3 microns, so that in the process of replacing the carrier film at the bottom of the LED chip by the lamination process, the plurality of columnar units 221 can be used to share the lateral force applied to the edge of the epitaxial unit 21. Optionally, the columnar units 221 can be arranged around the epitaxial unit 21, and the plurality of columnar units 221 can be used to protect the sides of the epitaxial unit 21, further reducing the situation where the epitaxial unit 21 is crushed due to the pressure, and alleviating the problems of edge collapse, corner collapse, etc. generated during the production process of the LED chip.
[0120] On the basis of any of the above embodiments, in one embodiment of the present application, in the first direction, the distance of the gap between the dam structure and the epitaxial unit is not less than 3 microns, and not greater than the width of the second region, so as to avoid the distance between the dam structure and the epitaxial unit being too small, increasing the short circuit between the dam structure and the epitaxial unit. It should be noted that in this embodiment, the second region of the first substrate is the region where the cutting path in the traditional LED chip is located, and the width of the second region is the width of the cutting path in the traditional LED chip, so that the addition of the dam structure does not increase the size of the LED chip in the first direction, but the present application does not limit this, and it depends on the specific situation.
[0121] On the basis of any of the above embodiments, in one embodiment of the present application, in the first direction, the width of the dam structure is greater than 5 microns, so that in the process of replacing the carrier film at the bottom of the LED chip by the lamination process, the dam structure can provide a fixed sufficient support force for the force applied to the epitaxial unit, and better share the lateral force applied to the edge of the epitaxial unit 21, so that the dam structure can be used to effectively protect the side edges of the epitaxial unit, further reduce the possibility of the epitaxial unit being crushed due to pressure, and alleviate the problems of edge collapse, corner collapse, etc. generated in the process of manufacturing the LED chip, but the present application does not limit this, and it depends on the specific situation.
[0122] Optionally, in one embodiment of the present application, after the N electrode is formed, the method for manufacturing the LED chip further includes:
[0123] Roughening the portion of the N-type roughening layer not covered by the N-electrode to improve the light extraction efficiency of the light emitting side of the LED chip;
[0124] A protection layer is formed to cover the N-type roughening layer and the dam structure. It should be noted that, in this embodiment, the protection layer exposes a portion of the N-electrode to facilitate the lead-out of the N-electrode.
[0125] Optionally, in one embodiment of the present application, the protective layer is a silicon nitride layer, but the present application does not limit this and it depends on the specific circumstances.
[0126] S4: Fig.13 As shown, a P electrode 30 is formed on a side of the first substrate 10 away from the epitaxial unit.
[0127] Optionally, in one embodiment of the present application, before forming a P electrode on a side of the first substrate away from the epitaxial unit, the method further includes: grinding the first substrate from a side of the first substrate away from the epitaxial unit until a first substrate of a target thickness is obtained, and then forming a P electrode on the surface of the first substrate away from the epitaxial unit.
[0128] S5: Continue as Fig.13 As shown, the second carrier film 401 is fixed on the side of the P electrode 30 away from the first substrate 10 , that is, the entire LED chip is pasted onto the second carrier film 401 .
[0129] S6: Fig.14 As shown, the first substrate 10 is split from the side of the second carrier film 401 away from the P electrode 30 to form a plurality of LED grains.
[0130] Optionally, in one embodiment of the present application, laser cutting is used to split the first substrate from the side of the second carrier film away from the P electrode to form a plurality of LED grains.
[0131] It should be noted that the first substrate is split from the side of the second carrier film away from the P electrode to form a plurality of LED dies. The cutting position can be defined by the position of the dam structure so that the cutting position is located on the side of the dam structure away from the epitaxial unit. Fig.13 The cutting position K in the cutting process is set so that when the first substrate is split from the side of the second carrier film away from the P electrode, the metal sputtering generated by the laser cutting is blocked by the dam structure, so as to effectively reduce the leakage ratio of the LED chip caused by the metal sputtering generated by the laser cutting onto the epitaxial unit.
[0132] S7: Fig.15 As shown, a film turning process is adopted to remove the second carrier film on the surface of the first substrate 10 away from the epitaxial layer, and a first carrier film 40 is fixed on the surface of the first substrate 10 away from the epitaxial layer.
[0133] Optionally, in one embodiment of the present application, using a film turning process to remove the second carrier film on the surface of the first substrate away from the epitaxial layer, and fixing the first carrier film on the surface of the first substrate away from the epitaxial layer includes:
[0134] Fixing a third carrier film on a side of the epitaxial unit away from the first substrate;
[0135] removing the second carrier film;
[0136] Fixing a first carrier film on a side of the first substrate away from the epitaxial unit;
[0137] The third carrier film is removed.
[0138] In summary, when an LED chip is manufactured using the LED chip manufacturing method provided in the embodiment of the present application, a dam structure is formed on at least part of the outer side of the epitaxial unit, so that in the process of replacing the supporting film at the bottom of the LED chip using the lamination process, the dam structure can be used to share the lateral force applied to the edge of the epitaxial unit, thereby reducing the possibility of the epitaxial unit being crushed due to pressure, alleviating problems such as edge collapse and corner collapse generated during the manufacturing process of the LED chip, and reducing abnormal appearance.
[0139] Moreover, when an LED chip is manufactured using the LED chip manufacturing method provided in the embodiment of the present application, in the process of splitting the first substrate from the side of the second carrier film away from the P electrode to form a plurality of LED grains, the cutting position can be defined by the position of the dam structure, so that the cutting position is located on the side of the dam structure away from the epitaxial unit. Therefore, when the first substrate is split from the side of the second carrier film away from the P electrode, the dam structure is used to block metal sputtering generated by laser cutting, so as to effectively reduce the leakage ratio of the LED chip caused by metal sputtering generated by laser cutting.
[0140] In this specification, each embodiment is described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.
[0141] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same figure marks throughout the embodiments of the specification identify the same structure. It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such articles or equipment. In the absence of more restrictions, the elements limited by the sentence "including one..." do not exclude the existence of other identical elements in the article or equipment including the above elements.
[0142] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. An LED chip, characterized in that: include: A first substrate, wherein a surface of the first substrate has a first area and a second area surrounding the first area; An epitaxial unit located in a first region of the first substrate and a dam structure located in a second region of the first substrate, the epitaxial unit comprising a stacked P-type semiconductor layer, a quantum well active layer and an N-type semiconductor layer, the dam structure being located at least in a partial region outside the epitaxial unit in a first direction, and a gap being provided between the dam structure and the epitaxial unit, and the first direction being parallel to a plane where the first substrate is located; A P electrode is located on a side of the first substrate away from the epitaxial unit.
2. The LED chip according to claim 1, characterized in that: The dam structure is arranged around the epitaxial unit.
3. The LED chip according to claim 1, characterized in that: The dam structure is composed of a plurality of columnar units, and the distance between adjacent columnar units is not less than 3 micrometers.
4. The LED chip according to any one of claims 1 to 3, characterized in that: In the first direction, a distance between the dam structure and the epitaxial unit is not less than 3 micrometers and not greater than a width of the second region.
5. The LED chip according to any one of claims 1 to 3, characterized in that: In the first direction, the width of the dam structure is greater than 5 microns.
6. The LED chip according to claim 1, characterized in that: The P-type semiconductor layer includes a P-type confinement layer located on a side of the quantum well active layer away from the N-type semiconductor layer; the LED chip also includes a P-type window layer located on a side of the P-type semiconductor layer away from the quantum well active layer.
7. The LED chip according to claim 6, characterized in that: Also includes: An omnidirectional reflection layer is located between the P-type window layer and the first substrate.
8. The LED chip according to claim 7, characterized in that: The omnidirectional reflection layer comprises: a first ohmic contact layer located on a surface of the P-type window layer facing the first substrate, wherein the first ohmic contact layer covers the third region of the P-type window layer and exposes the fourth region of the P-type window layer; a dielectric layer located on a surface of the first ohmic contact layer facing the first substrate, wherein the dielectric layer has a plurality of through holes, and the through holes expose a partial area of the first ohmic contact layer; a conductive filling member located in the through hole; a mirror layer located on the side of the dielectric layer facing the first substrate, the mirror layer being a conductive layer and electrically connected to the conductive filling member; The P electrode is electrically connected to the P-type semiconductor layer through the first substrate, the mirror layer, the conductive filler and the first ohmic contact layer.
9. The LED chip according to claim 8, characterized in that: The dielectric layer comprises a stacked first component layer, a second component layer and a third component layer, wherein the first component layer is an ITO layer or an IZO layer or an Al2O3 layer, the second component layer is a SiO2 layer, and the third component layer is an Al2O3 layer or an ITO layer or an IZO layer; The conductive filler comprises a stacked Au layer, a Zn layer and an Au layer, or a stacked Au layer, a Be layer and an Au layer; The mirror layer includes a stacked Ag layer, a TiW layer, a Ti layer, a Pt layer, and an Au layer.
10. The LED chip according to claim 1, characterized in that: The N-type semiconductor layer includes an N-type confinement layer located on a side of the quantum well active layer away from the P-type semiconductor layer, and an N-type roughening layer located on a side of the N-type confinement layer away from the quantum well active layer.
11. A method for manufacturing an LED chip, characterized in that: include: Forming an epitaxial layer on the surface of a semiconductor substrate, wherein the epitaxial layer includes a stacked N-type semiconductor layer, a quantum well active layer, and a P-type semiconductor layer; Fixing the side of the epitaxial layer away from the semiconductor substrate to a first substrate, and removing the semiconductor substrate; The epitaxial layer is cut from a side of the epitaxial layer away from the first substrate to form a plurality of epitaxial units and a plurality of dam structures, wherein the dam structures correspond to the epitaxial units one by one, and in a first direction, the dam structures are at least located in at least a portion of the outer side of the epitaxial units, and there is a gap between the dam structures and the epitaxial units, and the first direction is parallel to the plane where the first substrate is located; forming a P electrode on a side of the first substrate away from the epitaxial unit; A second carrier film is fixed on a side of the P electrode away from the first substrate; Splitting the first substrate from the side of the second carrier film away from the P electrode to form a plurality of LED grains; The second carrier film on the surface of the first substrate away from the epitaxial layer is removed by using a film turning process, and the first carrier film is fixed on the surface of the first substrate away from the epitaxial layer.
12. The method for manufacturing an LED chip according to claim 11, characterized in that: Before fixing the side of the epitaxial layer away from the semiconductor substrate to the first base plate, the method further comprises: An omnidirectional reflection layer is formed on a side of the P-type semiconductor layer away from the quantum well active layer, and the P electrode is electrically connected to the P-type semiconductor layer through the omnidirectional reflection layer and the first substrate.