Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes: a substrate including an emission area and a non-emission area; a first anode electrode at the emission region; a first cathode electrode over the first anode electrode; a first pixel defining layer; at the non-emission region, and defining a first opening; a bank structure over the first pixel defining layer and including a second bank layer contacting the first cathode electrode and a third bank layer including a second tip protruding from a side surface of the second bank layer toward the emission region; a second pixel defining layer over the bank structure, defining a second opening, overlapping the second tip in a direction perpendicular to the substrate, and contacting the second tip; and a first encapsulation layer over the second pixel defining layer.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0157798 filed in the Korean Intellectual Property Office on November 15, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0003] With the development of information-oriented society, various demands for display devices are increasing. For example, display devices are being adopted by a variety of electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, and an organic light-emitting display device. Among such flat panel display devices, a light-emitting display device includes a light-emitting element that can emit light by itself, so that each of the pixels of the display panel can emit light by itself. Therefore, the light-emitting display device can display an image without a backlight unit that supplies light to the display panel.

[0004] Recently, with the development of various electronic devices, the demand for high-resolution display devices is increasing. Because high-resolution display devices require high pixel density, the interval between light-emitting elements in each emission area can be narrowed. Therefore, high-resolution display devices can be formed via a patterning process that forms individual pixels rather than a process that uses a fine metal mask. Summary of the invention

[0005] Aspects of the present disclosure provide a display device including a bank structure and capable of solving an arc fault occurring during a manufacturing process.

[0006] It should be noted that aspects of the present disclosure are not limited to the above contents, and other aspects of the present disclosure will be clear to those skilled in the art from the following description.

[0007] According to one or more embodiments of the present disclosure, a display device includes: a substrate including an emission region and a non-emission region; a first anode electrode at the emission region; a first cathode electrode above the first anode electrode; a first pixel defining layer at the non-emission region and defining a first opening; a dam structure above the first pixel defining layer and including a second dam layer and a third dam layer, the second dam layer contacts the first cathode electrode, and the third dam layer includes a second tip protruding from a side surface of the second dam layer toward the emission region; a second pixel defining layer above the dam structure, defining a second opening, overlapping the second tip in a direction perpendicular to the substrate, and contacting the second tip; and a first encapsulation layer above the second pixel defining layer.

[0008] The display device may further include a first bank layer between the first pixel defining layer and the second bank layer, contacting the first pixel defining layer, and including a first tip protruding from a side surface of the second bank layer toward the emission region.

[0009] The second bank layer may have higher conductivity than the first and third bank layers.

[0010] The first cathode electrode may cover the first tip.

[0011] The first pixel defining layer and the second pixel defining layer may include different inorganic materials.

[0012] The display device may further include a residual pattern between the first anode electrode and the first pixel defining layer in a direction perpendicular to the substrate and overlapping the first tip and the second tip in a direction perpendicular to the substrate.

[0013] In a plan view, the first opening may be completely surrounded by the second opening.

[0014] The display device may further include: a second anode electrode, spaced apart from the first anode electrode, with the first pixel defining layer between the second anode electrode and the first cathode electrode; a second cathode electrode, above the second anode electrode, contacting the second embankment layer, and electrically connected to the first cathode electrode through the second embankment layer.

[0015] The display device may also include: a second encapsulation layer, above the first encapsulation layer, and including an organic material, wherein the first encapsulation layer includes a first inorganic layer and a second inorganic layer, the first inorganic layer covers the first cathode electrode, and the second inorganic layer covers the second cathode electrode and is separated from the first inorganic layer by the second encapsulation layer at the non-emitting area.

[0016] The second pixel defining layer may include a first surface facing the second encapsulation layer and including a first portion overlapping the first inorganic layer, a second portion overlapping the second inorganic layer, and a third portion between the first and second portions and contacting the second encapsulation layer.

[0017] The display device may also include: a first electrode pattern, which is above the second pixel defining layer, spaced apart from the first cathode electrode, and includes the same material as the first cathode electrode; and a second electrode pattern, which is above the second pixel defining layer, spaced apart from the second cathode electrode, and includes the same material as the second cathode electrode.

[0018] The first electrode pattern and the second electrode pattern may be spaced apart from each other in a direction parallel to the substrate with the second encapsulation layer between the first electrode pattern and the second electrode pattern.

[0019] According to one or more embodiments of the present disclosure, a display device includes: a substrate including an emission region and a non-emission region; an anode electrode at the emission region; a cathode electrode above the anode electrode; a first pixel defining layer at the non-emission region and defining a first opening; a dam structure above the first pixel defining layer and including a first dam layer, a second dam layer, and a third dam layer stacked on each other in a direction perpendicular to the substrate; and a second pixel defining layer above the dam structure, defining a second opening and including a first layer and a second layer, the first layer contacting the third dam layer, and the second layer being above the first layer and including a second tip protruding from a side surface of the first layer toward the emission region.

[0020] The second bank layer may be completely surrounded by the first bank layer and the third bank layer.

[0021] The cathode electrode may contact the third bank layer.

[0022] The first bank layer may include a first tip protruding from a side surface of the second bank layer toward the emission region and overlapping the second tip in a direction perpendicular to the substrate.

[0023] The first layer and the second layer may include different inorganic materials.

[0024] The first pixel defining layer may include a third layer and a fourth layer, the third layer facing the substrate, the fourth layer being over the third layer and including a first tip protruding from a side surface of the third layer toward the emission region.

[0025] The first tip may be in the first opening.

[0026] According to one or more embodiments of the present disclosure, a method for manufacturing a display device includes: preparing a substrate including an emission area and a non-emission area; forming an anode electrode at the emission area; forming a sacrificial layer above the anode electrode; forming a first pixel-defining material layer that completely covers the sacrificial layer and the substrate; forming a dyke material layer that completely covers the first pixel-defining material layer; forming a second pixel-defining material layer; forming a photoresist above the second pixel-defining material layer; removing portions of the first pixel-defining material layer, the dyke material layer, and the second pixel-defining material layer overlapping the anode electrode through an etching process to form a hole that exposes the sacrificial layer; removing an inner sidewall of the hole through an etching process to expose the anode electrode; forming the first pixel-defining layer, the second pixel-defining material layer, and the ... A layer and a dam structure, the dam structure is protected by the second pixel defining layer to be protected from the influence of the etchant during the etching process, and the dam structure includes a stacked structure of a second dam layer, a first dam layer and a third dam layer, the first dam layer is below the second dam layer and includes a first tip protruding from the side surface of the second dam layer toward the emission region, and the third dam layer is above the second dam layer and includes a second tip protruding from the side surface of the second dam layer toward the emission region; forming an emission layer and a cathode electrode above the anode electrode and the second pixel defining layer; forming a first encapsulation layer above the cathode electrode; and removing the emission layer, the cathode electrode and the first encapsulation layer above the second pixel defining layer, leaving portions of the emission layer, the cathode electrode and the first encapsulation layer at the emission region and at the periphery of the emission region.

[0027] According to one or more embodiments of the present disclosure, a display device may include: a levee structure; and a pixel defining layer, on which the levee structure may include different conductive materials. At least one of the levee structure and the pixel defining layer includes a tip protruding toward an emission region, so that the display device according to one or more embodiments of the present disclosure can form light-emitting elements spaced apart from each other in the emission region without a fine metal mask. In addition, the pixel defining layer according to one or more embodiments of the present disclosure can protect the levee structure, thereby solving arc faults in the levee structure that may occur during the manufacturing process.

[0028] It should be noted that aspects of the present disclosure are not limited to the above-mentioned aspects, and other aspects of the present disclosure will be apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects of the present disclosure will become more apparent by describing embodiments of the present disclosure in detail with reference to the attached drawings.

[0030] Figure 1 is a perspective view illustrating an electronic device according to one or more embodiments of the present disclosure.

[0031] Figure 2is a perspective view illustrating a display device included in an electronic device according to one or more embodiments of the present disclosure.

[0032] Figure 3 yes Figure 2 Schematic cross-sectional view of a display device.

[0033] Figure 4 It is shown Figure 3 A plan view of the layout of the emission area in the display area.

[0034] Figure 5 It is along Figure 4 A cross-sectional view of the display layer taken along line X1-X1'.

[0035] Figure 6 It is schematically shown Figure 5 An enlarged cross-sectional view of a non-emitting area positioned between a first emitting area and a second emitting area.

[0036] Figure 7 yes Figure 6 An enlarged cross-sectional view of area P.

[0037] Figure 8 is a diagram showing a method according to one or more other embodiments Figure 3 A plan view of the layout of the emission area in the display area.

[0038] Fig. 9 It is along Figure 8 A cross-sectional view of the display layer taken along line X3-X3'.

[0039] Fig.10 It is schematically shown Fig. 9 An enlarged cross-sectional view of a non-emitting area positioned between a first emitting area and a second emitting area.

[0040] Fig.11 yes Fig.10 An enlarged cross-sectional view of area Q.

[0041] Fig.12 According to one or more other embodiments, Figure 8 A cross-sectional view of the display layer taken along line X3-X3'.

[0042] Fig.13 It is schematically shown Fig.12 An enlarged cross-sectional view of a non-emitting area positioned between a first emitting area and a second emitting area.

[0043] Figures 14 to 25 It shows the manufacturing Figure 5 Schematic cross-sectional view of a method of displaying element layers shown in FIG. DETAILED DESCRIPTION

[0044] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals always refer to the same elements. However, the present disclosure may be implemented in various different forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the disclosure will be thorough and complete, and these embodiments will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for those of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Throughout the drawings and written descriptions, unless otherwise stated, the same reference numerals indicate the same elements, and therefore, their redundant descriptions may not be repeated.

[0045] When a certain embodiment can be implemented differently, the specific process order may be different from the described order. For example, two processes described in succession may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described order.

[0046] In the accompanying drawings, for clarity, the relative size, thickness and ratio of elements, layers and regions can be exaggerated and / or simplified. For ease of explanation, spatial relative terms such as "below ... ", "below ... ", "lower part", "below ... ", "above ... " and "upper part" can be used here to describe the relationship between an element or feature and another element (multiple elements) or feature (multiple features) as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the accompanying drawings, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, then the element described as "below" or "below" or "below" of other elements or features will be oriented to "above" other elements or features subsequently. Therefore, the example terms "below ... " and "below ... " can cover both upper and lower orientations. The device can be oriented in addition (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used here should be interpreted accordingly.

[0047] In the drawings, the X-axis direction, the Y-axis direction, and the Z-axis direction are not limited to the three axes of the rectangular coordinate system (e.g., the x-axis, the y-axis, and the z-axis), and can be interpreted in a broader sense. For example, the X-axis direction, the Y-axis direction, and the Z-axis direction may be perpendicular or substantially perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0048] It will be understood that, although the terms "first", "second", "third", etc., may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first region, first layer or first part described below may be referred to as the second element, second component, second region, second layer or second part.

[0049] It will be understood that when an element or layer is referred to as being "on," "connected to," or "bound to" another element or layer, it can be directly on, directly connected to, or directly bound to the other element or layer, or there may be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected to" another layer, region, or element, it can be directly electrically connected to the other layer, region, or element and / or can be indirectly electrically connected with one or more intervening layers, regions, or elements positioned therebetween. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0050] The term used here is for the purpose of describing a particular embodiment, and is not intended to limit the present disclosure. As used here, unless the context clearly states otherwise, the singular "one" and "one (kind / person)" are also intended to include plural forms. It will also be understood that when the terms "include", "comprise", "have", "have" and variations thereof are used in this specification, the stated features, wholes, steps, operations, elements and / or components are specified to exist, but one or more other features, wholes, steps, operations, elements, components and / or their groups are not excluded from existence or addition. As used here, the term "and / or" includes any combination and all combinations of one or more of the related listed items. For example, the expression "A and / or B" indicates A, B or A and B. When the expression such as "at least one (kind / person) in ... " is after a column of elements, the entire column of elements is modified, and the listed individual elements are not modified. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0051] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than terms of degree, and are intended to account for the inherent deviations in measurements or calculations that one of ordinary skill in the art would recognize. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the term "use" and variations thereof may be considered synonymous with the term "utilizing" and variations thereof, respectively.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0053] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0054] Figure 1 is a perspective view showing an electronic device 1 according to one or more embodiments of the present disclosure.

[0055] Reference Figure 1 , the electronic device 1 displays a moving image or a still image. The electronic device 1 may refer to any electronic device that provides a display screen. For example, the electronic device 1 may include a television, a laptop computer, a monitor, an electronic billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display device, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, a portable video camera, etc.

[0056] exist Figure 1In the invention, a first direction (X-axis direction), a second direction (Y-axis direction) and a third direction (Z-axis direction) are defined. The first direction (X-axis direction) and the second direction (Y-axis direction) may be perpendicular to each other, the first direction (X-axis direction) and the third direction (Z-axis direction) may be perpendicular to each other, and the second direction (Y-axis direction) and the third direction (Z-axis direction) may be perpendicular to each other. The first direction (X-axis direction) may refer to the horizontal direction in the drawing (for example, in the plan view), the second direction (Y-axis direction) may refer to the vertical direction in the drawing (for example, in the plan view), and the third direction (Z-axis direction) may refer to the up and down direction (for example, thickness direction) in the drawing (for example, in the cross-sectional view). As used herein, unless otherwise specifically stated, a direction may refer to a direction indicated by an arrow and a direction opposite thereto. If it is appropriate to distinguish between such two opposite directions, one of the two directions may be referred to as "one side in the direction" and the other direction may be referred to as "the opposite side in the direction". In Figure 1 , a side indicated by an arrow indicating a direction is referred to as a side in the direction, and the opposite side is referred to as an opposite side in the direction.

[0057] In the following description of the surface of the electronic device 1 or the elements of the electronic device 1, for the sake of convenience, the surface on the side facing the displayed image (for example, the side indicated by the arrow in the third direction (Z-axis direction)) will be referred to as the upper surface, and the opposite surface will be referred to as the lower surface. However, it should be understood that the present disclosure is not limited to this. The surface and the opposite surface of each of the elements may be referred to as the front surface and the rear surface, respectively, or may be referred to as the first surface and the second surface, respectively. In addition, in the description of the relative positions of the elements of the electronic device 1, the side in the third direction (Z-axis direction) may be referred to as the upper side, and the opposite side in the third direction (Z-axis direction) may be referred to as the lower side.

[0058] The shape of the electronic device 1 can be modified in various ways. For example, the electronic device 1 can have a shape such as a rectangle with longer lateral sides, a rectangle with longer vertical sides, a square, a quadrilateral with rounded corners (vertices), other polygons, a circle, etc.

[0059] The electronic device 1 may include a display area DA and a non-display area NDA. In the display area DA, an image can be displayed. In the non-display area NDA, no image is displayed. The display area DA may be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA may generally occupy the center of the electronic device 1.

[0060] Figure 2 is a perspective view showing the display device 10 included in the electronic device 1 .

[0061] Reference Figure 2, the electronic device 1 may include a display device 10. The display device 10 may provide a display screen for displaying images in the electronic device 1. Examples of the display device 10 may include an inorganic light emitting diode display device, an organic light emitting display device, a quantum dot light emitting display device, a plasma display device, a field emission display device, etc. In the following description, an organic light emitting diode display device is used as an example of a display device, but the present disclosure is not limited thereto. As long as the technical idea of ​​the present disclosure can be applied in the same manner, any other display device may be used.

[0062] When viewed from the top, the display device 10 may have a shape similar to that of the electronic device 1. For example, the display device 10 may have a shape similar to a rectangle having shorter sides in a first direction (X-axis direction) and longer sides in a second direction (Y-axis direction). The corner where the shorter side in the first direction (X-axis direction) meets the longer side in the second direction (Y-axis direction) may be rounded to have a curvature (e.g., a predetermined curvature). However, it should be understood that the present disclosure is not limited to this. The corner may be formed at a right angle. When viewed from the top, the shape of the display device 10 is not limited to a quadrilateral shape, but may be formed into a shape similar to other polygonal shapes, circular shapes, or elliptical shapes.

[0063] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 .

[0064] The display panel 100 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA including pixels for displaying an image and a non-display area NDA positioned around the display area DA.

[0065] The display area DA may emit light from a plurality of emission areas or a plurality of openings to be described later. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer and a self-luminous element, the pixel circuit including a switching element, and the pixel defining layer defining an emission area or an opening. For example, the self-luminous element may include, but is not limited to, at least one of an organic light-emitting diode including an organic emission layer, a quantum dot light-emitting diode (quantum LED) including a quantum dot emission layer, an inorganic light-emitting diode (inorganic LED) including an inorganic semiconductor, and a micro light-emitting diode (micro LED). In the following figures, a self-luminous element is shown as an organic light-emitting diode.

[0066] The non-display area NDA may be outside the display area DA (eg, in a plan view). The non-display area NDA may be defined as an edge of the main area MA of the display panel 100 .

[0067] The sub-region SBA may extend from one side of the main region MA. The sub-region SBA may include a flexible material that can be bent, folded or curled. For example, when the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction (e.g., the third direction or the Z-axis direction). The sub-region SBA may include a pad (also referred to as a "pad") connected to the display driver 200 and the circuit board 300. According to one or more other embodiments, the sub-region SBA may be removed, and the display driver 200 and the pad may be positioned in the non-display area NDA.

[0068] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may be implemented as an integrated circuit (IC) and may be attached to the display panel 100 by a chip on glass (COG) technology, a chip on plastic (COP) technology, or ultrasonic bonding. For example, the display driver 200 may be positioned in the sub-area SBA and may overlap with the main area MA in the thickness direction when the sub-area SBA is bent. For another example, the display driver 200 may be mounted on the circuit board 300.

[0069] The circuit board 300 may be attached on the pad area of ​​the display panel 100 using an anisotropic conductive film (ACF). The circuit board 300 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as a chip on film (COF).

[0070] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be connected to the touch sensor layer 180 (see FIG. 1 ) of the display panel 100. Figure 3 ). The touch driver 400 may be implemented as an integrated circuit.

[0071] Figure 3 yes Figure 2 Schematic cross-sectional view of a display device 10.

[0072] Reference Figure 3 The display panel 100 may include a display layer DPL, a touch sensor layer 180 and a color filter layer 190. The display layer DPL may include a substrate 110, a thin film transistor layer 130, a display element layer 150, and a thin film encapsulation layer 170.

[0073] The substrate 110 may be a base substrate or a base member. The substrate 110 may be a flexible substrate that can be bent, folded or curled. For example, the substrate 110 may include, but is not limited to, a polymer resin such as polyimide (PI). According to one or more other embodiments, the substrate 110 may include a glass material or a metal material.

[0074] The thin film transistor layer 130 may be positioned on the substrate 110. The thin film transistor layer 130 may be positioned in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor layer 130 may include a thin film transistor layer for forming a pixel PX (see FIG. Figure 4 ) of multiple thin film transistors TFT (see Figure 5 ).

[0075] The display element layer 150 may be positioned on the thin film transistor layer 130. The display element layer 150 may be positioned in the display area DA. The display element layer 150 may include a plurality of light emitting elements ED (see Figure 5 ). For example, the self-luminous element may include, but is not limited to, at least one of an organic light emitting diode including an organic emission layer, a quantum dot light emitting diode (quantum dot LED) including a quantum dot emission layer, an inorganic light emitting diode (inorganic LED) including an inorganic semiconductor, and a micro light emitting diode (micro LED).

[0076] The thin film encapsulation layer 170 may be positioned on the display element layer 150. The thin film encapsulation layer 170 may overlap the display area DA and the non-display area NDA. The thin film encapsulation layer 170 may cover the upper surface and the side surface of the display element layer 150, and may protect the display element layer 150 from external oxygen and moisture. The thin film encapsulation layer 170 may include at least one inorganic film and at least one organic film for encapsulating the display element layer 150.

[0077] The touch sensor layer 180 may be positioned on the thin film encapsulation layer 170. The touch sensor layer 180 may overlap the display area DA and the non-display area NDA. The touch sensor layer 180 may sense a user's touch through mutual capacitance sensing or self capacitance sensing.

[0078] The color filter layer 190 may be positioned on the touch sensor layer 180. The color filter layer 190 may overlap the display area DA and the non-display area NDA. The color filter layer 190 may absorb some light introduced from outside the display device 10 to reduce reflection of external light. Therefore, the color filter layer 190 can reduce or prevent color distortion caused by reflection of external light.

[0079] Because color filter layer 190 is positioned directly on touch sensor layer 180, display device 10 may not require a separate substrate for color filter layer 190. Therefore, the thickness of display device 10 can be relatively small. In addition, in some embodiments, color filter layer 190 may be removed.

[0080] like Figure 3As shown in , a portion of the display layer DPL overlapping the sub-area SBA may be bent. When a portion of the display layer DPL is bent, the display driver 200, the circuit board 300, and the touch driver 400 may overlap the main area MA in the third direction (Z-axis direction).

[0081] Figure 4 It is shown Figure 3 1 is a plan view of a layout of the emission area EA in the display area DA.

[0082] Reference Figure 4 , the display area DA may include the first emission area EA1, the second emission area EA2, and the third emission area EA3 and the non-emission area NLA. The non-emission area NLA may surround the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0083] The non-emission area NLA can block the light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3. Therefore, the non-emission area NLA can help reduce or prevent the mixing of the light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3. In the non-emission area NLA, a first pixel defining layer 151 (see Figure 5 ), dike structure 160 (see Figure 5 ) and a second pixel defining layer 155 (see Figure 5 ), which will be described later.

[0084] The emission area EA may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that emit light of different colors. Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may emit red light, green light, or blue light. The color of the light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3 may vary according to the type of the light emitting element ED, which will be described later. According to one or more embodiments of the present disclosure, the first emission area EA1 may emit light of a first color (e.g., red light), the second emission area EA2 may emit light of a second color (e.g., green light), and the third emission area EA3 may emit light of a third color (e.g., blue light). However, it should be understood that the present disclosure is not limited thereto. Although the first emission area EA1, the second emission area EA2, and the third emission area EA3 have the same size and shape in the drawings, the present disclosure is not limited thereto. The size and shape of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be adjusted as desired according to the desired characteristics.

[0085] The first emission area EA1, the second emission area EA2, and the third emission area EA3 may be defined by the first opening OP1 and the second opening OP2. Figure 5 , the first opening OP1 may be defined by the first pixel defining layer 151, and the second opening OP2 may be defined by the second pixel defining layer 155. When viewed from the top, the second opening OP2 may completely surround the first opening OP1. When viewed from the top, the second opening OP2 may be completely surrounded by the non-emission area NLA.

[0086] According to some embodiments, at least one first emission region EA1, at least one second emission region EA2, and at least one third emission region EA3 arranged adjacent to each other may form a single pixel group PXG. The pixel group PXG may be the smallest unit emitting white light. However, the type and / or number of each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 forming the pixel group PXG may vary according to the embodiment.

[0087] Figure 5 It is along Figure 4 A cross-sectional view of the display layer DPL taken along line X1-X1'. Figure 5 Schematic cross section of the display layer DPL in the display area DA is shown. Figure 5 The cross-section of the substrate 110, the thin film transistor layer 130, the display element layer 150, and the thin film encapsulation layer 170 of the display device 10 is shown. The substrate 110 has been described above, and thus will not be described again.

[0088] Reference Figure 5 , the thin film transistor layer 130 may be positioned on the substrate 110. The thin film transistor layer 130 may include a first buffer layer 111, a thin film transistor TFT, a gate insulator (or referred to as a gate insulating layer) 113, a first interlayer dielectric layer 121, a capacitor electrode CPE, a second interlayer dielectric layer 123, a first connection electrode CNE1, a first via layer 125, a second connection electrode CNE2, and a second via layer 127.

[0089] The first buffer layer 111 may be positioned on the substrate 110. The first buffer layer 111 may include an inorganic film capable of reducing or preventing air or moisture permeation. For example, the first buffer layer 111 may include a plurality of inorganic films alternately stacked on each other.

[0090] The thin film transistor TFT may be positioned on the first buffer layer 111 and may form a pixel circuit connected to each of the plurality of pixels PX, or may be a part of a pixel circuit connected to each of the plurality of pixels PX. For example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include an active layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0091] The active layer ACT may be positioned on the first buffer layer 111. The active layer ACT may overlap the gate electrode GE in the third direction (Z-axis direction) and may be insulated from the gate electrode GE by the gate insulator 113. A material of a portion of the active layer ACT may be made conductive to form the source electrode SE and the drain electrode DE.

[0092] The gate electrode GE may be positioned on the gate insulator 113. The gate electrode GE may overlap the active layer ACT with the gate insulator 113 interposed therebetween.

[0093] The gate insulator 113 may be positioned over the active layer ACT. The gate insulator 131 may cover the active layer ACT and the first buffer layer 111, and may insulate the active layer ACT from the gate electrode GE. The gate insulator 113 may define a contact hole through which the first connection electrode CNE1 passes.

[0094] The first interlayer dielectric layer 121 may cover the gate electrode GE and the gate insulator 113 . The first interlayer dielectric layer 121 may define a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer dielectric layer 121 may be connected to the contact hole of the gate insulating layer 113 and the contact hole of the second interlayer dielectric layer 123 .

[0095] The capacitor electrode CPE may be positioned on the first interlayer dielectric layer 121. The capacitor electrode CPE may overlap the gate electrode GE in the third direction (Z-axis direction). The capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0096] The second interlayer dielectric layer 123 may cover the capacitor electrode CPE and the first interlayer dielectric layer 121. The second interlayer dielectric layer 123 may define a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer dielectric layer 123 may be connected to the contact hole of the first interlayer dielectric layer 121 and to the contact hole of the gate insulating layer 113.

[0097] The first connection electrode CNE1 may be positioned on the second interlayer dielectric layer 123. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT with the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole formed in the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, and the gate insulator 113 to contact the drain electrode DE of the thin film transistor TFT.

[0098] The first via layer 125 may cover the first connection electrode CNE1 and the second interlayer dielectric layer 123. The first via layer 125 may provide a flat surface over underlying structures. The first via layer 125 may define a contact hole through which the second connection electrode CNE2 passes.

[0099] The second connection electrode CNE2 may be positioned on the first via layer 125. The second connection electrode CNE2 may be inserted into a contact hole formed in the first via layer 125 to contact the first connection electrode CNE1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 with the anode electrode AE.

[0100] The second via layer 127 may cover the second connection electrode CNE2 and the first via layer 125. The second via layer 127 may define a contact hole through which the anode electrode AE ​​passes.

[0101] The display element layer 150 may be positioned on the second via layer 127. The display element layer 150 may include a light emitting element ED, a first pixel defining layer 151, a residual pattern 153, a second pixel defining layer 155, and a bank structure 160.

[0102] The light emitting element ED may include an anode electrode AE, an emission layer EL and a common electrode (or cathode electrode) CE. The light emitting element ED may include a first light emitting element ED1 positioned in a first emission area EA1, a second light emitting element ED2 positioned in a second emission area EA2 and a third light emitting element ED3 positioned in a third emission area EA3.

[0103] The light emitting elements ED overlapped with the corresponding emission areas EA1, EA2 and EA3 may emit light of different corresponding colors according to the material of the emission layer EL. For example, the first light emitting element ED1 may emit light of a first color (e.g., red light), the second light emitting element ED2 may emit light of a second color (e.g., green light), and the third light emitting element ED3 may emit light of a third color (e.g., blue light).

[0104] The anode electrode AE ​​may be positioned on the second via layer 127. The anode electrode AE ​​may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2.

[0105] The anode electrode AE ​​may include a first anode electrode AE1 positioned in the first emission area EA1, a second anode electrode AE2 positioned in the second emission area EA2, and a third anode electrode AE3 positioned in the third emission area EA3. The first, second, and third anode electrodes AE1, AE2, and AE3 may be spaced apart from each other on the second via layer 127.

[0106] According to one or more embodiments of the present disclosure, the anode electrode AE ​​may have a reflective material layer (such as a layer of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof) and a material layer having a high work function (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 For example, the anode electrode AE ​​may have a multilayer structure of, but not limited to, ITO / Mg, ITO / MgF, ITO / Ag, or ITO / Ag / ITO.

[0107] The first pixel defining layer 151 may be positioned on the second via layer 127 and the anode electrode AE. The first pixel defining layer 151 may separate and insulate the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 from each other. The first pixel defining layer 151 may define a first opening OP1. The first pixel defining layer 151 may be completely positioned on the second via layer 127, and may expose a portion of the upper surface of the anode electrode AE. In other words, the first pixel defining layer 151 may expose the anode electrode AE ​​in the first opening OP1, and the emission layer EL may be directly positioned on the anode electrode AE ​​in the first opening OP1.

[0108] The first pixel defining layer 151 may include an inorganic insulating material. For example, the first pixel defining layer 151 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0109] The embankment structure 160 may be positioned on the first pixel defining layer 151. The embankment structure 160 may be positioned in the non-emission area NLA. The embankment structure 160 may include a first embankment layer 161, a second embankment layer 163, and a third embankment layer 165 positioned on the first pixel defining layer 151. The embankment structure 160 may have a structure in which the first embankment layer 161, the second embankment layer 163, and the third embankment layer 165 are sequentially stacked.

[0110] The first bank layer 161 may include a first tip TIP1 protruding from the second bank layer 163 toward the emission area EA. In addition, the third bank layer 165 may include a second tip TIP2 protruding from the second bank layer 163 toward the emission area EA.

[0111] In the display device 10, since the embankment structure 160 includes the tip TIP, the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 can be formed in the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively, even without a fine metal mask during the process of manufacturing the display device 10. The manufacturing process will be described below.

[0112] The second pixel defining layer 155 may be positioned on the bank structure 160. The second pixel defining layer 155 may help reduce or prevent the bank structure 160 from being exposed to an etchant during an etching process in a process of manufacturing the display device 10.

[0113] The second pixel defining layer 155 may define a second opening OP2. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may be defined by the second opening OP2.

[0114] The second pixel defining layer 155 may include an inorganic insulating material. For example, the second pixel defining layer 155 may include silicon oxide, silicon nitride and / or silicon oxynitride. According to one or more embodiments of the present disclosure, the second pixel defining layer 155 may have a different material from the first pixel defining layer 151. For example, if the first pixel defining layer 151 includes silicon oxide, the second pixel defining layer 155 may include silicon nitride and / or silicon oxynitride in addition to silicon oxide. This can utilize the different etching rates of the first pixel defining layer 151 and the second pixel defining layer 155 in the process of manufacturing the first pixel defining layer 151 and the second pixel defining layer 155. The manufacturing process will be described later.

[0115] The emission layer EL may be positioned on the anode electrode AE. The emission layer EL may be an organic emission layer made of an organic material and may be formed on the anode electrode AE ​​via a deposition process. If the thin film transistor TFT applies a voltage (e.g., a predetermined voltage) to the anode electrode AE ​​and if the cathode electrode CE receives a common voltage or a cathode voltage, holes and electrons may move to the emission layer EL through the hole transport layer and the electron transport layer, respectively, and they are recombined in the emission layer EL to emit light.

[0116] The emission layer EL may include a first emission layer EL1, a second emission layer EL2, and a third emission layer EL3 positioned in a first emission region EA1, a second emission region EA2, and a third emission region EA3, respectively. For example, the first emission layer EL1 may emit red light of a first color, the second emission layer EL2 may emit green light of a second color, and the third emission layer EL3 may emit blue light of a third color. However, it should be understood that the present disclosure is not limited thereto.

[0117] According to some embodiments, the anode electrode AE ​​and the first pixel defining layer 151 may be spaced apart from each other in the third direction (Z-axis direction). The residual pattern 153 may be positioned at a position where the anode electrode AE ​​and the first pixel defining layer 151 are spaced apart from each other. The residual pattern 153 will be described later.

[0118] The cathode electrode CE may be positioned on the emission layer EL. The cathode electrode CE may include a transparent conductive material so that light generated in the emission layer EL can be emitted. The cathode electrode CE may receive a common voltage or a low level voltage. When the anode electrode AE ​​receives a voltage equal to the data voltage and the cathode electrode CE receives a low level voltage, a potential difference is formed between the anode electrode AE ​​and the cathode electrode CE, so that the emission layer EL can emit light.

[0119] According to one or more embodiments of the present disclosure, the cathode electrode CE may include a material layer having a small work function, such as Li, Ca, LiF, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF 2 Or a layer of Ba or a compound or mixture thereof (eg, a mixture of Ag and Mg) or a multilayer structure such as LiF / Ca or LiF / Al. The cathode electrode CE may further include a transparent metal oxide layer positioned on a material layer having a small work function.

[0120] The cathode electrode CE may include a first cathode electrode CE1, a second cathode electrode CE2, and a third cathode electrode CE3 positioned in the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively. The first cathode electrode CE1 may be positioned on the first emission layer EL1 in the first emission area EA1, the second cathode electrode CE2 may be positioned on the second emission layer EL2 in the second emission area EA2, and the third cathode electrode CE3 may be positioned on the third emission layer EL3 in the third emission area EA3.

[0121] The cathode electrodes CE may be respectively positioned in the first emission area EA1 , the second emission area EA2 , and the third emission area EA3 so as to be spaced apart from each other. The cathode electrodes CE may not be directly connected to each other but may be electrically connected to each other through the second bank layer 163 .

[0122] A plurality of first, second, and third organic patterns ELP1, ELP2, and ELP3 and first, second, and third electrode patterns CEP1, CEP2, and CEP3 may be positioned on the second pixel defining layer 155. A plurality of first, second, and third organic patterns ELP1, ELP2, and ELP3 and first, second, and third electrode patterns CEP1, CEP2, and CEP3 may be positioned to surround the first opening OP1.

[0123] The first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 may be positioned on the second pixel defining layer 155 in contact therewith. The first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 may include the same material as the first emission layer EL1, the second emission layer EL2, and the third emission layer EL3, respectively. For example, the first organic pattern ELP1 may include the same material as the first emission layer EL1, the second organic pattern ELP2 may include the same material as the second emission layer EL2, and the third organic pattern ELP3 may include the same material as the third emission layer EL3. Because the embankment structure 160 includes a tip TIP, the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 may be traces formed when they are disconnected from the first emission layer EL1, the second emission layer EL2, and the third emission layer EL3.

[0124] The first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be positioned on the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, respectively. For example, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be positioned directly on the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, respectively. The arrangement relationship between the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 and the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 may be the same as the arrangement relationship between the first emission layer EL1, the second emission layer EL2, and the third emission layer EL3 and the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3. The first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may include the same material as the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3, respectively. Since the bank structure 160 includes the tip TIP, the first, second, and third electrode patterns CEP1, CEP2, and CEP3 may be traces formed when they are disconnected from the first, second, and third cathode electrodes CE1, CE2, and CE3.

[0125] The thin film encapsulation layer 170 may be positioned on the first, second, and third cathode electrodes CE1, CE2, and CE3 and the first, second, and third electrode patterns CEP1, CEP2, and CEP3. The thin film encapsulation layer 170 may contact the first, second, and third cathode electrodes CE1, CE2, and CE3 and the first, second, and third electrode patterns CEP1, CEP2, and CEP3.

[0126] The thin film encapsulation layer 170 may include a first encapsulation layer 171, a second encapsulation layer 173, and a third encapsulation layer 175 sequentially stacked on each other. The first encapsulation layer 171 and the third encapsulation layer 175 may be inorganic encapsulation layers, and the second encapsulation layer 173 positioned between the first encapsulation layer 171 and the third encapsulation layer 175 may be an organic encapsulation layer.

[0127] Each of the first encapsulation layer 171 and the third encapsulation layer 175 may include one or more inorganic insulating materials. The inorganic insulating material may include aluminum oxide (Al 2 O 3 ), titanium oxide (Ti 2 O 3 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 )、zinc oxide (ZnO), silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) or silicon oxynitride (Si 2 N 2 O).

[0128] The second encapsulation layer 173 may include a polymer material. The polymer material may include acrylic resin, epoxy resin, polyimide, polyethylene, etc. For example, the second encapsulation layer 173 may include acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.). The second encapsulation layer 173 may be formed by curing a monomer or by applying a polymer.

[0129] The first encapsulation layer 171 may include a first inorganic layer 171-1, a second inorganic layer 171-2, and a third inorganic layer 171-3. The first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may overlap with the emission areas EA1, EA2, and EA3, respectively. For example, the first inorganic layer 171-1 may be positioned in the first emission area EA1 and may cover the first light emitting element ED1. In addition, the second inorganic layer 171-2 may be positioned in the second emission area EA2 and may cover the second light emitting element ED2. Further, the third inorganic layer 171-3 may be positioned in the third emission area EA3 and may cover the third light emitting element ED3.

[0130] Although the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 are formed in the same layer in the drawings, the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be formed in different processes. For example, the first inorganic layer 171-1 may be formed after forming the first cathode electrode CE1, the second inorganic layer 171-2 may be formed after forming the second cathode electrode CE2, and the third inorganic layer 171-3 may be formed after forming the third cathode electrode CE3. The manufacturing process will be described below.

[0131] Figure 6 It is schematically shown Figure 5 An enlarged cross-sectional view of the non-emission area NLA positioned between the first emission area EA1 and the second emission area EA2.

[0132] According to Figure 6 In one or more corresponding embodiments, the first emission area EA1 and the second emission area EA2 may be spaced apart from each other, and the non-emission area NLA is between the first emission area EA1 and the second emission area EA2. As described above, the first opening OP1 may be defined by the first pixel defining layer 151, and the second opening OP2 may be defined by the second pixel defining layer 155.

[0133] The first bank layer 161 may be positioned on the first pixel defining layer 151. The first bank layer 161 may include a metal material having high electrical stability and proper adhesion to metal and may be, for example, molybdenum (Mo). However, it should be understood that the present disclosure is not limited thereto. In addition to molybdenum (Mo), the first bank layer 161 may also include one of chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0134] According to some embodiments, the first bank layer 161 may include a first side surface 1a facing the first emission region EA1 and a second side surface 1b facing the second emission region EA2. The first side surface 1a of the first bank layer 161 may protrude from the second bank layer 163 toward the first emission region EA1 (e.g., may protrude beyond the second bank layer 163 or further than the second bank layer 163), and the second side surface 1b of the first bank layer 161 may protrude from the second bank layer 163 toward the second emission region EA2.

[0135] During the process of manufacturing the display device 10, in the etching process, the first bank layer 161 may include a relatively stable metal material compared to the second bank layer 163. In other words, according to one or more embodiments of the present disclosure, the etching rate of the first bank layer 161 may be lower than the etching rate of the second bank layer 163. Therefore, the first side surface 1a and the second side surface 1b of the first bank layer 161 may protrude from the second bank layer 163 beyond both sides, respectively. In other words, the first bank layer 161 may include a first tip TIP1, which protrudes from the second bank layer 163 toward the first emission area EA1 and the second emission area EA2 in a first direction (X-axis direction) and in a direction opposite to the first direction (X-axis direction).

[0136] In the display device 10 , since the first bank layer 161 includes the first tip TIP1 , the first, second, and third light emitting elements ED1 , ED2 , and ED3 may be formed without a fine metal mask during a process of manufacturing the display device 10 .

[0137] The second bank layer 163 may contact the first bank layer 161. The second bank layer 163 may include a material having an appropriate conductivity, and thus may electrically connect the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3, which are respectively positioned in the first emission area EA1, the second emission area EA2, and the third emission area EA3. For example, the second bank layer 163 may include at least one of aluminum (Al) and copper (Cu). In an embodiment, the second bank layer 163 may have a higher conductivity than the first bank layer 161 and the third bank layer 165.

[0138] According to some embodiments, the second bank layer 163 may include a first side surface 3a facing the first emission region EA1 and a second side surface 3b facing the second emission region EA2. The first side surface 3a of the second bank layer 163 may be recessed from the first side surface 1a of the first bank layer 161 in the first direction (X-axis direction) (e.g., further recessed than the first side surface 1a of the first bank layer 161 in the first direction (X-axis direction), and the second side surface 3b of the second bank layer 163 may be recessed from the second side surface 1b of the first bank layer 161 in a direction opposite to the first direction (X-axis direction). This may be because the second bank layer 163 includes a material having a relatively high etching rate compared to the first bank layer 161 and the third bank layer 165.

[0139] The first emission layer EL1, the first cathode electrode CE1, and the first inorganic layer 171-1 may contact the first side surface 3a of the second bank layer 163. The second emission layer EL2, the second cathode electrode CE2, and the second inorganic layer 171-2 may contact the second side surface 3b of the second bank layer 163. As described above, the first cathode electrode CE1 and the second cathode electrode CE2 may be electrically connected to each other through the second bank layer 163.

[0140] The third bank layer 165 may contact the second bank layer 163. The third bank layer 165 may include a metal material having high electrical stability and proper adhesion to metal and may be, for example, molybdenum (Mo). However, it should be understood that the present disclosure is not limited thereto. In addition to molybdenum (Mo), the third bank layer 165 may also include one of chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0141] According to some embodiments, the third bank layer 165 may include a first side surface 5a facing the first emission region EA1 and a second side surface 5b facing the second emission region EA2. The first side surface 5a of the third bank layer 165 may protrude from the first side surface 3a of the second bank layer 163 toward the first emission region EA1, and the second side surface 5b of the third bank layer 165 may protrude from the second side surface 3b of the second bank layer 163 toward the second emission region EA2.

[0142] During the process of manufacturing the display device 10, in the etching process, the third bank layer 165 may include a relatively stable metal material compared to the second bank layer 163. In other words, the etching rate of the third bank layer 165 may be lower than the etching rate of the second bank layer 163. Therefore, the first side surface 5a and the second side surface 5b of the third bank layer 165 may protrude from the second bank layer 163 toward the emission area EA. In other words, the third bank layer 165 may include a second tip TIP2, and the second tip TIP2 protrudes from the second bank layer 163 on both sides toward the first emission area EA1 and the second emission area EA2, respectively. For example, an undercut may be formed between the first side surface 3a of the second bank layer 163 and the second tip TIP2 and between the second side surface 3b of the second bank layer 163 and the second tip TIP2.

[0143] In the display device 10, since the third bank layer 165 includes the second tip TIP2, the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 can be formed without a fine metal mask during the process of manufacturing the display device 10. That is, the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 can be formed in the display device 10 through deposition and optical processes without a fine metal mask.

[0144] In addition, in the display device 10, since the third bank layer 165 includes the second tip TIP2, the first emission layer EL1 and the first organic pattern ELP1 can be spaced apart from each other, and the first cathode electrode CE1 and the first electrode pattern CEP1 can be spaced apart from each other. In addition, in the display device 10, since the third bank layer 165 includes the second tip TIP2, the second emission layer EL2 and the second organic pattern ELP2 can be spaced apart from each other, and the second cathode electrode CE2 and the second electrode pattern CEP2 can be spaced apart from each other.

[0145] The second pixel defining layer 155 may contact the third bank layer 165. The second pixel defining layer 155 will be described later.

[0146] The residual pattern 153 may be positioned between the first anode electrode AE1 and the first pixel defining layer 151 in the third direction (Z-axis direction), and may be positioned between the second anode electrode AE2 and the first pixel defining layer 151 in the third direction (Z-axis direction). In addition, the residual pattern 153 may overlap the protruding tip TIP of the embankment structure 160 in the third direction (Z-axis direction).

[0147] During the manufacturing process, the display device 10 may include a sacrificial layer SFL (see FIG. 1 ) between the first pixel defining layer 151 and the first, second, and third anode electrodes AE1, AE2, and AE3. Fig.14). The sacrificial layer SFL may be positioned between the first pixel defining layer 151 and the first, second, and third anode electrodes AE1, AE2, and AE3, and then may be partially removed via a subsequent wet etching process. In doing so, the unremoved portion of the sacrificial layer SFL may remain as a residual pattern 153 between the first pixel defining layer 151 and the first, second, and third anode electrodes AE1, AE2, and AE3.

[0148] The first cathode electrode CE1 may completely cover the first emission layer EL1, and the second cathode electrode CE2 may completely cover the second emission layer EL2. In addition, the first emission layer EL1 and the second emission layer EL2 may contact a portion of the first tip TIP1 of the first bank layer 161 to cover them.

[0149] The first inorganic layer 171-1 may completely cover the first light emitting element ED1 in the first emission area EA1, and may partially cover the first electrode pattern CEP1 in the non-emission area NLA. In addition, the second inorganic layer 171-2 may completely cover the second light emitting element ED2 in the second emission area EA2, and may partially cover the second electrode pattern CEP2 in the non-emission area NLA. The first inorganic layer 171-1 and the second inorganic layer 171-2 may be spaced apart from each other, exposing the second pixel defining layer 155 in the non-emission area NLA.

[0150] In the non-emission area NLA, the first organic pattern ELP1, the first electrode pattern CEP1, and the first inorganic layer 171-1, and the second organic pattern ELP2, the second electrode pattern CEP2, and the second inorganic layer 171-2 may have a groove portion TP. In the display device 10, the manufacturing process may include a process of etching the first organic pattern ELP1, the first electrode pattern CEP1, the first inorganic layer 171-1, the second organic pattern ELP2, the second electrode pattern CEP2, and the second inorganic layer 171-2. The groove portion TP may be formed via an etching process. The groove portion TP may be covered by the second encapsulation layer 173. The second encapsulation layer 173 and the third encapsulation layer 175 have been described above, and thus will not be described again.

[0151] Although only the structures in the first emission area EA1 and the second emission area EA2 are shown and described for convenience of explanation, the structure in the third emission area EA3 may include the same features.

[0152] Figure 7 yes Figure 6 An enlarged cross-sectional view of area P.

[0153] Reference Figure 7, the second pixel defining layer 155 may overlap the second tip TIP2 of the third bank layer 165 , and may contact the second tip TIP2 of the third bank layer 165 .

[0154] According to some embodiments, the second pixel defining layer 155 may include a first surface (eg, top surface) 155 c facing the second encapsulation layer 173 and a second surface (eg, bottom surface) 155 d facing the third bank layer 165 .

[0155] According to some embodiments, the first surface 155c of the second pixel defining layer 155 may be divided into a first portion c1, a second portion c2, and a third portion c3 according to the elements to which the portions c1, c2, and c3 contact, respectively. For example, the first portion c1 may contact the first organic pattern ELP1, the second portion c2 may contact the second organic pattern ELP2, and the third portion c3 may contact the second encapsulation layer 173. The first organic pattern ELP1 and the second organic pattern ELP2 may be spaced apart from each other, and the third portion c3 of the second pixel defining layer 155 (for example, in a plan view) is between the first organic pattern ELP1 and the second organic pattern ELP2. That is, the first organic pattern ELP1 and the second organic pattern ELP2, the first electrode pattern CEP1 and the second electrode pattern CEP2, and the first inorganic layer 171-1 and the second inorganic layer 171-2 may be spaced apart from each other, and the second encapsulation layer 173 is between them. In other words, the first portion c1 may overlap the first electrode pattern CEP1 and the first inorganic layer 171-1, and the second portion c2 may overlap the second electrode pattern CEP2 and the second inorganic layer 171-2. The third portion c3 may not overlap any of the first organic pattern ELP1, the second organic pattern ELP2, the first electrode pattern CEP1, the second electrode pattern CEP2, the first inorganic layer 171-1, and the second inorganic layer 171-2.

[0156] Figure 8 is a diagram showing a method according to one or more other embodiments Figure 3 1 is a plan view of a layout of the emission area EA in the display area DA.

[0157] Reference Figure 8 , the first emission area EA1, the second emission area EA2, and the third emission area EA3 included in the display device 30 may be defined by the first opening OP1 and the second opening OP3. For example, the first opening OP1 may be defined by the first pixel defining layer 151, and the second opening OP3 may be defined by the second pixel defining layer 159, which will be described later. When viewed from the top, the second opening OP3 may completely surround the first opening OP1. When viewed from the top, the second opening OP3 may be completely surrounded by the non-emission area NLA.

[0158] Fig. 9 It is along Figure 8 1 is a cross-sectional view of the display layer DPL taken along the line X3-X3' of FIG. The display layer DPL may include a substrate 110, a thin film transistor layer 130, a display element layer 150, and a thin film encapsulation layer 170. The substrate 110, the thin film transistor layer 130, and the thin film encapsulation layer 170 included in the display device 30 may include the same structure and features as the display device 10 according to one or more other embodiments. Therefore, redundant descriptions will be omitted, and the structure of the display element layer 150 included in the display device 30 will be described.

[0159] According to Fig. 9 Corresponding to one or more embodiments, the display element layer 150 may include a light emitting element ED, a first pixel defining layer 151 , a residual pattern 153 , a second pixel defining layer 159 , and a bank structure 160 .

[0160] The bank structure 160 may include a first bank layer 161, a second bank layer 163, and a third bank layer 165 positioned on the first pixel defining layer 151. The first bank layer 161 may contact the first pixel defining layer 151, and may include a first tip TIP1 protruding from the second bank layer 163 toward the emission area EA. The first bank layer 161 and the second bank layer 163 may include the same structure and features as those of the above-described display device 10, and a redundant description thereof will be omitted.

[0161] The third bank layer 165 may completely cover the second bank layer 163. In other words, the second bank layer 163 may be completely surrounded by the first bank layer 161 and the third bank layer 165. In addition, the third bank layer 165 may completely cover the first bank layer 161. However, it should be understood that the present disclosure is not limited thereto. According to the manufacturing process, the third bank layer 165 may expose a portion of the first bank layer 161.

[0162] The second pixel defining layer 159 may be positioned on the embankment structure 160. The second pixel defining layer 159 may include a first layer 159A and a second layer 159B. The first layer 159A of the second pixel defining layer 159 may contact the third embankment layer 165 and may define a second opening OP3. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may be defined by the second opening OP3. In addition, the second layer 159B of the second pixel defining layer 159 may contact the first layer 159A and may include (e.g., in a plan view) a second tip TIP3 protruding from the first layer 159A toward the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0163] In the display device 30, since the second pixel defining layer 159 includes the second tip TIP3, even without a fine metal mask during the process of manufacturing the display device 30, the first light-emitting element ED1, the second light-emitting element ED2 and the third light-emitting element ED3 can also be formed in the first emission area EA1, the second emission area EA2 and the third emission area EA3, respectively.

[0164] The second pixel defining layer 159 may include an inorganic insulating material, for example, one of silicon oxide, silicon nitride, and silicon oxynitride. It should be noted that the first layer 159A and the second layer 159B may be made of different materials. For example, if the first layer 159A is made of silicon oxide, the second layer 159B may include silicon nitride and silicon oxynitride in addition to silicon oxide. This can form the second tip TIP3 of the second pixel defining layer 159 by utilizing the different etching rates of the first layer 159A and the second layer 159B in the manufacturing process of the display device 30.

[0165] The first, second, and third organic patterns ELP1, ELP2, and ELP3 and the first, second, and third electrode patterns CEP1, CEP2, and CEP3 may be positioned on the second pixel defining layer 159. The first, second, and third organic patterns ELP1, ELP2, and ELP3 and the first, second, and third electrode patterns CEP1, CEP2, and CEP3 may be positioned to surround the first opening OP1.

[0166] The emission layer EL may include first, second, and third emission layers EL1, EL2, and EL3 positioned in the first, second, and third emission regions EA1, EA2, and EA3, respectively. The emission layer EL may contact the third bank layer 165 in the second opening OP3.

[0167] The residual pattern 153 may be positioned between the anode electrode AE ​​and the first pixel defining layer 151 in the third direction (Z-axis direction), and may contact the emission layer EL.

[0168] The cathode electrode CE may include first, second, and third cathode electrodes CE1, CE2, and CE3 positioned in the first, second, and third emission regions EA1, EA2, and EA3, respectively. The cathode electrode CE may contact the third bank layer 165 in the second opening OP3.

[0169] The first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may cover the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 in the first opening OP1, respectively, and may cover the third bank layer 165 in the second opening OP3. The first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be different from the display device 10 according to one or more other embodiments in that they do not contact the second bank layer 163. In addition, the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may cover the second tip TIP3 of the second layer 159B.

[0170] The second encapsulation layer 173 may provide a flat surface over the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 in the first opening OP1, and may contact the second layer 159B of the second pixel defining layer 159 in the non-emission area NLA. In addition, the first encapsulation layer 171, the second encapsulation layer 173, and the third encapsulation layer 175 included in the thin film encapsulation layer 170 have been described above, and a redundant description thereof will be omitted.

[0171] Fig.10 It is schematically shown Fig. 9 An enlarged cross-sectional view of the non-emission area NLA positioned between the first emission area EA1 and the second emission area EA2.

[0172] According to Fig.10 In one or more corresponding embodiments, the first emission area EA1 and the second emission area EA2 may be spaced apart from each other, and the non-emission area NLA is between the first emission area EA1 and the second emission area EA2. As described above, the first opening OP1 may be defined by the first pixel defining layer 151, and the second opening OP3 may be defined by the second pixel defining layer 159.

[0173] According to some embodiments, the first bank layer 161 may include a first side surface 1a facing the first emission region EA1 and a second side surface 1b facing the second emission region EA2. The first side surface 1a of the first bank layer 161 may protrude from the second bank layer 163 toward the first emission region EA1, and the second side surface 1b of the first bank layer 161 may protrude from the second bank layer 163 toward the second emission region EA2. That is, the first bank layer 161 may have a first tip TIP1 protruding toward the first emission region EA1 and the second emission region EA2.

[0174] According to some embodiments, the second bank layer 163 may include a first side surface 3a, a second side surface 3b, and a first surface (e.g., a top surface) 3c. The first side surface 3a may face the first emission area EA1, the second side surface 3b may face the second emission area EA2, and the first surface 3c may face the second pixel defining layer 159. The first side surface 3a and the second side surface 3b may be connected by the first surface 3c.

[0175] The third bank 165 may contact the first side surface 3a, the second side surface 3b, and the first surface 3c of the second bank 163. In other words, the third bank 165 may completely cover the first side surface 3a, the second side surface 3b, and the first surface 3c of the second bank 163.

[0176] The second pixel defining layer 159 will be described later.

[0177] The first cathode electrode CE1 and the second cathode electrode CE2 may be electrically connected to each other through the third bank layer 165 and the second bank layer 163 .

[0178] The residual pattern 153 may overlap the first tip TIP1 of the first bank layer 161 and the second tip TIP3 of the second layer 159B of the second pixel defining layer 159 in the third direction (Z-axis direction).

[0179] The first inorganic layer 171-1 may completely cover the first light emitting element ED1 in the first opening OP1, and may completely cover the third bank layer 165, the second pixel defining layer 159, the first organic pattern ELP1, and the first electrode pattern CEP1 in the second opening OP3. In addition, the first inorganic layer 171-1 may cover a portion of the first electrode pattern CEP1 in the non-emission area NLA, and the first inorganic layer 171-1 may contact the first cathode electrode CE1, the third bank layer 165, the second pixel defining layer 159, the first organic pattern ELP1, and the first electrode pattern CEP1 in the second opening OP3.

[0180] In addition, the second inorganic layer 171-2 may completely cover the second light emitting element ED2 in the first opening OP1, and may completely cover the third bank layer 165, the second pixel defining layer 159, the second organic pattern ELP2, and the second electrode pattern CEP2 in the second opening OP3. In addition, the second inorganic layer 171-2 may cover a portion of the second electrode pattern CEP2 in the non-emission area NLA, and the second inorganic layer 171-2 may contact the second cathode electrode CE2, the third bank layer 165, the second pixel defining layer 159, the second organic pattern ELP2, and the second electrode pattern CEP2 in the second opening OP3. Other redundant descriptions will be omitted.

[0181] Fig.11 yes Fig.10 An enlarged cross-sectional view of area Q.

[0182] According to Fig.11 Corresponding to one or more embodiments, the first layer 159A of the second pixel defining layer 159 included in the display device 30 may contact the third bank layer 165 .

[0183] According to some embodiments, the first layer 159A of the second pixel defining layer 159 may include a first side surface A1 facing the first emission region EA1 and a second side surface A2 facing the second emission region EA2. In addition, the second layer 159B of the second pixel defining layer 159 may include a first side surface B1, a second side surface B2, a first surface (e.g., a top surface) B3, and a second surface (e.g., a bottom surface) B4. For example, the first side surface B1 may face the first emission region EA1, the second side surface B2 may face the second emission region EA2, the first surface B3 may face the second encapsulation layer 173, and the second surface B4 may face the first layer 159A. The first side surface B1 and the second side surface B2 may be connected by the first surface B3 and the second surface B4, and the first surface B3 and the second surface B4 may be opposite to each other.

[0184] According to some embodiments, the first side surface B1 of the second layer 159B may protrude from (e.g., exceed) the first side surface A1 of the first layer 159A in a direction opposite to the first direction (X-axis direction) toward the first emission region EA1. In addition, the second side surface B2 of the second layer 159B may protrude from the second side surface A2 of the second layer 159B in the first direction (X-axis direction) toward the second emission region EA2. Therefore, the second layer 159B may have a second tip TIP3 protruding at both sides of the first layer 159A in the first direction (X-axis direction), respectively. That is, an undercut may be formed between the second tip TIP3 and the first side surface A1 and between the second tip TIP3 and the second side surface A2.

[0185] According to some embodiments, the first surface B3 of the second layer 159B may be divided into a first portion B31, a second portion B32, and a third portion B33 according to the elements to which the portions B31, B32, and B33 respectively contact. For example, the first portion B31 may contact the first organic pattern ELP1, the second portion B32 may contact the second organic pattern ELP2, and the third portion B33 may contact the second encapsulation layer 173 (see Fig.10). The first organic pattern ELP1 and the second organic pattern ELP2 may be spaced apart from each other, and the third portion B33 of the second pixel defining layer 159 (e.g., in a plan view) is between the first organic pattern ELP1 and the second organic pattern ELP2. That is, the first organic pattern ELP1 and the second organic pattern ELP2, the first electrode pattern CEP1 and the second electrode pattern CEP2, and the first inorganic layer 171-1 and the second inorganic layer 171-2 may be spaced apart from each other, and the second encapsulation layer 173 (e.g., in a plan view) is between them.

[0186] In other words, the first portion B31 may overlap the first electrode pattern CEP1 and the first inorganic layer 171-1, and the second portion B32 may overlap the second electrode pattern CEP2 and the second inorganic layer 171-2. The third portion B33 may not overlap any of the first organic pattern ELP1, the second organic pattern ELP2, the first electrode pattern CEP1, the second electrode pattern CEP2, the first inorganic layer 171-1, and the second inorganic layer 171-2.

[0187] Fig.12 According to one or more other embodiments, Figure 8 A cross-sectional view of the display layer DPL taken along line X3-X3'. Fig.13 It is schematically shown Fig.12 An enlarged cross-sectional view of the non-emission area NLA positioned between the first emission area EA1 and the second emission area EA2.

[0188] The display layer DPL may include a substrate 110, a thin film transistor layer 130, a display element layer 150, and a thin film encapsulation layer 170. The substrate 110, the thin film transistor layer 130, and the thin film encapsulation layer 170 included in the display device 50 may include the same structure and features as those of the above-described display device 30. Therefore, redundant descriptions will be omitted, and the structure of the display element layer 150 included in the display device 50 will be described.

[0189] According to Fig.12 and Fig.13 Corresponding to one or more embodiments, the display element layer 150 may include a light emitting element ED, a first pixel defining layer 151, a residual pattern 153, a second pixel defining layer 159 and a levee structure 160. The first pixel defining layer 151 is different from the first pixel defining layer 151 of the above-mentioned display device 30 in that the former includes a first layer 151A and a second layer 151B. Other redundant descriptions will be omitted.

[0190] like Fig.13As shown in FIG. 1 , the first layer 151A included in the first pixel defining layer 151 may be positioned on the second via layer 127 and the anode electrode AE. The first layer 151A may define a first opening OP1.

[0191] According to some embodiments, the first layer 151A may include a first side surface A5 facing the first emission region EA1 and a second side surface A6 facing the second emission region EA2 .

[0192] In addition, the second layer 151B of the first pixel defining layer 151 may be positioned on the first layer 151A in contact therewith. In other words, the second layer 151B may be positioned between the first layer 151A and the first bank layer 161 .

[0193] According to some embodiments, the second layer 151B may include a first side surface B5 facing the first emission region EA1 and a second side surface B6 facing the second emission region EA2. The first side surface B5 of the second layer 151B may protrude from the first side surface A5 of the first layer 151A toward the first emission region EA1 in a direction opposite to the first direction (X-axis direction). In addition, the second side surface B6 of the second layer 151B may protrude from the second side surface A6 of the second layer 151B in the first direction (X-axis direction) toward the second emission region EA2. Therefore, the second layer 151B may have a third tip TIP5 protruding at both sides of the first layer 151A in the first direction (X-axis direction). An undercut may be formed between the third tip TIP5 and the first side surface A5 and between the third tip TIP5 and the second side surface A6.

[0194] Since the display device 50 includes the third tip TIP5 , the first light emitting element ED1 , the second light emitting element ED2 , and the third light emitting element ED3 may be formed without a fine metal mask during a process of manufacturing the display device 50 .

[0195] According to some embodiments, the first pixel defining layer 151 may include an inorganic insulating material, for example, one of silicon oxide, silicon nitride, and silicon oxynitride. It should be noted that the first layer 151A and the second layer 151B may be made of different materials. For example, when the first layer 151A is made of silicon oxide, the second layer 151B may include silicon nitride and silicon oxynitride, but not silicon oxide. This can form the third tip TIP5 of the second layer 151B by utilizing the different etching rates of the first layer 151A and the second layer 151B in the manufacturing process of the display device 50.

[0196] The first emission layer EL1 and the second emission layer EL2 may contact the third tip TIP5 of the first pixel defining layer 151 to cover them. Other redundant descriptions will be omitted.

[0197] The embankment structure 160 may be positioned on the second layer 151B of the first pixel defining layer 151 in contact therewith. The embankment structure 160 may include a first embankment layer 161, a second embankment layer 163, and a third embankment layer 165. The first embankment layer 161 may include a first tip TIP1 protruding from the second embankment layer 163 toward the first emission area EA1 and the second emission area EA2. The third embankment layer 165 may completely cover the second embankment layer 163. The first tip TIP1 may not overlap with the third tip TIP5 in the third direction (Z-axis direction). In addition, a portion of the third embankment layer 165 may overlap with the third tip TIP5 in the third direction (Z-axis direction), and a portion of the third embankment layer 165 may contact the third tip TIP5. Other redundant descriptions will be omitted.

[0198] The second pixel defining layer 159 may be positioned on the embankment structure 160. The second pixel defining layer 159 may include a first layer 159A and a second layer 159B, and the first layer 159A of the second pixel defining layer 159 may define a second opening OP3. In addition, the second layer 159B of the second pixel defining layer 159 may include a second tip TIP3 protruding from the first layer 159A toward the first emission area EA1 and the second emission area EA2. Other redundant descriptions will be omitted.

[0199] Figures 14 to 25 It shows the manufacturing Figure 5 Schematic cross-sectional view of a method for manufacturing a display device 10 shown in FIG. 1 . Hereinafter, the manufacturing method will be described according to the order in which the layers are formed. Figure 5 The process of display layer DPL is shown in FIG.

[0200] Reference Fig.14 , an anode electrode AE, a sacrificial layer SFL, a first pixel defining material layer 151L, a first bank material layer 161L, a second bank material layer 163L, a third bank material layer 165L, and a second pixel defining material layer 155L may be formed on the thin film transistor layer 130. In one or more embodiments, the thin film transistor layer 130 may be positioned on the substrate 110, and ... Figure 5 The structure of the thin film transistor layer 130 is described, and a redundant description thereof will be omitted.

[0201] The anode electrode AE ​​may include a first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3 that are spaced apart from each other on the thin film transistor layer 130. A sacrificial layer SFL may be positioned on each of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The sacrificial layer SFL may help reduce or prevent the possibility that the top surfaces of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 contact the first pixel defining material layer 151L.

[0202] The sacrificial layer SFL may include an oxide semiconductor. For example, the sacrificial layer SFL may include at least one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), and the like.

[0203] A first pixel defining material layer 151L, a first bank material layer 161L, a second bank material layer 163L, a third bank material layer 165L, and a second pixel defining material layer 155L may be positioned over the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 and the sacrificial layer SFL. The first pixel defining material layer 151L may be positioned to completely cover the sacrificial layer SFL and the thin film transistor layer 130, and the first bank material layer 161L, the second bank material layer 163L, and the third bank material layer 165L may be positioned to completely cover the first pixel defining material layer 151L. The first bank material layer 161L may be directly positioned on the first pixel defining material layer 151L, and the second bank material layer 163L and the third bank material layer 165L may be sequentially positioned on the first bank material layer 161L. The second pixel defining material layer 155L may be positioned to completely cover the third bank material layer 165L.

[0204] Then, refer to Fig.15 , a photoresist PR may be formed on the second pixel defining material layer 155L except for a portion overlapping the first anode electrode AE1. Subsequently, the first pixel defining material layer 151L, the first bank material layer 161L, the second bank material layer 163L, the third bank material layer 165L, and the second pixel defining material layer 155L are partially etched (first etching) using the photoresist PR as a mask.

[0205] According to one or more embodiments, the first etching process may be implemented as dry etching. When the first etching process (first etching) is performed as a dry etching process, the first pixel defining material layer 151L, the first bank material layer 161L, the second bank material layer 163L, and the third bank material layer 165L, and a portion of the second pixel defining material layer 155L overlapping the first anode electrode AE1 may be isotropically etched.

[0206] Through this process, Fig.16 As shown in FIG. 1 , the hole HOL may be formed at a portion overlapping the first anode electrode AE1 , and the sacrificial layer SFL positioned on the first anode electrode AE1 may be exposed.

[0207] Then, refer to Fig.17 , the inner part of the hole HOL formed in line with the first anode electrode AE1 is etched (second etching). According to one or more embodiments, the second etching process may be performed as a wet etching process.

[0208] The first bank material layer 161L and the third bank material layer 165L may have an etching rate lower than that of the second bank material layer 163L. Therefore, a side surface of the first bank material layer 161L may form a first tip TIP1 protruding from a side surface of the second bank material layer 163L toward the hole HOL, and a side surface of the third bank material layer 165L may form a second tip TIP2 protruding from a side surface of the second bank material layer 163L toward the hole HOL.

[0209] In addition, the first pixel defining material layer 151L and the second pixel defining material layer 155L include different inorganic materials and thus may have different corresponding etching rates. Therefore, even if the first pixel defining material layer 151L and the second pixel defining material layer 155L are formed via the same process, the first pixel defining material layer 151L and the second pixel defining material layer 155L may have different shapes.

[0210] Meanwhile, the sacrificial layer SFL positioned on the first anode electrode AE1 may be partially removed through this process. It should be noted that the sacrificial layer SFL may not be completely removed but may remain as a residual pattern 153 in the space between the first pixel defining material layer 151L and the first anode electrode AE1.

[0211] Then, refer to Fig.18 , a first emission layer EL1 and a first cathode electrode CE1 are deposited on the first anode electrode AE1. The first emission layer EL1 and the first cathode electrode CE1 may be formed through a thermal evaporation process.

[0212] Since the display device 10 includes the first tip TIP1 and the second tip TIP2 , it is possible to form the first emission layer EL1 and the first cathode electrode CE1 on the first anode electrode AE1 without a fine metal mask.

[0213] It should be noted that the deposition process for forming the first emission layer EL1 may be performed at an angle of about 45° to about 50° from the upper surface of the first anode electrode AE1. Therefore, the first emission layer EL1 may be formed to fill the space between the first anode electrode AE1 and the first pixel defining material layer 151L, and may also be formed on a portion of the side surface of the second bank material layer 163L hidden by the second tip TIP2.

[0214] The deposition process for forming the first cathode electrode CE1 may be performed at an angle of about 30° or less from the upper surface of the first anode electrode AE1. In other words, the deposition process for forming the first cathode electrode CE1 may be performed in a relatively horizontal direction compared to the deposition process for forming the first emission layer EL1. Therefore, the first cathode electrode CE1 may completely cover the first emission layer EL1, and may also be formed on a portion of the side surface of the second bank material layer 163L hidden by the second tip TIP2. In this way, the first light emitting element ED1 may be formed.

[0215] The first emission layer EL1 and the first cathode electrode CE1 may be positioned not only on the first anode electrode AE1 but also on the second pixel defining material layer 155L. In other words, the first emission layer EL1 and the first cathode electrode CE1 may be positioned on the second pixel defining material layer 155L above the second anode electrode AE2 and the third anode electrode AE3.

[0216] Subsequently, a first encapsulation material layer 171L covering the first cathode electrode CE1 is formed on the entire surface. The first encapsulation material layer 171L may be formed via a chemical vapor deposition (CVD) process. The first encapsulation material layer 171L may form a uniform film regardless of the underlying structure having different heights. For example, the first encapsulation material layer 171L may also cover the step formed due to the first light emitting element ED1, and may also cover the undercut formed due to the second tip TIP2 and the second embankment material layer 163L. In addition, the first encapsulation material layer 171L may completely cover the first cathode electrode CE1 positioned on the second pixel defining material layer 155L.

[0217] Reference Fig.19 , a photoresist PR is formed on the first light emitting element ED1 and the periphery of the first light emitting element ED1, and an etching process (third etching) is performed, leaving the first light emitting element ED1 and the periphery of the first light emitting element ED1. For example, the third etching process can be performed by alternately performing a wet etching process and a dry etching process. In this process, the first emission layer EL1, the first cathode electrode CE1, and the first encapsulation material layer 171L on which the photoresist PR is not formed can be completely removed.

[0218] Through this process, Fig. 20 As shown in , the first inorganic layer 171 - 1 may be formed, and the first emission layer EL1 and the first cathode electrode CE1 positioned on the second pixel defining material layer 155L may be formed as the first organic pattern ELP1 and the first electrode pattern CEP1.

[0219] Then, refer to Figure 21 to Figure 23, repeat the above process to form the second light emitting element ED2. For example, a photoresist PR is formed so that a portion overlapping the second anode electrode AE2 is exposed, and a hole HOL is formed in the portion overlapping the second anode electrode AE2 through a dry etching process. Subsequently, portions of the first bank material layer 161L, the second bank material layer 163L, and the third bank material layer 165L overlapping the inner portion of the hole HOL may be wet-etched to form a first tip TIP1 of the first bank material layer 161L and a second tip TIP2 of the third bank material layer 165L.

[0220] Subsequently, the second emission layer EL2, the second cathode electrode CE2 and the first encapsulation material layer 171L are deposited on the entire surface. In this process, the second emission layer EL2, the second cathode electrode CE2 and the first encapsulation material layer 171L are formed on the second anode electrode AE2, so that the second light emitting element ED2 can be formed.

[0221] In addition, the second emission layer EL2, the second cathode electrode CE2, and the first encapsulation material layer 171L may be completely formed over the first anode electrode AE1 and the third anode electrode AE3. Therefore, the second emission layer EL2, the second cathode electrode CE2, and the first encapsulation material layer 171L formed in this process may be positioned on the first inorganic layer 171-1.

[0222] Then, if Fig. 22 As shown in , a photoresist PR is formed on the second light emitting element ED2 and the periphery of the second light emitting element ED2, and an etching process (fourth etching) is performed, leaving the second light emitting element ED2 and the periphery of the second light emitting element ED2. For example, the fourth etching process can be performed by alternately performing a wet etching process and a dry etching process. In this process, the second emission layer EL2, the second cathode electrode CE2, and the first encapsulation material layer 171L on which the photoresist PR is not formed can be completely removed.

[0223] Through this process, Fig.23 As shown in FIG. 1 , the second inorganic layer 171 - 2 may be formed, and the second emission layer EL2 and the second cathode electrode CE2 positioned on the second pixel defining material layer 155L may be formed as the second organic pattern ELP2 and the second electrode pattern CEP2 .

[0224] As described above, in the display device 10, the etching process may be repeatedly performed. Generally, when the metal material is exposed to the etchant during the etching process, the metal material may cause an arc fault. It should be noted that the display device 10 includes a second pixel defining material layer 155L on the third bank material layer 165L including the metal material, so that the metal material can be protected from being exposed to the etchant during the repeated etching process. Therefore, the display device 10 can solve the arc fault caused during the manufacturing process.

[0225] Then, refer to Fig.24 , repeat the above process to form a third light emitting element ED3 and a third inorganic layer 171-3. The description of the repeated process is omitted. Through this process, the third emission layer EL3 and the third cathode electrode CE3 positioned on the second pixel defining material layer 155L will be formed into a third organic pattern ELP3 and a third electrode pattern CEP3.

[0226] Through this process, the first pixel defining material layer 151L may be formed as Figure 5 , the first bank material layer 161L may be formed as the first bank layer 161, the second bank material layer 163L may be formed as the second bank layer 163, and the third bank material layer 165L may be formed as the third bank layer 165. In addition, the second pixel defining material layer 155L may be formed as the second pixel defining layer 155.

[0227] Then, refer to Fig.25 , a second encapsulation layer 173 may be formed on the entire surface to provide a flat surface above the first encapsulation layer 171 having different heights, and then a third encapsulation layer 175 may be formed on the entire second encapsulation layer 173, so that Figure 5 The display element layer 150 of the display device 10 shown in FIG.

[0228] As described above, since the display device 10 includes the first tip TIP1 of the first bank layer 161 and the second tip TIP2 of the third bank layer 165, the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 spaced apart from each other can be formed without a fine metal mask. In addition, since the display device 10 includes the second pixel defining layer 155 on the third bank layer 165, an arc fault caused during a manufacturing process can be prevented.

[0229] The foregoing is an explanation of some embodiments of the present disclosure and should not be interpreted as limiting it. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications can be made in the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of the aspects within each embodiment should generally be considered to be applicable to other similar aspects in other embodiments. Therefore, as will be clear to those of ordinary skill in the art, unless otherwise specifically stated, the features, characteristics and / or elements described in conjunction with a particular embodiment can be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it should be understood that the foregoing is an explanation of various example embodiments and should not be interpreted as being limited to the specific embodiments disclosed herein, and that various modifications to the disclosed embodiments and other example embodiments are intended to be included in the spirit and scope of the present disclosure as defined in the appended claims and their equivalents.

Claims

1. A display device, comprising: a substrate, including an emitting region and a non-emitting region; a first anode electrode at the emission region; a first cathode electrode, above the first anode electrode; a first pixel defining layer at the non-emission region and defining a first opening; a bank structure above the first pixel defining layer and including a second bank layer and a third bank layer, the second bank layer contacting the first cathode electrode, the third bank layer including a second tip protruding from a side surface of the second bank layer toward the emission region; a second pixel defining layer, over the bank structure, defining a second opening, overlapping the second tip in a direction perpendicular to the substrate, and contacting the second tip; as well as A first encapsulation layer is above the second pixel defining layer.

2. The display device according to claim 1, further comprising: The first bank layer contacts the first pixel defining layer between the first pixel defining layer and the second bank layer, and includes a first tip protruding from the side surface of the second bank layer toward the emission region.

3. The display device according to claim 2, wherein: The second bank layer has higher conductivity than the first bank layer and the third bank layer.

4. The display device according to claim 3, wherein: The first cathode electrode covers the first tip.

5. The display device according to claim 4, wherein: The first pixel defining layer and the second pixel defining layer include different inorganic materials.

6. The display device according to claim 4, further comprising: A residual pattern is between the first anode electrode and the first pixel defining layer in the direction perpendicular to the substrate and overlaps the first tip and the second tip in the direction perpendicular to the substrate.

7. The display device according to claim 1, wherein: In a plan view, the first opening is completely surrounded by the second opening.

8. The display device according to claim 1, further comprising: a second anode electrode spaced apart from the first anode electrode, with the first pixel defining layer between the second anode electrode and the first anode electrode; as well as A second cathode electrode is above the second anode electrode, contacts the second bank layer, and is electrically connected to the first cathode electrode through the second bank layer.

9. The display device according to claim 8, further comprising: a second encapsulation layer, above the first encapsulation layer, and comprising an organic material, The first encapsulation layer includes: a first inorganic layer covering the first cathode electrode; and a second inorganic layer covering the second cathode electrode and separated from the first inorganic layer by the second encapsulation layer at the non-emitting region.

10. The display device according to claim 9, wherein: The second pixel defining layer includes a first surface facing the second encapsulation layer and including a first portion overlapping the first inorganic layer, a second portion overlapping the second inorganic layer, and a third portion between the first portion and the second portion and contacting the second encapsulation layer.

11. The display device according to claim 9, further comprising: a first electrode pattern, over the second pixel defining layer, spaced apart from the first cathode electrode, and comprising the same material as the first cathode electrode; as well as The second electrode pattern is over the second pixel defining layer, is spaced apart from the second cathode electrode, and includes the same material as the second cathode electrode.

12. The display device according to claim 11, wherein: The first electrode pattern and the second electrode pattern are spaced apart from each other in a direction parallel to the substrate, and the second encapsulation layer is between the first electrode pattern and the second electrode pattern.

13. A display device, comprising: a substrate, including an emitting region and a non-emitting region; an anode electrode at the emission region; a cathode electrode, above the anode electrode; a first pixel defining layer at the non-emission region and defining a first opening; a bank structure, above the first pixel defining layer, and including a first bank layer, a second bank layer, and a third bank layer stacked on each other in a direction perpendicular to the substrate; as well as The second pixel defining layer, over the embankment structure, defines a second opening and includes a first layer and a second layer, wherein the first layer contacts the third embankment layer, and the second layer is over the first layer and includes a second tip protruding from a side surface of the first layer toward the emission region.

14. The display device according to claim 13, wherein: The second bank layer is completely surrounded by the first bank layer and the third bank layer.

15. The display device according to claim 14, wherein: The cathode electrode contacts the third bank layer.

16. The display device according to claim 14, wherein: The first bank layer includes a first tip that protrudes from a side surface of the second bank layer toward the emission region and overlaps the second tip in the direction perpendicular to the substrate.

17. The display device according to claim 16, wherein: The first layer and the second layer include different inorganic materials.

18. The display device according to claim 15, wherein: The first pixel defining layer includes a third layer and a fourth layer, the third layer faces the substrate, and the fourth layer is above the third layer and includes a first tip protruding from a side surface of the third layer toward the emission region.

19. The display device according to claim 18, wherein: The first tip is in the first opening.

20. A method for manufacturing a display device, the method comprising: preparing a substrate including an emissive region and a non-emissive region; forming an anode electrode at the emission region; forming a sacrificial layer above the anode electrode; forming a first pixel definition material layer completely covering the sacrificial layer and the substrate; forming a bank material layer completely covering the first pixel defining material layer; forming a second pixel defining material layer; forming a photoresist over the second pixel defining material layer; removing portions of the first pixel defining material layer, the bank material layer, and the second pixel defining material layer overlapping the anode electrode through an etching process to form a hole exposing the sacrificial layer; removing the inner sidewall of the hole by an etching process to expose the anode electrode; forming a first pixel defining layer, a second pixel defining layer, and a bank structure, wherein the bank structure is protected by the second pixel defining layer from the etchant during an etching process, and the bank structure includes a stacked structure of a second bank layer, a first bank layer, and a third bank layer, wherein the first bank layer is below the second bank layer and includes a first tip protruding from a side surface of the second bank layer toward the emission region, and the third bank layer is above the second bank layer and includes a second tip protruding from a side surface of the second bank layer toward the emission region; forming an emission layer and a cathode electrode above the anode electrode and the second pixel defining layer; forming a first encapsulation layer above the cathode electrode; as well as The emission layer, the cathode electrode, and the first encapsulation layer above the second pixel defining layer are removed, leaving portions of the emission layer, the cathode electrode, and the first encapsulation layer at the emission region and at the periphery of the emission region.

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