Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel comprises a substrate; the driving circuit layer is arranged on one side of the substrate, the driving circuit layer comprises a plurality of data lines arranged in a display area and a plurality of electrostatic protection circuits arranged in a non-display area, and the non-display area is arranged around the display area; the light-emitting device layer is arranged on the side, away from the substrate, of the driving circuit layer and located in the display area; the ion barrier layer is arranged on the side, away from the substrate, of the driving circuit layer and located in the non-display area; and the orthographic projection of the ion barrier layer on the substrate is overlapped with at least part of orthographic projection of the electrostatic protection circuit on the substrate.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) displays have the advantages of being foldable, bendable, and having narrow borders, and have broad application prospects. With the continuous development of display technology, the demand for large-size display screens is increasing. Current OLED display panels are prone to circuit failure. Summary of the invention

[0003] Based on this, it is necessary to provide a display panel and a display device.

[0004] In a first aspect, the present application provides a display panel, comprising:

[0005] substrate;

[0006] A driving circuit layer is provided on one side of the substrate, the driving circuit layer includes a plurality of data lines provided in the display area and a plurality of electrostatic protection circuits provided in the non-display area, and the non-display area is provided around the display area;

[0007] A light emitting device layer, provided on a side of the driving circuit layer away from the substrate and located in the display area;

[0008] The ion blocking layer is arranged on a side of the driving circuit layer away from the substrate and located in the non-display area; and the orthographic projection of the ion blocking layer on the substrate overlaps with at least part of the orthographic projection of the electrostatic protection circuit on the substrate.

[0009] In one embodiment, the display panel further includes:

[0010] A first planarization layer, disposed between the driving circuit layer and the ion blocking layer, covering at least a portion of the electrostatic protection circuit;

[0011] Preferably, the first planarization layer completely covers the electrostatic protection circuit;

[0012] Preferably, the driving circuit layer further comprises a plurality of pixel driving circuits arranged in the display area, and the pixel driving circuits are connected to the data lines; the first planarization layer comprises a first planar portion covering the pixel driving circuits and a second planar portion covering the electrostatic protection circuit, and a gap is provided between the first planar portion and the second planar portion, and an orthographic projection of the gap on the substrate surrounds at least a portion of the periphery of the electrostatic protection circuit;

[0013] The ion blocking layer covers at least a portion of the top surface of the second flat portion on a side away from the driving circuit layer, and a side surface of the second flat portion facing the gap;

[0014] Preferably, the orthographic projection of the electrostatic protection circuit on the substrate is located within the orthographic projection of the ion blocking layer on the substrate;

[0015] Preferably, the width of the gap is 1 μm to 20 μm;

[0016] Preferably, the gap is a circumferentially closed structure surrounding the plurality of electrostatic protection circuits;

[0017] Preferably, the orthographic projection of the gap on the substrate surrounds the entire periphery of the orthographic projection of the electrostatic protection circuit on the substrate;

[0018] Preferably, the gap penetrates the first planarization layer along the thickness direction of the substrate;

[0019] Preferably, the edge of the ion blocking layer is spaced apart from the first flat portion;

[0020] Preferably, the distance between the edge of the ion blocking layer and the first flat portion is between 1 μm and 9 μm.

[0021] In one embodiment, the driving circuit layer includes a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a third metal layer which are stacked, and the data line is arranged in the first metal layer or the second metal layer, and is connected to one end of the electrostatic protection circuit arranged in the third metal layer through a via structure penetrating the second insulating layer and / or the third insulating layer;

[0022] Preferably, a first via hole penetrating to the first metal layer is provided in the second insulating layer and the third insulating layer, the data line is connected to the electrostatic protection circuit through the first via hole, and the material of the third metal layer is filled in the first via hole and completely covers the top surface of the first metal layer exposed to the first planarization layer;

[0023] Preferably, a second via hole penetrating through the second metal layer is provided in the third insulating layer, the data line is connected to the electrostatic protection circuit via the second via hole, and the material of the third metal layer is filled in the second via hole and completely covers the top surface of the second metal layer exposed to the first planarization layer;

[0024] Preferably, the driving circuit layer further comprises a fourth insulating layer and a fourth metal layer provided on a side of the third metal layer away from the substrate, and the ion blocking layer and the fourth metal layer are provided in the same layer and with the same material;

[0025] Preferably, the ion blocking layer comprises a stacked arrangement of Ti / Al / Ti.

[0026] In one embodiment, the display panel further includes:

[0027] A power supply voltage line, the power supply voltage line is connected to the pixel driving circuit, and the power supply voltage line is also connected to the ion blocking layer;

[0028] Preferably, the power supply voltage line is at least partially disposed in a gap between the first flat portion and the second flat portion;

[0029] Preferably, the power supply voltage line is provided in the third metal layer, and the ion blocking layer covers at least a portion of the top surface of the power supply voltage line away from the third insulating layer;

[0030] Preferably, the width of the power supply voltage line is 5 μm to 20 μm;

[0031] Preferably, the first planarization layer also covers at least a portion of the surface of the power supply voltage line close to the ion blocking layer, and the first planarization layer disposed on the surface of the power supply voltage line is provided with a third via hole for exposing the power supply voltage line, and the ion blocking layer is in contact with the power supply voltage line through the third via hole;

[0032] Preferably, the inner diameter of the third via hole is between 1 μm and 8 μm.

[0033] In one embodiment, the display panel further includes:

[0034] A chip pad, used for connecting a display driver chip, the chip pad being located on a side of the multiple electrostatic protection circuits away from the display area and connected to the electrostatic protection circuits;

[0035] Wherein, the ion blocking layer also covers the side of the second flat portion facing the chip pad;

[0036] Preferably, the chip pad is provided on the third metal layer.

[0037] In one embodiment, the light emitting device layer includes a first electrode layer, a light emitting material layer, and a second electrode layer stacked in a direction away from the substrate; the ion blocking layer is provided in the same layer and material as the first electrode layer;

[0038] Preferably, the material of the ion barrier layer includes at least one of metal and metal oxide;

[0039] Preferably, the ion blocking layer comprises a stacked structure of ITO / Ag / ITO.

[0040] In one embodiment, the display panel further includes:

[0041] A second planarization layer, at least a portion of the second planarization layer is disposed on a side of the ion blocking layer away from the substrate;

[0042] Preferably, the orthographic projection of the second planarization layer on the substrate at least partially overlaps with the orthographic projection of the ion blocking layer on the substrate;

[0043] Preferably, the orthographic projection of the ion blocking layer on the substrate is located within the orthographic projection of the second planarization layer on the substrate;

[0044] Preferably, the second planarization layer also extends into the gap;

[0045] Preferably, the second planarization layer is made of the same material as the first planarization layer;

[0046] Preferably, the display panel further comprises a pixel definition layer provided on a side of the driving circuit layer close to the light emitting device layer, and the second planarization layer is provided in the same layer and with the same material as the pixel definition layer;

[0047] Preferably, the orthographic projection of the second planarization layer on the substrate at least partially overlaps with the orthographic projection of the gap on the substrate;

[0048] Preferably, the orthographic projection of the gap on the substrate is located within the orthographic projection of the second planarization layer on the substrate;

[0049] Preferably, the second planarization layer has a thickness of 5 μm to 2 μm.

[0050] In one of the embodiments, in one of the embodiments, the display panel further includes:

[0051] A device encapsulation layer, disposed on a side of the light-emitting device layer away from the substrate;

[0052] A polarizing layer, disposed on a side of the device packaging layer away from the substrate;

[0053] A UV adhesive layer is arranged on a side of the ion blocking layer away from the electrostatic protection circuit and is spaced apart from the polarizing layer;

[0054] Wherein, the ion blocking layer is used to block ions from the polarizing layer;

[0055] Preferably, the ions from the polarizing layer are potassium ions;

[0056] Preferably, the device encapsulation layer comprises a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer which are stacked;

[0057] Preferably, the orthographic projection of the device packaging layer on the substrate overlaps with at least a portion of the electrostatic protection circuit;

[0058] Preferably, the material of the inorganic encapsulation layer includes at least one of SiON and SiNx;

[0059] Preferably, the inorganic encapsulation layer includes SiON with a thickness of 0.5 μm to 5 μm and SiNx with a thickness of 0.5 μm to 5 μm.

[0060] In one embodiment, the display panel further includes:

[0061] An optical adhesive layer is provided between the device packaging layer and the polarizing layer, and the optical adhesive layer is spaced apart from the UV adhesive layer.

[0062] In a second aspect, the present application provides a display device, comprising the display panel as described above.

[0063] The above-mentioned display panel and display device, by forming an ion blocking layer on the electrostatic protection circuit, the orthographic projection of the ion blocking layer on the substrate covers at least part of the orthographic projection of the electrostatic protection circuit on the substrate, which can block the migration path of ions to the electrostatic protection circuit to a large extent, thereby inhibiting the electrolytic reaction occurring in the electrostatic protection circuit, and further avoiding corrosion of the electrolytic reaction to the electrostatic protection circuit, reducing the failure risk of the electrostatic protection circuit, and improving the display effect and service life of the display panel and display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only used for the purpose of illustrating the preferred embodiments and are not to be considered as limitations of the present application. In addition, the same reference numerals are used throughout the drawings to represent the same components.

[0065] Figure 1 is one of the cross-sectional schematic diagrams of a display panel according to an embodiment;

[0066] Figure 2 Schematic diagram of a plan view of an electrostatic protection circuit, a data line and a chip pad according to an embodiment;

[0067] Figure 3 A schematic plan view of an electrostatic protection circuit, a data line, a pad and a first planarization layer of a display panel according to an embodiment;

[0068] Figure 4A schematic plan view of an electrostatic protection circuit, a data line, a pad, a first planarization layer, and an ion blocking layer of a display panel according to an embodiment;

[0069] Figure 5 for Figure 4 A partial enlarged view of the structure in the dotted frame of the display panel of the embodiment;

[0070] Figure 6 for Figure 3 A partial enlarged view of the structure in the dotted frame of the display panel of the embodiment;

[0071] Figure 7 is a second cross-sectional schematic diagram of a display panel according to an embodiment;

[0072] Figure 8 is a flow chart of a method for manufacturing a display panel according to an embodiment;

[0073] Fig. 9 is a schematic cross-sectional view of a display panel after step S706 in one embodiment;

[0074] Fig.10 is a schematic cross-sectional view of a display panel after step S708 in one embodiment;

[0075] Fig.11 is a schematic cross-sectional view of a display panel after forming a second planarization layer according to an embodiment;

[0076] Fig.12 is a schematic plan view of a display panel after forming a second planarization layer according to an embodiment;

[0077] Fig.13 FIG. 4 is a schematic structural diagram of a display device according to an embodiment.

[0078] Component number description:

[0079] Display panel: 10; display area: 10a; non-display area: 10b; substrate: 100; base: 110; first buffer layer: 120; second buffer layer: 130; drive circuit layer: 200; active layer: 2001; first insulating layer: 2002; first metal layer: 2003; second insulating layer: 2004; second metal layer: 2005; third insulating layer: 2006; third metal layer: 2007; fourth insulating layer: 2008; fourth metal layer: 2009; data line: 201; power supply voltage line: 202; electrostatic Protection circuit: 210; ion blocking layer: 220; first planarization layer: 230; first flat portion: 2301; second flat portion: 2302; gap: 2303; first via hole: 2304; second via hole: 2305; third via hole: 2306; second planarization layer: 240; light-emitting device layer: 300; first electrode layer: 310; light-emitting material layer: 320; pixel definition layer: 330; UV adhesive layer: 400; device packaging layer: 500; polarizing layer: 600; optical adhesive layer: 700; chip pad: 800. DETAILED DESCRIPTION

[0080] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0081] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0082] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0083] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present application.

[0084] Furthermore, in the specification, the phrase “planar distribution schematic diagram” refers to a drawing when a target portion is viewed from above, and the phrase “cross-sectional schematic diagram” refers to a drawing when a section taken by vertically cutting the target portion is viewed from the side.

[0085] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0086] In the related art, electrostatic discharge (ESD) problems are usually caused by the inability to eliminate static electricity accumulation. Electrostatic discharge can cause damage to components in the display panel 10 and affect the performance of the product. Therefore, it is necessary to set an electrostatic protection circuit 210 on the display panel 10 to release the electrostatic charge on the source line. However, the wiring in the electrostatic protection circuit 210 may fail, thereby affecting the display effect and product life. After research, the inventor found that in the high temperature and high humidity experiment, the potassium ions in the polarizer diffused to the electrostatic protection circuit 210 with the help of water, and produced an electrolytic reaction with the structure in the electrostatic protection circuit 210, thereby corroding the wiring located in the first metal layer 2003 and the second metal layer 2005 in the electrostatic protection circuit 210, causing the electrostatic protection circuit 210 to fail. Furthermore, the inventor also found that the wiring of the first metal layer 2003 and the second metal layer 2005 was not completely covered at the via, causing the wiring to be exposed and corroded.

[0087] In view of the above problems, the embodiment of the present application provides a display panel 10 and a display device, by disposing an ion blocking layer 220 on the side of the array film layer away from the substrate 100, and making the orthographic projection of the ion blocking layer 220 on the substrate 100 overlap with at least part of the electrostatic protection circuit 210 on the substrate 100. In this way, the ion blocking layer 220 can block the ions in the polarizing layer 600 from migrating to the electrostatic protection circuit 210, avoiding the corrosion of the circuits in the electrostatic protection circuit 210 by the migrating ions, preventing the electrostatic protection circuit 210 from failing, thereby improving the reliability of the electrostatic protection circuit 210, and further improving the display effect and service life of the display panel 10 and the display device.

[0088] The embodiment of the present application provides a display panel 10 , which may be, but is not limited to, an organic light emitting diode display (Organic Light Emitting Diode, OLED) or a quantum dot light emitting diode display (Quantum Dot Light Emitting Diodes, QLED). Figure 1 FIG. 1 is a schematic cross-sectional view of a display panel 10 according to an embodiment of the present invention. Figure 1The display panel 10 includes a substrate 100, a driving circuit layer 200, a light emitting device layer 300 and an ion blocking layer 220. The display panel 10 can be divided into a display area 10a and a non-display area 10b which are adjacently arranged. The non-display area 10b can be arranged around the display area 10a.

[0089] The substrate 100 includes a base 110, a first buffer layer 120 and a second buffer layer 130 which are stacked in sequence. The base 110 may be a glass base 110 or a polyimide base 110, the first buffer layer 120 may be a silicon nitride layer, and the second buffer layer 130 may be a silicon oxide layer.

[0090] The driving circuit layer 200 is disposed on one side of the substrate 100. The driving circuit layer 200 includes a plurality of data lines 201 disposed in the display area 10a and a plurality of electrostatic protection circuits 210 disposed in the non-display area 10b. The plurality of electrostatic protection circuits 210 are respectively connected to the plurality of data lines 201. It should be noted that the specific structure of the electrostatic protection circuit 210 can refer to the relevant technology and is not limited here. The electrostatic protection circuit 210 of any structure can be protected by the ion blocking layer 220 of the embodiment of the present application.

[0091] The light emitting device layer 300 is disposed on a side of the driving circuit layer 200 away from the substrate and is located in the display area 10 a.

[0092] The ion blocking layer 220 is disposed on a side of the driving circuit layer 200 away from the substrate 100 and is located in the non-display area 10b. The orthographic projection of the ion blocking layer 220 on the substrate 100 overlaps with at least a portion of the orthographic projection of the electrostatic protection circuit 210 on the substrate 100. Further, the orthographic projection of the electrostatic protection circuit 210 on the substrate 100 is located within the orthographic projection of the ion blocking layer 220 on the substrate 100.

[0093] Specifically, the material of the ion blocking layer 220 includes a conductive material. The ions blocked by the ion blocking layer 220 may be potassium ions, for example, potassium ions from the polarizing layer 600. In the process of the ions in the polarizing layer 600 migrating toward the electrostatic protection circuit 210, they may migrate in an ionic state or in combination with other substances. Exemplarily, the potassium ions in the polarizing layer 600 may combine with water and migrate toward the electrostatic protection circuit 210 with the help of water.

[0094] In the embodiment of the application, by overlapping the orthographic projection of the ion blocking layer 220 on the substrate 100 with at least part of the orthographic projection of the electrostatic protection circuit 210 on the substrate 100, the migration path of ions to the electrostatic protection circuit 210 can be blocked to a large extent, thereby suppressing the electrolytic reaction occurring at the electrostatic protection circuit 210, thereby avoiding corrosion of the electrostatic protection circuit 210 by the electrolytic reaction, reducing the failure risk of the electrostatic protection circuit 210, and improving the display effect and service life of the display panel 10 and the display device.

[0095] In one embodiment, the display panel 10 further includes a first planarization layer 230, which is disposed between the driving circuit layer 200 and the ion blocking layer 220 and covers at least a portion of the electrostatic protection circuit 210. Further, the first planarization layer 230 completely covers the electrostatic protection circuit 210. In the embodiment of the application, by providing the first planarization layer 230, subsequent film layers can be prepared on a relatively flat interface, thereby improving the preparation quality of subsequent film layers.

[0096] In one embodiment, the driving circuit layer 200 further includes a plurality of pixel driving circuits disposed in the display area 10 a , and the pixel driving circuits are connected to the data lines 201 . Figure 2 FIG. 2 is a schematic plan view of an electrostatic protection circuit 210, a data line 201 and a chip pad 800 according to an embodiment of the present invention. Figure 2 The display panel 10 further includes a chip pad 800. The chip pad 800 is used to connect the display driver chip. The chip pad 800 is located on a side of the multiple electrostatic protection circuits 210 away from the display area 10a and is connected to the electrostatic protection circuit 210. The electrostatic protection circuit 210 is used to release the charge on the data line 201 through the electrostatic release line 2103 under the control of the display driver chip.

[0097] Figure 3 FIG. 2 is a schematic plan view of an electrostatic protection circuit 210, a data line 201, a chip pad 800 and a first planarization layer 230 of a display panel 10 according to an embodiment of the present invention. Figure 1 and Figure 3 , the first planarization layer 230 includes a covering pixel driving circuit ( Figure 3 The first flat portion 2301 (not shown) and the second flat portion 2302 covering the electrostatic protection circuit 210. There is a gap 2303 between the first flat portion 2301 and the second flat portion 2302, and the ion blocking layer 220 covers at least a portion of the top surface of the second flat portion 2302 away from the driving circuit layer 200, and the side surface of the second flat portion 2302 facing the gap 2303.

[0098] Among them, the width of the gap 2303 is 1μm to 20μm. Exemplarily, the width of the gap 2303 is 1μm, 2μm, 5μm, 10μm, 15μm, and 20μm. The orthographic projection of the gap 2303 on the substrate 100 is arranged around at least part of the periphery of the orthographic projection of the electrostatic protection circuit 210 on the substrate 100, and the ion blocking layer 220 extends into the gap 2303. In this way, on the one hand, the ion blocking layer 220 can wrap the side of the film layer in the area where the electrostatic protection circuit 210 is located to prevent the migration of ions from the lateral invasion of the electrostatic protection circuit 210; on the other hand, by setting the gap 2303, the contact area between the ion blocking layer 220 and the first planarization layer 230 can be increased, thereby improving the connection stability between the two and reducing the risk of film peeling.

[0099] In one embodiment, continue to refer to Figure 3 The gap 2303 is a circumferentially closed structure surrounding the multiple electrostatic protection circuits 210, that is, the orthographic projection of the gap 2303 on the substrate 100 surrounds the entire periphery of the orthographic projection of the electrostatic protection circuit 210 on the substrate 100. In the embodiment of the application, the ion blocking layer 220 can fully isolate the ion migration path of the electrostatic protection circuit 210, thereby minimizing the invasion of ions from all around the electrostatic protection circuit 210.

[0100] Exemplarily, the orthographic projection of the gap 2303 on the substrate 100 is annular. It should be noted that the gap 2303 may also include a plurality of slot segments, which are arranged around the electrostatic protection circuit 210, and two adjacent slot segments are spaced apart.

[0101] Optionally, the gap 2303 penetrates the first planarization layer 230 along the thickness direction of the substrate 100. In this way, the ion blocking layer 220 can completely wrap the first planarization layer 230 above the electrostatic protection circuit 210, thereby preventing the migration of ions along the first planarization layer 230 to the electrostatic protection circuit 210, and making the ion blocking layer 220 have a better blocking effect.

[0102] It is understandable that the gap 2303 may not penetrate the first planarization layer 230. The specific configuration of the gap 2303 is not particularly limited in the embodiment of the present application.

[0103] Figure 4 FIG. 2 is a schematic plan view of an electrostatic protection circuit 210 , a data line 201 , a chip pad 800 , a first planarization layer 230 , and an ion blocking layer 220 of a display panel 10 according to an embodiment of the present invention. Figure 5 for Figure 4 The partially enlarged view of the structure in the dashed frame of the display panel 10 of the embodiment, refer to Figure 5, the edge of the ion blocking layer 220 is spaced from the first flat portion 2301. The distance L between the edge of the ion blocking layer 220 and the first flat portion 2301 is 1 μm to 9 μm. It should be noted that the distance L between the edge of the ion blocking layer 220 and the first flat portion 2301 can be understood as the distance between the edge of the orthographic projection of the ion blocking layer 220 on the substrate 100 and the edge of the orthographic projection of the first flat portion 2301 on the substrate 100. Exemplarily, the distance L can be 1 μm, 3 μm, 5 μm, 7 μm, or 9 μm. In the embodiment of the application, through the above-mentioned size setting method, a certain process margin can be reserved to meet the deviation of the manufacturing process while ensuring that the ion blocking layer 220 completely covers the second flat portion 2302.

[0104] In one embodiment, continue to refer to Figure 1 The driving circuit layer 200 includes an active layer 2001, a first insulating layer 2002, a first metal layer 2003, a second insulating layer 2004, a second metal layer 2005, a third insulating layer 2006, a third metal layer 2007, a fourth insulating layer 2008 and a fourth metal layer 2009, which are stacked. The data line 201 is arranged in the first metal layer 2003 or the second metal layer 2005, and is connected to one end of the electrostatic protection circuit 210 arranged in the third metal layer 2007 through a via structure penetrating the second insulating layer 2004 and / or the third insulating layer 2006. By setting the via structure, the data line 201 can be connected to the electrostatic protection circuit 210, so as to realize the release of static electricity on the data line 201.

[0105] Specifically, the second insulating layer 2004 and the third insulating layer 2006 are provided with a first via hole 2304 penetrating to the first metal layer 2003, the data line 201 is connected to the electrostatic protection circuit 210 via the first via hole 2304, and the material of the third metal layer 2007 is filled in the first via hole 2304, and completely covers the top surface of the first metal layer 2003 exposed to the first planarization layer 230. The third insulating layer 2006 is provided with a second via hole 2305 penetrating to the second metal layer 2005, the data line 201 is connected to the electrostatic protection circuit 210 via the second via hole 2305, and the material of the third metal layer 2007 is filled in the second via hole 2305, and completely covers the top surface of the second metal layer 2005 exposed to the first planarization layer 230. In the embodiment of the application, the first via hole 2304 and the second via hole 2305 are filled with the material of the third metal layer 2007, which can effectively block the first metal layer 2003, the second metal layer 2005 and the first planarization layer 230, so that the electrolytic reaction cannot be generated at the electrostatic protection circuit 210, thereby avoiding corrosion of the electrostatic protection circuit 210 caused by the electrolytic reaction. It can be understood that if all data lines 201 are provided in the same metal layer, only one of the first via hole 2304 and the second via hole 2305 can also be provided, which is not limited here.

[0106] The ion blocking layer 220 can be provided in the same layer and the same material as the fourth metal layer 2009, and the ion blocking layer 220 and the fourth metal layer 2009 can be made in the same manufacturing process to reduce the process flow. Exemplarily, the material of the ion blocking layer 220 can include at least one of a metal and a metal oxide, for example, the ion blocking layer 220 can include Ti / Al / Ti. Among them, the thickness of the first layer of Ti can be 500 angstroms to 1000 angstroms, the thickness of the Al layer can be 5000 angstroms to 10000 angstroms, and the thickness of the second layer of Ti can be 300 angstroms to 8000 angstroms. For example, the thickness of the first layer of Ti is 750 angstroms, the thickness of the Al layer is 7000 angstroms, and the thickness of the second layer of Ti can be 500 angstroms. The above-mentioned stacked arrangement method can make the ion blocking layer 220 have an extremely tight atomic arrangement, so as to have better blocking performance.

[0107] Continue to refer Figures 1 to 4 In one embodiment, the display panel 10 further includes a power supply voltage line 202. The power supply voltage line 202 is connected to the pixel driving circuit, and the power supply voltage line 202 is also connected to the ion blocking layer 220. The power supply voltage line 202 may be an ELVDD signal line. In the embodiment of the application, the ion blocking layer 220 may be connected to the power supply voltage, and the ion blocking layer 220 may shield the electrostatic protection circuit 210, thereby shielding the interference of the external electric field on the electrostatic protection circuit 210.

[0108] In one embodiment, the power supply voltage line 202 is at least partially disposed in the gap 2303 between the first flat portion 2301 and the second flat portion 2302. Specifically, the power supply voltage line 202 is disposed in the third metal layer 2007, and the ion blocking layer 220 covers at least a portion of the top surface of the power supply voltage line 202 away from the third insulating layer 2006. In the embodiment of the application, the power supply voltage line 202 can be effectively disposed using the space of the gap 2303, and the ion blocking layer 220 can be formed on one side of the power supply voltage line 202 and the second flat portion 2302 in the same process flow, thereby simplifying the process flow. It is understandable that the power supply voltage line 202 can be disposed only in the gap 2303, or can be further extended to the first flat portion 2301 and / or the second flat portion 2302, which is not limited here. Figure 6 for Figure 3 The partially enlarged view of the structure in the dashed frame of the display panel 10 of the embodiment, refer to Figure 6 In one embodiment, the width W of the power supply voltage line 202 is 5 μm to 20 μm. For example, the width W may be 5 μm, 8 μm, 10 μm, 12 μm, 15 μm or 20 μm.

[0109] In one embodiment, continue to refer to Figure 6 , the first planarization layer 230 also covers at least a portion of the surface of the power supply voltage line 202 close to the ion blocking layer 220, and the first planarization layer 230 disposed on the surface of the power supply voltage line 202 is provided with a third via 2306 for exposing the power supply voltage line 202, and the ion blocking layer 220 contacts the power supply voltage line 202 through the third via 2306. The inner diameter of the third via 2306 is 1 μm to 8 μm. Exemplarily, the inner diameter of the third via 2306 can be 1 μm, 3 μm, 5 μm, or 8 μm. In the embodiment of the application, the edge of the ion blocking layer 220 can be overlapped onto the power supply voltage line 202 through the third via 2306, thereby realizing the electrical connection between the ion blocking layer 220 and the power supply voltage line 202.

[0110] Continue to refer Figure 1 In one embodiment, the chip pad 800 is disposed in the third metal layer 2007. The chip pad 800 is disposed in a metal layer relatively far from the substrate 100, so that it is easier to connect the chip pad 800 to the display driver chip. Furthermore, the ion blocking layer 220 also covers the side of the second flat portion 2302 facing the chip pad 800. In the embodiment of the application, the ion blocking layer 220 can inhibit the migration of ions from invading the electrostatic protection circuit 210 through the side of the second flat portion 2302, and can increase the contact area between the ion blocking layer 220 and the second flat portion 2302, thereby improving the connection stability between the two.

[0111] In one embodiment, the display panel 10 further includes a second planarization layer 240. At least a portion of the second planarization layer 240 is disposed on a side of the ion blocking layer 220 away from the substrate 100. In the embodiment of the application, the second planarization layer 240 can protect the ion blocking layer 220, prevent the ion blocking layer 220 from being damaged by the anode etchant, and thus prevent the blocking performance of the ion blocking layer 220 from being reduced.

[0112] Further, the orthographic projection of the second planarization layer 240 on the substrate 100 overlaps with the orthographic projection of the ion blocking layer 220 on the substrate 100, and extends into the gap 2303. Further, the orthographic projection of the ion blocking layer 220 on the substrate 100 is located within the orthographic projection of the second planarization layer 240 on the substrate 100, so that the ion blocking layer 220 can be protected to the greatest extent, and the contact area between the second planarization layer 240 and other film layers can be increased, thereby improving the connection stability of the second planarization layer 240. The orthographic projection of the second planarization layer 240 on the substrate 100 overlaps at least partially with the orthographic projection of the gap 2303 on the substrate 100. Further, the orthographic projection of the gap 2303 on the substrate 100 is located within the orthographic projection of the second planarization layer 240 on the substrate 100. In this way, the contact area between the second planarization layer 240 and other film layers can be increased, thereby improving the connection stability of the second planarization layer 240 and reducing the risk of film layer peeling.

[0113] In one embodiment, the second planarization layer 240 is made of the same material as the first planarization layer 230. The thickness of the second planarization layer 240 is 0.5 μm to 2 μm. For example, the thickness of the second planarization layer 240 is 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, or 2 μm.

[0114] Figure 7 FIG. 2 is a second cross-sectional schematic diagram of a display panel 10 according to an embodiment. Figure 7 In one embodiment, the light emitting device layer 300 includes a first electrode layer 310, a light emitting material layer 320, and a second electrode layer (not shown) stacked in a direction away from the substrate 100, and the display panel 10 also includes a pixel definition layer 330 disposed on the side of the driving circuit layer 200 close to the light emitting device layer 300, and the pixel definition layer 330 surrounds and forms a plurality of pixel openings. The ion blocking layer 220 and the first electrode layer 310 are provided in the same layer and with the same material. In this way, the ion blocking layer 220 and the first electrode layer 310 can be manufactured in the same manufacturing process, which is conducive to reducing the manufacturing difficulty and manufacturing cost.

[0115] In one embodiment, the second planarization layer 240 is formed of the same material as the pixel definition layer 330. Thus, the pixel definition layer 330 and the second planarization layer 240 can be manufactured in the same process, which is beneficial to reducing the number of manufacturing processes and thus reducing the manufacturing difficulty.

[0116] In one embodiment, the material of the ion blocking layer 220 includes a conductive material. Exemplarily, the material of the ion blocking layer 220 may include at least one of a metal and a metal oxide, for example, the material of the ion blocking layer 220 includes at least one of silver and indium tin oxide. Exemplarily, the ion blocking layer 220 may be ITO / Ag / ITO. In this way, the ion blocking layer 220 may have an extremely tight atomic arrangement, thereby having a good blocking performance. Optionally, the thickness of the ITO layer is between 50 angstroms and 150 angstroms, and the thickness of the Ag layer is between 500 angstroms and 1500 angstroms. Exemplarily, the thickness of the ITO layer is 50 angstroms, 80 angstroms, 100 angstroms, 120 angstroms, 150 angstroms, etc. The thickness of the Ag layer is 500 angstroms, 700 angstroms, 900 angstroms, 1000 angstroms, 1200 angstroms, 1500 angstroms, etc.

[0117] Continue to refer Figure 1 and Figure 7 In one embodiment, the display panel 10 further includes a polarizing layer 600 and a UV adhesive layer 400. The polarizing layer 600 is disposed on a side of the light-emitting device layer 300 away from the substrate 100, and the ion blocking layer 220 is used to block ions from the polarizing layer 600. The UV adhesive layer 400 is disposed on a side of the ion blocking layer 220 away from the electrostatic protection circuit 210, and is spaced apart from the polarizing layer 600 to protect the driving circuit layer 200 of the non-display area 10b. It should be noted that the UV adhesive layer 400 is easy to provide a migration path. Therefore, by means of the UV adhesive layer 400 and the polarizing layer 600 that are spaced apart, it is possible to effectively prevent ions from migrating to the electrostatic protection circuit 210 through the path of the UV adhesive layer 400, thereby increasing the difficulty of potassium ions migrating, thereby facilitating the prevention of failure of the electrostatic protection circuit 210.

[0118] In one embodiment, the display panel 10 further includes a device encapsulation layer 500, which is disposed on a side of the light-emitting device layer 300 away from the substrate 100. The device encapsulation layer 500 includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer that are stacked. Among them, the inorganic encapsulation layer can minimize or completely prevent the penetration of moisture, oxygen, and / or hydrogen into the driving circuit layer 200 and the light-emitting element. Therefore, the outermost inorganic encapsulation layer can completely cover the organic encapsulation layer, thereby forming a barrier space that can block the entry of water and oxygen. Among them, the material of the inorganic encapsulation layer includes at least one of SiON and SiNx. Further, the inorganic encapsulation layer includes 0.5μm to 1.5μm SiON and 0.5μm to 1.5μm SiNx, for example, 0.5μm SiON and 0.5μm SiNx, or 1μm SiON and 1μm SiNx, or 1.5μm SiON and 1.5μm SiNx.

[0119] In one of the embodiments, the device encapsulation layer 500 is disposed between the light-emitting device layer 300 and the polarizing layer 600, and covers the side of the light-emitting device layer 300 facing the UV adhesive layer 400. In the embodiment of the application, the inorganic encapsulation layer has a good ion barrier effect, so it can greatly reduce the potassium ions migrating from the polarizing layer 600 to the electrostatic protection circuit 210. Optionally, the orthographic projection of the device encapsulation layer 500 on the substrate 100 covers at least part of the electrostatic protection circuit 210. In this way, the device encapsulation layer 500 can also prevent the potassium ions in the polarizing layer 600 from migrating to the electrostatic protection circuit 210.

[0120] In one embodiment, the display panel 10 further includes an optical adhesive layer 700. The optical adhesive layer 700 is disposed between the device packaging layer 500 and the polarizing layer 600, and the optical adhesive layer 700 is spaced apart from the UV adhesive layer 400.

[0121] The present application provides a method for manufacturing a display panel 10. Figure 8 is a flow chart of a method for manufacturing a display panel 10 according to an embodiment, referring to Figure 8 , the manufacturing method of the display panel 10 includes steps S702 to S708.

[0122] Step S702 , providing a substrate 100 .

[0123] Step S704 , forming a driving circuit layer 200 on the surface of the substrate 100 .

[0124] refer to Figure 2 The driving circuit layer 200 includes a plurality of data lines 201 disposed in the display area 10a and a plurality of electrostatic protection circuits 210 disposed in the non-display area 10b. The plurality of electrostatic protection circuits 210 are respectively connected to the plurality of data lines 201.

[0125] In step S706 , a first planarization layer 230 is formed on the surface of the driving circuit layer 200 to cover the electrostatic protection circuit 210 .

[0126] Fig. 9 FIG. 1 is a schematic cross-sectional view of the display panel 10 after step S706 of an embodiment, with reference to FIG. Figure 3 and Fig. 9 , the first planarization layer 230 may be divided into a first planar portion 2301 and a second planar portion 2302 by a gap 2303 .

[0127] Step S708 , forming an ion blocking layer 220 on the surface of the first planarization layer 230 .

[0128] Fig.10 FIG. 1 is a schematic cross-sectional view of the display panel 10 after step S708 of an embodiment, with reference to FIG. Figure 4 and Fig.10 The orthographic projection of the ion blocking layer 220 on the substrate 100 covers at least a portion of the orthographic projection of the electrostatic protection circuit 210 on the substrate 100 .

[0129] In one embodiment, the method for manufacturing the display panel 10 further includes forming a second planarization layer 240 to form Fig.11 and Fig.12 The display panel 10 shown in FIG. 1 may further include a light emitting device layer 300, a device encapsulation layer 500, an optical adhesive layer 700, a polarizing layer 600, and an optical adhesive layer 400 to form a structure such as Figure 1 The display panel 10 is shown.

[0130] An embodiment of the present application further provides a display device, which includes the display panel 10 of any of the above embodiments. Fig.13 is a schematic diagram of the structure of a display device according to an embodiment, referring to Fig.13 In some embodiments, the display device may be a display terminal, such as a tablet computer. In other embodiments, the display device may be a mobile communication terminal, such as a mobile phone terminal. In other embodiments, the display device may also be a wearable device, a VR device, a vehicle-mounted device, etc.

[0131] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: include: substrate; A driving circuit layer is provided on one side of the substrate, the driving circuit layer includes a plurality of data lines provided in the display area and a plurality of electrostatic protection circuits provided in the non-display area, and the non-display area is provided around the display area; A light emitting device layer, provided on a side of the driving circuit layer away from the substrate and located in the display area; The ion blocking layer is arranged on a side of the driving circuit layer away from the substrate and located in the non-display area; and the orthographic projection of the ion blocking layer on the substrate overlaps with at least part of the orthographic projection of the electrostatic protection circuit on the substrate.

2. The display panel according to claim 1, characterized in that: The display panel further includes: A first planarization layer, disposed between the driving circuit layer and the ion blocking layer, covering at least a portion of the electrostatic protection circuit; Preferably, the first planarization layer completely covers the electrostatic protection circuit; Preferably, the driving circuit layer further comprises a plurality of pixel driving circuits arranged in the display area, and the pixel driving circuits are connected to the data lines; the first planarization layer comprises a first planar portion covering the pixel driving circuits and a second planar portion covering the electrostatic protection circuit, and a gap is provided between the first planar portion and the second planar portion, and an orthographic projection of the gap on the substrate surrounds at least a portion of the periphery of the electrostatic protection circuit; The ion blocking layer covers at least a portion of the top surface of the second flat portion on a side away from the driving circuit layer, and a side surface of the second flat portion facing the gap; Preferably, the orthographic projection of the electrostatic protection circuit on the substrate is located within the orthographic projection of the ion blocking layer on the substrate; Preferably, the width of the gap is 1 μm to 20 μm; Preferably, the gap is a circumferentially closed structure surrounding the plurality of electrostatic protection circuits; Preferably, the orthographic projection of the gap on the substrate surrounds the entire periphery of the orthographic projection of the electrostatic protection circuit on the substrate; Preferably, the gap penetrates the first planarization layer along the thickness direction of the substrate; Preferably, the edge of the ion blocking layer is spaced apart from the first flat portion; Preferably, the distance between the edge of the ion blocking layer and the first flat portion is between 1 μm and 9 μm.

3. The display panel according to claim 2, characterized in that: The driving circuit layer includes a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a third metal layer which are stacked, the data line is arranged in the first metal layer or the second metal layer, and is connected to one end of the electrostatic protection circuit arranged in the third metal layer through a via structure penetrating the second insulating layer and / or the third insulating layer; Preferably, a first via hole penetrating to the first metal layer is provided in the second insulating layer and the third insulating layer, the data line is connected to the electrostatic protection circuit through the first via hole, and the material of the third metal layer is filled in the first via hole and completely covers the top surface of the first metal layer exposed to the first planarization layer; Preferably, a second via hole penetrating through the second metal layer is provided in the third insulating layer, the data line is connected to the electrostatic protection circuit via the second via hole, and the material of the third metal layer is filled in the second via hole and completely covers the top surface of the second metal layer exposed to the first planarization layer; Preferably, the driving circuit layer further comprises a fourth insulating layer and a fourth metal layer provided on a side of the third metal layer away from the substrate, and the ion blocking layer and the fourth metal layer are provided in the same layer and with the same material; Preferably, the ion blocking layer comprises a stacked layer of Ti / Al / Ti.

4. The display panel according to claim 3, characterized in that: The display panel further includes: A power supply voltage line, the power supply voltage line is connected to the pixel driving circuit, and the power supply voltage line is also connected to the ion blocking layer; Preferably, the power supply voltage line is at least partially disposed in a gap between the first flat portion and the second flat portion; Preferably, the power supply voltage line is provided in the third metal layer, and the ion blocking layer covers at least a portion of the top surface of the power supply voltage line away from the third insulating layer; Preferably, the width of the power supply voltage line is 5 μm to 20 μm; Preferably, the first planarization layer also covers at least a portion of the surface of the power supply voltage line close to the ion blocking layer, and the first planarization layer disposed on the surface of the power supply voltage line is provided with a third via hole for exposing the power supply voltage line, and the ion blocking layer is in contact with the power supply voltage line through the third via hole; Preferably, the inner diameter of the third via hole is between 1 μm and 8 μm.

5. The display panel according to claim 3, characterized in that: The display panel further includes: A chip pad, used for connecting a display driver chip, the chip pad being located on a side of the multiple electrostatic protection circuits away from the display area and connected to the electrostatic protection circuits; Wherein, the ion blocking layer also covers the side surface of the second flat portion facing the chip pad; Preferably, the chip pad is provided on the third metal layer.

6. The display panel according to claim 2, characterized in that: The light emitting device layer comprises a first electrode layer, a light emitting material layer and a second electrode layer stacked in a direction away from the substrate; the ion blocking layer is provided in the same layer and material as the first electrode layer; Preferably, the material of the ion barrier layer includes at least one of metal and metal oxide; Preferably, the ion blocking layer comprises a stacked structure of ITO / Ag / ITO.

7. The display panel according to claim 2, characterized in that: The display panel further includes: A second planarization layer, at least a portion of the second planarization layer is disposed on a side of the ion blocking layer away from the substrate; Preferably, the orthographic projection of the second planarization layer on the substrate at least partially overlaps with the orthographic projection of the ion blocking layer on the substrate; Preferably, the orthographic projection of the ion blocking layer on the substrate is located within the orthographic projection of the second planarization layer on the substrate; Preferably, the second planarization layer also extends into the gap; Preferably, the second planarization layer is made of the same material as the first planarization layer; Preferably, the display panel further comprises a pixel definition layer provided on a side of the driving circuit layer close to the light emitting device layer, and the second planarization layer is provided in the same layer and with the same material as the pixel definition layer; Preferably, the orthographic projection of the second planarization layer on the substrate at least partially overlaps with the orthographic projection of the gap on the substrate; Preferably, the orthographic projection of the gap on the substrate is located within the orthographic projection of the second planarization layer on the substrate; Preferably, the second planarization layer has a thickness of 1.5 μm to 2 μm.

8. The display panel according to claim 2, characterized in that: The display panel further includes: A device encapsulation layer, disposed on a side of the light-emitting device layer away from the substrate; A polarizing layer, disposed on a side of the device packaging layer away from the substrate; A UV adhesive layer is arranged on a side of the ion blocking layer away from the electrostatic protection circuit and is spaced apart from the polarizing layer; Wherein, the ion blocking layer is used to block ions from the polarizing layer; Preferably, the ions from the polarizing layer are potassium ions; Preferably, the device encapsulation layer comprises a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer which are stacked; Preferably, the orthographic projection of the device packaging layer on the substrate overlaps with at least a portion of the electrostatic protection circuit; Preferably, the material of the inorganic encapsulation layer includes at least one of SiON and SiNx; Preferably, the inorganic encapsulation layer includes SiON with a thickness of 0.5 μm to 1.5 μm and SiNx with a thickness of 0.5 μm to 1.5 μm.

9. The display panel according to claim 8, characterized in that: The display panel further includes: An optical adhesive layer is provided between the device packaging layer and the polarizing layer, and the optical adhesive layer is spaced apart from the UV adhesive layer.

10. A display device, characterized in that: Comprising a display panel as described in any one of claims 1 to 9.

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