Display device

Abstract

A display device is disclosed. The display device includes a display area and a non-display area, a transistor disposed on the display area of a substrate, the transistor including a semiconductor layer, and at least one inspection pattern disposed on the non-display area of the substrate, the at least one inspection pattern including a semiconductor pattern, the at least one inspection pattern further includes a first conductive pattern and a second conductive pattern spaced apart from each other in a thickness direction with the semiconductor pattern disposed therebetween, and an inspection source electrode and an inspection drain electrode, the inspection source electrode is electrically connected to a portion of the semiconductor pattern, the inspection drain electrode is electrically connected to another portion of the semiconductor pattern, and the second conductive pattern is in electrical contact with the semiconductor pattern.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device or a light emitting display device. The light emitting display device may include an organic light emitting display device including an organic light emitting element, an inorganic light emitting display device including an inorganic light emitting element such as an inorganic semiconductor, and an ultra-small light emitting display device including an ultra-small light emitting element.

[0004] The organic light emitting element may include two opposing electrodes and a light emitting layer interposed therebetween. The light emitting layer receives electrons and holes from the two electrodes and recombines the electrons and holes to generate excitons, and the generated excitons change from an excited state to a ground state, thereby emitting light.

[0005] Organic light emitting display devices including organic light emitting elements can be lightweight and thin and have low power consumption because they do not require a light source such as a backlight, and are also attracting attention as next-generation display devices because they have high-quality characteristics such as a wide viewing angle, high brightness and contrast, and a fast response speed.

[0006] It should be understood that this background of the technology section is intended in part to provide a useful background for understanding the technology. However, this background of the technology section may also include ideas, concepts or cognitions that were not known or understood by a person skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0007] Aspects of the present disclosure provide a display device capable of managing characteristics of a thin film transistor in a display area using an inspection pattern arranged in a non-display area.

[0008] However, the aspects of the present disclosure are not limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0009] According to aspects of the present disclosure, a display device may include a display area and a non-display area, a transistor and at least one inspection pattern, the transistor being arranged on the display area of ​​a substrate, the transistor including a semiconductor layer, at least one inspection pattern being arranged on the non-display area of ​​the substrate, at least one inspection pattern including a semiconductor pattern, wherein at least one inspection pattern may also include a first conductive pattern and a second conductive pattern and an inspection source electrode and an inspection drain electrode, the first conductive pattern and the second conductive pattern being spaced apart from each other in a thickness direction when the semiconductor pattern is arranged between the first conductive pattern and the second conductive pattern, the inspection source electrode being electrically connected to a portion of the semiconductor pattern, the inspection drain electrode being electrically connected to another portion of the semiconductor pattern, and the second conductive pattern being in contact with the semiconductor pattern.

[0010] In an implementation, the display device may further include a first insulating layer and a second insulating layer disposed on the substrate and disposed between the semiconductor pattern and the first conductive pattern.

[0011] In an implementation, the semiconductor pattern may include a pattern channel region and first and second conductive regions that are spaced apart from each other with the pattern channel region disposed therebetween.

[0012] In an implementation, the first conductive pattern may overlap the pattern channel region.

[0013] In an implementation, the inspection source electrode may be electrically connected to the first conductive region, and the inspection drain electrode may be electrically connected to the second conductive region.

[0014] In an implementation, the second conductive pattern may be disposed on the semiconductor pattern and overlap the first conductive pattern.

[0015] In an implementation, the display device may further include a third insulating layer disposed between the second conductive pattern and the semiconductor pattern, wherein the second conductive pattern electrically contacts the semiconductor pattern through a first through hole penetrating the third insulating layer.

[0016] In an embodiment, the display device may further include a fourth insulating layer disposed between the inspection source and drain electrodes and the second conductive pattern, wherein the inspection source and drain electrodes are electrically connected to the semiconductor pattern through second and third through holes penetrating the fourth insulating layer, respectively.

[0017] In an embodiment, the display device may further include a fourth insulating layer disposed on the second conductive pattern, and first, second, third, and fourth inspection electrodes disposed on the fourth insulating layer and spaced apart from each other.

[0018] In an embodiment, the first inspection electrode may be electrically connected to the first conductive pattern, and the second inspection electrode may be electrically connected to the second conductive pattern.

[0019] In an embodiment, the third inspection electrode may extend from the inspection source electrode, and the fourth inspection electrode may extend from the inspection drain electrode.

[0020] In an embodiment, a semiconductor layer of the transistor in the display region and a semiconductor pattern of the at least one inspection pattern may include the same material.

[0021] In an embodiment, the semiconductor layer of the transistor in the display region and the semiconductor pattern of the at least one inspection pattern may include an oxide semiconductor.

[0022] In an implementation, the display device may further include a connection pattern disposed between the first conductive pattern and the semiconductor pattern, wherein the first conductive pattern may be electrically connected to the semiconductor pattern through the connection pattern.

[0023] According to aspects of the present disclosure, a display device may include a display area and a non-display area, a transistor and an inspection pattern, the transistor being arranged on the display area of ​​a substrate, the transistor including a semiconductor layer, the inspection pattern being arranged on the non-display area of ​​the substrate, the inspection pattern including a semiconductor pattern, wherein the inspection pattern may also include a first conductive pattern and a second conductive pattern, an inspection source electrode and an inspection drain electrode, and a connection pattern, the first conductive pattern and the second conductive pattern being spaced apart from each other in a thickness direction when the semiconductor pattern is arranged between the first conductive pattern and the second conductive pattern, the inspection source electrode being electrically connected to a portion of the semiconductor pattern, the inspection drain electrode being electrically connected to another portion of the semiconductor pattern, the connection pattern being arranged between the first conductive pattern and the semiconductor pattern, and the connection pattern being electrically contacted with the first conductive pattern and the semiconductor pattern.

[0024] In an embodiment, the semiconductor layer of the transistor in the display region and the semiconductor pattern of the inspection pattern may include an oxide semiconductor.

[0025] In an embodiment, the display device may further include a first insulating layer and a second insulating layer arranged between the semiconductor pattern and the first conductive pattern, wherein the connection pattern is arranged in a first through hole penetrating the first insulating layer and the second insulating layer, and the first through hole overlaps the first conductive pattern and the semiconductor pattern.

[0026] In an embodiment, the semiconductor pattern may include a pattern channel region and first and second conductive regions spaced apart from each other with the pattern channel region disposed therebetween, and the connection pattern contacts the pattern channel region.

[0027] In an implementation, the first conductive pattern, the second conductive pattern, and the connecting pattern may overlap a pattern channel region of the semiconductor pattern.

[0028] In an implementation, the display device may further include a third insulating layer disposed between the semiconductor pattern and the second conductive pattern, wherein the second conductive pattern is spaced apart from the semiconductor pattern.

[0029] The display device according to the embodiment can infer the hydrogen content of the semiconductor layer of the pixel transistor in the display area by forming an inspection pattern including a semiconductor pattern in the non-display area and measuring the capacitance of the semiconductor pattern. Therefore, by monitoring the characteristics of the pixel transistor of the display device, the quality of the display device can be improved.

[0030] However, the effects of the embodiments are not limited to those set forth herein. The above and other effects of the embodiments will become more apparent to those skilled in the art by referring to the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 is a schematic plan view showing a display device according to an embodiment;

[0033] Figure 2 It is shown Figure 1 A schematic plan view of a display panel;

[0034] Figure 3 is a schematic diagram showing an equivalent circuit of a pixel according to an embodiment;

[0035] Figure 4 is a schematic diagram showing an equivalent circuit of a pixel according to an embodiment;

[0036] Figure 5 is a schematic cross-sectional view showing a display panel according to an embodiment;

[0037] Figure 6 is a schematic plan view showing an inspection pattern according to an embodiment;

[0038] Figure 7 is along Figure 6 A schematic cross-sectional view taken along line Q1-Q1';

[0039] Figure 8 is a graph showing changes in characteristics of a transistor depending on the hydrogen content of a semiconductor layer;

[0040] Fig. 9 is a graph showing changes in characteristics of a transistor having a semiconductor layer not containing hydrogen;

[0041] Fig.10is a graph showing changes in characteristics of a transistor having a semiconductor layer containing hydrogen;

[0042] Fig.11 is a graph showing capacitance of a semiconductor pattern according to frequency;

[0043] Fig.12 is a schematic cross-sectional view showing an inspection pattern of a display device according to an embodiment;

[0044] Fig.13 is a schematic cross-sectional view showing an inspection pattern of a display device according to an embodiment; and

[0045] Fig.14 is a schematic plan view showing a display panel according to an embodiment. DETAILED DESCRIPTION

[0046] Now, the present disclosure will be described more fully below with reference to the accompanying drawings in which embodiments are shown. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0047] In the drawings, the size, thickness, ratio, and dimensions of elements may be exaggerated for convenience of description and for clarity. Like reference numerals refer to like elements throughout.

[0048] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0049] For the purpose of its meaning and interpretation, in the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in conjunction or disjunction and may be understood to be equivalent to "and / or".

[0050] For the purpose of its meaning and interpretation, in the specification and claims, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of". For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0051] It will also be understood that when a layer is referred to as being 'on' another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like components throughout the specification.

[0052] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0053] The term "overlap" or "overlapping" means that a first object may be located above or below or to the side of a second object, and vice versa. In addition, the term "overlap" may include stacking, stacking, facing or facing, extending over, covering or partially covering, or any other suitable term that will be appreciated and understood by a person of ordinary skill in the art.

[0054] The terms "facing" and "facing" mean that the first element can be directly or indirectly opposite to the second element. In the case where a third element is between the first element and the second element, although still facing each other, the first element and the second element can be understood as being indirectly opposite to each other.

[0055] When an element is described as “not overlapping” or “will not overlap” another element, this may include the elements being spaced apart, offset or staggered from each other, or any other suitable terminology as would be appreciated and understood by one of ordinary skill in the art.

[0056] The terms "comprises", "including", "includes" and / or "comprising", "having", "with" and / or "having" and variations thereof when used in this specification specify the presence of stated features, integers, steps, operations, elements, parts and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups thereof.

[0057] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account errors associated with the measurements and with the measurement of a particular quantity (e.g., limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0058] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly rigid sense unless explicitly defined as such herein.

[0059] It should be understood that when an element (or region, layer, part, etc.) is referred to in the specification as being "on", "connected to" or "coupled to" another element, it can be directly arranged on the other element mentioned above, directly connected to or coupled to the other element mentioned above, or intervening elements may be arranged therebetween.

[0060] It should be understood that the term "connected to" or "coupled to" may include physical or electrical connections or couplings.

[0061] Each of the features of the various embodiments of the present disclosure may be combined or combined with each other in part or in whole. Each embodiment may be implemented independently of each other, or may be implemented together.

[0062] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0063] Figure 1 is a schematic plan view showing a display device 10 according to an embodiment. Figure 2 It is shown Figure 1 Schematic plan view of the display panel 110.

[0064] Reference Figure 1 and Figure 2 The display device 10 is a device that displays a moving image or a still image, and can be used as a display screen of each of various products such as televisions, notebook computers, monitors, billboards, and Internet of Things (IOT) devices, and portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notepads, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs). These are examples, and the display device 10 can also be employed in other electronic devices.

[0065] In an embodiment, the display device 10 may be a light-emitting display device, such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro or nano light-emitting display device using a micro or nano light-emitting diode (LED), but is not limited thereto. For example, the display device 10 may be a type of display device other than a light-emitting display device. Hereinafter, an embodiment in which the display device 10 is an organic light-emitting display device will be disclosed.

[0066] The display device 10 may include a display panel 110 including pixels PX, and a first driver 120 and a second driver 130 for supplying a driving signal to the pixels PX. The display device 10 may also include additional components. For example, the display device 10 may also include a power supply unit (power supplier) for supplying a power supply voltage to the pixels PX, the first driver 120 and the second driver 130, a timing control unit (timing controller) for controlling the operation of the first driver 120 and the second driver 130, and the like.

[0067] The display panel 110 may include a display area DA and a non-display area NDA. The display area DA may be an area that may include pixels PX and display an image. The non-display area NDA is a remaining area other than the display area DA, and an image may not be displayed in the non-display area NDA. In an embodiment, the non-display area NDA may be positioned around the display area DA and surround the display area DA.

[0068] exist Figure 1 and Figure 2 In the embodiment, a first direction DR1, a second direction DR2, and a third direction DR3 may be defined. In an embodiment, the first direction DR1 and the second direction DR2 may be perpendicular to each other, the first direction DR1 and the third direction DR3 may be perpendicular to each other, and the second direction DR2 and the third direction DR3 may be perpendicular to each other. For example, the first direction DR1 may be a horizontal direction of the display panel 110, and the second direction DR2 may be a vertical direction of the display panel 110. The third direction DR3 may be a thickness direction of the display panel 110.

[0069] In an embodiment, the display panel 110 may have a rectangular shape in a plan view. For example, the display panel 110 may include two first sides extending in a first direction DR1 and two second sides extending in a second direction DR2 intersecting the first direction DR1. Figure 1 and Figure 2The display panel 110 is shown in which the first side in the horizontal direction is longer than the second side in the vertical direction, but the shape of the display panel 110 is not limited thereto. For example, the display panel 110 may also have a shape in which the second side in the vertical direction is longer than the first side in the horizontal direction, or a shape in which the first side and the second side have substantially the same length.

[0070] In an embodiment, the display panel 110 may include an angled corner at a portion where the first side and the second side intersect, but is not limited thereto. For example, the display panel 110 may also include a rounded corner at a portion where the first side and the second side intersect.

[0071] The planar shape of the display panel 110 is not limited to the rectangular shape shown, but other shapes may also be applied. For example, the display panel 110 may have a square shape, other polygonal shapes other than quadrilaterals, a circular shape, an elliptical shape, an irregular shape, or other shapes in a plan view.

[0072] In an embodiment, the display panel 110 may be substantially flat on a plane defined by the first and second directions DR1 and DR2, and may have a uniform thickness in the third direction DR3. In an embodiment, the display panel 110 may also be provided in a three-dimensional shape having a bent surface, etc.

[0073] The display panel 110 may be provided as a panel having rigid characteristics so as not to be substantially deformed, or may be provided as a flexible panel that is deformably formed into a shape such as being folded, bent, or rolled at at least one portion. The display panel 110 may be provided to the display device 10 in an unbent state, or may be provided in a bent state in some sections.

[0074] The display panel 110 may include a substrate SUB and pixels PX arranged on the substrate SUB. The pixels PX may be arranged in a display area DA on the substrate SUB.

[0075] The substrate SUB is a base member for manufacturing or providing the display panel 110, and may form a base surface of the display panel 110. The substrate SUB may include a display area DA and a non-display area NDA positioned around the display area DA.

[0076] The display area DA may have various shapes depending on the embodiment. For example, the display area DA may have a square shape, other polygonal shapes other than quadrilaterals, a circular shape, an elliptical shape, an irregular shape, or other shapes. In an embodiment, the display area DA may have a shape matching the shape of the display panel 110, but is not limited thereto.

[0077] The display area DA may include a pixel area in which pixels PX are provided and / or arranged. For example, each pixel PX may be arranged in each pixel area located in the display area DA. In an embodiment, the display device 10 may be a light-emitting display device, and each pixel PX may include a light-emitting element located in each light-emitting area and a pixel circuit connected to the light-emitting element. When describing an embodiment, "connection" may include electrical connection and / or physical connection.

[0078] In each pixel region, a light emitting element of a corresponding pixel is positioned, and each pixel region may include a light emitting region in which the pixel emits light and a pixel circuit region in which circuit elements constituting a pixel circuit of the corresponding pixel are positioned. In an embodiment, the light emitting region and the pixel circuit region of each pixel PX may overlap each other, but are not limited thereto.

[0079] The pixels PX may be arranged (or disposed) in the display area DA. For example, the pixels PX may be arranged in a stripe structure, a triangle structure, structure or other arrangement structure.

[0080] The non-display area NDA may include a driving circuit area positioned on at least one side of the display area DA and a pad area PA in which pads PD are arranged. At least one driver, pads PD and / or wires may be arranged in the non-display area NDA.

[0081] At least one driver or a portion of the driver for driving the pixel PX may be arranged in the driving circuit region. As an example, the circuit elements constituting the first driver 120 may be arranged in the driving circuit region on the substrate SUB. In an embodiment, the circuit elements of the first driver 120 may be formed in the display panel 110 together with the pixel PX.

[0082] The pad PD may be arranged in the pad area PA. At least one circuit board 140 may be arranged and / or bonded to the pad area PA. In an embodiment, a plurality of circuit boards 140 connected to different pads PD may be arranged on the pad area PA. The pad PD may include a signal pad and a power pad for transmitting a driving signal and a power supply voltage for driving the pixel PX and / or the first driver 120 to the inside of the display panel 110.

[0083] The first driver 120 and the second driver 130 may generate a driving signal for controlling the operation timing and brightness of the pixel PX, and supply the driving signal to the pixel PX. For example, the first driver 120 may be a gate driver including a scan driver, and may be connected to the pixel PX through a corresponding gate line. The first driver 120 may generate a corresponding gate signal (for example, a gate driver including a gate driver for controlling the operation timing of the pixel PX) and a gate driver for controlling the brightness of the pixel PX. Figure 3The second driver 130 may be a data driver including a source driver circuit and may be connected to the pixel PX through a corresponding data line. The second driver 130 may supply a corresponding data signal to the pixel PX.

[0084] In an implementation, at least one of the first driver 120 and the second driver 130 or a portion of at least one driver may be built in the display panel 110. For example, the first driver 120 or a portion of the first driver 120 may be disposed on a substrate SUB of the display panel 110 and may be disposed and / or formed in the non-display area NDA.

[0085] exist Figure 1 , it is shown that the first driver 120 is formed on one side of the display area DA (e.g., the non-display area NDA located on the right side of the display area DA), but the embodiment is not limited thereto. For example, the first driver 120 may be positioned only on the other side of the display area DA (e.g., the non-display area NDA located on the left side of the display area DA), or may be positioned on both sides of the display area DA (e.g., the non-display area NDA located on the left and right sides of the display area DA). By way of example, a portion of the first driver 120 (e.g., some of the circuit elements constituting the first driver 120) may be positioned in the non-display area NDA, and another portion of the first driver 120 (e.g., the remaining circuit elements of the circuit elements constituting the first driver 120) may be positioned in a non-luminescent area (e.g., an area between luminescent areas of the pixels PX) in the display area DA.

[0086] In an embodiment, the other of the first driver 120 and the second driver 130 or a portion of the other driver may be arranged or formed outside the display panel 110, and may be electrically connected to the display panel 110. For example, the second driver 130 or a portion of the second driver 130 may be implemented with a plurality of integrated circuit chips, and may be arranged on a circuit board 140 electrically connected to the pixel PX of the display panel 110. In an embodiment, the second driver 130 may be integrated into an integrated circuit chip separated from the timing control unit, or may be integrated into each integrated circuit chip together with the timing control unit. The second driver 130 may be implemented with at least one integrated circuit chip, and may be mounted on the non-display area NDA of the display panel 110.

[0087] The circuit board 140 may be connected to the display panel 110 through the pad PD. In an embodiment, the circuit board 140 may be a flexible printed circuit board (FPCB), a rigid printed circuit board (PCB), or a flexible film such as a chip on film (COF), but is not limited thereto. In an embodiment, the circuit board 140 may be connected to the timing control unit and / or the power supply unit through another circuit board or a connector.

[0088] In an embodiment, an inspection pattern TAG may be arranged in the non-display area NDA. The inspection pattern TAG is used to inspect the characteristics of the thin film transistor, and the inspection may be performed by connecting a measuring device to the inspection pattern TAG. Therefore, the hydrogen content of the thin film transistor, etc. may be inferred by inspecting the characteristics of the thin film transistor from the inspection pattern TAG. Through this, the quality of the display device 10 may be improved through process evaluation and compensation.

[0089] At least one inspection pattern TAG may be arranged in the non-display area NDA. For example, the inspection pattern TAG may be arranged in a space between the first driver 120 and the pad area PA. In an embodiment, a plurality of inspection patterns TAG may also be arranged.

[0090] The inspection pattern TAG may be used to infer the characteristics of the thin film transistor in the display area DA, for example, the hydrogen content of the semiconductor layer. Since the inspection pattern TAG is arranged in the non-display area NDA, the inspection pattern TAG remains even after the display device 10 is completed. Therefore, the thin film transistor may be evaluated not only during the manufacturing process of the display device 10 but also after the display device 10 is completed, and the quality of the display device 10 may be improved by compensation accordingly. The inspection pattern TAG will be described in detail later.

[0091] Figure 3 is a schematic diagram showing an equivalent circuit of a pixel PX according to an embodiment. Figure 3 The pixel PX in FIG. 1 is an example, and the structure or type of the pixel PX may vary according to embodiments.

[0092] Apart from Figure 1 and Figure 2 In addition, refer to Figure 3 , the pixel PX may include a light emitting element ED and a pixel circuit PC connected to the light emitting element ED. The light emitting element ED is the light source of the pixel PX and may be, for example, an organic light emitting diode, but is not limited thereto. The pixel circuit PC may control the light emission timing and brightness of the light emitting element ED.

[0093] The pixel circuit PC may include a pixel transistor TRS and at least one pixel capacitor CST. For example, the pixel circuit PC may include first to fifth transistors T1 to T5 and first and second capacitors C1 and C2. The structure of the pixel circuit PC or the types of circuit elements constituting the pixel circuit PC may be variously changed according to the embodiment. Figure 3 An embodiment in which the pixel transistor TRS is an N-type transistor is shown, but the type of the pixel transistor TRS is not limited thereto. For example, at least one pixel transistor TRS may also be formed as a P-type transistor.

[0094] The pixel circuit PC may supply the driving current Id to the light emitting element ED in response to the driving signals supplied from the first driver 120 and the second driver 130. For example, the pixel circuit PC may supply the driving current Id to the light emitting element ED in response to each gate signal GS supplied from the first driver 120 through each gate line GL and the data signal DATA supplied from the second driver 130 through the data line DL.

[0095] The second transistor T2 may be a driving transistor in which the size of its drain-source current (e.g., driving current Id) in the pixel PX is determined according to the gate-source voltage. The first transistor T1, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be switching transistors that are turned on or off according to the corresponding gate-source voltage (substantially the corresponding gate voltage). Depending on the type (e.g., P-type or N-type transistor) and / or operating conditions of each of the first transistor T1 to the fifth transistor T5, the first electrode of each of the first transistor T1 to the fifth transistor T5 may be a drain electrode (or drain region) or a source electrode (or source region), and its second electrode may be an electrode different from the first electrode. For example, in the case where the first electrode is a drain electrode, the second electrode may be a source electrode.

[0096] The pixel PX may be connected to a first gate line GWL transmitting a first gate signal GW (e.g., a scan signal), a second gate line GIL transmitting a second gate signal GI, a third gate line GRL transmitting a third gate signal GR, an emission control line ECL transmitting an emission control signal EM, and a data line DL transmitting a data signal DATA. The pixel PX may be connected to a first pixel power line VDL transmitting a first pixel voltage ELVDD (also referred to as a “first pixel power supply voltage”) and a second pixel power line VSL transmitting a second pixel voltage ELVSS (also referred to as a “second pixel power supply voltage”). In an embodiment, the pixel PX may also be connected to an initialization power line VIL transmitting an initialization voltage VINT (also referred to as a “third pixel power supply voltage”) and a reference power line VRL transmitting a reference voltage VREF (also referred to as a “fourth pixel power supply voltage”).

[0097] In an embodiment, the first to fifth transistors T1 to T5 may be positioned in each pixel region (eg, Figure 5 In the pixel area PXA of one pixel PX provided in the display area DA in FIG, and may be an oxide transistor (also referred to as an "oxide semiconductor transistor") including an oxide semiconductor (e.g., an oxide semiconductor material). For example, the semiconductor layer of each of the first transistor T1 to the fifth transistor T5 may be formed of an oxide semiconductor. However, the embodiment is not limited thereto. For example, at least one pixel transistor TRS may also be formed of a semiconductor material other than an oxide semiconductor (e.g., amorphous silicon or polycrystalline silicon).

[0098] The oxide semiconductor may have high carrier mobility (for example, high electron mobility in the case of an N-type transistor) and low leakage current, and therefore, even if the driving time of the oxide transistor becomes longer, a voltage drop may not occur significantly. For example, since the brightness and / or color of an image does not change significantly due to a voltage drop even when driven at a low frequency, a pixel PX including an oxide transistor may be driven at a low frequency. In the case of a display device 10 in which the first transistor T1 to the fifth transistor T5 include an oxide semiconductor, leakage current of the pixel PX may be reduced or prevented, and power consumption may be reduced.

[0099] Since the oxide semiconductor is sensitive to light, the amount of current, etc. may vary due to external light. In an embodiment, a light-blocking pattern or a lower electrode (e.g., a bottom gate electrode) may be arranged below a semiconductor layer constituting at least one pixel transistor TRS (e.g., at least one of the first transistor T1 to the fifth transistor T5). Therefore, it is possible to prevent or reduce the change in the amount of current of the pixel transistor TRS caused by light, and stabilize the operating characteristics of the pixel transistor TRS.

[0100] The first transistor T1 (also referred to as a "first pixel transistor") may include a gate electrode connected to the first gate line GWL, a first electrode connected to the data line DL, and a second electrode connected to the first node N1. The first transistor T1 may be turned on by a first gate signal GW (e.g., a first gate signal GW of a gate-on voltage) transmitted to the first gate line GWL, and connect the data line DL and the first node N1 to each other. Therefore, the data signal DATA transmitted to the data line DL may be transmitted to the first node N1.

[0101] The second transistor T2 (also referred to as a "second pixel transistor") may include a gate electrode connected to the first node N1 (or gate node), a first electrode (e.g., a drain electrode or a drain region) connected to the second node N2, and a second electrode (e.g., a source electrode or a source region) connected to the third node N3. The first electrode of the second transistor T2 may be connected to the first pixel power line VDL via the fifth transistor T5, and the second electrode thereof may be connected to the light emitting element ED. The second transistor T2 may be used as a driving transistor of the pixel PX, and may control the size (e.g., current amount) of the driving current Id flowing to the light emitting element ED in response to the data signal DATA transmitted according to the switching operation of the first transistor T1.

[0102] In an embodiment, the second transistor T2 may further include a bottom gate electrode BG connected to the third node N3 (also referred to as a "back gate electrode of the second transistor T2" or a "second bottom gate electrode"). When the second transistor T2 is formed as a transistor having a double gate structure (e.g., a double gate transistor having a source-sink structure) by connecting the bottom gate electrode BG of the second transistor T2 to the third node N3 connected to the second electrode (e.g., source electrode) of the second transistor T2, the operating characteristics of the second transistor T2 may be improved.

[0103] The third transistor T3 (also referred to as a "third pixel transistor") may include a gate electrode connected to the third gate line GRL, a first electrode connected to the reference power line VRL, and a second electrode connected to the first node N1. The third transistor T3 may be turned on by a third gate signal GR transmitted to the third gate line GRL, and transmit a reference voltage VREF transmitted to the reference power line VRL to the first node N1.

[0104] The fourth transistor T4 (also referred to as a "fourth pixel transistor") may include a gate electrode connected to the second gate line GIL, a first electrode connected to the third node N3, and a second electrode connected to the initialization power line VIL. The fourth transistor T4 may be turned on by the second gate signal GI transmitted to the second gate line GIL, and transmit the initialization voltage VINT transmitted to the initialization power line VIL to the third node N3.

[0105] The fifth transistor T5 (also referred to as a "fifth pixel transistor") may include a gate electrode connected to the emission control line ECL, a first electrode connected to the first pixel power line VDL, and a second electrode connected to the second node N2 (or the first electrode of the second transistor T2). The fifth transistor T5 may be turned on by an emission control signal EM (e.g., an emission control signal EM of a gate-on voltage) transmitted to the emission control line ECL, and control the light emission timing of the pixel PX.

[0106] The first capacitor C1 may be connected between the first node N1 and the third node N3. For example, the first capacitor C1 may be connected between the gate electrode and the second electrode of the second transistor T2. The first capacitor C1 is a storage capacitor of the pixel PX and may store a threshold voltage of the second transistor T2 and a voltage corresponding to the data signal DATA (e.g., data voltage).

[0107] The second capacitor C2 may be connected between the first pixel power line VDL and the third node N3. In an embodiment, the capacitance of the second capacitor C2 may be smaller than the capacitance of the first capacitor C1.

[0108] The light emitting element ED may be connected between the third node N3 and the second pixel power line VSL. For example, the light emitting element ED may include a first electrode (e.g., an anode or a pixel electrode) connected to the third node N3, a second electrode (e.g., a cathode or an opposite electrode) facing the first electrode and connected to the second pixel power line VSL, and a light emitting layer between the first electrode and the second electrode. In an embodiment, the first electrode of the light emitting element ED may be a separate electrode provided to each pixel PX separately, and the second electrode of the light emitting element ED may be a common electrode shared by a plurality of pixels PX. While the driving current Id is supplied from the pixel circuit PC, the light emitting element ED may emit light having a brightness corresponding to the driving current Id.

[0109] Figure 4 is a schematic diagram showing an equivalent circuit of a pixel PX according to an embodiment. For example, Figure 4 Shown with Figure 3 Additional embodiments related to the switching transistor among the pixel transistor TRS.

[0110] Apart from Figures 1 to 3 In addition, refer to Figure 4 , at least one of the switching transistors provided in the pixel PX may include a bottom gate electrode BG (or a back gate electrode) facing the gate electrode (e.g., the top gate electrode) across the semiconductor layer. For example, at least one of the first transistor T1, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may include a bottom gate electrode BG.

[0111] Figure 4 An embodiment is disclosed in which a corresponding bottom gate electrode BG is provided to all pixel transistors TRS, and a reference numeral is used only for the bottom gate electrode BG provided to one pixel transistor TRS (e.g., the second transistor T2). However, the embodiment is not limited thereto. For example, at least one pixel transistor TRS may not include a bottom gate electrode BG and / or may not be formed as a gate-sink structure or a source-sink structure.

[0112] In an embodiment, the first transistor T1, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may include corresponding bottom gate electrodes BG. In an embodiment, the bottom gate electrode BG of each of the first transistor T1, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be connected to the gate electrode of the corresponding pixel PX. For example, each of the first transistor T1, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be formed as a double-gate transistor having a gate-sink structure.

[0113] By providing the first transistor T1, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 with corresponding bottom gate electrodes BG, it is possible to prevent or reduce the change in the current amount of the first transistor T1, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 caused by light. In the case where the bottom gate electrode BG of each of the first transistor T1, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 is connected to the gate electrode (also referred to as the "top gate electrode") of each of the first transistor T1, the third transistor T3, the fourth transistor T4 and the fifth transistor T5, the operating characteristics (e.g., switching characteristics) of each of the first transistor T1, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 can be improved and / or stabilized. For example, by forming at least one switching transistor with a dual gate structure of a gate-sink structure, the cut-off characteristics and switching speed of the switching transistor can be improved, an additional voltage tolerance range can be ensured, leakage current can be reduced, and voltage stability can be improved. As an example, by forming a small-sized switching transistor formed as an oxide transistor with a short channel length with a dual gate structure such as a gate-sink structure, the operating characteristics of the switching transistor can be improved.

[0114] Figure 5 is a schematic cross-sectional view showing a display panel 110 according to an embodiment.

[0115] Figure 5 The first transistor T1 and the second transistor T2 arranged in any one pixel area PXA are illustrated as examples of circuit elements that may be provided or arranged in the panel circuit layer PCL of the display panel 110 . Figure 5 A light-emitting display panel including a light-emitting element ED (e.g., an organic light-emitting diode) is shown as an example of a display panel 110 to which the embodiment can be applied. However, the type and / or structure of the display panel 110 according to the embodiment is not limited thereto. For example, the display panel 110 may include a light-emitting element of another type and / or structure, or may be a display panel of another type and / or structure other than a light-emitting display panel.

[0116] and Figures 1 to 4 Refer to Figure 5, the display panel 110 may include a substrate SUB, a panel circuit layer PCL, a light emitting element layer LEL, and a thin film encapsulation layer TFEL. The panel circuit layer PCL, the light emitting element layer LEL, and the thin film encapsulation layer TFEL may be arranged or provided to overlap each other on the substrate SUB. As an example, based on the display area DA, the panel circuit layer PCL, the light emitting element layer LEL, and the thin film encapsulation layer TFEL may be sequentially arranged or formed on the substrate SUB along the third direction DR3. However, the embodiment is not limited thereto, and the mutual positions of the panel circuit layer PCL, the light emitting element layer LEL, and the thin film encapsulation layer TFEL may be changed. As an example, the panel circuit layer PCL and the light emitting element layer LEL may be integrated, or the light emitting element layer LEL may be arranged on the upper side of the panel circuit layer PCL.

[0117] In an embodiment, the display panel 110 may further include additional elements provided on the upper and lower sides of the thin film encapsulation layer TFEL. For example, the display panel 110 may further include at least one of a sensor layer (e.g., a touch sensor layer), an optical layer (e.g., a color filter layer and / or a wavelength conversion layer), and a protective layer (e.g., a protective film, an insulating layer, an upper substrate, and / or a window). Each of the sensor layer, the optical layer, and the protective layer may be provided on the upper side of the thin film encapsulation layer TFEL, or may be provided between the light emitting element layer LEL and the thin film encapsulation layer TFEL. In an embodiment, the sensor layer, the optical layer, and / or the protective layer may be provided on the display panel 110. For example, the sensor layer, the optical layer, and / or the protective layer may be manufactured integrally with the display panel 110. In an embodiment, within the spirit and scope of the present disclosure, the sensor layer, the optical layer, and / or the protective layer may be manufactured separately from the display panel 110 and attached to the display panel 110 by an adhesive layer or the like.

[0118] The substrate SUB is a base member for forming the display panel 110, and may be a substrate (or film) having rigid or flexible properties. In an embodiment, the substrate SUB may be a substrate that may include an insulating material such as glass and has rigid properties, and may not bendable. In an embodiment, the substrate SUB may be a flexible substrate that may include polyimide or another insulating material and is capable of deformation (such as bending, folding, or curling), and may bendable or may not bendable. The type and / or material of the substrate SUB may vary according to the embodiment.

[0119] The substrate SUB may include at least a display area DA. In an embodiment, the display area DA may include pixel areas PXA each corresponding to the pixel PX. For example, in the display area DA, respective pixel areas PXA in which respective pixels PX are arranged may be defined.

[0120] In an embodiment, a buffer layer BUF may be disposed on the substrate SUB. In an embodiment, the display panel 110 may not include the buffer layer BUF, and in this case, the panel circuit layer PCL may be directly disposed on the substrate SUB.

[0121] The buffer layer BUF may include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials). The buffer layer BUF may protect the pixel PX from moisture penetrating the substrate SUB susceptible to moisture penetration. The material of the buffer layer BUF may be variously changed according to the embodiment.

[0122] The panel circuit layer PCL may be disposed on the buffer layer BUF. The panel circuit layer PCL may include circuit elements including a pixel transistor TRS and a pixel capacitor CST, and lines (eg, signal lines and power lines).

[0123] The panel circuit layer PCL may further include an insulating layer disposed on the substrate SUB. For example, the panel circuit layer PCL may include first, second, third, and fourth insulating layers INS1, INS2, INS3, INS4, and a first passivation layer PVX1 sequentially disposed on the substrate SUB along the third direction DR3.

[0124] In an embodiment, if Figure 5 As shown in , the panel circuit layer PCL may further include a connection electrode CNE and a second passivation layer PVX2 disposed on the first passivation layer PVX1 .

[0125] In an embodiment, each of the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 may include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials).

[0126] Each of the first through hole layer VIA1 and the second through hole layer VIA2 may include at least one organic insulating layer including an organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin or other organic insulating material). The surface (e.g., upper surface) of the first through hole layer VIA1 and the second through hole layer VIA2 may be substantially flat. The type, material, shape and / or structure of the insulating layer provided in the panel circuit layer PCL may be changed differently according to the embodiment.

[0127] The pixel transistor TRS may be included in the pixel circuit PC of each pixel PX and may be positioned in the display area DA. For example, the first transistor T1 and the second transistor T2 provided for each pixel PX may be arranged in each pixel area PXA in which the corresponding pixel PX is positioned. At least one other pixel transistor TRS and / or at least one pixel capacitor CST may also be arranged in each pixel area PXA.

[0128] In an embodiment, at least one pixel transistor TRS may include a bottom gate electrode BG. For example, the first transistor T1 may include a first bottom gate electrode BG1, and the second transistor T2 may include a second bottom gate electrode BG2. In an embodiment, the first bottom gate electrode BG1 and the second bottom gate electrode BG2 may be arranged on the same layer in the panel circuit layer PCL.

[0129] The first transistor T1 may include a first bottom gate electrode BG1 disposed on a substrate SUB, a first semiconductor layer ACT1 disposed on the first bottom gate electrode BG1 and including a first channel region CH1, a first drain region DR1, and a first source region SR1, and a first gate electrode GE1 (hereinafter referred to as “first top gate electrode GE1”) disposed on the first semiconductor layer ACT1.

[0130] At least a portion of the first semiconductor layer ACT1 may be disposed on the first bottom gate electrode BG1. For example, at least a portion of the first semiconductor layer ACT1 including the first channel region CH1 may overlap the first bottom gate electrode BG1. The first top gate electrode GE1 may be disposed on a portion of the first semiconductor layer ACT1 including the first channel region CH1, and the third insulating layer INS3 may be disposed between the first top gate electrode GE1 and the first semiconductor layer ACT1.

[0131] In an embodiment, the first transistor T1 may further include a first drain electrode DE1 and a first source electrode SE1 connected to different portions of the first semiconductor layer ACT1. By way of example, the first transistor T1 does not include a separate drain electrode and / or source electrode, and the first drain region DR1 and / or the first source region SR1 of the first semiconductor layer ACT1 may be connected to other circuit elements, lines and / or conductive patterns to serve as the drain electrode and / or source electrode of the first transistor T1.

[0132] The first bottom gate electrode BG1 may be disposed between the substrate SUB and the first insulating layer INS1. For example, the first bottom gate electrode BG1 may be disposed on the buffer layer BUF and covered by the first insulating layer INS1.

[0133] The first bottom gate electrode BG1 may overlap the first semiconductor layer ACT1. For example, the first bottom gate electrode BG1 may be arranged on the lower side of the first semiconductor layer ACT1 to overlap at least the first channel region CH1. The first insulating layer INS1 and the second insulating layer INS2 may be arranged between the first bottom gate electrode BG1 and the first semiconductor layer ACT1. The first bottom gate electrode BG1 and the first semiconductor layer ACT1 may be spaced apart from each other by a distance corresponding to the thickness of the first insulating layer INS1 and the second insulating layer INS2. The first bottom gate electrode BG1 may face the first top gate electrode GE1 across the first semiconductor layer ACT1.

[0134] The first bottom gate electrode BG1 may or may not be connected to another electrode of the first transistor T1. In an embodiment, the first bottom gate electrode BG1 may be electrically connected to the first top gate electrode GE1, and may function as a back gate electrode for adjusting characteristics of the first transistor T1.

[0135] The first semiconductor layer ACT1 may be disposed on the second insulating layer INS2. In an embodiment, the first semiconductor layer ACT1 may be disposed on the second insulating layer INS2 and may be covered by the third insulating layer INS3.

[0136] The first semiconductor layer ACT1 may include a first channel region CH1 overlapping the first top gate electrode GE1, and a first drain region DR1 and a first source region SR1 spaced apart from each other across the first channel region CH1. For example, the first drain region DR1 and the first source region SR1 may be positioned on both sides of the first channel region CH1. The first channel region CH1 may be a region that is non-conductive and maintains semiconductor properties, and the first drain region DR1 and the first source region SR1 may be conductive regions.

[0137] The first semiconductor layer ACT1 may overlap the first bottom gate electrode BG1 and the first top gate electrode GE1. For example, the first channel region CH1 of the first semiconductor layer ACT1 may be disposed between and may overlap the first bottom gate electrode BG1 and the first top gate electrode GE1.

[0138] The first semiconductor layer ACT1 may be completely covered by the third insulating layer INS3. For example, the first semiconductor layer ACT1 may be covered by the third insulating layer INS3 except for a portion where at least one contact hole (e.g., the first contact hole CNT1 and the second contact hole CNT2) for connection with the first drain electrode DE1 and / or the first source electrode SE1 is formed. Accordingly, since the amount of hydrogen flowing into the first semiconductor layer ACT1 during the process of forming the panel circuit layer PCL is reduced, the conductivity (e.g., carrier concentration) of the first semiconductor layer ACT1 and / or the formation length of the first channel region CH1 may be appropriately controlled.

[0139] The first top gate electrode GE1 may be disposed on the third insulating layer INS3. In an implementation, the first top gate electrode GE1 may be disposed on the third insulating layer INS3 and covered by the fourth insulating layer INS4.

[0140] The first top gate electrode GE1 may be disposed on the first semiconductor layer ACT1 to overlap the first channel region CH1. The first top gate electrode GE1 and the first semiconductor layer ACT1 may be spaced apart from each other via the third insulating layer INS3.

[0141] The first drain electrode DE1 and the first source electrode SE1 may be arranged on the fourth insulating layer INS4. The first drain electrode DE1 may be connected to a portion of the first semiconductor layer ACT1. For example, the first drain electrode DE1 may be connected to the first drain region DR1 through a first contact hole CNT1 penetrating the third insulating layer INS3 and the fourth insulating layer INS4. The first source electrode SE1 may be connected to another portion of the first semiconductor layer ACT1. For example, the first source electrode SE1 may be connected to the first source region SR1 through a second contact hole CNT2 penetrating the third insulating layer INS3 and the fourth insulating layer INS4.

[0142] The second transistor T2 may include a second bottom gate electrode BG2 arranged on the substrate SUB, a second semiconductor layer ACT2 arranged on the second bottom gate electrode BG2 and including a second channel region CH2, a second drain region DR2, and a second source region SR2, and a second gate electrode GE2 (hereinafter referred to as "second top gate electrode GE2") arranged on the second semiconductor layer ACT2. At least a portion of the second semiconductor layer ACT2 may be arranged on the second bottom gate electrode BG2. For example, at least a portion of the second semiconductor layer ACT2 including the second channel region CH2 may overlap with the second bottom gate electrode BG2. The second top gate electrode GE2 may be arranged on a portion of the second semiconductor layer ACT2 including the second channel region CH2, and a third insulating layer INS3 may be arranged between the second top gate electrode GE2 and the second semiconductor layer ACT2.

[0143] In an embodiment, the second transistor T2 may further include a second drain electrode DE2 and a second source electrode SE2 connected to different portions of the second semiconductor layer ACT2. By way of example, the second transistor T2 does not include a separate drain electrode and / or source electrode, and the second drain region DR2 and / or the second source region SR2 of the second semiconductor layer ACT2 may be connected to other circuit elements, lines and / or conductive patterns to serve as the drain electrode and / or source electrode of the second transistor T2.

[0144] The second bottom gate electrode BG2 may be arranged on the buffer layer BUF, and may be arranged on the same layer as that of the first bottom gate electrode BG1. The second bottom gate electrode BG2 may overlap the second semiconductor layer ACT2. For example, the second bottom gate electrode BG2 may be arranged on the lower side of the second semiconductor layer ACT2 to overlap at least the second channel region CH2. The first insulating layer INS1 and the second insulating layer INS2 may be arranged between the second bottom gate electrode BG2 and the second semiconductor layer ACT2. The second bottom gate electrode BG2 and the second semiconductor layer ACT2 may be spaced apart from each other by a distance corresponding to the thickness of the first insulating layer INS1 and the second insulating layer INS2. The second bottom gate electrode BG2 may face the second top gate electrode GE2 across the second semiconductor layer ACT2.

[0145] The second bottom gate electrode BG2 may or may not be connected to another electrode of the second transistor T2. In an embodiment, the second bottom gate electrode BG2 may be connected to the second source electrode SE2 of the second transistor T2 and may function as a back gate electrode for adjusting characteristics of the second transistor T2.

[0146] The second semiconductor layer ACT2 may be disposed on the second insulating layer INS2 , may be disposed at the same layer as that of the first semiconductor layer ACT1 , and may include the same oxide semiconductor as that of the first semiconductor layer ACT1 .

[0147] The second semiconductor layer ACT2 may include a second channel region CH2 overlapping the second top gate electrode GE2 and a second drain region DR2 and a second source region SR2 spaced apart from each other across the second channel region CH2. For example, the second drain region DR2 and the second source region SR2 may be positioned on both sides of the second channel region CH2. The second channel region CH2 may be a region that is non-conductive and maintains semiconductor properties, and the second drain region DR2 and the second source region SR2 may be conductive regions.

[0148] The second semiconductor layer ACT2 may overlap the second bottom gate electrode BG2 and the second top gate electrode GE2. For example, the second channel region CH2 of the second semiconductor layer ACT2 may be disposed between the second bottom gate electrode BG2 and the second top gate electrode GE2 and may overlap the second bottom gate electrode BG2 and the second top gate electrode GE2.

[0149] The second semiconductor layer ACT2 may be completely covered by the third insulating layer INS3. For example, the second semiconductor layer ACT2 may be covered by the third insulating layer INS3 except for a portion where at least one contact hole (e.g., the third contact hole CNT3 and the fourth contact hole CNT4) for connection with the second drain electrode DE2 and / or the second source electrode SE2 is formed. Accordingly, since the amount of hydrogen flowing into the second semiconductor layer ACT2 during the process of forming the panel circuit layer PCL is reduced, the conductivity (e.g., carrier concentration) of the second semiconductor layer ACT2 and / or the formation length of the second channel region CH2 may be appropriately controlled.

[0150] The second top gate electrode GE2 may be disposed on the third insulating layer INS3 , and may be disposed at the same layer as that of the first top gate electrode GE1 .

[0151] The second top gate electrode GE2 may be disposed on the second semiconductor layer ACT2 to overlap the second channel region CH2. The second top gate electrode GE2 and the second semiconductor layer ACT2 may be spaced apart from each other via the third insulating layer INS3.

[0152] The second drain electrode DE2 and the second source electrode SE2 may be disposed on the fourth insulating layer INS4 and covered by the first passivation layer PVX1 .

[0153] The second drain electrode DE2 may be connected to a portion of the second semiconductor layer ACT2. For example, the second drain electrode DE2 may be connected to the second drain region DR2 through a third contact hole CNT3 penetrating the third insulating layer INS3 and the fourth insulating layer INS4.

[0154] The second source electrode SE2 may be connected to another portion of the second semiconductor layer ACT2. For example, the second source electrode SE2 may be connected to the second source region SR2 through a fourth contact hole CNT4 penetrating the third insulating layer INS3 and the fourth insulating layer INS4. In an embodiment, the second source electrode SE2 may also be connected to the second bottom gate electrode BG2. For example, the second source electrode SE2 may be connected to the second bottom gate electrode BG2 through a fifth contact hole CNT5 penetrating the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4.

[0155] The pixel transistor TRS including the first transistor T1 and the second transistor T2 may be covered by at least one passivation layer. Figure 5 As shown in , the pixel transistor TRS may be covered by the first passivation layer PVX1 and the second passivation layer PVX2.

[0156] exist Figure 5In the embodiment shown in , the second transistor T2 of each pixel PX can be connected to the light emitting element ED of the corresponding pixel PX through the connection electrode CNE. The connection electrode CNE can be arranged on the first through hole layer VIA1 and covered by the second passivation layer PVX2. For example, the connection electrode CNE can be arranged between the first through hole layer VIA1 and the second passivation layer PVX2.

[0157] The connection electrode CNE may be connected to one electrode of the second transistor T2. As an example, the connection electrode CNE may be disposed on the second source electrode SE2 and connected to the second source electrode SE2 through at least one contact hole or via penetrating the first passivation layer PVX1 and the first via layer VIA1.

[0158] Each of the electrodes, conductive patterns, and lines provided in the conductive layer of the panel circuit layer PCL may include at least one conductive material and may have a single-layer or multi-layer structure. For example, the first bottom gate electrode BG1 and the second bottom gate electrode BG2, the first top gate electrode GE1 and the second top gate electrode GE2, the first source electrode SE1 and the second source electrode SE2, the first drain electrode DE1 and the second drain electrode DE2, and the connection electrode CNE may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, alloys thereof, or other conductive materials, and may each have a single-layer or multi-layer structure.

[0159] In an embodiment, the first semiconductor layer ACT1 and the second semiconductor layer ACT2 may include an oxide semiconductor. For example, the first semiconductor layer ACT1 and the second semiconductor layer ACT2 may include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), indium zinc oxide (IZO), indium oxide (InO), titanium oxide (TiO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc tin oxide (IZTO), and indium tin gallium zinc oxide (ITGZO) or other oxide semiconductors. The oxide semiconductor used to form the oxide transistor including the first transistor T1 and the second transistor T2 is not limited to the above materials and may be changed differently according to the embodiment. In an embodiment, the first semiconductor layer ACT1 and the second semiconductor layer ACT2 may include the same oxide semiconductor.

[0160] In an embodiment, the semiconductor layer of the pixel transistor TRS may be made of an oxide semiconductor having high mobility (eg, high mobility (eg, about 50 cm2) having high electron concentration) such as indium tin gallium zinc oxide (ITGZO) or indium gallium oxide (IGO). 2 / Vs or higher mobility) is formed. In the case where the pixel transistor TRS is formed of an oxide semiconductor with high mobility, each transistor can be formed with a fine size (for example, including the size of an active layer having a width and / or length ranging from about several microns to tens of microns) while appropriately ensuring the mobility of each transistor. Therefore, even in a high-resolution display device with a pixel area PXA of a relatively narrow area, the pixel transistor TRS can be easily arranged and / or formed, and the element characteristics and / or operating characteristics of the pixel transistor TRS can be appropriately ensured. For example, even if the channel length of at least one switching transistor provided in the pixel PX is reduced, the operating characteristics of the switching transistor (for example, appropriate switching characteristics) can be ensured. Therefore, the area occupied by the pixel transistor TRS can be appropriately and / or easily reduced, and the design space for other circuit elements or lines, etc. can be ensured. In addition, since the pixel transistor TRS is formed of an oxide semiconductor with high mobility, the power consumption of the display device 10 can be reduced.

[0161] The light emitting element layer LEL may be disposed on the panel circuit layer PCL and may be positioned in the display area DA. For example, the light emitting element layer LEL may be disposed on the panel circuit layer PCL in the display area DA.

[0162] The light emitting element layer LEL may include a light emitting element ED of the pixel PX. For example, the light emitting element layer LEL may include a pixel defining film PDL (also referred to as a "bank") that separates the light emitting regions of each of the pixels PX and a light emitting element ED positioned in each light emitting region. In an embodiment, the light emitting element layer LEL may further include a spacer SPC disposed on a portion of the pixel defining film PDL.

[0163] Each light emitting element ED may include a first electrode PE (e.g., an anode) connected to at least one pixel transistor TRS (e.g., a second transistor T2) included in a corresponding pixel PX, and a light emitting layer EML and a second electrode CE (e.g., a cathode) sequentially arranged on the first electrode PE. In an embodiment, the light emitting element ED may further include a first functional layer (e.g., a hole layer including a hole transport layer) between the first electrode PE and the light emitting layer EML, and a second functional layer (e.g., an electron layer including an electron transport layer) between the light emitting layer EML and the second electrode CE.

[0164] The first electrode PE of the light emitting element ED may be disposed on the panel circuit layer PCL. Figure 5 In the embodiment shown in , the first electrode PE may be disposed on the second via layer VIA2 to correspond to each light emitting region, and may be connected to the connection electrode CNE through at least one contact hole or via penetrating the second passivation layer PVX2 and the second via layer VIA2.

[0165] The first electrode PE may include a conductive material. In an embodiment, the first electrode PE may include a metal material having a high reflectivity. For example, the first electrode PE may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), and aluminum (Al), or may have a structure including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au) or nickel (Ni) multilayer structures (e.g., ITO / Mg, ITO / MgF 2 , ITO / Ag, ITO / Ag / ITO, etc.).

[0166] The light-emitting layer EML of the light-emitting element ED may include a polymer material or a low-molecular material. The light emitted from the light-emitting layer EML may contribute to displaying an image. In an embodiment, a light-emitting layer EML may be provided for each pixel PX, and the light-emitting layer EML of each pixel PX may emit visible light of a color corresponding to the corresponding pixel PX. In an embodiment, the light-emitting layer EML may be a common layer shared by pixels PX of different colors, and a wavelength conversion layer and / or a color filter corresponding to the color (or wavelength band) of light to be emitted from each pixel PX may be arranged in the light-emitting region of at least some of the pixels PX.

[0167] The second electrode CE of the light emitting element ED may include a conductive material. In an embodiment, the second electrode CE may be a common film formed throughout the entire display area DA to cover the light emitting layer EML and the pixel defining film PDL. In an embodiment, the second electrode CE may be formed of a transparent conductive material (TCO) such as ITO, IZO, ZnO, or ITZO capable of transmitting light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0168] The pixel defining film PDL may have an opening corresponding to each light emitting region and may surround the light emitting region. For example, the pixel defining film PDL may be formed to cover the edge of the first electrode PE of the light emitting element ED and may include an opening exposing the remaining portion of the first electrode PE. The region where the exposed first electrode PE overlaps with the light emitting layer EML (or the region including it) may be defined as the light emitting region of each pixel PX.

[0169] In an embodiment, the pixel defining layer PDL may include at least one organic insulating layer including an organic insulating material. For example, the pixel defining layer PDL may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin or benzocyclobutene (BCB) or other organic insulating materials.

[0170] A spacer SPC may be arranged on a portion of the pixel defining film PDL. The spacer SPC may include at least one organic insulating layer including an organic insulating material. The spacer SPC may include the same material as that of the pixel defining film PDL, or may include a material different from that of the pixel defining film PDL. In an embodiment, the pixel defining film PDL and the spacer SPC may be sequentially formed by respective mask processes. In an embodiment, the pixel defining film PDL and the spacer SPC may be simultaneously formed using a halftone mask. In this case, the pixel defining film PDL and the spacer SPC may be regarded as an integrated insulating film.

[0171] The thin film encapsulation layer TFEL may be arranged on the light emitting element layer LEL. The thin film encapsulation layer TFEL may cover the light emitting element layer LEL in the display area DA and extend to the non-display area NDA to contact the panel circuit layer PCL. For example, the thin film encapsulation layer TFEL may be arranged in the display area DA to cover the light emitting element layer LEL, and an end of the thin film encapsulation layer TFEL may be positioned in a portion of the non-display area NDA adjacent to the display area DA. The thin film encapsulation layer TFEL may block oxygen or moisture from penetrating into the light emitting element layer LEL, and may mitigate electrical and / or physical impacts on the panel circuit layer PCL and the light emitting element layer LEL.

[0172] In an embodiment, the thin film encapsulation layer TFEL may have a multilayer structure including a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3 sequentially stacked on the light emitting element layer LEL. Each of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be an inorganic encapsulation layer including an inorganic material. The second encapsulation layer TFE2 may be an organic encapsulation layer including an organic material. The structure and / or material of the thin film encapsulation layer TFEL may vary according to the embodiment.

[0173] Figure 6 is a schematic plan view showing an inspection pattern TAG according to an embodiment. Figure 7 is along Figure 6 Schematic cross-sectional view taken along line Q1-Q1'.

[0174] Except for reference Figure 5 Also refer to Figure 6 and Figure 7According to an embodiment, the inspection pattern TAG may include a first conductive pattern COP1, a first inspection electrode INE1 connected to the first conductive pattern COP1, a semiconductor pattern SCP, a second conductive pattern COP2, a second inspection electrode INE2 connected to the second conductive pattern COP2, an inspection source electrode IPS connected to a portion of the semiconductor pattern SCP, a third inspection electrode INE3 connected to the inspection source electrode IPS, an inspection drain electrode IPD connected to another portion of the semiconductor pattern SCP, and a fourth inspection electrode INE4 connected to the inspection drain electrode IPD.

[0175] The first conductive pattern COP1 may be disposed on the substrate SUB. For example, the first conductive pattern COP1 may be disposed on the substrate SUB on which the buffer layer BUF is formed, and may be directly disposed on the buffer layer BUF.

[0176] The first conductive pattern COP1 may be arranged at Figure 5 The first bottom gate electrode BG1 and the second bottom gate electrode BG2 of the panel circuit layer PCL shown in FIG. 1 are the same layer. For example, the first conductive pattern COP1 may be formed simultaneously with the first bottom gate electrode BG1 and the second bottom gate electrode BG2 through the same process.

[0177] The first insulating layer INS1 and the second insulating layer INS2 may be arranged on the first conductive pattern COP1. The first insulating layer INS1 may be the first insulating layer INS1 of the panel circuit layer PCL, and the second insulating layer INS2 may be the second insulating layer INS2 of the panel circuit layer PCL. For example, the first insulating layer INS1 and the second insulating layer INS2 may extend from the display area DA to the non-display area NDA, and may be arranged on the first conductive pattern COP1.

[0178] The semiconductor pattern SCP may be disposed on the second insulating layer INS2. The semiconductor pattern SCP may be disposed directly on the second insulating layer INS2. The semiconductor pattern SCP may be disposed on the same layer as the first semiconductor layer ACT1 and the second semiconductor layer ACT2 of the panel circuit layer PCL. For example, the semiconductor pattern SCP may be formed simultaneously with the first semiconductor layer ACT1 and the second semiconductor layer ACT2 by the same process.

[0179] The semiconductor pattern SCP may include an oxide semiconductor. For example, the semiconductor pattern SCP may include an oxide semiconductor shown in the first semiconductor layer ACT1 and the second semiconductor layer ACT2 of the panel circuit layer PCL.

[0180] The semiconductor pattern SCP may include a first conductive region COR1, a pattern channel region PCH, and a second conductive region COR2. The pattern channel region PCH may overlap with the second conductive pattern COP2. The first conductive region COR1 and the second conductive region COR2 may be spaced apart from each other across the pattern channel region PCH. For example, the first conductive region COR1 and the second conductive region COR2 may be positioned on both sides of the pattern channel region PCH. The pattern channel region PCH may be a region that is non-conductive and maintains semiconductor properties, and the first conductive region COR1 and the second conductive region COR2 may be conductive regions.

[0181] The third insulating layer INS3 may be disposed on the semiconductor pattern SCP. The third insulating layer INS3 may be the third insulating layer INS3 of the panel circuit layer PCL. For example, the third insulating layer INS3 may extend from the display area DA to the non-display area NDA and may be disposed on the semiconductor pattern SCP.

[0182] The second conductive pattern COP2 may be disposed on the third insulating layer INS3. For example, the second conductive pattern COP2 may be disposed on the third insulating layer INS3 and covered by the fourth insulating layer INS4.

[0183] The second conductive pattern COP2 may be arranged at Figure 5 The second conductive pattern COP2 may be formed at the same layer as the first top gate electrode GE1 of the panel circuit layer PCL shown in FIG. For example, the second conductive pattern COP2 may be formed simultaneously with the first top gate electrode GE1 by the same process. The second conductive pattern COP2 may overlap the first conductive pattern COP1 and may be arranged to overlap the pattern channel region PCH of the semiconductor pattern SCP.

[0184] The second conductive pattern COP2 may be connected to a portion of the semiconductor pattern SCP. For example, the second conductive pattern COP2 may be connected to the semiconductor pattern SCP through a first through hole VH1 penetrating the third insulating layer INS3. In an embodiment, the second conductive pattern COP2 may be in direct contact with an upper surface of the semiconductor pattern SCP. In an embodiment, the second conductive pattern COP2 may be in direct contact with a pattern channel region PCH of the semiconductor pattern SCP.

[0185] The fourth insulating layer INS4 may be disposed on the second conductive pattern COP2. The fourth insulating layer INS4 may be the fourth insulating layer INS4 of the panel circuit layer PCL. For example, the fourth insulating layer INS4 may extend from the display area DA to the non-display area NDA and may be disposed on the second conductive pattern COP2.

[0186] The first inspection electrode INE1, the second inspection electrode INE2, the third inspection electrode INE3, the fourth inspection electrode INE4, the inspection source electrode IPS, and the inspection drain electrode IPD may be arranged on the fourth insulating layer INS4. Figure 5 The first and second source electrodes SE1 and SE2 and the first and second drain electrodes DE1 and DE2 of the panel circuit layer PCL shown in FIG. 1 are the same layers and may be formed simultaneously with them by the same process.

[0187] The first inspection electrode INE1 may be arranged to overlap a portion of the first conductive pattern COP1. The first inspection electrode INE1 may be connected to a portion of the first conductive pattern COP1. For example, the first inspection electrode INE1 may be connected to the first conductive pattern COP1 through a second through hole VH2 penetrating the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4.

[0188] The second inspection electrode INE2 may be arranged to overlap a portion of the second conductive pattern COP2. The second inspection electrode INE2 may be connected to a portion of the second conductive pattern COP2. For example, the second inspection electrode INE2 may be connected to the second conductive pattern COP2 through a third through hole VH3 penetrating the fourth insulating layer INS4.

[0189] The inspection source electrode IPS may be arranged to overlap a portion of the semiconductor pattern SCP. The inspection source electrode IPS may be connected to a portion of the semiconductor pattern SCP. For example, the inspection source electrode IPS may be connected to the first conductive region COR1 of the semiconductor pattern SCP through a fourth through hole VH4 penetrating the third insulating layer INS3 and the fourth insulating layer INS4.

[0190] The third inspection electrode INE3 may be connected to the inspection source electrode IPS. For example, the third inspection electrode INE3 may be formed integrally with the inspection source electrode IPS. However, the present disclosure is not limited thereto, and the third inspection electrode INE3 may be formed separately from the inspection source electrode IPS and may be connected to the inspection source electrode IPS through a through hole.

[0191] The inspection drain electrode IPD may be arranged to overlap another portion of the semiconductor pattern SCP. The inspection drain electrode IPD may be connected to another portion of the semiconductor pattern SCP. For example, the inspection drain electrode IPD may be connected to the second conductive region COR2 of the semiconductor pattern SCP through a fifth through hole VH5 penetrating the third insulating layer INS3 and the fourth insulating layer INS4.

[0192] The fourth inspection electrode INE4 may be connected to the inspection drain electrode IPD. For example, the fourth inspection electrode INE4 may be formed integrally with the inspection drain electrode IPD. However, the present disclosure is not limited thereto, and the fourth inspection electrode INE4 may be formed separately from the inspection drain electrode IPD and may be connected to the inspection drain electrode IPD through a through hole.

[0193] The inspection pattern TAG may be formed to include the same semiconductor pattern SCP as the first semiconductor layer ACT1 of the first transistor T1 and the second semiconductor layer ACT2 of the second transistor T2 of the display area DA. Therefore, the characteristics of the pixel transistor TRS may be inferred by inspecting the characteristics of the inspection pattern TAG.

[0194] Figure 8 is a graph showing changes in the characteristics of a transistor depending on the hydrogen content of a semiconductor layer. For example, Figure 8 By depending on the gate voltage V G The drain current I D Electrical characteristics of transistors formed in the cases where no hydrogen gas was supplied, hydrogen gas was supplied at about 3 sccm (standard cubic centimeters per minute), and hydrogen gas was supplied at about 10 sccm during formation of the semiconductor layer are shown.

[0195] Fig. 9 is a graph showing changes in characteristics of a transistor having a semiconductor layer not containing hydrogen. Fig.10 is a graph showing changes in characteristics of a transistor having a semiconductor layer containing hydrogen. For example, Fig. 9 Shows Figure 8 A hysteresis curve of a transistor formed without supplying hydrogen during formation of a semiconductor layer, and Fig.10 Shows Figure 8 A hysteresis curve of a transistor formed in the case where hydrogen gas is supplied at about 3 sccm during formation of a semiconductor layer.

[0196] Reference Figure 8 , without supplying hydrogen, the threshold voltage Vth was about 3.82 and the subthreshold swing (SS) was about 1.89, and when hydrogen was supplied at about 3 sccm, the threshold voltage Vth was about 3.82 and the subthreshold swing (SS) was about 1.89. When hydrogen was supplied at about 10 sccm, the semiconductor layer became conductive.

[0197] Reference Fig. 9 and Fig.10 , found that the hysteresis of transistors containing hydrogen in the semiconductor layer was reduced compared to transistors without hydrogen in the semiconductor layer.

[0198] pass Figures 8 to 10 It can be seen that the hydrogen content of the semiconductor layer has a significant influence on the characteristics of the transistor.

[0199] Through this, the present disclosure checks the characteristics of the pixel transistor TRS and confirms the hydrogen content of the semiconductor layer by checking the pattern TAG, and maintains uniform display quality by checking and monitoring the characteristics of the pixel transistor TRS in the display area DA even when the characteristics of the pixel transistor TRS in the display area DA change according to the manufacturing process conditions.

[0200] In the following, reference will be made to the above Figures 1 to 7 A method of inspecting the display device 10 including the inspection pattern TAG is described.

[0201] Since the inspection pattern TAG may include the semiconductor pattern SCP which is the same semiconductor layer as that of the pixel transistor TRS of the display area DA, the inspection pattern TAG represents the pixel transistor TRS in the display area DA, and the inspection pattern TAG may be used to confirm the characteristics of the pixel transistor TRS in the display area DA. For example, the characteristics of the transistor may be the capacitance value of the semiconductor layer.

[0202] In an embodiment, a manufacturing process of the pixel transistor TRS of the panel circuit layer PCL and a manufacturing process of the inspection pattern TAG may be simultaneously performed during a manufacturing process of the display device 10. For example, a bottom gate electrode BG of the pixel transistor TRS and a first conductive pattern COP1 of the inspection pattern TAG, semiconductor layers ACT1 and ACT2 of the pixel transistor TRS and a semiconductor pattern SCP of the inspection pattern TAG, top gate electrodes GE1 and GE2 of the pixel transistor TRS and a second conductive pattern COP2 of the inspection pattern TAG, and source electrodes SE1 and SE2 and drain electrodes DE1 and DE2 of the pixel transistor TRS and first inspection electrodes INE1, second inspection electrodes INE2, third inspection electrodes INE3, and fourth inspection electrodes INE4 of the inspection pattern TAG may be simultaneously formed by the same process, respectively.

[0203] After forming the pixel transistor TRS and the inspection pattern TAG, inspection may be performed by connecting a measurement device to the inspection pattern TAG. The measurement device may be provided with a terminal that may apply an electrical signal to the first, second, third, and fourth inspection electrodes INE1, INE2, INE3, and INE4.

[0204] In an embodiment, the capacitance of the back channel of the semiconductor pattern SCP of the inspection pattern TAG may be measured. Here, the back channel of the semiconductor pattern SCP may refer to a channel formed on the lower side of the semiconductor pattern SCP adjacent to the first conductive pattern COP1. The capacitance of the back channel may be obtained by measuring the capacitance of the semiconductor pattern SCP when the back channel is formed in the semiconductor pattern SCP.

[0205] As a method of forming a back channel in the semiconductor pattern SCP of the inspection pattern TAG, the back channel may be formed by applying an AC signal (eg, frequency) to the first conductive pattern COP1 through the first inspection electrode INE1 and applying a DC signal to the second conductive pattern COP2 through the second inspection electrode INE2 in a measuring device.

[0206] As described above, the second conductive pattern COP2 may be in direct contact with and connected to the upper surface of the semiconductor pattern SCP. The third insulating layer INS3 is interposed between the second conductive pattern COP2 and the semiconductor pattern SCP. Since the third insulating layer INS3 is thick, even if an electrical signal is applied to the second conductive pattern COP2 and the first conductive pattern COP1, a tunneling effect does not occur between the second conductive pattern COP2 and the first conductive pattern COP1. In an embodiment, by directly contacting the second conductive pattern COP2 with the semiconductor pattern SCP, a tunneling effect may occur between the second conductive pattern COP2 and the first conductive pattern COP1. In the case where there are electron traps caused by hydrogen in the semiconductor pattern SCP, current may travel through the traps due to the tunneling effect.

[0207] For example, when an electric signal is applied to the first and second conductive patterns COP1 and COP2 , current may flow between the first and second conductive patterns COP1 and COP2 , and current and capacitance in the semiconductor pattern SCP may be measured through the third and fourth inspection electrodes INE3 and INE4 .

[0208] Fig.11 is a graph showing the capacitance Qcp of a semiconductor pattern according to frequency. For example, Fig.11 The capacitance of the semiconductor pattern SCP according to the frequency of the AC signal applied to the second conductive pattern COP2 is shown.

[0209] Reference Fig.11 , as the frequency of the AC signal applied to the second conductive pattern COP2 increases, the capacitance Qcp of the semiconductor pattern SCP decreases.

[0210] In an embodiment, the capacitance value of the semiconductor pattern SCP in which the back channel is formed may be measured using the inspection pattern TAG. Using such capacitance value, the hydrogen content of the semiconductor pattern SCP may be found by comparing the capacitance value with a reference table in which hydrogen content according to the capacitance value is analyzed.

[0211] Therefore, during the manufacturing process of the display device 10 , the characteristics of the pixel transistor TRS may be monitored by measuring the hydrogen content of the semiconductor pattern SCP at regular intervals using the inspection pattern TAG.

[0212] Fig.12 is a schematic cross-sectional view showing an inspection pattern of a display device according to an embodiment. Fig.12 Shown above Figure 7 Another embodiment of .

[0213] Except for reference Figures 1 to 6 In addition, refer to Fig.12 , this implementation is similar to Figure 7 The embodiment of the present invention may be different in that the inspection pattern TAG may further include a connection pattern CNP connecting the first conductive pattern COP1 and the semiconductor pattern SCP, and the second conductive pattern COP2 is spaced apart from the semiconductor pattern SCP. Hereinafter, description of the same configuration as that of the above-described embodiment will be omitted, and differences from the above-described embodiment will be described.

[0214] According to an embodiment, the inspection pattern TAG may include a first conductive pattern COP1, a first inspection electrode INE1 connected to the first conductive pattern COP1, a connection pattern CNP connecting the first conductive pattern COP1 and the semiconductor pattern SCP, a semiconductor pattern SCP, a second conductive pattern COP2, a second inspection electrode INE2 connected to the second conductive pattern COP2, an inspection source electrode IPS connected to a portion of the semiconductor pattern SCP, a third inspection electrode INE3 connected to the inspection source electrode IPS, an inspection drain electrode IPD connected to another portion of the semiconductor pattern SCP, and a fourth inspection electrode INE4 connected to the inspection drain electrode IPD.

[0215] The connection pattern CNP may be arranged on the first conductive pattern COP1. For example, the connection pattern CNP may be arranged to be in direct contact with the first conductive pattern COP1. The connection pattern CNP may overlap with the semiconductor pattern SCP, and may be arranged to overlap with the pattern channel region PCH of the semiconductor pattern SCP. The connection pattern CNP may be arranged in a sixth through hole VH6 penetrating the first insulating layer INS1 and the second insulating layer INS2. The sixth through hole VH6 may be arranged to overlap with the first conductive pattern COP1, the second conductive pattern COP2, and the semiconductor pattern SCP. The connection pattern CNP may be connected to the first conductive pattern COP1 and the semiconductor pattern SCP through the sixth through hole VH6. For example, the connection pattern CNP may be in direct contact with the lower surface of the pattern channel region PCH. The first conductive pattern COP1, the second conductive pattern COP2, and the connection pattern CNP may be arranged to overlap with the pattern channel region PCH of the semiconductor pattern SCP.

[0216] The connection pattern CNP may be arranged to contact the side surfaces of the first insulating layer INS1 and the second insulating layer INS2. In an embodiment, the upper surface of the connection pattern CNP may be aligned with the upper surface of the second insulating layer INS2. However, the present disclosure is not limited thereto, and at least a portion of the connection pattern CNP may also be arranged to extend to the upper surface of the second insulating layer INS2.

[0217] The connection pattern CNP may include a conductive material. For example, the connection pattern CNP may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg) and other metals, alloys thereof or other conductive materials, and may have a single layer or multilayer structure.

[0218] The semiconductor pattern SCP may be disposed on the connection pattern CNP and the second insulating layer INS2, and the third insulating layer INS3 may be disposed on the semiconductor pattern SCP. The second conductive pattern COP2 may be disposed on the third insulating layer INS3 to overlap with the semiconductor pattern SCP. Figure 7 Differently, the second conductive pattern COP2 may be arranged to be spaced apart from the semiconductor pattern SCP.

[0219] In an embodiment, the capacitance of the front channel of the semiconductor pattern SCP of the inspection pattern TAG may be measured. Here, the front channel of the semiconductor pattern SCP may refer to a channel formed on the upper side of the semiconductor pattern SCP adjacent to the second conductive pattern COP2. Therefore, the first conductive pattern COP1 may be contacted with the semiconductor pattern SCP through the connection pattern CNP, and the second conductive pattern COP2 may be arranged to be spaced apart from the semiconductor pattern SCP to form the front channel.

[0220] The capacitance of the front channel can be obtained by measuring the capacitance of the semiconductor pattern SCP in the case where the front channel is formed in the semiconductor pattern SCP. As a method of forming the front channel in the semiconductor pattern SCP of the inspection pattern TAG, the front channel can be formed by applying a DC signal to the first conductive pattern COP1 through the first inspection electrode INE1 in a measuring device, and applying an AC signal (e.g., frequency) to the second conductive pattern COP2 through the second inspection electrode INE2. In an embodiment, the first conductive pattern COP1 is directly connected to the semiconductor pattern SCP through the connection pattern CNP, and a tunneling effect can occur between the second conductive pattern COP2 and the first conductive pattern COP1.

[0221] Therefore, when an electric signal is applied to the first and second conductive patterns COP1 and COP2 , current may flow between the first and second conductive patterns COP1 and COP2 , and current and capacitance in the semiconductor pattern SCP may be measured through the third and fourth inspection electrodes INE3 and INE4 .

[0222] Fig.13 is a schematic cross-sectional view showing an inspection pattern of a display device according to an embodiment. Fig.13 Shown above Figure 7 and Fig.12 Different implementations of the method.

[0223] Except for reference Figures 1 to 6 In addition, refer to Fig.13 , an embodiment shows a method including Figure 7 and Fig.12 For example, this embodiment may be different from the above-described embodiment in that the inspection pattern TAG may include a connection pattern CNP connecting the first conductive pattern COP1 and the semiconductor pattern SCP, and the second conductive pattern COP2 contacts the semiconductor pattern SCP.

[0224] In an embodiment, the capacitance of the double channel of the semiconductor pattern SCP of the inspection pattern TAG may be measured. Here, the double channel of the semiconductor pattern SCP may refer to both a front channel formed on the upper side of the semiconductor pattern SCP adjacent to the second conductive pattern COP2 and a back channel formed on the lower side of the semiconductor pattern SCP adjacent to the first conductive pattern COP1. Therefore, the double channel may be formed by contacting the first conductive pattern COP1 with the semiconductor pattern SCP through the connection pattern CNP, and contacting the second conductive pattern COP2 with the semiconductor pattern SCP.

[0225] The capacitance of the double channel can be obtained by measuring the capacitance of the semiconductor pattern SCP in the case where the front channel and the back channel are formed in the semiconductor pattern SCP. As a method of forming the double channel in the semiconductor pattern SCP of the inspection pattern TAG, the double channel can be formed by applying an AC signal (e.g., frequency) to the first conductive pattern COP1 through the first inspection electrode INE1 in a measuring device, and applying an AC signal (e.g., frequency) to the second conductive pattern COP2 through the second inspection electrode INE2.

[0226] In an embodiment, the first conductive pattern COP1 is directly connected to the semiconductor pattern SCP through the connection pattern CNP, and the second conductive pattern COP2 is connected to the semiconductor pattern SCP, and a tunneling effect may occur between the second conductive pattern COP2 and the first conductive pattern COP1. Therefore, when an electrical signal is applied to the first conductive pattern COP1 and the second conductive pattern COP2, a current may flow between the first conductive pattern COP1 and the second conductive pattern COP2, and the current and capacitance in the semiconductor pattern SCP may be measured through the third inspection electrode INE3 and the fourth inspection electrode INE4.

[0227] Therefore, the characteristics of the pixel transistor TRS may be monitored by measuring the capacitance of the semiconductor pattern SCP at regular intervals using the inspection pattern TAG and confirming the hydrogen content during the manufacture of the display device 10 .

[0228] Fig.14 is a schematic plan view showing a display panel 110 according to an embodiment.

[0229] Reference Fig.14 This embodiment is different from the above Figure 2 The embodiment may be different in that the display panel 110 may include a plurality of inspection patterns TAG1, TAG2, and TAG3.

[0230] A plurality of check patterns TAG1, TAG2, and TAG3 may be arranged in the non-display area NDA. For example, the first check pattern TAG1 may be arranged in the space between the first driver 120 and the pad area PA, and the second check pattern TAG2 may be arranged adjacent to the first check pattern TAG1 across the pad area PA. The third check pattern TAG3 may be arranged on the upper left side of the display panel 110. However, the present disclosure is not limited thereto, and the plurality of check patterns TAG1, TAG2, and TAG3 may be arranged at any position in the non-display area NDA. The plurality of check patterns TAG1, TAG2, and TAG3 may be arranged in the space between the first driver 120 and the pad area PA.

[0231] In an embodiment, the first inspection pattern TAG1 may be Figure 7 The inspection pattern shown in FIG. 1 , the second inspection pattern TAG2 may be Fig.12 The inspection pattern shown in , and the third inspection pattern TAG3 may be Fig.13 For example, the first inspection pattern TAG1 may be an inspection pattern that can measure capacitance of a back channel, the second inspection pattern TAG2 may be an inspection pattern that can measure capacitance of a front channel, and the third inspection pattern TAG3 may be an inspection pattern that can measure capacitance of a double channel.

[0232] In an embodiment, the hydrogen content of the semiconductor pattern SCP may be analyzed by measuring capacitance of each channel of the inspection pattern including the plurality of inspection patterns TAG1 , TAG2 , and TAG3 .

[0233] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications can be made to the embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed embodiments are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, comprising: Display area and non-display area; A transistor, wherein the transistor is arranged on the display area of ​​the substrate, and the transistor includes a semiconductor layer; as well as at least one inspection pattern, the at least one inspection pattern being arranged on the non-display area of ​​the substrate, the at least one inspection pattern comprising a semiconductor pattern, Wherein, the at least one inspection pattern further comprises: a first conductive pattern and a second conductive pattern, the first conductive pattern and the second conductive pattern being spaced apart from each other in a thickness direction with the semiconductor pattern arranged between the first conductive pattern and the second conductive pattern; and an inspection source electrode and an inspection drain electrode, the inspection source electrode being electrically connected to a portion of the semiconductor pattern, the inspection drain electrode being electrically connected to another portion of the semiconductor pattern, and The second conductive pattern contacts the semiconductor pattern.

2. The display device according to claim 1, further comprising: A first insulating layer and a second insulating layer are disposed on the substrate and between the semiconductor pattern and the first conductive pattern.

3. The display device according to claim 1, wherein: The semiconductor pattern includes a pattern channel region and first and second conductive regions that are spaced apart from each other with the pattern channel region disposed therebetween.

4. The display device according to claim 3, wherein: The first conductive pattern overlaps the pattern channel region.

5. The display device according to claim 3, wherein: The inspection source electrode is electrically connected to the first conductive region, and the inspection drain electrode is electrically connected to the second conductive region.

6. The display device according to claim 1, wherein: The second conductive pattern is arranged on the semiconductor pattern and overlaps the first conductive pattern.

7. The display device according to claim 1, further comprising: a third insulating layer disposed between the second conductive pattern and the semiconductor pattern, The second conductive pattern contacts the semiconductor pattern through a first through hole penetrating the third insulating layer.

8. The display device according to claim 1, further comprising: a fourth insulating layer disposed between the inspection source electrode and the inspection drain electrode and the second conductive pattern, The inspection source electrode and the inspection drain electrode are electrically connected to the semiconductor pattern through a second through hole and a third through hole penetrating the fourth insulating layer, respectively.

9. The display device according to claim 1, further comprising: a fourth insulating layer, the fourth insulating layer being arranged on the second conductive pattern; as well as A first inspection electrode, a second inspection electrode, a third inspection electrode, and a fourth inspection electrode are arranged on the fourth insulating layer and are spaced apart from each other.

10. The display device according to claim 9, wherein: The first inspection electrode is electrically connected to the first conductive pattern, and the second inspection electrode is electrically connected to the second conductive pattern.

11. The display device according to claim 9, wherein: The third inspection electrode extends from the inspection source electrode, and the fourth inspection electrode extends from the inspection drain electrode.

12. The display device according to claim 1, wherein: The semiconductor layer of the transistor in the display region and the semiconductor pattern of the at least one inspection pattern include the same material.

13. The display device according to claim 12, wherein: The semiconductor layer of the transistor in the display region and the semiconductor pattern of the at least one inspection pattern include an oxide semiconductor.

14. The display device according to claim 1, further comprising: a connection pattern arranged between the first conductive pattern and the semiconductor pattern, Wherein, the first conductive pattern is electrically connected to the semiconductor pattern through the connecting pattern.

15. A display device, comprising: Display area and non-display area; a transistor disposed on the display region of the substrate and comprising a semiconductor layer; as well as an inspection pattern disposed on the non-display area of ​​the substrate and including a semiconductor pattern, Wherein, the inspection pattern further includes: a first conductive pattern and a second conductive pattern, the first conductive pattern and the second conductive pattern being spaced apart from each other in a thickness direction with the semiconductor pattern arranged between the first conductive pattern and the second conductive pattern; an inspection source electrode and an inspection drain electrode, the inspection source electrode being electrically connected to a portion of the semiconductor pattern and the inspection drain electrode being electrically connected to another portion of the semiconductor pattern; and a connection pattern disposed between the first conductive pattern and the semiconductor pattern, and The connection pattern contacts the first conductive pattern and the semiconductor pattern.

16. The display device according to claim 15, wherein: The semiconductor layer of the transistor in the display region and the semiconductor pattern of the inspection pattern include an oxide semiconductor.

17. The display device according to claim 15, further comprising: a first insulating layer and a second insulating layer, the first insulating layer and the second insulating layer being arranged between the semiconductor pattern and the first conductive pattern, The connection pattern is arranged in a first through hole penetrating the first insulating layer and the second insulating layer, and the first through hole overlaps with the first conductive pattern and the semiconductor pattern.

18. The display device according to claim 15, wherein: The semiconductor pattern includes a pattern channel region and a first conductive region and a second conductive region, the first conductive region and the second conductive region being spaced apart from each other with the pattern channel region disposed between the first conductive region and the second conductive region, and The connection pattern contacts the pattern channel region.

19. The display device according to claim 18, wherein: The first conductive pattern, the second conductive pattern, and the connecting pattern overlap the pattern channel region of the semiconductor pattern.

20. The display device according to claim 15, further comprising: a third insulating layer, the third insulating layer being arranged between the semiconductor pattern and the second conductive pattern, Wherein, the second conductive pattern is spaced apart from the semiconductor pattern.

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