Communication system and method based on hybrid multiplication active code

Abstract

The disclosed hybrid multiplication positive code-based communication system and method are used for: (i) receiving an information bit stream; (ii) reshaping the information bit stream into at least a first rectangular information matrix M1 of size Kr1 * Kc1 and a second rectangular information matrix M2 of size Kr2 * Kc2; (iii) converting the rectangular information matrices M1 and M2, respectively, into 2D multiplicative code encoding matrices X1 and X2, with the sizes of the 2D multiplicative code encoding matrices X1 and X2, respectively, Nr1 * Nc1 and Nr2 * Nc2, using multiplicative codes; (iv) converting the 2D multiplicative coding matrices X1 and X2 into a coded bitstream X '; (v) encoding the encoded bit stream X'into a polar encoded bit stream X ''using the polar code.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. application No. 17 / 965,171, filed on October 13, 2022, and entitled “Communication system and method based on hybrid multiplication quantization code.” Technical Field

[0003] The present invention relates generally to digital communications, and more particularly to communication systems and methods based on hybrid multiplicative quantization codes. Background Art

[0004] Recently, fiber-optic communication systems have been widely deployed, from data center interconnects to cellular network backhaul to transcontinental submarine systems. In modern high-throughput optical communication systems, forward error correction (FEC) is a key technology to protect data from channel noise and inherent system impairments. However, FEC technology usually consumes a lot of power and may account for a large portion of the total power consumption of the transceiver chip (e.g., more than 30%). Due to high-throughput applications, low-power FEC technology with parallel decoding capabilities is of great significance for fiber-optic communication systems.

[0005] Polar codes are commonly used to achieve symmetric capacity for binary-input, discrete memoryless channels with low encoding and decoding complexity. Polar codes have an explicit construction method and their capacity realization properties have been studied.

[0006] However, a major problem with this type of polar codes is the high decoding delay of decoding algorithms based on successive cancellation (SC). In particular, the sequential nature of SC decoders significantly reduces the achievable throughput. Recently, techniques for fast SC decoding algorithms have been proposed to improve the decoding delay, where many computations have been parallelized. These techniques are mainly based on identifying certain types of special nodes in the binary tree of polar codes, where the decoding of polar codes can be performed in parallel instead of following a serial SC schedule.

[0007] Even with a fast SC decoding algorithm, conventional polar codes suffer from short minimum distance and error propagation issues in addition to latency issues. Therefore, for long-length polar codes known to achieve capacity, decoding latency is high even with a fast decoder, making these polar codes unattractive for low-latency applications.

[0008] Therefore, improving the latency of fiber optic communication systems has attracted attention. Summary of the invention

[0009] The embodiments of the present invention are based on the developer's understanding of the limitations associated with the prior art, namely the high decoding delay of the successive cancellation (SC) based decoding algorithm of the polar code. In particular, the sequential nature of the SC decoder and the successive cancellation list (SCL) decoder significantly reduces the achievable throughput. More specifically, for long-length polar codes with known achievable capacity, the decoding delay is high even with a fast decoder, which makes these polar codes unattractive for low-latency applications.

[0010] Developers of the present technology have designed communication systems and methods based on hybrid product polar codes. Various non-limiting embodiments of the present invention can be based on hybrid product polar codes (HPPC). Product polar codes are parallel concatenated codes whose decoding process can be easily parallelized. Product polar codes have good error correction performance, high minimum distance, low latency and high throughput. Among product polar codes, vertical component codes and horizontal component codes can be selected as short-length polar codes with low latency. Although product polar codes can benefit from low latency and high-throughput decoding, due to the short length of the component codes, the bit error rate performance can be improved by using polar codes in addition to product polar codes, especially in low signal-to-noise (SNR) regions. In this way, optical fiber communication systems can be improved in terms of latency and BER.

[0011] According to a first broad aspect of the present invention, there is provided a communication system, comprising: a transmitter, comprising a multiplication scalar code encoder, wherein the multiplication scalar code encoder is used to: receive an information bit stream; reshape the information bit stream into a size of at least K r1 ×K c1 The first rectangular information matrix M1 and size K r2 ×K c2 A second rectangular information matrix M2, wherein in the rectangular information matrices M1 and M2, K r1 and K r2 are the number of rows, K c1 and K c2 The rectangular information matrices M1 and M2 are respectively converted into 2D multiplication code encoding matrices X1 and X2 using multiplication code, wherein the sizes of the 2D multiplication code encoding matrices X1 and X2 are N r1 ×N c1 and N r2 ×N c2 , where, in the encoding matrices X1 and X2, N r1 and N r2are the number of rows, N c1 and N c1 are the number of columns respectively; converting the 2D multiplication polarization code encoding matrices X1 and X2 into a coded bit stream X′; a polar code encoder, configured to encode the coded bit stream X′ into a polarization coded bit stream X″ using the polar code.

[0012] According to any embodiment of the present invention, the communication system further includes: an interleaver for rearranging the polarization coded bit stream X″ to generate a rearranged polarization coded bit stream X″′; a bit to symbol mapper for mapping the rearranged polarization coded bit stream X″′ to a non-binary symbol set S; a transmitter symbol processor for processing the non-binary symbol set S to generate a processed non-binary symbol set S′, and sending the processed non-binary symbol set S′ to a receiver.

[0013] According to any embodiment of the present invention, a code rate R of the multiplication quantization code is less than a first threshold.

[0014] According to any embodiment of the present invention, a code rate R of the multiplication quantization code is greater than a second threshold.

[0015] According to a second broad aspect of the present invention, there is provided a communication system, comprising: a receiver, comprising: a receiver symbol processor, for: receiving a processed non-binary symbol set S' from a transmitter, processing the received processed non-binary symbol set S' to reverse the operations performed by the transmitter symbol processor included in the transmitter, and generating an extracted non-binary symbol set S''; a symbol to log-likelihood ratio (LLR) converter, for converting the extracted non-binary symbol set S'' into LLRs; a deinterleaver, for rearranging the LLRs to reverse the effect of interleaving performed by the transmitter; a polarimetric decoder, for: performing polarimetric decoding based on successive elimination on the rearranged LLRs and generating polarimetric decoded LLRs, and rearranging the polarimetric decoded LLRs into a size of N r ×N c The 2D matrix of polar decoder LLRs, where N r is the number of rows, N c is the number of columns; a multiplicative quantization code decoder, configured to perform multiplicative quantization decoding on the 2D matrix of the polar decoder LLR to generate information bits representing the original information bits sent by the transmitter.

[0016] According to any embodiment of the present invention, the multiplicative quantization code decoder performs the multiplicative quantization code decoding in an iterative manner.

[0017] According to any embodiment of the present invention, the multiplication polarization code decoder performs N-based multiplication on the rows of the 2D matrix of the polar decoder LLR. r Parallel decoding of rapid serial elimination lists.

[0018] According to any embodiment of the present invention, the multiplication polarization code decoder performs N-based multiplication on the columns of the 2D matrix of the polar decoder LLR. c Parallel decoding of rapid serial elimination lists.

[0019] According to any embodiment of the present invention, the multiplication polarization code decoder calculates the prior information L according to the 2D matrix of the polar decoder LLR apr (i,j) and the posterior information L app (i, j), where i and j represent the i-th row and j-th column of the 2D matrix of the polar decoder LLR.

[0020] According to any embodiment of the present invention, the multiplication quantization code calculates the a posteriori information L by the following equation: app (i,j):

[0021]

[0022] Where η is the iterative correlation scaling factor, C*(j) is the candidate codeword, is the minimum path metric among the competing codewords for bit position j, PML0 is the minimum path metric associated with the most likely codeword in the list of candidate codewords provided to the SCL algorithm, is the candidate codeword with the minimum square distance in the candidate codeword list.

[0023] According to any embodiment of the present invention, the multiplication positive code decoder is based on the prior information L apr (i, j) and the posterior information L app (i, j) The formula for calculating the information bit is as follows:

[0024] L ex (i,j)=L app (i,j)-L apr (i,j)

[0025] Among them, L ex (i, j) is the extrinsic information representing the information bits on the i-th row and j-th column of the 2D matrix of the polar decoder LLR.

[0026] According to a third broad aspect of the present invention, there is provided a communication method, comprising: receiving an information bit stream; reshaping the information bit stream into a size of at least K r1 ×K c1The first rectangular information matrix M1 and size K r2 ×K c2 A second rectangular information matrix M2, wherein in the rectangular information matrices M1 and M2, K r1 and K r2 are the number of rows, K c1 and K c2 The rectangular information matrices M1 and M2 are respectively converted into 2D multiplication code encoding matrices X1 and X2 using multiplication code, wherein the sizes of the 2D multiplication code encoding matrices X1 and X2 are N r1 ×N c1 and N r2 ×N c2 , where, in the encoding matrices X1 and X2, N r1 and N r2 are the number of rows, N c1 and N c1 are the number of columns respectively; converting the 2D multiplication polarization code encoding matrices X1 and X2 into a coded bit stream X′; and encoding the coded bit stream X′ into a polarization coded bit stream X″ using the polar code.

[0027] According to any embodiment of the present invention, the communication method further includes: rearranging the polarization coded bit stream X″ to generate a rearranged polarization coded bit stream X″′; mapping the rearranged polarization coded bit stream X″′ to a non-binary symbol set S; processing the non-binary symbol set S and generating a processed non-binary symbol set S′; and sending the processed non-binary symbol set S to a receiver. ′ .

[0028] According to any embodiment of the present invention, a code rate R of the multiplication quantization code is less than a first threshold.

[0029] According to any embodiment of the present invention, a code rate R of the multiplication quantization code is greater than a second threshold.

[0030] According to a fourth broad aspect of the present invention, there is provided a communication method, comprising: receiving a processed non-binary symbol set S' from a transmitter; processing the received processed non-binary symbol set S' and reversing the operations performed by a transmitter symbol processor included in the transmitter; generating an extracted non-binary symbol set S''; converting the extracted non-binary symbol set S'' into LLRs; rearranging the LLRs to reverse the effect of interleaving performed by the transmitter; performing polarization decoding based on successive elimination on the rearranged LLRs and generating polarization decoded LLRs; rearranging the polarization decoded LLRs into a size of N r ×N cThe 2D matrix of polar decoder LLRs, where N r is the number of rows, N c is the number of columns; performing multiplication polarization decoding on the 2D matrix of the polarization decoder LLR, and generating information bits representing the original information bits sent by the transmitter.

[0031] According to any embodiment of the invention, the multiplicative quantization code decoding is performed in an iterative manner.

[0032] According to any embodiment of the present invention, the communication method further comprises: performing N-based r Parallel decoding of rapid serial elimination lists.

[0033] According to any embodiment of the present invention, the communication method further comprises: performing N-based c Parallel decoding of rapid serial elimination lists.

[0034] According to any embodiment of the present invention, the communication method further comprises: calculating the prior information L according to the 2D matrix of the polar decoder LLR apr (i,j) and the posterior information L app (i, j), where i and j represent the i-th row and j-th column of the 2D matrix of the polar decoder LLR.

[0035] According to any embodiment of the present invention, the communication method further comprises: calculating the a posteriori information L by the following equation: app (i,j):

[0036]

[0037] Where η is the iteration-related scaling factor, C * (j) is a candidate codeword, is the minimum path metric among the competing codewords for bit position j, PML0 is the minimum path metric associated with the most likely codeword in the list of candidate codewords provided to the SCL algorithm, is the candidate codeword with the minimum square distance in the candidate codeword list.

[0038] According to any embodiment of the present invention, the communication method further comprises: apr (i, j) and the posterior information L app (i, j) The formula for calculating the information bit is as follows:

[0039] L ex (i,j)=L app (i,j)-L apr (i,j)

[0040] Among them, L ex (i, j) is the extrinsic information representing the information bits on the i-th row and j-th column of the 2D matrix of the polar decoder LLR. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Other features and advantages of the present invention will become apparent through the following detailed description in conjunction with the accompanying drawings, in which:

[0042] FIG. 1 (Prior Art) shows a communication system for encoding and decoding polar codes having a length of N=8 and an information bit length of K=4;

[0043] FIG2 (Prior Art) shows a binary tree representation of polar code P(8,4);

[0044] Figure 3 shows a high-level functional block diagram of a transmitter included in a communication system according to various non-limiting embodiments of the present invention;

[0045] Figure 4 A high-level functional block diagram of a parallel hybrid product polar code (HPPC) encoder system included in a communication system according to various non-limiting embodiments of the present invention is shown;

[0046] Figure 5 shows a high-level functional block diagram of a receiver included in a communication system according to various non-limiting embodiments of the present invention;

[0047] Figure 6 shows a multiplication quantization code decoding process performed by a multiplication quantization code decoder according to various non-limiting embodiments;

[0048] Figure 7 shows a representative binary tree of an HPPC according to various non-limiting embodiments of the present invention;

[0049] Figure 8 shows the BER performance of 128K HPPC corresponding to a binary tree according to various non-limiting embodiments of the present invention;

[0050] Fig. 9 A flow chart illustrating a process for a communication method based on a hybrid multiplication quantization code according to various non-limiting embodiments of the present invention;

[0051] Fig.10 A flow chart illustrating a process for a communication method based on a hybrid multiplication quantization code according to various non-limiting embodiments of the present invention is shown.

[0052] It should be understood that in all drawings and corresponding descriptions, like features are identified by like reference numerals. In addition, it should also be understood that the drawings and the following descriptions are for illustration purposes only, and such disclosure does not limit the scope of the claims. DETAILED DESCRIPTION

[0053] The present invention aims to address at least some of the shortcomings of the current technology. In particular, the present invention describes a communication system and method based on hybrid multiplication quantization codes.

[0054] Unless otherwise defined or illustrated by the context, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong.

[0055] In the context of this specification, unless otherwise expressly provided, the words "first", "second", "third", etc. are used as adjectives and are used only to distinguish nouns that modify each other, rather than to describe any specific relationship between these nouns. Thus, for example, it should be understood that the use of the terms "first processor" and "third processor" is not intended to imply any particular order, type, chronological order, hierarchy or ranking (for example) between processors / processors, nor is their use (by itself) intended to imply that there must be any "second processor" in any given case. In addition, as discussed in other contexts herein, reference to a "first" element and a "second" element does not exclude that the two elements are the same actual real-world element. Thus, for example, in some cases, the "first" processor and the "second" processor may be the same software and / or hardware; in other cases, they may be different software and / or hardware.

[0056] It should be understood that when an element is described as being "connected" or "coupled" to another element, it may be directly or indirectly connected or coupled to the other element, and there may be intermediate elements. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intermediate elements. Other words used to describe the relationship between elements (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.) should be interpreted in a similar manner.

[0057] In the context of this specification, when one element is referred to as being “associated with” another element, in some embodiments, the two elements may be directly or indirectly linked, related, connected, coupled, the second element employs the first element, etc., without limiting the scope of the present invention.

[0058] The terms used herein are only used to describe specific representative embodiments and are not used to limit the present technology. The singular forms "a / a" and "the / the" used herein also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" used in this specification is used to illustrate the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0059] The implementation of the present technology has at least one of the above-mentioned objectives and / or aspects, but does not necessarily have all of these objectives and / or aspects. It should be understood that some aspects of the present technology are generated in an attempt to achieve the above-mentioned objectives, and these aspects may not meet the objectives and / or may meet other objectives not specifically described herein.

[0060] The examples and conditional language described in this article are mainly to help readers understand the principles of the present technology, rather than to limit its scope to these specific examples and conditions. It is understood that those skilled in the art can design various devices that, although not explicitly described or shown in this article, embody the principles of the present technology and are included in the spirit and scope of the present technology.

[0061] In addition, for ease of understanding, the following description may describe a relatively simplified implementation of the present technology. Those skilled in the art may understand that various implementations of the present technology may have greater complexity.

[0062] In some cases, useful examples of modifications to the present technology may also be listed. This is only for ease of understanding, not for defining the scope of the present technology or clarifying the limits of the present technology. These modifications are not an exhaustive list, and those skilled in the art may make other modifications while still remaining within the scope of the present technology. In addition, if no modification examples are listed, it should not be interpreted that modifications cannot be made and / or that the content described is the only way to implement the element of the present technology.

[0063] In addition, all statements herein describing the principles, aspects, and implementations of the present technology and specific examples thereof are intended to cover their structural and functional equivalents, whether they are currently known or developed in the future. Thus, for example, it will be understood by those skilled in the art that any block diagram herein is a conceptual view of an illustrative circuit that embodies the principles of the present technology. Similarly, it will be understood that any flow chart, flow chart, state transition diagram, pseudo code, etc. represent various processes that can be substantially represented in a computer-readable medium and thus executed by a computer or processor, whether or not such computer or processor is explicitly shown.

[0064] The functions of the various elements shown in the figure, including any functional blocks marked as "processor" or "processing unit", can be provided by using dedicated hardware and hardware capable of executing software related to appropriate software. When the processor provides functions, these functions can be provided by a single dedicated processor, a single shared processor, or multiple separate processors, some of which can be shared. In some embodiments of the present technology, the processor can be a general-purpose processor, such as a central processing unit (CPU), or a processor dedicated to a specific purpose, such as a graphics processing unit (GPU). In addition, the explicit use of the term "processor" or "controller" should not be interpreted as specifically referring to hardware capable of executing software, and may also implicitly include but are not limited to digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read-only memory (ROM), random access memory (RAM) and non-volatile memory for storing software. Other traditional and / or custom hardware may also be included.

[0065] In the context of the present invention, the expression "data" includes data of any nature or kind that can be stored in a database. Thus, data includes, but is not limited to, audiovisual works (images, films, recordings, presentations, etc.), data (location data, numerical data, etc.), texts (opinions, comments, questions, messages, etc.), documents, spreadsheets, etc.

[0066] Software modules or modules or units represented as software may be represented herein as flow chart elements or any combination of other elements indicating execution process steps and / or text descriptions. Such modules may be executed by hardware shown explicitly or implicitly.

[0067] With these basic principles, the present invention aims to address at least some of the shortcomings of the current technology. Specifically, the present invention describes a communication system and method based on hybrid multiplicative quantization codes.

[0068] FIG. 1 (Prior Art) shows a communication system 100 for encoding and decoding polar codes of length N=8 and information channel length K=4. As shown, the communication system 100 includes a transmitter 102 and a receiver 106. The transmitter 102 may include a binary polar encoder. The encoder uses a polar code of length N=2 nThe binary polar code P(N,K) with information channel length K is inputted as vector u={u0,u1,…,u N-1} is mapped to the output vector x = {x0, x1, ..., x N-1}, so that

[0069] x=uG N (1)

[0070] matrix is the generator matrix, where B N is the bit-reversal permutation matrix, is the n-th tensor power of F2, defined as:

[0071]

[0072] The symbol 0 is used to represent the all-zero submatrix, and F2 is defined as:

[0073]

[0074] matrix N polarized channels are synthesized from N independent copies of a given channel. Among the different polarized channels, the K most reliable channels are used to carry information. In other words, the input vector u = {u0, u1, ..., u N-1} consists of K information bits and NK fixed bits known to the receiver, called frozen bits. The index set of k information bits corresponding to the most reliable bit channel and the index set of kk frozen bits corresponding to the least reliable bit channel are expressed as and In order to distinguish frozen bits from information bits, a binary vector d = (d0, d1, ..., d N-1 ), such that:

[0075]

[0076] The reliability orders of different polarization channels can be obtained based on technologies such as density evolution (DE), Tal-Vardy method, and Gaussian approximation (GA).

[0077] The transmitter 102 transmits the output vector x={x0, x1, . . . , x N-1}. Output vector x = {x0, x1, …, x N-1} may be affected by noise. The receiver 106 receives a noisy codeword from the communication channel 104, and the receiver 106 calculates the log likelihood ratio (LLR) vector y={y0, y1, ..., y N-1}, and provide it to the polar code decoder. Then, the decoder estimates the input vector and output vector of the encoder, using and express.

[0078] In this regard, FIG. 2 (Prior Art) shows a binary tree representation 200 of polar code P(8,4). Typically, polar code decoders rely on successive cancelation (SC) decoding. SC decoding can basically be viewed as information exchange between nodes in the binary tree 200. Specifically, each node receives a signal with 2 s The soft information vector of elements is denoted as α. The vector α of the root node at the top of the tree 200 is the channel LLR vector, that is, y = {y0, y1, ..., y N-1}, and the α of other nodes is received from the parent node of other nodes. Except for the leaf nodes at the bottom of the tree 200, each node uses the soft information vector α to calculate the information toward its left child node by the following equation:

[0079]

[0080] in, is the information vector α towards the left child node l The i-th (0≤i≤2 s-1 -1) elements. Unless the node receives a binary vector β l , where the entry From its left child, otherwise the information towards the right child cannot be calculated. The information towards the right child is given by the following equation:

[0081]

[0082] in, The i-th (0≤i≤2) information vector pointing to the right child node s-1 -1) elements. Finally, after receiving the binary vector β from the right child node r After that, send a value of 2 to the parent node. s The binary vector β is calculated by the following equation:

[0083]

[0084] In the above equation, Represents the vector β land β r Element-wise addition modulo 2 of .

[0085] At each leaf node k, a hard decision is made on the soft LLRs received from the parent node to compute In addition, the binary vector β calculated at the root node is consistent with the estimated codeword same.

[0086] When applied to polar codes with short to medium length, the error correction performance of SC can be improved by using list-based decoding. The successive cancellation list (SCL) algorithm estimates the bit considering its possible values ​​0 and 1. At each estimation, the number of codeword candidates (paths) doubles. In order to limit the increase in the complexity of the algorithm, only a set of L codeword candidates is always remembered. Therefore, after each estimation, half of the paths are discarded. To this end, a path metric (PM) is associated with each path and updated at each new estimation. PM can be viewed as a cost function, allowing L paths with the smallest PM to survive. In LLR-based SCL, the path metric can be obtained by the following equation:

[0087]

[0088] The initial path metric is Symbol l is the path index, is the estimate of bit i on path l. The above metric basically means that whenever the decision is opposite to the sign of the bit LLR, the corresponding path is penalized by the absolute value of the LLR, otherwise, the penalty is zero.

[0089] A major issue with polar codes is the high decoding delay of SC-based decoding algorithms. Specifically, the sequential nature of the SC decoder and the SCL decoder significantly reduces the achievable throughput. More specifically, for long-length polar codes with known achievable capacity, the decoding delay is high even with a fast decoder, which makes these polar codes unattractive for low-latency applications.

[0090] Various non-limiting embodiments of the present invention may be based on hybrid product polarcode (HPPC). A product polarcode is a parallel concatenated code whose decoding process can be easily parallelized. The product polarcode has good error correction performance, high minimum distance, low latency and high throughput. In the product polarcode, vertical component codes and horizontal component codes may be selected as short-length polar codes with low latency. Although the product polarcode may benefit from low latency and high throughput decoding, due to the short length of the component codes, the bit error rate performance may be improved by using polar codes in addition to the product polarcode, especially in low signal-to-noise (SNR) regions. In this way, the optical fiber communication system may be improved in terms of latency and BER.

[0091] to this end, Figure 3 1 shows a high-level functional block diagram of a transmitter 300 integrated in a communication system 100 according to various non-limiting embodiments of the present invention. Figure 3 As shown, the transmitter 300 may include a preprocessor 304, a multiplication polarization code encoder 306, a polarization code encoder 308, an interleaver 310, a bit-to-symbol mapper 312, and a transmitter symbol processor 314. It should be noted that the transmitter 300 may include other modules and components, such as a processor and a controller. However, for the sake of simplicity, Figure 3 These modules and components are omitted.

[0092] The preprocessor 304 may be configured to receive the information bit stream 302, and the preprocessor 304 may reshape the information bits 302 into bits of size K and r1 ×K c1 and K r2 ×K c2 At least two rectangular information matrices M1 and M2, where in the rectangular information matrix M1, K r1 Can be the number of rows, K c1 It can be the number of columns. In the rectangular information matrix M2, K r2 Can be the number of rows, K c2 The preprocessor 304 may convert the rectangular information matrix M1 into a matrix of size K. r1 ×N c1 The rectangular matrix U c1 , where in the rectangular matrix U c1 In, K r1 Can be the number of rows, N c1 Can be the number of columns. In addition, N c1 The value can be greater than K c1 In a similar manner, the preprocessor 304 may transform the rectangular information matrix M2 into a matrix of size K r2 ×Nc2 The rectangular matrix U c2 , where in the rectangular matrix U c2 In, K r2 Can be the number of rows, N c2 Can be the number of columns. In addition, the value of 2 can be greater than K c2 .

[0093] Rectangular matrix U c1 and U c2 A plurality of bit channels may be included. Some of the bit channels may be information bit channels, and other bit channels may be frozen bit channels. In certain non-limiting embodiments, the frozen bit channels may refer to those channels that are least preferred for transmitting information bits, and the information bit channels may refer to preferred channels that may transmit information bits. It should be noted that how to select a given bit channel as an information bit channel or a frozen bit channel should not limit the scope of the present invention.

[0094] In order to transform the rectangular information matrices M1 and M2 into rectangular matrices U c1 and U c2 , the preprocessor 304 may place the information bits in the columns of the rectangular information matrices N1 and M2 in the rectangular matrices U c1 and U c2 The preprocessor 304 can convert the rectangular matrix U c1 and U c2 Forwarded to the multiplication quantization code encoder 306. The multiplication quantization code encoder 306 can use the column components of the multiplication quantization code to quantize the rectangular matrix U c1 and U c2 The encoding matrix can be expressed as the column encoding matrix X c1 and X c2 .

[0095] It should be noted that the component code rate in the multiplication code can be very low or very high. The binary tree of the low code rate and / or high code rate multiplication code can be significantly simplified, resulting in low decoding delay. In some non-limiting embodiments, the code rate R of the multiplication code can be less than a first threshold value, for example, the code rate R of the multiplication code can be less than 0.4. In other non-limiting embodiments, the code rate R of the multiplication code can be greater than a second threshold value, for example, the code rate R of the multiplication code can be greater than 0.6.

[0096] The multiplication positive code encoder 306 can provide the column encoding matrix X to the pre-processor 304 c1 and X c2 The preprocessor 304 can divide the sizes into K r1 ×N c1 and K r2 ×N c2The column encoding matrix X c1 and X c2 Convert to size N r1 ×N c1 and N r2 ×N c2 The rectangular matrix U r1 and U r2 , where N r1 It can be a rectangular matrix U r1 The number of rows, N r2 It can be a rectangular matrix U r2 In addition, B r1 The value can be greater than K r1 , N r2 The value can be greater than K r2 . Relative to the rectangular matrix U c1 and U c2 The frozen bit channel in the rectangular matrix U r1 and U r2 More frozen bit channels may be included. The preprocessor 304 may encode the column matrix X c1 and X c2 The information bits in the rows are placed in the rectangular matrix U r1 and U r2 The preprocessor 304 can convert the rectangular matrix U r1 and U r2 Forwarded to the multiplication quantization code encoder 306. The multiplication quantization code encoder 306 can use the row components of the multiplication quantization code to quantize the rectangular matrix U r1 and U r2 The encoding matrix can be expressed as a 2D product of the quantization code encoding matrices X1 and X2.

[0097] It is to be understood that, although the preprocessor 304 and the multiplication quantization code encoder 306 have been shown as different components, in certain non-limiting embodiments, the preprocessor 304 and the multiplication quantization code encoder 306 may be implemented as a single module. In other words, the preprocessor 304 may be included in the multiplication quantization code encoder 306 without limiting the scope of the present invention.

[0098] In certain non-limiting embodiments, the multiplicative polarization code encoder 306 may convert the 2D multiplicative polarization code encoding matrices X1 and X2 into a coded bit stream X′. The multiplicative polarization code encoder 306 may provide the coded bit stream X′ to the polar code encoder 308. The polar code encoder 308 may be configured to encode the coded bit stream X′ using a polar code.

[0099] In certain non-limiting embodiments, the output of the polar code encoder 308 may be expressed as follows:

[0100] C(P)=X′.G (1)

[0101] G is the generator matrix of the 2×2 polarization kernel, which can be expressed as the following equation:

[0102]

[0103] When performing polarization coding, the generator matrix G may polarize the bits so that the bit capacity of at least some of the bit channels associated with the polarization code encoder 308 becomes 1, and the capacity of the remaining channels may be zero. Based on the required code rate R, information bits may be transmitted on bit channels with high capacity (e.g., 1), and no information may be transmitted on bit channels with low capacity (e.g., 0). The output of the polarization code encoder 308 may be represented as a polarization coded bit stream X″.

[0104] exist Figure 3 The serial operation of encoding the information bits 302 has been shown in FIG. In various non-limiting embodiments, the multiplication quantization code encoding of the information bits 302 can be parallelized, wherein the multiplication quantization code encoding can be performed in parallel. Therefore, Figure 4 4 shows a parallel HPPC encoder system 400 according to various non-limiting embodiments of the present invention. As shown in the figure, the parallel HPPC encoder system 400 may include a plurality of preprocessors 404-1, 404-2, and 404-3, a plurality of multiplication polarization code encoders 406-1, 406-2, and 406-3, and a plurality of polar code encoders 408-1 and 408-2. It should be noted that the parallel HPPC encoder system 400 may include other components, however, for the sake of simplicity, the following are not described in detail. Figure 4 These components are omitted.

[0105] Each of the plurality of pre-processors 404-1, 404-2, and 404-3 may be configured to receive a portion of the information bits 402. For example, the pre-processor 404-1 may convert the portion of the received information bits 402 into a K-sized r1 ×K c1 The preprocessor 404-2 can convert the received information bits 402 into a rectangular information matrix M1 of size K. r2 ×K c2 The preprocessor 404-3 can convert the received information bits 402 into a rectangular information matrix M2 of size K. r3 ×K c3The rectangular information matrix M2. The multiplicative code encoder 406-1 and the preprocessor 404-1 can be used together to convert the rectangular information matrix M1 into a 2D multiplicative code encoding matrix X1, and then into a coded bit stream X′1. In a similar manner, the multiplicative code encoder 406-2 and the preprocessor 404-2 can be used together to convert the rectangular information matrix M2 into a 2D multiplicative code encoding matrix X2, and then into a coded bit stream X′2. In addition, the multiplicative code encoder 406-3 and the preprocessor 404-3 can be used together to convert the rectangular information matrix M3 into a 2D multiplicative code encoding matrix X3, and then into a coded bit stream X′3.

[0106] The multiplicative polarization code encoder 406-1 and the polarization code encoder 406-2 may forward the coded bit stream X'1 and the coded bit stream X'2 to the polarization code encoder 408-1. The multiplicative polarization code encoder 406-3 may forward the coded bit stream X'3 to the polarization code encoder 408-2.

[0107] The polar code encoder 408-1 may perform polar code-based encoding on the coded bit stream X′1 and the coded bit stream X′2, and may generate a polar code bit stream X″1. The polar code encoder 408-1 may forward the polar code bit stream X″1 to the polar code encoder 408-2. The polar code encoder 408-2 may perform polar code-based encoding on the polar code bit stream X″1 and the coded stream X′3, and may generate a polar code bit stream X″1. Therefore, with the aid of the parallel HPPC encoder system 400, the multiplication polarization code encoding of the information bits 402 may be further parallelized.

[0108] Back to Figure 3 Optionally, the polar code encoder 308 may forward the polarization coded bit stream X″ to the interleaver 310. The interleaver 310 may rearrange the polarization coded bit stream X″ to generate a rearranged polarization coded bit stream X″′. The interleaver 310 may shuffle the polarization coded bit stream X″ in a predefined manner. For example, if there are 16 coded information bits, the rearranged coded polarization coded bits X″′ may have a sequence X″′=X1,X9,X2,X 10 …X8,X 16 It should be noted that how the interleaver 310 rearranges the polarization coded bits X″ should not limit the scope of the present invention.

[0109] Optionally, the interleaver 310 may forward the rearranged encoded polarization coded bits X'' to a bit-to-symbol mapper 312. The bit-to-symbol mapper 312 may map the rearranged encoded polarization coded bits X''' to a non-binary symbol set S according to a suitable pulse amplitude modulation technique. In a non-limiting embodiment, the bit-to-symbol mapper 312 may rely on a 4-PAM technique. For example, the polarization coded information bits X1 and X9 may be mapped to a non-binary symbol S1, and the polarization coded information bits X2 and X9 may be mapped to a non-binary symbol S2. 10 It can be mapped to a non-binary symbol S2, and so on. Since the mapping technique can be 4-PAM, the different symbols can be –3, –1, +1, and +3. The corresponding bit representation can be: symbol –3 is 00, symbol –1 is 01, symbol +1 is 10, and symbol +3 is 11.

[0110] Alternatively, the bit-to-symbol mapper 312 may forward the set of non-binary symbols S to the transmitter symbol processor 314 for processing and transmission. The transmitter symbol processor 314 may process the non-binary symbols S to generate a processed set of non-binary symbols S′. In certain non-limiting embodiments, the processing of the processed non-binary symbols S may involve various operations such as modulating the symbols to a high-frequency carrier, or any operation that prepares the non-binary symbols S for transmission to the transmission medium 316. It should be noted that the transmission medium 316 may be a wireless medium, a wired medium, or an optical medium, without limiting the scope of the present invention. According to the transmission medium 316, the transmitter symbol processor 314 may process the non-binary symbols S. In addition, in certain non-limiting embodiments, the transmitter symbol processor 314 may perform an upsampling operation on the non-binary symbols S before modulation. The transmitter symbol processor 314 may send the processed non-binary symbols S′ to the transmission medium 316.

[0111] According to various non-limiting embodiments of the present invention, the communication system 100 may further include a receiver 500, such as Figure 5 As shown in the figure, the receiver 500 may include a receiver symbol processor 502, a symbol to LLR converter 504, a deinterleaver 506, a polar decoder 508, and a multiplication polarization code decoder 510. It should be noted that the receiver 500 may include other modules and components, such as a processor and a controller. However, for the sake of simplicity, Figure 5 These modules and components are omitted.

[0112] The receiver 500 may receive the processed non-binary symbols S′ from the transmission medium 316. The receiver symbol processor 502 may process the received processed non-binary symbols S′ to reverse the operations performed by the transmitter symbol processor 314. For example, the receiver symbol processor 502 may perform downsampling, demodulation, etc. The receiver symbol processor 502 generates a set of extracted non-binary symbols S″.

[0113] The receiver symbol processor 502 may forward the extracted non-binary symbol S″ to a symbol-to-LLR converter 504 . The symbol-to-LLR converter 504 may convert the extracted non-binary symbol S″ into a set of LLRs. It should be noted that the LLRs may correspond to the information bits 302 .

[0114] Symbol to LLR converter 504 may forward the LLRs to deinterleaver 506. Deinterleaver 506 may rearrange the LLRs to reverse the effect of the interleaving performed by interleaver 310.

[0115] Deinterleaver 122 may forward the M rearranged LLRs to polar decoder 508. Polar decoder 508 may perform SC-based polar decoding on the rearranged LLRs and may generate polar decoded LLRs. In addition to polar decoding, polar decoder 508 may be configured to rearrange the polar decoded LLRs into a 2D matrix. Polar code decoder 508 may provide the 2D matrix of polar decoder LLRs to multiplication code decoder 510. Multiplication code decoder 510 may perform multiplication decoding in an iterative manner in conjunction with polar decoder 508.

[0116] Figure 6 FIG. 6 shows a multiplication quantization code decoding process 600 performed by the multiplication quantization code decoder 508 according to various non-limiting embodiments. As shown in the figure, N r and N c can represent the number of rows and columns of the 2D matrix of the polar decoder LLR respectively. Let (i, j), The elements on the i-th row and j-th column of the 2D matrix representing the polar decoder LLR, L in (i, j) may be the LLR of the (i, j) bit received from the parent node of the product code in the binary tree. In the iterative decoding of the polar product code, the multiplication polarization code decoder 510 may be LLR of the (i, j) bit received from the parent node of the product code in the binary tree. apr (i, j) is used as a priori information and N is performed on the rows of the 2D matrix of the polar decoder LLR. r Parallel Fast SCL Decoding. To perform iterative decoding on columns and rows, the soft decision output (extrinsic information) can be propagated between column decoding and row decoding. In other words, the multiplicative quantization code decoder 510 can determine the a posteriori information L app (i,j), and use the posterior information Lapp (i, j) represents the extrinsic information of information bit 512 by the following equation:

[0117] L ex (i,j)=L app (i,j)-L apr (i,j) (3)

[0118] In some non-limiting embodiments, the multiplication quantization code decoder 510 may convert the prior information L apr (i,j) is used as the N column of the 2D matrix of the polar decoder LLR c The multiplication quantization code decoder 510 can use the above external information to update the prior information L apr (i, j), the multiplication code decoder 510 can update the prior information L by the following equation apr (i,j):

[0119] L apr (i,j)=L in (i,j)+γL ex (i,j) (4)

[0120] In addition, the multiplication quantization code decoder 510 can calculate the posterior information L according to the following simplified method: app (i,j):

[0121]

[0122] where γ and η are iteration-dependent scaling factors that can be updated by simulation in each iteration. For each bit position j, the set It can be composed of candidate codewords in the list, and the jth bit of the candidate codeword can be expressed as candidate codeword C * (j) The j-th bit of the minimum distance codeword is different. The codeword with the minimum square distance in can be represented by C * Represented as a candidate codeword PML0 can be the minimum path metric belonging to the most likely codeword given by the SCL algorithm, It can be the minimum path metric among the competing codewords for bit position j.

[0123] It should be noted that in the simplified method represented by equation (5), the path metric provided by the SCL decoder included in the multiplication quantization code decoder 510 can be used to calculate the a posteriori information, without calculating the relationship between the lth candidate codeword and the input a priori vector L as required by the conventional technology. apr The square distance between (i,j). This simplified method can reduce the complexity.

[0124] Perform N on the columns of the 2D matrix of polar decoder LLRs c After parallel fast SCL decoding, one full iteration 602 may be completed. Based on the above equation, in some non-limiting embodiments, after the first iteration 602, the multiplication quantization code decoder 510 may update the prior information L apr (i, j), for the next round of iteration 604 and N execution of the row r Parallel fast SCL decoding. In some non-limiting embodiments, a maximum number of iterations I can be predefined in the multiplication quantization code decoder 510. max In other non-limiting embodiments, the multiplicative quantization code decoder 510 may be combined with an early termination criterion. In the event that the estimated codewords for horizontal decoding and vertical decoding are the same in an iteration, the multiplicative quantization code decoder 510 may terminate the decoding operation.

[0125] The multiplicative quantization code decoder 510 may generate information bits 512 representing the original information bits 302 .

[0126] Figure 7 A representative binary tree 700 of HPPC according to various non-limiting embodiments of the present invention is shown. As shown, the binary tree 700 may include a parent node 702 and two child nodes 704 and 706. The parent node 702 may be associated with a polar code, and the child nodes 704 and 706 may be associated with a multiplicative polar code. In one example, the dimension of the child node 704 may be 128×256, and the dimension of the child node 706 may be 256×256.

[0127] Figure 8 BER performance 800 of 128K HPPC corresponding to binary tree 700 according to various non-limiting embodiments of the present invention is shown. BER performance 800 may include curves 802, 804, and 806. Curve 802 may correspond to 128K conventional polar codes. To evaluate the BER performance of HPPC, in one embodiment, the number of iterations of subnode 704 with a dimension of 128×256 and subnode 706 with a dimension of 256×256 may be set to 4 and 5, respectively. In addition, the list size of subnodes 704 and 706 may both be set to 4. In another embodiment, the number of iterations of subnodes 704 and 706 may be increased to 5 and 6. In this embodiment, the list size of the row component may be set to 8 for the first 2 iterations, and the list size may be set to 4 for the remaining iterations. Compared to curve 802 corresponding to conventional polar codes, the BER performance shown in curves 804 and 806 corresponding to different embodiments of HPPC may have better performance.

[0128] It should be noted that the delay of the polar code decoded by the fast SC-based decoder is proportional to the number of leaf nodes in the binary tree representation of the code. In the above embodiment, for the polar code, the number of leaf nodes considering special nodes is 3546, while for the row component and column component of the child node 704 and the row component and column component of the child node 706, the number of special nodes is 41, 6, 16 and 12 respectively. Therefore, if the iterative decoding of HPPC is considered, the delay of HPPC is about one order of magnitude lower than the delay of the polar code.

[0129] Therefore, it can be said that the delay of various embodiments of the present invention is improved compared to the delay associated with traditional polar codes and is suitable for high throughput applications. Unlike traditional polar codes, the HPPC-based technology has parallel decoding capabilities. In addition, unlike traditional polar codes, the HPPC-based technology may have a steep BER slope due to a larger minimum distance. Compared with traditional long-length polar codes, the HPPC-based technology reduces the error propagation problem, making the HPPC technology a better candidate for soft inner code in the cascade scheme. In addition to the above benefits, the HPPC-based technology can also benefit from the fast SC decoding algorithm of the component code, which is based on the concept of special nodes.

[0130] Fig. 9 A flow chart of a process 900 for a hybrid multiplication quantization code based communication method is shown according to various non-limiting embodiments of the present invention.

[0131] As shown, the process 900 begins at step 902, where the transmitter receives an information bit stream. As described above, the pre-processor 304 included in the receiver 300 can be used to receive the information bit stream 302.

[0132] Process 900 proceeds to step 904, where the transmitter reshapes the information bit stream into a size of at least K r1 ×K c1 The first rectangular information matrix M1 and size K r2 ×K c2 The second rectangular information matrix M2, where in the rectangular information matrices M1 and M2, K r1 and K r2 are the number of rows, K c1 and K c2 As mentioned above, the preprocessor 304 included in the transmitter 300 can be used to reshape the information bit stream 302 into columns of size K and r1 ×K c1 and K r2 ×K c2 Rectangular information matrices M1 and M2.

[0133] The process proceeds to step 906, where the transmitter uses the multiplication code to convert the rectangular information matrices M1 and M2 into 2D multiplication code encoding matrices X1 and X2, respectively, where the sizes of the 2D multiplication code encoding matrices X1 and X2 are N, respectively. r1 ×N c1 and N r2 ×N c2 , where, in the encoding matrices X1 and X2, N r1 and N r2 are the number of rows, N c1 and N c1 As mentioned above, the multiplication code encoder 306 included in the transmitter 300 can be used to convert the rectangular information matrices M1 and M2 into 2D multiplication code encoding matrices X1 and X2 using multiplication code, and the sizes of the 2D multiplication code encoding matrices X1 and X2 are N, respectively. r1 ×N c1 and N r2 ×N c2 .

[0134] The process proceeds to step 908, where the transmitter converts the 2D multiplication quantization code encoding matrices X1 and X2 into a coded bit stream X'. As described above, the multiplication quantization code encoder 306 included in the transmitter 300 can convert the 2D multiplication quantization code encoding matrices X1 and X2 into a coded bit stream X'.

[0135] Finally, at step 910, the transmitter encodes the coded bit stream X′ into a polar coded bit stream X″ using the polar code. As described above, the polar code encoder 308 included in the transmitter 300 can be used to encode the coded bit stream X′ into a polar coded bit stream X″ using the polar code.

[0136] Fig.10 A flow chart of a process 1000 for a hybrid multiplication quantization code based communication method is shown according to various non-limiting embodiments of the present invention.

[0137] As shown, the process 1000 begins at step 1002, where the receiver receives a processed set of non-binary symbols S' from the transmitter. As previously described, the receiver 500 may receive the processed non-binary symbols S' from the transmission medium 316. The processed non-binary symbols S' may be sent by the transmitter 300 via the transmission medium 316.

[0138] The process 1000 proceeds to step 1004, where the receiver processes the received processed non-binary symbol set S' and reverses the operations performed by the transmitter symbol processor included in the transmitter. As previously described, the receiver symbol processor 502 included in the receiver 500 can be used to process the received processed non-binary symbol set S' and reverse the operations performed by the transmitter symbol processor included in the transmitter 500, and can be used to process the received processed non-binary symbol set S' and reverse the operations performed by the transmitter symbol processor 314 included in the transmitter 300.

[0139] Process 1000 proceeds to step 1006, where the receiver generates a set of extracted non-binary symbols S". As described above, the receiver symbol processor 502 included in the receiver 500 may be used to generate the set of extracted non-binary symbols S".

[0140] Process 1000 proceeds to step 1008, where the receiver converts the extracted non-binary symbol set S" into LLRs. As previously described, the symbol to LLR converter 504 included in the receiver 500 may be used to convert the extracted non-binary symbol S" into a set of LLRs.

[0141] Process 1000 proceeds to step 1010 where the receiver rearranges the LLRs to reverse the effect of the interleaving performed by the transmitter. As described above, deinterleaver 506 included in receiver 500 may be used to rearrange the LLRs to reverse the effect of the interleaving performed by transmitter 300.

[0142] Process 1000 proceeds to step 1012, where the receiver performs polarization decoding based on successive cancellation on the rearranged LLRs and generates polarization-decoded LLRs. As described above, polar code decoder 508 included in receiver 500 can be used to perform polarization decoding based on successive cancellation on the rearranged LLRs and generate polarization-decoded LLRs.

[0143] Process 1000 proceeds to step 1014, where the receiver rearranges the polar-decoded LLRs into a size N r ×N c The 2D matrix of polar decoder LLRs, where N r is the number of rows, N c As mentioned above, the polar code decoder 508 included in the receiver 500 can be used to rearrange the polar decoded LLR into a size of N r ×N c The 2D matrix of polar decoder LLRs.

[0144] Finally, at step 1016, the receiver performs multiplication quantization decoding on the 2D matrix of polar decoder LLRs and generates information bits representing the original information bits sent by the transmitter. As described above, the multiplication quantization code decoder 510 included in the receiver can be used to perform multiplication quantization decoding on the 2D matrix of polar decoder LLRs and generate information bits 512 representing the original information bits 302 sent by the transmitter 300.

[0145] It should be understood that the operation and functionality of the communication system 100, the constituent components and associated processes may be implemented by any one or more of hardware-based, software-based and firmware-based elements. Such operational alternatives do not limit the scope of the present invention in any way.

[0146] It should also be understood that although the embodiments presented herein have been described with reference to specific features and structures, it is apparent that various modifications and combinations may be made without departing from these disclosures. Therefore, the specification and drawings are only to be regarded as illustrations of the implementations or embodiments discussed and their principles as defined by the appended claims, and are intended to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention.

Claims

1. A communication system, characterized in that: include: A transmitter, comprising a multiplication positive code encoder, wherein the multiplication positive code encoder is used to: receiving an information bit stream; Reshape the information bit stream into a size of at least K r1 ×K c1 The first rectangular information matrix M1 and size K r2 ×K c2 A second rectangular information matrix M2, wherein in the rectangular information matrices M1 and M2, K r1 and K r2 are the number of rows, K c1 and K c2 are the number of columns respectively; The rectangular information matrices M1 and M2 are converted into 2D multiplication code encoding matrices X1 and X2 respectively using multiplication code, wherein the 2D multiplication code encoding matrix X 12 and X2 are N respectively. r1 ×N c1 and N r2 ×N c2 , where, in the encoding matrices X1 and X2, N r1 and N r2 are the number of rows, N c1 and N c2 are the number of columns respectively; Convert the 2D multiplication quantization code encoding matrices X1 and X2 into an encoding bit stream X′; A polar code encoder is used to encode the coded bit stream X' into a polar coded bit stream X" using the multiplicative polarization code.

2. The communication system according to claim 1, characterized in that Also includes: an interleaver, configured to rearrange the polarization coded bit stream X″ to generate a rearranged polarization coded bit stream X″′; a bit-to-symbol mapper, configured to map the rearranged polar coded bit stream X′″ into a non-binary symbol set S; The transmitter symbol processor is used to process the non-binary symbol set S to generate a processed non-binary symbol set S′, and send the processed non-binary symbol set S′ to a receiver.

3. The communication system according to claim 1 or 2, characterized in that: A code rate R of the multiplication quantization code is less than a first threshold.

4. The communication system according to claim 1 or 2, characterized in that: A code rate R of the multiplication quantization code is greater than a second threshold.

5. A communication system, characterized in that: include: Receiver, comprising: Receiver symbol processor for: receiving a processed non-binary symbol set S′ from a transmitter; processing said received processed set of non-binary symbols S′ to reverse said operation performed by a transmitter symbol processor included in said transmitter; Generate a set of extracted non-binary symbols S″; A symbol to log-likelihood ratio (LLR) converter, configured to convert the extracted non-binary symbol set S″ into LLR; a deinterleaver for rearranging the LLRs to reverse the effect of the interleaving performed by the transmitter; Polar decoder for: performing polarization decoding based on successive cancellation on the rearranged LLRs and generating polarization-decoded LLRs; The polar decoded LLRs are rearranged into a size of N r ×N c The 2D matrix of polar decoder LLRs, where N r is the number of rows, N c is the number of columns; A multiplicative quantization decoder is configured to perform multiplicative quantization decoding on the 2D matrix of the polar decoder LLRs to generate information bits representing original information bits transmitted by the transmitter.

6. The communication system according to claim 5, characterized in that: The multiplicative quantization code decoder performs the multiplicative quantization code decoding in an iterative manner.

7. The communication system according to claim 5 or 6, characterized in that: The multiplicative polarization code decoder performs N-based multiplication on the rows of the 2D matrix of the polar decoder LLRs. r Parallel decoding of rapid serial elimination lists.

8. The communication system according to any one of claims 5 to 7, characterized in that: The multiplication code decoder performs N-based multiplication on the columns of the 2D matrix of the polar decoder LLRs. c Parallel decoding of rapid serial elimination lists.

9. The communication system according to any one of claims 5 to 8, characterized in that: The multiplication code decoder calculates the prior information L according to the 2D matrix of the polar decoder LLR apr (i,j) and the posterior information L app (i, j), where i and j represent the i-th row and j-th column of the 2D matrix of the polar decoder LLR.

10. The communication system according to claim 9, characterized in that: The multiplication quantization code calculates the a posteriori information L by the following equation app (i,j): Where η is the iterative correlation scaling factor, C*(j) is the candidate codeword, is the minimum path metric among the competing codewords for bit position j, PML0 is the minimum path metric associated with the most likely codeword in the list of candidate codewords provided to the SCL algorithm, is the candidate codeword with the minimum square distance in the candidate codeword list.

11. The communication system according to claim 9, characterized in that: The multiplication quantization code decoder is based on the prior information L apr (i, j) and the posterior information L app (i, j) The equation for calculating the information bit is as follows: L ex (i,j)=L app (i,j)-L apr (i,j) Among them, L ex (i, j) is the extrinsic information representing the information bits on the i-th row and j-th column of the 2D matrix of the polar decoder LLR.

12. A communication method, characterized in that: include: receiving an information bit stream; Reshape the information bit stream into a size of at least K r1 ×K c1 The first rectangular information matrix M1 and size K r2 ×K c2 A second rectangular information matrix M2, wherein in the rectangular information matrices M1 and M2, K r1 and K r2 are the number of rows, K c1 and K c2 are the number of columns respectively; The rectangular information matrices M1 and M2 are converted into 2D multiplication quantization code encoding matrices X1 and X2 respectively using multiplication quantization codes, wherein the sizes of the 2D multiplication quantization code encoding matrices X1 and X2 are N respectively. r1 ×N c1 and N r2 ×N c2 , where, in the encoding matrices X1 and X2, N r1 and N r2 are the number of rows, N c1 and N c2 are the number of columns respectively; Convert the 2D multiplication quantization code encoding matrices X1 and X2 into an encoding bit stream X′; The coded bit stream X′ is encoded into a polar coded bit stream X″ using the polar code.

13. The communication method according to claim 12, characterized in that: Also includes: Rearranging the polarization coded bit stream X″ to generate a rearranged polarization coded bit stream X″′; Mapping the rearranged polar coded bit stream X″′ into a non-binary symbol set S; Processing the non-binary symbol set S and generating a processed non-binary symbol set S′; The processed non-binary symbol set S' is sent to a receiver.

14. The communication method according to claim 12 or 13, characterized in that: A code rate R of the multiplication quantization code is less than a first threshold.

15. The communication method according to claim 12 or 13, characterized in that: A code rate R of the multiplication quantization code is greater than a second threshold.

16. A communication method, characterized in that: include: receiving a processed non-binary symbol set S′ from a transmitter; processing said received processed set of non-binary symbols S′ and reversing said operations performed by a transmitter symbol processor included in said transmitter; Generate a set of extracted non-binary symbols S″; Converting the extracted non-binary symbol set S″ into LLR; rearrange the LLRs to reverse the effect of the interleaving performed by the transmitter; performing polarization decoding based on successive cancellation on the rearranged LLRs and generating polarization-decoded LLRs; The polar decoded LLRs are rearranged into a size of N r ×N c The 2D matrix of polar decoder LLRs, where N r is the number of rows, N c is the number of columns; A multiplicative polarization decoding is performed on the 2D matrix of the polar decoder LLRs and information bits representing original information bits transmitted by the transmitter are generated.

17. The communication method according to claim 16, characterized in that: The multiplicative quantization code decoding is performed in an iterative manner.

18. The communication method according to claim 16 or 17, characterized in that: Also includes: Perform N-based r Parallel decoding of rapid serial elimination lists.

19. The communication method according to any one of claims 16 to 18, characterized in that: Also includes: Perform N-based c Parallel decoding of rapid serial elimination lists.

20. The communication method according to any one of claims 16 to 19, characterized in that: Also includes: The prior information L is calculated based on the 2D matrix of the polar decoder LLR apr (i,j) and the posterior information L app (i, j), where i and j represent the i-th row and j-th column of the 2D matrix of the polar decoder LLR.

21. The communication method according to claim 20, characterized in that: Also includes: The posterior information L is calculated by the following equation app (i,j): Where η is the iterative correlation scaling factor, C*(j) is the candidate codeword, is the minimum path metric among the competing codewords for bit position j, PML0 is the minimum path metric associated with the most likely codeword in the list of candidate codewords provided to the SCL algorithm, is the candidate codeword with the minimum square distance in the candidate codeword list.

22. The communication method according to claim 20, characterized in that: Also includes: According to the prior information L apr (i, j) and the posterior information L app (i, j) The formula for calculating the information bit is as follows: L ex (i,j)=L app (i,j)-L apr (i,j) Among them, L ex (i, j) is the extrinsic information representing the information bits on the i-th row and j-th column of the 2D matrix of the polar decoder LLR.

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