Communication interface controller with output monitoring

Abstract

The invention relates to a communication interface controller with output monitoring. In described examples, an integrated circuit (102) includes a first pin (130), a second pin (132), a processor (114), a bus monitor (120), a clock circuit (112), and a transceiver (118). The processor (114) provides instructions to the transceiver (118) and the bus monitor (120) indicating an indicated target address, a read / write flag, and a memory address. The transceiver (118) provides a clock signal to the first pin (130) and the bus monitor (120), and provides a message to the second pin (132) and the bus monitor (120) such that the message includes a destination address of message transmission, the read / write flag, and the memory address. The bus monitor (120) compares the indicated target address to a target address of the message transmission and provides a signal to the processor (114) in response to the comparison.

Description

Technical Field

[0001] This application generally relates to controller-target communication interfaces, and more particularly, to detecting output faults of a controller. Background Art

[0002] Inter-Integrated Circuit (I 2 C, pronounced I-squared-C and alternatively referred to as I2C or IIC) is a synchronous, multi-controller / multi-target, single-ended serial communication bus. In some instances, I 2 C is used to communicatively couple integrated circuits (ICs) (e.g., low-speed peripheral ICs) to a processor or microcontroller. In some instances, I 2 C enables short-distance communication between ICs attached to each other on a printed circuit board (PCB). In some instances, I 2 C is used to connect ICs for industrial or automotive applications. Summary of the Invention

[0003] In the described example, an integrated circuit includes a first pin, a second pin, a processor, a bus monitor, a clock circuit, and a transceiver. The processor provides instructions indicating a target address, a read / write flag, and a memory address to the transceiver and the bus monitor. The transceiver provides a clock signal to the first pin and the bus monitor, and provides a message to the second pin and the bus monitor such that the message includes the target address to which the message is being sent, the read / write flag, and the memory address. The bus monitor compares the indicated target address with the target address to which the message is being sent, and provides a signal to the processor in response to the comparison. Description of the Drawings

[0004] Figure 1 is a functional block diagram of an example I2C system.

[0005] Figure 2 is a functional block and circuit diagram of a second example I2C system.

[0006] Figure 3A is Figure 1 a bit structure of an example I2C communication between a controller microcontroller unit and a target for implementing a write command.

[0007] Figure 3B is Figure 1 a bit structure of an example I2C communication between a controller microcontroller unit and a target for implementing a read command.

[0008] Figure 4 is a timing diagram showing the timing of a serial clock signal and a serial data signal for providing a start condition signal and a stop condition signal.

[0009] Figure 5 It is a functional block diagram of a third instance I2C system.

[0010] Figure 6 It is a process 600 for the controller MCU used to operate Figure 1 thereof. Detailed implementation

[0011] In some instances, the I2C system 100 includes at least one controller MCU 102 having a transceiver 118 coupled via a serial data (SDA) bus 108 to one or more targets 104a, 104b, ……, 104N. The transceiver 118 receives instructions from the CPU 114 and, in accordance with the instructions, the transceiver 118 transmits a serial data stream to the serial data (SDA) bus 108. The serial data stream contains various information, including an address for identifying one of the targets such that the addressed target can respond appropriately. To reduce the likelihood of inaccurate target addressing by the MCU 102, the controller MCU 102 also includes a bus monitor 120 that compares the target address indicated by the CPU 114 instruction with the corresponding target address indicated by the transceiver 118 directed by the CPU to check for proper addressing of the target. If a target address mismatch is detected, error mitigation is implemented.

[0012] Herein, some different but related structures or signals have reference numerals in the [digit][letter] format, such as targets 104a, 104b, …… 104N and controllers 202a, 202b, …… 202M. In some instances, these structures or signals using [digit] and not using [letter] are generally referred to singularly or as a group, such as target 104 and controller 202. Also, the same reference numeral or other reference designator is used in the drawings to indicate features that are structurally and / or functionally related.

[0013] Figure 1 It is a functional block diagram of an example I2C system 100. The I2C system 100 includes a controller microcontroller unit (controller MCU) 102 serving as the controller 202 of the I2C system 100 (see Figure 2 )), a plurality of target ICs (targets) 104 serving as targets of the I2C system 100, a serial clock (SCL) bus 106, and an SDA bus 108. There are N targets 104, including a first target (target 1) 104a, a second target (target 2) 104b to an Nth target (target N) 104N. Communication occurs between the controller MCU 102 and any one of the targets 104 via the SDA bus 108. As will be seen later from Figure 3ATo elaborate, such communication is provided by packets of serial data on the SDA bus 108, where different groups of serial data can provide, for example, a single control bit (e.g., read, write, start, stop, acknowledge) or multiple data bits (e.g., target address).

[0014] The controller MCU 102 includes an I2C unit 110, a clock 112 that provides a clock signal at a base frequency, a central processing unit (CPU) 114, and an event handler 116. The I2C unit 110 includes an I2C transceiver 118 and a bus monitor 120. The I2C transceiver 118 includes a processor 122 and a first memory 124. The bus monitor 120 includes a comparator 126 and a second memory 128.

[0015] The output of the clock 112 is connected to the clock input of the I2C transceiver 118. The data terminals of the CPU 114 are connected via a CPU bus to the data terminals of the I2C transceiver 118 and the first data input of the bus monitor 120. The ignore condition output of the I2C transceiver 118 is connected to the ignore condition input of the bus monitor 120. The SCL terminal of the I2C transceiver 118 is connected to the SCL pin 130 of the controller MCU 102 and the clock input of the bus monitor 120. The SDA terminal of the I2C transceiver 118 is connected to the SDA pin 132 of the controller MCU 102 and the second data input of the bus monitor 120. The error interrupt output of the bus monitor 120 is connected to the input of the event handler 116, and the bus monitor 120 provides an asserted or de-asserted error interrupt signal from the error interrupt output. The asserted error interrupt signal corresponds to an I2C addressing fault detected by the bus monitor 120.

[0016] The SCL pin 130 is connected to the SCL bus 106. The SDA pin 132 is connected to the SDA bus 108. The target 104 includes a clock input and a data input respectively. The corresponding clock input of the target 104 is connected to the SCL bus 106, and the corresponding data input of the target 104 is connected to the SDA bus 108. Regarding Figure 2 An example structure and functionality are described in which the controller MCU 102 applies signals to the SDA bus 108 and monitors the signals on the SDA bus.

[0017] Figure 2 is a functional block and circuit diagram of a second instance I2C system 200 having a plurality of controllers 202 and a plurality of targets 104 (i.e., a multi-controller 202 and multi-target 104 topology). Figure 2An example circuit system for determining the logical value of bits in an SDA signal is also shown. Each of the controller 202 and the target 104 is connected to the SCL bus 106 and the SDA bus 108 respectively. The SDA bus 108 includes a voltage source 204 that provides a source voltage and a resistor 206. The I2C system 200 also includes a ground 208.

[0018] There are M controllers 202. The controller 202 includes a first controller (controller 1) 202a, a second controller (controller 2) 202b to an Mth controller (controller M) 202M. In some examples, each of the controllers 202 may correspond to the controller MCU 102. Each of the controllers 202 is connected to the SCL bus 106 and the SDA bus 108.

[0019] The first controller 202a is shown and described on behalf of the controller 202. In some examples, the first controller 202a corresponds to the controller MCU 102. The first controller 202a includes a buffer 210, an n-channel metal-oxide-semiconductor field-effect transistor (NMOS) 212, and a ground pin 214.

[0020] The SDA pin 132 of the first controller 202a is connected to the input of the buffer 210 and the drain of the NMOS 212. The output of the buffer 210 is connected to the data input of the I2C transceiver 118, and the gate of the NMOS 212 is connected to the data output of the transceiver 118. This data input and data output of the I2C transceiver 118 correspond to the SDA terminal of the I2C transceiver 118 described with respect to Figure 1 The source of the NMOS 212 is connected to the ground 208 via the ground pin 214.

[0021] The SDA bus 108, which is a serial interface, is connected to provide two different logical states. In this regard, the SDA bus 108 is connected to the voltage source 204 via the resistor 206 such that the SDA bus 108 is defaultly pulled high (pulled up to the source voltage), where the high represents the first of the two different logical states (e.g., logical zero). The I2C transceiver 118 can connect the SDA bus 108 to the ground 208 by providing a gate voltage to the NMOS 212 to turn on the NMOS 212. Thus, turning on the NMOS 212 pulls the SDA bus 108 to a low (ground) voltage, where the low represents the second of the two different logical states (e.g., logical one). The I2C transceiver 118 can monitor the SDA signal on the SDA bus 108 via the SDA pin 132 and the buffer 210 by turning off the NMOS 212 and thus monitor the represented logical value. This is called the first controller 202a releasing the SDA bus 108.

[0022] Each of the controllers 202 may send an SDA signal representing a read or write command to the SDA bus 108. Further description of the SDA signal is provided with respect to Figure 3A and 3B and 4. The read or write command will be executed by the target 104 corresponding to the target address included in the SDA signal stream. If multiple controllers 202 send SDA signals simultaneously, an arbitration process described below is used to determine the controller for which the read or write command is executed first. In some instances, the controller 202 may also function as the target 104.

[0023] In some instances, the CPU 114 knows the target addresses of the targets 104 connected to the SCL bus 106 and the SDA bus 108. In some instances, a processor external to the I2C system 200 that uses the controller MCU 102 to communicate with the target 104 (e.g., by sending instructions to the controller MCU 102 to be converted into messages sent by the I2C transceiver 118 to the corresponding target 104) knows the target addresses of the targets 104 connected to the SCL bus 106 and the SDA bus 108. The target addresses are determined by system-level configuration.

[0024] Returning to Figure 1 , the CPU 114 controls the I2C transceiver 118 to control the execution of read commands and write commands by the specified target 104. Thus, each target 104 may monitor the SDA bus 108 to detect commands issued by the I2C transceiver 118 and, if addressed to a particular target 104, execute the command accordingly. For both read commands and write commands, the CPU 114 provides instructions that include an indication of whether a read or write is to be performed, an indication of the target address of the corresponding one of the targets 104, the target memory address within the indicated target 104, and the data to be written to the target memory address within the indicated target 104. The target address provided by the CPU 114 is written to the first memory 124 and the second memory 128. Thus, the same target address from the instructions provided by the CPU 114 is written to both the first memory 124 and the second memory 128.

[0025] Because the CPU 114 is connected to both the I2C transceiver 118 and the bus monitor 120 via the CPU bus, the destination address provided by the CPU 114 can be written to the first memory 124 and the second memory 128 in parallel without software mediation. Thus, both the first memory 124 and the second memory 128 can be written as a hardware process without additional software overhead. This enables faster I2C message processing and simpler control software development. After the I2C transceiver 118 receives an instruction from the CPU 114, the I2C transceiver generates a message (SDA signal) and sends the message to the SDA bus 108. The destination address provided by the message sent by the I2C transceiver 118 to the SDA bus 108 is then written to the second memory 128. Thus, both the destination address provided by the CPU 114 and the destination address provided by the I2C transceiver 118 are written to the second memory 128.

[0026] The clock 112 provides a clock signal to the I2C transceiver 118 at a base frequency. The I2C transceiver 118 generates an SCL signal in response to the clock signal having a frequency corresponding to the I2C data rate. In some instances, the I2C message (SDA signal) has a data rate between 100 kilohertz (kHz) and 400 kHz. The I2C transceiver 118 generates an SDA signal that has data transitions timed in response to the clock edges of the SCL signal. A data transition is a voltage transition of the SDA signal from high to low or from low to high. Regarding Figure 4 the data transition timing and the sampling of the SDA signal using the SCL signal are further described.

[0027] The I2C transceiver 118 provides the SCL signal to the SCL bus 106 via the SCL pin 130 and provides the SDA signal to the SDA bus 108 via the SDA pin 132, as further described below. The I2C transceiver 118 also provides the SCL signal, the SDA signal, and an ignore condition signal to the bus monitor 120. In response to the ignore condition signal, the bus monitor 120 stops comparing the two destination addresses stored in the second memory 128. This corresponds to the bus monitor 120 not continuing to determine whether it should generate an error interrupt signal. Recall that the destination address in the instruction provided by the CPU 114 is stored in the second memory 128. And, the destination address in the SDA signal provided by the I2C transceiver 118 to the SDA bus 108 is stored in the second memory 128.

[0028] In some instances, the additional actions taken by the bus monitor 120 or the I2C transceiver 118 after ignoring the condition signal depend on the type of the ignored condition signal. The arbitration failure signal or the illegal stop signal may be asserted by the I2C transceiver 118 as the ignored condition signal. The arbitration failure signal and the illegal stop signal are described separately (further) below. In some instances, the ignored condition occurs during the normal operation of the I2C system 200.

[0029] The bus monitor 120 samples the SDA signal received from the I2C transceiver 118 via the feedback connection. The bus monitor 120 samples the SDA signal using the SCL signal (also received via the feedback connection) to determine the target address indicated by the SDA signal. The target address indicated by the SDA signal is stored in the second memory 128. The comparator 126 compares the target address provided by the CPU 114 with the target address indicated by the SDA signal. If the target addresses are the same, the bus monitor 120 provides a de-asserted error interrupt signal to the event handler 116. The de-asserted error interrupt signal indicates that the target address included in the SDA signal matches the target address provided by the CPU 114.

[0030] If the target addresses are different, the bus monitor 120 provides an asserted error interrupt signal to the event handler 116. The asserted error interrupt signal indicates a target addressing failure. In some instances, the bus monitor 120 provides an error interrupt signal to the event handler 116 immediately after detecting a target addressing failure without waiting to determine whether an ignored condition signal will be received.

[0031] In some instances, the target addressing failure may be caused by a failure within the controller MCU 102 (with the controller 202) or by a failure on the SDA bus 108. In some instances, the target addressing failure is caused by a random hardware failure (correspondingly, a reliability issue) in the I2C transceiver 118 or on the SDA bus 108 (or 204). The random hardware failure in the I2C transceiver 118 may occur in the processor 122 or the first memory 124. The event handler 116 may be implemented using hardware, software (e.g., software instructions stored in the memory and executed by the CPU 114), or a combination of both.

[0032] In some instances, in response to the asserted error interrupt signal (target addressing failure), the CPU 114 initiates a stop condition on the SDA bus 108 using the I2C transceiver 118. In some instances, initiating the stop condition corresponds to transmitting a stop condition signal 408 ( Figure 4)。In some instances, in response to an asserted error interrupt signal, the event handler 116 may trigger a power-on reset (POR) of the controller MCU 102. In some instances, in response to an asserted error interrupt signal, the event handler 116 may send a message indicating improper functioning of the controller MCU 102 to the IC controlling the I2C system 100 and put the controller MCU 102 into a safe state, in which the controller MCU 102 does not send signals to the SCL bus 106 and the SDA bus 108.

[0033] As described above, the I2C transceiver 118 also provides an SCL signal to the SCL bus 106 via the SCL pin 130 and provides an SDA signal to the SDA bus 108 via the SDA pin 132. All targets 104 connected to the SCL bus 106 and the SDA bus 108 receive the SCL signal and the SDA signal. The target 104 corresponding to the target address included in the SDA signal executes the read and / or write instructions included in the SDA signal.

[0034] In response to an SDA signal corresponding to a write command, the target 104 indicated by the SDA signal writes the data included in the SDA signal to the memory address included in the SDA signal. In response to an SDA signal corresponding to a read command, the target 104 indicated by the SDA signal writes the memory address indicated by the SDA signal to the memory of the target 104, reads data from the memory indicated by the address, and provides the read data to the I2C transceiver 118. In some instances, the transceiver 118 provides the read data and the acknowledgment signal received from the target 104 to the CPU 114. Regarding Figure 3A and 3B The I2C read and write signal structures and processes are further described.

[0035] Now describe the ignore condition signal. In Figure 4 The stop condition signal 408 further described therein ends the I2C communication (message) between the controller 202 and the target 104. An illegal stop is a stop condition signal 408 that appears at a position within the I2C communication that does not correspond to a normal I2C read or write message. Regarding Figure 4 The stop condition signal 408 and the illegal stop signal are further described.

[0036] Two controllers 202 that simultaneously attempt to send an SDA signal are said to be in arbitration. If two controllers 202 (see Figure 2)If an attempt is made to send an SDA signal simultaneously, an asserted arbitration failure signal can be generated. As described above, the I2C transceiver 118 sends a logic one as the ground voltage and thus connects the SDA bus 108 to ground 208 to send a logic one. The I2C transceiver 118 sends a logic zero as the source voltage and thus releases the SDA bus 108 from the connection to ground 208 to allow the SDA bus 108 to be pulled up by the voltage source 204 to send a logic zero.

[0037] The controller 202 that first attempts to send a logic zero (releasing the SDA bus 108 to go high) while another controller 202 attempts to send a logic one (connecting the SDA bus 108 to ground 208 to pull the SDA bus 108 low) will not be able to successfully send a logic zero due to the connection to ground 208. The unsuccessful controller 202 is said to have lost arbitration. The unsuccessful controller 202 knows it is unsuccessful because it receives the SDA signal on the SDA bus 108 via the buffer 210. The failed arbitration corresponds to the SDA bus 108 carrying the SDA signal that has a lower voltage than a logic zero (higher), specifically, the voltage of the ground connection made by the arbitration-winning controller 202.

[0038] The I2C transceiver 118 that unsuccessfully attempts to send a logic one provides an asserted arbitration failure signal to its corresponding bus monitor 120 and stops sending its SDA signal. The arbitration-winning controller 202 is allowed to send its SDA signal without interference, and the arbitration-losing controller 202 waits until the SDA signal of the arbitration winner ends. In some instances, the end of the SDA signal corresponds to the stop condition signal 408 as described with respect to Figure 4 The stop condition signal 408.

[0039] After the stop condition signal 408, the arbitration-losing controller 202 attempts to send its SDA signal again. If the bus monitor 120 receives an asserted arbitration failure signal, the bus monitor 120 stops operating with respect to the interrupted SDA signal. When the interrupted SDA signal is retransmitted, the bus monitor 120 processes the retransmission message as if the initial transmission attempt had not occurred.

[0040] Figure 3A Yes Figure 1 Is the bitwise structure of an example I2C communication 300 between the controller MCU 102 and the target 104 for implementing a write command.

[0041] The I2C transceiver 118 of the controller MCU 102 sends a start condition (S) signal 302 on the SDA bus 108, sends a target address 304 specifying the pth target (e.g., in the example, target 104a) to execute the write command, and sends a read / write bit set to zero 306. Regarding Figure 4 further describes the start condition signal 302. The bits of the seven target addresses 304 are numbered A6 corresponding to the most significant bit (MSB) to A0 corresponding to the least significant bit (LSB). The seven-bit target address enables addressing of 2 7 ^7 = 128 targets 104. The bar above W instead of R indicates that when bit 306 is equal to zero, the write meaning is asserted, and when bit 306 is equal to one, the read meaning is asserted.

[0042] After receiving the start condition signal 302, the target address 304, and bit 306, the target 104a corresponding to the target address 304 sends a first acknowledgment (ACK or A) bit 308 to confirm receipt to the SDA bus 108. Then, the controller MCU 102 sends a register address 310 to the SDA bus 108, indicating the memory address in the target 104a of the register to be written. In some instances, the register address 310 is a one-byte (eight-bit) address, numbered B7 at the MSB to B0 at the LSB. The target 104a writes the register address 310 into the memory of the target 104a and performs the requested memory write with reference to the written register address 310.

[0043] After the target 104a sends a second ACK bit 312 to confirm receipt of the register address 310 and the ready status to the SDA bus 108, the controller MCU 102 sends register data 314 to be written to the register address 310 to the target 104a. In some instances, the register data 314 is a one-byte (eight-bit) data, numbered D7 at the MSB to D0 at the LSB. After the target 104a receives and writes the register data 314, the target 104a sends a third ACK bit 316 to the controller MCU 102.

[0044] After the third ACK bit 316, the controller MCU 102 may send additional bytes of the register data 314, or (as illustrated) may send a stop condition signal 318 to the target 104a to end the I2C communication 300. The stop condition signal 318 also indicates to other controllers 202 that the SCL bus 106 and the SDA bus 108 are available for messaging.

[0045] Figure 3B is Figure 1The bit structure of the I2C communication 320 for implementing the read command between the controller MCU 102 and the target 104. The initial part of the I2C communication 320 corresponds to the initial part of the I2C communication through the second ACK bit 312. The I2C communication 320 for implementing the read command starts with providing the target address 304 of the specified target 104a, providing a bit 306 equal to zero so that the register address 310 will be written, and providing the register address 310 at which the read will start. Thus, the target memory address at which the read will start is first written, and data is read from the memory at that address (and in some instances, from the memory at sequentially subsequent addresses). After the controller MCU 102 receives the second ACK bit 312 indicating that the register address 310 has been written from the target 104a, the controller MCU 102 sends a repeated start condition (Sr) signal 322, and the Sr signal enables the sending of the

[0046] bit 306 corresponding to the read operation. In some instances, the repeated start condition signal 322 has an SCL and SDA signal timing similar to or the same as the start condition signal 302 that initiates the I2C communication 300 or 320 (see ). After sending the repeated start condition signal 322, the controller MCU 102 sends the target address 324 again, and then sends a Figure 4 bit 306 equal to one, indicating the read operation. Figure 4 ) In response to the

[0047] bit 306, the target 104a sends a third ACK bit 328, and then sends the bytes of the read register data 330 starting at the register address 310 retrieved from the memory of the target 104. After the controller MCU 102 receives the read register data 330, the controller MCU may send an ACK bit to the target 104a, and the ACK bit enables the target 104a to sequentially read another byte of data from the memory address after the end of the read register data 330. Alternatively, as in the illustrated instance, the MCU controller 102 may send a negative acknowledgment bit (NACK or NA) 332 to the target 104a. The NACK bit 332 commands the target 104a to suspend the communication and release the SDA bus 108. The MCU controller 102 will follow the NACK bit with a stop condition signal 334. In some instances, the ACK bit is asserted low, and the NACK bit is asserted high.

[0048] Figure 4 ​Timing diagram 400 shows the timing of SCL signal 402 and SDA signal 404 for providing start condition signal 406 and stop condition signal 408. Data transfer 410 is performed between start condition signal 406 and stop condition signal 408 from slave controller 202 to target 104 and / or from target 104 to controller 202.

[0049] When SCL signal 402 is high, start condition signal 406 corresponds to the falling edge of SDA signal 404. When SCL signal 402 is high, stop condition signal 408 corresponds to the rising edge of SDA signal 404. An illegal stop that triggers (as described above) an illegal stop signal corresponds to a stop condition signal 408 generated at a portion of the SDA signal 404 that does not correspond to one of the positions of the expected stop condition signal 408 described with respect to Figure 3A and 3B the expected stop condition signal 408.

[0050] When I2C transceiver 118 detects an illegal stop condition, the I2C transceiver sends an illegal stop signal to bus monitor 120, and the state machine of I2C transceiver 118 resets. The state machine of I2C transceiver 118 tracks which bit (or other signal) in the I2C communication that I2C transceiver 118 is currently sending (e.g., I2C communication 300 for implementing a write command or I2C communication 320 for implementing a read command). Thus, the I2C transceiver 118 state machine tracks which bit (or other signal) in which field (e.g., register address 310 or target address 324) is currently being generated by I2C transceiver 118 and transmitted to SDA bus 108. In response to the illegal stop signal, bus monitor 120 aborts the comparison between the target address provided by CPU 114 and the target address transmitted by I2C transceiver 118, and avoids providing a false alarm indication to event handler 116.

[0051] Thus, the transmission of I2C data bits ( Figure 4 not shown) corresponds to the SDA signal 404 not changing during the duration of the high period (half a clock cycle) of the SCL signal 402. In other words, to provide data, the SDA signal 404 switches when the SCL signal 402 is low and remains constant when the SCL signal 402 is high. This corresponds to the SDA signal 404 having a constant low (logic one) or high (logic zero) value while the SCL signal 402 provides a rising edge and then a falling edge. Thus, the frequency and phase of the SCL signal 402 can be described as being synchronized with the data of the SDA signal 404.

[0052] Figure 5It is a functional block diagram of a third instance I2C system 500. In the I2C system 500, the bus monitor 120 includes a finite state machine (FSM) 502, a first multiplexer (MUX 1) 504, a second multiplexer (MUX 2) 506, and a logic inverter 508. The memory 128 includes an input target address memory 510 and an output target address memory 512. The input target address memory 510 refers to the input received by the I2C transceiver 118 from the CPU 114, and the output target address memory 512 refers to the output of the I2C transceiver 118 sent to the target 104 as the SDA signal. The input target address memory 510 and the output target address memory 512 correspond to Figure 1 the second memory 128.

[0053] The data terminal of the CPU 114 is connected to the data terminal of the I2C transceiver 118, the first input of the MUX 1 504, and the input of the logic inverter 508 via the CPU bus. The output of the logic inverter 508 is connected to the second input of the MUX 1 504. The diagnostic test output of the CPU 114 provides a diagnostic test signal to the control input of the MUX 1 504. The output of the MUX 1 504 is connected to the input of the input target address memory 510. The enable output of the CPU 114 provides an enable signal to the control input of the MUX 2 506.

[0054] The SCL terminal of the I2C transceiver 118 is connected to the SCL pin 130 and the clock input of the FSM 502. The SDA terminal of the I2C transceiver 118 is connected to the SDA pin 132 and the data input of the FSM 502. The output of the FSM 502 is connected to the input of the output target address memory 512. The output of the input target address memory 510 is connected to the first data input of the comparator 126, and the output of the output target address memory 512 is connected to the second data input of the comparator 126.

[0055] The first ignore output of the I2C transceiver 118 is connected to the first ignore input of the comparator 126 and provides an arbitration failure signal. The second ignore output of the I2C transceiver 118 is connected to the second ignore input of the comparator 126 and provides an illegal stop signal.

[0056] The output of the comparator 126 is connected to the first input of the MUX 2 506. The second input of the MUX 2 506 receives a signal with a logic zero value, and the signal corresponds to a de-asserted error interrupt signal. The output of the MUX 2 506 provides an error interrupt signal to the event handler 116.

[0057] FSM 502 extracts the target address from the SDA signal (the message sent by transceiver 118) in response to the SCL signal. Figure 4 describes extracting data from the SDA signal (parsing the SDA signal in response to the SCL signal). In some examples, the FSM 502 is programmed and / or includes hardware to extract a configured number of bits after the start condition signal 406 in the SDA signal. Thus, in the case corresponding to the above description of Figure 3A and 3B In the described examples of I2C communication 300 or 320 corresponding to a write command or a read command (respectively), the target address is a set of bits that sequentially follows the start condition signal 406. The configured number of bits is the number of bits in the target address corresponding to the target 104 connected to the SCL bus 106 and the SDA bus 108. In some examples, the configured number of bits is seven or ten (or a different number).

[0058] In some instances, FSM 502 detects an ignore condition, such as an arbitration loss condition or an invalid stop condition. In some instances, FSM 502 does so in response to an ignore condition signal provided by I2C transceiver 118. In some instances, FSM 502 detects an ignore condition, such as an arbitration loss condition or an invalid stop condition. In some instances, FSM 502 does so in response to an ignore condition signal provided by I2C transceiver 118. Figure 4 The description parses the SDA signal in response to the SCL signal to independently detect an ignore condition.

[0059] The comparator 126 compares the target address stored in the input target address memory 512 with the target address stored in the output target address memory 512 and provides an output in response to the comparison. In some examples, if the two target addresses are different, the comparator 126 provides a logic one output, corresponding to an addressing failure, and if the two target addresses are the same, the comparator provides a logic zero output, corresponding to normal addressing operation. If the enable signal is asserted, MUX2 506 provides the output of the comparator 126 to the event handler 116. If the enable signal is de-asserted, MUX 2 506 provides a logic zero to the event handler 116, indicating normal operation or a do-not-care state.

[0060] ​​If the diagnostic test signal is deasserted, MUX 1 504 provides the signal received at its non-inverting input to the input destination address memory 510. If the diagnostic test signal is asserted, MUX 1 504 provides the signal received at its inverting input to the input destination address memory 510. Thus, the CPU 114 can test the valid functionality of the comparator 126 by intentionally injecting a fault with an inverted signal by asserting the diagnostic test signal. If the diagnostic test signal is asserted, the valid functionality of the comparator 126 will correspond to an error interrupt signal indicating an addressing failure. If the diagnostic test signal is deasserted, the valid functionality of the comparator 126 is assumed (or previously verified by diagnostics), and the output of the comparator 126 will depend on the valid functionality of the I2C transceiver 118.

[0061] Figure 6 is the process 600 of the controller MCU 102 for operation Figure 1 In step 602, an instruction is sent from the processor of the controller IC to the transceiver of the controller IC. The instruction specifies the address of the specified target IC, a read or write command, and the memory address of the specified target IC. In some instances, the controller IC is the controller MCU 102, the processor is the CPU 114, the instruction is the data provided by the CPU 114 to the I2C transceiver 118, and the command is a read command or a write command.

[0062] In step 604, an attempt is made to transmit a message containing the target address, command, and memory address from the controller IC to the bus using the transceiver. In some instances, the bus is the SDA bus 108. In step 606, the message from the transceiver is provided to the bus monitor of the controller IC. In some instances, steps 604 and 606 correspond to the signal path of the SDA signal transmitted by the I2C transceiver 118, specifically, transmitted via the SDA pin 132 to the SDA bus 108 and to the bus monitor 120.

[0063] In step 608, the bus monitor is used to determine whether the target address included in the instruction is the same as the target address included in the message. If the target addresses are the same, then in step 610, a response message is received from the target IC specified by the target address in the message using the transceiver. If the target addresses are not the same, then in step 612, an error interrupt signal is sent to the event handler.

[0064] In some instances, the systems and methods described herein that include bus monitor 120 enable the I2C controller 202 to meet the requirements of safety or other standards, such as safety requirements, such as those of the International Electrotechnical Commission (IEC) 61784. For example, IEC 61784 requires addressing authentication. In some instances, this requirement is met by detecting an addressing fault via bus monitor 120 and providing an error interrupt signal.

[0065] Within the scope of the claims, modifications may be made in the described instances, and other instances are possible.

[0066] In some instances, event handler 116 is part of CPU 114.

[0067] In some instances, the circuits described herein (e.g., targeter 104, processor 122, comparator 126, CPU 114, or MCU 102) may be implemented using a processor (e.g., a CPU, a digital signal processor (DSP), or an MCU).

[0068] In some instances, the disclosed processes and structures are used to implement data integrity verification for communication protocols other than I2C, such as Serial Peripheral Interface (SPI) or Universal Asynchronous Receiver / Transmitter (UART).

[0069] In some instances, the target address within I2C (or other) communication contains a different number of bits than described above, e.g., ten bits, corresponding to 2 10 = 1024 addressable targets.

[0070] In some instances, CPU 114 provides read / write commands as read / write flags. In some instances, CPU 114 provides instructions in the form of indicating a target address, a read / write flag, and a memory address. In some instances, the I2C transceiver 118 (e.g., the processor 122 of the I2C transceiver 118) interprets the instructions to generate corresponding I2C communications. Thus, in some instances, the formats of the instructions and the I2C communications (e.g., bit-by-bit format) are different.

[0071] In some instances, the disclosed processes and structures are used to compare signal fields other than the target address to confirm that a portion of a message transmitted by a transceiver of a controller to a target matches a corresponding portion of an instruction from a processor of the controller that indicates the transceiver to generate and transmit the message.

[0072] In some instances, the bus monitor 120 compares fields in messages transmitted by the I2C transceiver 118 to the SDA bus 108 with corresponding fields in instructions transmitted by the CPU 114 to the I2C transceiver 118 that are other than or different from the destination address field.

[0073] In some instances, a processor external to the controller 202 provides instructions that the I2C transceiver 118 uses to generate messages (I2C communications).

[0074] In some instances, the processors described herein are implemented using a CPU, a digital signal processor (DSP), or an MCU.

[0075] The term "coupled" is used throughout this specification. The term can encompass a connection, communication, or signal path that implements a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform an action, then: in a first instance, device A is coupled to device B, or in a second instance, if an intermediate component C does not substantially change the functional relationship between device A and device B such that device B is controlled by device A via the control signal provided by device A, then device A is coupled to device B through the intermediate component C.

[0076] In this specification, the term "and / or" (when used in the form of, for example, A, B, and / or C) refers to any combination or subset of A, B, and C, such as: (a) only A; (b) only B; (c) only C; (d) A and B; (e) A and C; (f) B and C; and (g) A, B, and C. Also, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to an embodiment that includes any one of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0077] A device "configured to" perform a task or function can be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or can be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration can be performed through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnects of the device, or through a combination thereof.

[0078] As used herein, the terms "terminal", "node", "interconnect", "pin", "ball grid array (BGA) ball", and "lead" can be used interchangeably. Unless specifically stated to the contrary, these terms generally refer to the interconnects or their ends between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components.

[0079] A circuit or apparatus described herein as including certain components may alternatively be adapted to be coupled to those components to form the described circuitry or apparatus. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, e.g., by an end user and / or a third party.

[0080] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may alternatively be used with little or no change to the remainder of the circuitry. For example, metal oxide silicon FETs (“MOSFETs”) (e.g., n-channel MOSFETs, nMOSFETs, or p-channel MOSFETs, pMOSFETs), bipolar junction transistors (BJTs - e.g., NPN or PNP), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used instead of or in combination with the devices disclosed herein. The transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device-structure transistors. Additionally, the devices may be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0081] The circuits described herein may be reconfigured to include replacement components to provide functionality that is at least partially similar to the functionality available prior to the component replacement. Unless otherwise specified, a component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor.

[0082] Although some of the components of the described examples may be included in an integrated circuit and other components are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features described as being external to the integrated circuit may be included in the integrated circuit, and / or some of the features described as being internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / above a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board.

Claims

1. An integrated circuit IC, comprising: First pin; The second pin; a bus monitor having a first input, a second input, a third input, and an output; as well as a transceiver having an input, a first output, and a second output, the input of the transceiver and the first input of the bus monitor each being configured to receive an instruction indicating an indicated target address, a read / write flag, and a memory address, the first output of the transceiver being coupled to the first pin and the second input of the bus monitor, the second output of the transceiver being coupled to the second pin and the third input of the bus monitor, and the transceiver being configured to generate a message in response to the instruction such that the message includes a message target address, the read / write flag, and the memory address; Wherein the bus monitor is configured to compare a signal received at its first input with a signal received at its second input and to provide a signal in response to the comparison, the comparison being responsive to a signal received at a third input of the bus monitor.

2. The IC of claim 1, wherein the IC is an inter-integrated circuit controller.

3. The IC according to claim 1, wherein the bus monitor comprises a first memory and a second memory; and Wherein the bus monitor is configured to write the indicated target address to the first memory, and is configured to write the message target address to the second memory. 4 . The IC of claim 1 , wherein the bus monitor is configured to compare the indicated destination address with the message destination address.

5. The IC according to claim 1, It further includes a clock circuit having an output configured to provide a first clock signal having a first clock frequency; wherein the transmitter has a clock input coupled to the clock output of the clock circuit, and generates a second clock signal in response to the first clock signal, the second clock signal having a second clock frequency; and The transmitter is configured to generate the message in response to the second clock signal and to provide the second clock signal at a second output of the transmitter.

6. The IC according to claim 1, wherein the bus monitor comprises a finite state machine configured to determine the message target address in response to the signal received at the first input of the bus monitor and the signal received at the third input of the bus monitor; wherein the bus monitor is configured to determine the indicated target address in response to the signal received at the second input of the bus monitor; and Wherein the comparing action compares the message target address to the indicated target address.

7. The IC of claim 1 , wherein the transceiver includes a control output, the IC further comprising: Ground pin; as well as A transistor comprising a first terminal, a second terminal and a control terminal, the first terminal of the transistor being coupled to the first pin, the second terminal of the transistor being coupled to the ground pin, and the control terminal of the transistor being coupled to the control output of the transceiver.

8. The IC according to claim 1, wherein the bus monitor comprises a multiplexer having first and second inputs, a control input and an output, and a logic inverter comprising an input and an output; and wherein the first input of the multiplexer is configured to receive the instruction, the input of the logic inverter is configured to receive the instruction, the second input of the multiplexer is coupled to the output of the logic inverter, the control input of the multiplexer is configured to receive a diagnostic test control signal, and the output of the multiplexer is coupled to the second input of the bus monitor.

9. The IC of claim 1, wherein the bus monitor comprises a multiplexer having first and second inputs, a control input, and an output, and wherein the first input of the multiplexer is coupled to the output of the bus monitor.

10. An integrated circuit IC, comprising: First pin; The second pin; a processor having an input and an output, the processor being configured to provide via the output an instruction indicating an indicated target address, a read / write flag, and a memory address; a bus monitor having a first input, a second input, a third input, and an output, the output of the bus monitor being coupled to the input of the processor; as well as a transceiver having an input, a first output, and a second output, the output of the processor being coupled to the input of the transceiver and the first input of the bus monitor, the first output of the transceiver being coupled to the first pin and the second input of the bus monitor, the second output of the transceiver being coupled to the second pin and the third input of the bus monitor, and the transceiver being configured to generate a message in response to the instruction such that the message includes a message target address, the read / write flag, and the memory address; The bus monitor is configured to compare a signal received at its first input with a signal received at its second input and to provide a signal to the processor in response to the comparison, the comparison being responsive to a signal received at a third input of the bus monitor.

11. The IC of claim 10, wherein the IC is an inter-integrated circuit controller.

12. The IC according to claim 10, wherein the bus monitor comprises a first memory and a second memory; and Wherein the bus monitor is configured to write the indicated target address to the first memory, and is configured to write the message target address to the second memory.

13. The IC of claim 10, wherein the bus monitor is configured to compare the indicated destination address with the message destination address.

14. The IC according to claim 10, wherein the clock circuit is configured to provide a clock signal having a clock frequency; wherein the transmitter has a clock input, and the output of the clock circuit is coupled to the clock input of the transmitter; and Wherein the transmitter is configured to generate the message in response to the clock signal.

15. The IC according to claim 10, wherein the bus monitor comprises a finite state machine configured to determine the message target address in response to the signal received at the first input of the bus monitor and the signal received at the third input of the bus monitor; wherein the bus monitor is configured to determine the indicated target address in response to the signal received at the second input of the bus monitor; and Wherein the comparing action compares the message target address to the indicated target address.

16. The IC of claim 10, wherein the transceiver includes a control output, the IC further comprising: Ground pin; as well as A transistor comprising a first terminal, a second terminal and a control terminal, the first terminal of the transistor being coupled to the second pin, the second terminal of the transistor being coupled to the ground pin, and the control terminal of the transistor being coupled to the control output of the transceiver.

17. The IC according to claim 10, wherein the processor has a control output; wherein the bus monitor comprises a multiplexer having first and second inputs, a control input and an output, and a logic inverter comprising an input and an output; and wherein the first input of the multiplexer and the input of the logic inverter are each coupled to the output of the processor, the second input of the multiplexer is coupled to the output of the logic inverter, the control input of the multiplexer is coupled to the control output of the processor, and the output of the multiplexer is coupled to the second input of the bus monitor.

18. The IC according to claim 10, wherein the processor comprises a control output; and wherein the bus monitor comprises a multiplexer having first and second inputs, a control input, and an output, the first input of the multiplexer being coupled to the output of the bus monitor, the control output of the multiplexer being coupled to the control output of the processor, and the output of the multiplexer being coupled to the input of the processor.

19. A method of operating an integrated circuit IC, the method comprising: sending, by the processor to the transceiver, an instruction specifying an indicated address of a designated target IC, a read or write command, and a memory address of the designated target IC; transmitting, by the transceiver, a message from the IC, the message including a message address corresponding to the indicated address, the command, and the memory address; determining, using a bus monitor, whether the indicated address and the message address are the same; as well as A determination is made by the bus monitor whether to provide an error interrupt signal to an event handler based on whether the indicated address and the message address are the same.

20. The method of claim 19, further comprising: generating a clock signal having a clock frequency, wherein the transmitting comprises transmitting the clock signal from the IC by the transceiver; as well as Prior to the determining, the message is parsed using a finite state machine of the bus monitor in response to the clock signal to recover the message address from the message.

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