Display device and method of driving same

Abstract

The invention discloses a display device and a method of driving the same. The display device includes a display panel including sub-pixels and a display panel driver for driving the display panel. The sub-pixel includes a driving transistor, a storage capacitor connected to a control electrode of the driving transistor, a write transistor that writes a data voltage to the storage capacitor in response to a write gate signal, a first emission transistor that supplies a first power supply voltage to a first electrode of the driving transistor in response to a first emission signal, and a second emission transistor that supplies a second power supply voltage to a second electrode of the driving transistor. A holding capacitor including a first electrode receiving the first power supply voltage and a second electrode connected to the second electrode of the driving transistor; and a light emitting element emitting light. The first transmission signal has an active level in a first portion of each of first periods of one frame, and has an active level in each of second periods respectively located after the first periods.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0161378 filed in the Korean Intellectual Property Office on November 20, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to a display device and a method of driving the display device. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information increases. Accordingly, display devices such as liquid crystal display devices and organic light emitting display devices are increasingly used.

[0005] The display device may display an image using a plurality of sub-pixels. Depending on the structure and operation of each pixel circuit of the sub-pixel, mura, which is brightness non-uniformity of the display device, may occur in the display device. Summary of the invention

[0006] The embodiment provides a display device for reducing a cut-off time of a first emission signal.

[0007] Embodiments also provide a method of driving the display device.

[0008] According to aspects of the present disclosure, a display device is provided, comprising: a display panel including sub-pixels; and a display panel driver configured to drive the display panel, wherein the sub-pixels include: a driving transistor generating a driving current, the driving transistor including a control electrode, a first electrode, and a second electrode; a storage capacitor connected between the control electrode of the driving transistor and the second electrode of the driving transistor; a write transistor connected between a data line and the control electrode of the driving transistor, the write transistor writing a data voltage to the storage capacitor in response to a write gate signal; a first emission transistor connected between a first power supply voltage line providing a first power supply voltage and the first electrode of the driving transistor, the first emission transistor providing the first power supply voltage to the first electrode of the driving transistor in response to a first emission signal; a holding capacitor connected between the first power supply voltage line and the second electrode of the driving transistor; and a light-emitting element connected to the driving transistor, and wherein the first emission signal has a valid level in a first part of each of a first time period of a frame, and has a valid level in each of a second time period respectively located after the first time period.

[0009] In each of the first time periods, the first transmission signal may be switched between an active level and an inactive level.

[0010] The first period may include a first sub-period in which a data voltage is written to a sub-pixel and a second sub-period different from the first sub-period.

[0011] The subpixel may further include a first initialization transistor connected between a first initialization voltage line providing a first initialization voltage and the light emitting element, the first initialization transistor providing the first initialization voltage to the light emitting element in response to an initialization gate signal. The initialization gate signal may have an effective level in a second portion of the second sub-period in which the first emission signal has an ineffective level.

[0012] The initialization gate signal may have an inactive level in a first portion of the second sub-period.

[0013] The initialization gate signal may have an active level in a first portion of the second sub-period.

[0014] Each of the first periods may include a first sub-period in which a data voltage is written to the sub-pixel and a second sub-period different from the first sub-period. The sub-pixel may further include a first initialization transistor connected between a first initialization voltage line providing a first initialization voltage and the light-emitting element, the first initialization transistor providing the first initialization voltage to the light-emitting element in response to an initialization gate signal. The initialization gate signal may have a valid level in a second portion of at least one of the second sub-periods in which the first emission signal has an invalid level.

[0015] The first period may include a first sub-period in which the data voltage is written to the subpixel and a second sub-period different from the first sub-period. The write gate signal may have an active level in at least a portion of the first sub-period and an inactive level in the second sub-period and the second period.

[0016] The subpixel may further include a first initialization transistor connected between a first initialization voltage line providing a first initialization voltage and the light emitting element, the first initialization transistor providing the first initialization voltage to the light emitting element in response to an initialization gate signal. The initialization gate signal may have an effective level in a period in which the write gate signal has an effective level.

[0017] The sub-pixel may further include a reference transistor connected between a reference voltage line supplying a reference voltage and a control electrode of the driving transistor, the reference transistor supplying the reference voltage to the storage capacitor in response to a reference gate signal.

[0018] The first period may include a first sub-period in which a data voltage is written to a subpixel and a second sub-period different from the first sub-period. The reference gate signal may have an active level in at least a portion of the first sub-period and an inactive level in the second sub-period and the second period.

[0019] The subpixel may further include a first initialization transistor connected between a first initialization voltage line providing a first initialization voltage and the light emitting element, the first initialization transistor providing the first initialization voltage to the light emitting element in response to an initialization gate signal. The initialization gate signal may have an effective level in a period in which the first emission signal and the reference gate signal have effective levels.

[0020] The sub-pixel may further include a second emission transistor connected between the driving transistor and the light emitting element, the second emission transistor connecting the driving transistor to the light emitting element in response to a second emission signal.

[0021] The first period may include a first sub-period in which a data voltage is written to a subpixel and a second sub-period different from the first sub-period. The second emission signal may have an inactive level in at least a portion of the first sub-period and have an active level in the second sub-period and the second period.

[0022] The subpixel may further include a second initialization transistor connected between a second initialization voltage line supplying the second initialization voltage and the second electrode of the driving transistor, the second initialization transistor supplying the second initialization voltage to the storage capacitor in response to the initialization gate signal.

[0023] According to another aspect of the present disclosure, a method for driving a display device is provided, the method comprising: writing a data voltage to a sub-pixel in a first sub-period; providing a first emission signal having a valid level to the sub-pixel in a second period after the first sub-period, thereby allowing a light-emitting element of the sub-pixel to emit light; providing a first emission signal switched between a valid level and an invalid level to the sub-pixel in a second sub-period after the second period; and providing a first emission signal having a valid level to the sub-pixel in a second period after the second sub-period, thereby allowing the light-emitting element to emit light.

[0024] The sub-pixel may include: a driving transistor generating a driving current; a storage capacitor connected to a control electrode of the driving transistor; a writing transistor writing a data voltage to the storage capacitor in response to a writing gate signal; a first emission transistor providing a first power supply voltage to a first electrode of the driving transistor in response to a first emission signal; and a holding capacitor including a first electrode receiving the first power supply voltage and a second electrode connected to a second electrode of the driving transistor. The light-emitting element may emit light by receiving the driving current from the driving transistor.

[0025] The method may further include applying a first initialization voltage to the light emitting element in a portion of the second sub-period in which the first emission signal has an inactive level.

[0026] The method may further include applying a first initialization voltage to the light emitting element in a portion of the second sub-period in which the first emission signal has an active level.

[0027] When the data voltage is written to the sub-pixel, a first initialization voltage may be applied to the light emitting element. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the example embodiments to those skilled in the art.

[0029] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intervening elements may also be present between the two elements. The same reference numerals refer to the same elements throughout.

[0030] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0031] Figure 2 It is a graphic Figure 1 A circuit diagram of an example of a sub-pixel of a display device is shown in FIG.

[0032] Figure 3 It is a diagram of Figure 2 0 is a timing diagram of a comparative example in which sub-pixels are driven.

[0033] Figure 4 The diagram is based on Figure 3 Graph of mura of a comparative example shown in FIG.

[0034] Figure 5 It is a graphic with Figure 4 The timing diagram of how the sub-pixels corresponding to the dark portion are driven is shown in FIG.

[0035] Figure 6 It is a graphic with Figure 4 The timing diagram of driving the sub-pixels corresponding to the bright parts shown in FIG.

[0036] Figure 7 It is a diagram of Figure 2 0 is a timing diagram of an example in which a sub-pixel is driven.

[0037] Figure 8 is a timing diagram illustrating an example in which a display device drives sub-pixels according to an embodiment of the present disclosure.

[0038] Fig. 9 is a circuit diagram illustrating an example of a sub-pixel of a display device according to an embodiment of the present disclosure.

[0039] Fig.10 is a circuit diagram illustrating an example of a sub-pixel of a display device according to an embodiment of the present disclosure.

[0040] Fig.11 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure.

[0041] Fig.12 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0042] Fig.13 It is a diagram of Fig.12 The electronic device shown in FIG. 1 is a diagram of an example in which the electronic device is implemented as a television. DETAILED DESCRIPTION

[0043] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the following description, only the parts that are necessary for understanding the operation according to the present disclosure are described and the description of other parts is omitted, so as not to unnecessarily obscure the subject matter of the present disclosure. In addition, the present disclosure is not limited to the exemplary embodiments described herein, but can be embodied in various different forms. On the contrary, the exemplary embodiments described herein are provided to fully and completely describe the disclosed content, and will fully convey the ideas of the present disclosure to those of ordinary skill in the art.

[0044] Throughout the specification, when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or may be indirectly connected or coupled to the other element using one or more intervening elements therebetween. The technical terms used herein are only used to illustrate the purpose of a specific embodiment, and are not intended to limit the embodiments. It will be understood that when a component "includes" an element, unless there is another description to the contrary, it should be understood that the component does not exclude another element, but may further include another element. It will be understood that, for the purposes of this disclosure, "at least one of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z (e.g., XYZ, XY, YZ, XZ). Similarly, for the purposes of this disclosure, "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z (e.g., XYZ, XY, YZ, XZ).

[0045] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, the "first" element discussed below may also be referred to as the "second" element without departing from the teachings of the present disclosure.

[0046] For ease of description, spatially relative terms such as "below" and "above" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that in addition to the orientations described herein and depicted in the accompanying drawings, the spatially relative terms and the illustrated configurations are intended to also cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, the elements described as "below" or "below" other elements or features will then be oriented "above" other elements or features. Therefore, the exemplary term "above" can cover both the above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or oriented in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0047] In addition, embodiments of the present disclosure are described herein with reference to schematic diagrams of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Therefore, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the drawings are schematic in nature, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0048] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0049] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0050] refer to Figure 1 , the display device may include a display panel 100 and a display panel driver. The display panel driver may include a drive controller 200, a gate driver 300, a data driver 400, and an emission driver 500. In an embodiment, the drive controller 200 and the data driver 400 may be integrated into one chip.

[0051] The display panel 100 may include a display area DA in which an image is displayed and a non-display area NDA disposed adjacent to the display area DA. In an embodiment, the gate driver 300 and the emission driver 500 may be installed in the non-display area NDA.

[0052] The display panel 100 may include a plurality of gate lines GL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of sub-pixels SP electrically connected to the gate lines GL, the data lines DL, and the emission lines EL. The gate lines GL and the emission lines EL may extend in a first direction DR1, and the data lines DL may extend in a second direction DR2 crossing the first direction DR1.

[0053] The drive controller 200 may receive input image data IMG and an input control signal CONT from a main processor (e.g., a graphics processing unit (GPU), etc.). For example, the input image data IMG may include red image data, green image data, and blue image data. In an embodiment, the input image data IMG may further include white image data. In another example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0054] The driving controller 200 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0055] The driving controller 200 may generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0056] The driving controller 200 may generate a second control signal CONT2 for controlling the operation of the data driver 400 based on the input control signal CONT, and output the second control signal CONT2 to the data driver 400. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0057] The driving controller 200 may generate a data signal DATA using input image data IMG and an input control signal CONT. The driving controller 200 may output the data signal DATA to the data driver 400.

[0058] The driving controller 200 may generate a third control signal CONT3 for controlling the operation of the emission driver 500 based on the input control signal CONT, and output the third control signal CONT3 to the emission driver 500. The third control signal CONT3 may include a vertical start signal and an emission clock signal.

[0059] The gate driver 300 may generate a gate signal for driving the gate line GL in response to the first control signal CONT1 input from the driving controller 200. The gate driver 300 may output the gate signal to the gate line GL. For example, the gate driver 300 may sequentially output the gate signal to the gate line GL.

[0060] The data driver 400 may receive the second control signal CONT2 and the data signal DATA input from the driving controller 200. The data driver 400 may generate a data voltage obtained by converting the data signal DATA into a voltage in an analog form. The data driver 400 may output the data voltage to the data line DL.

[0061] The emission driver 500 may generate emission signals for driving the emission lines EL in response to the third control signal CONT3 input from the driving controller 200. The emission driver 500 may output the emission signals to the emission lines EL. For example, the emission driver 500 may sequentially output the emission signals to the emission lines EL.

[0062] Figure 2 It is a graphic Figure 1 A circuit diagram of an example of a sub-pixel of a display device is shown in FIG.

[0063] refer to Figure 2 , the sub-pixel SP may include: a driving transistor T1 generating a driving current; a storage capacitor C1 connected to a control electrode of the driving transistor T1; a writing transistor T2 writing a data voltage to the storage capacitor C1 in response to a writing gate signal GW; a first emission transistor T5 providing a first power supply voltage ELVDD provided from a first power supply voltage line to a first electrode of the driving transistor T1 in response to a first emission signal EM1; a holding capacitor C2 including a first electrode receiving the first power supply voltage ELVDD and a second electrode connected to a second electrode of the driving transistor T1; a light emitting element LD emitting light by receiving the driving current; a first initialization transistor T4 providing a first initialization voltage VINT1 provided from a first initialization voltage line to a first electrode (e.g., an anode electrode) of the light emitting element LD in response to an initialization gate signal GI; a reference transistor T3 providing a reference voltage VREF provided from a reference voltage line to the control electrode of the driving transistor T1 in response to a reference gate signal GR; and a second emission transistor T6 connecting the driving transistor T1 to the light emitting element LD in response to a second emission signal EM2. This will be described in detail later.

[0064] The driving transistor T1 may include a control electrode connected to the first node N1, a first electrode connected to the first emission transistor T5, a second electrode connected to the second node N2, and a back gate connected to the second node N2. The write transistor T2 may include a control electrode receiving a write gate signal GW, a first electrode connected to the data line DL, and a second electrode connected to the first node N1. The reference transistor T3 may include a control electrode receiving a reference gate signal GR, a first electrode receiving a reference voltage VREF, and a second electrode connected to the first node N1. The first initialization transistor T4 may include a control electrode receiving an initialization gate signal GI, a first electrode receiving a first initialization voltage VINT1, and a second electrode connected to the third node N3. The first emission transistor T5 may include a control electrode receiving a first emission signal EM1, a first electrode receiving a first power supply voltage ELVDD (e.g., a high power supply voltage), and a second electrode connected to the first electrode of the driving transistor T1. The second emission transistor T6 may include a control electrode receiving a second emission signal EM2, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The storage capacitor C1 may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2. The holding capacitor C2 may include a first electrode receiving the first power supply voltage ELVDD and a second electrode connected to the back gate of the driving transistor T1 and the second node N2. For example, the light emitting element LD may include a first electrode connected to the third node N3 and a second electrode receiving the second power supply voltage ELVSS (e.g., a low power supply voltage). However, the present disclosure is not limited to this structure of the subpixel SP.

[0065] In the following, it is assumed that transistors T1, T2, T3, T4, T5 and T6 are implemented using N-channel metal oxide semiconductor (NMOS) transistors. For example, each of transistors T1, T2, T3, T4, T5 and T6 can be an N-type oxide thin film transistor. In another embodiment, transistors T1, T2, T3, T4, T5 and T6 can be implemented using P-channel metal oxide semiconductor (PMOS) transistors. For example, each of transistors T1, T2, T3, T4, T5 and T6 can be a P-type silicon thin film transistor. In another embodiment, some of transistors T1, T2, T3, T4, T5 and T6 can be implemented using NMOS transistors, and others of transistors T1, T2, T3, T4, T5 and T6 can be implemented using PMOS transistors.

[0066] The oxide thin film transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor in which the active pattern (semiconductor layer) includes an oxide. However, this is merely illustrative, and the N-type transistor is not limited thereto. For example, the active pattern (semiconductor layer) included in the N-type transistor may include an inorganic semiconductor (e.g., amorphous silicon, polycrystalline silicon) or an organic semiconductor, etc. The silicon thin film transistor may be a transistor in which the active pattern (semiconductor layer) includes amorphous silicon or polycrystalline silicon (such as low temperature polycrystalline silicon (LTPS)), etc.

[0067] In the case of an NMOS transistor, a low voltage level may be an inactive level, and a high voltage level may be an active level. For example, when a signal applied to a control electrode of the NMOS transistor has a low voltage level, the NMOS transistor may be turned off. For example, when a signal applied to a control electrode of the NMOS transistor has a high voltage level, the NMOS transistor may be turned on.

[0068] In the case of a PMOS transistor, a low voltage level may be an effective level, and a high voltage level may be an ineffective level. For example, when a signal applied to a control electrode of a PMOS transistor has a low voltage level, the PMOS transistor may be turned on. For example, when a signal applied to a control electrode of a PMOS transistor has a high voltage level, the PMOS transistor may be turned off. That is, the effective level and the ineffective level may be determined according to the type of transistor.

[0069] Figure 3 It is a diagram of Figure 2 0 is a timing diagram of a comparative example in which sub-pixels are driven. Figure 4 The diagram is based on Figure 3 Graph of mura of a comparative example shown in FIG. Figure 5 It is a graphic with Figure 4 The timing diagram of how the sub-pixels corresponding to the dark portion are driven is shown in FIG. Figure 6 It is a graphic with Figure 4 The timing diagram of driving the sub-pixels corresponding to the bright parts shown in FIG.

[0070] Figures 3 to 6 is a diagram illustrating mura caused by a voltage drop (eg, IR Drop) of the first power supply voltage ELVDD, and refers to Figures 3 to 6 The contents described are related to comparative examples.

[0071] refer to Figure 2 and Figure 3 , the first period P1' and the second period P2' may be repeated alternately in one frame FR. The first period P1' may be a period in which the light emitting element LD does not emit light, and the second period P2' may be a period in which the light emitting element LD emits light.

[0072] In the first period P1', the first emission signal EM1 may have an inactive level except for a period for compensating for the threshold voltage Vth of the driving transistor T1. The first emission signal EM1 may have an active level throughout the second period P2'.

[0073] That is, the driving current may flow through the light emitting element LD in the second period P2 ′, and may not flow through the light emitting element LD in the first period P1 ′.

[0074] Figure 4 It is illustrated that white grayscale WG (eg, grayscale 255) is displayed in the top portion of the display area DA, and gray grayscale GG (eg, grayscale 127) is displayed in the other portion of the display area DA.

[0075] refer to Figures 2 to 4 , a region (ie, dark portion DP) where a grayscale darker than the gray grayscale GG is displayed and a region (ie, bright portion LP) where a grayscale brighter than the gray grayscale GG is displayed may appear in the display area DA. Hereinafter, this will be described in detail.

[0076] When current flows in a line to which the first power supply voltage ELVDD is provided, a voltage drop of the first power supply voltage ELVDD may occur. In particular, since a high drive current flows in the sub-pixel SP displaying the white grayscale WG, the difference in voltage drop between when the drive current flows in the sub-pixel SP displaying the white grayscale WG and when the drive current does not flow in the sub-pixel SP displaying the white grayscale WG may be large. Accordingly, when the drive current does not flow in the sub-pixel SP displaying the white grayscale WG instantaneously, the first power supply voltage ELVDD may increase. That is, the first power supply voltage ELVDD in the first period P1' for the sub-pixel SP displaying the white grayscale WG may increase. In addition, when the drive current flows in the sub-pixel SP displaying the white grayscale WG again, the first power supply voltage ELVDD may decrease.

[0077] refer to Figure 2 , Figure 4 and Figure 5 , when the first power supply voltage ELVDD increases in a period in which the first emission transistor T5 is turned off and before the write transistor T2 is turned on in one frame, a dark portion DP may appear. Due to the holding capacitor C2, the voltage of the second electrode of the driving transistor T1 may increase, and the gate-source voltage of the driving transistor T1 may decrease. Accordingly, the driving current may decrease. That is, a grayscale lower than the gray grayscale GG may be displayed in the dark portion DP.

[0078] refer to Figure 2 , Figure 4 and Figure 6, when the first power supply voltage ELVDD decreases in a period before the reference transistor T3 is turned on and then turned off in one frame, a bright portion LP may appear. Due to the holding capacitor C2, the voltage of the second electrode of the driving transistor T1 may decrease, and the gate-source voltage of the driving transistor T1 may increase. Accordingly, the driving current may increase. That is, a grayscale higher than the gray grayscale GG may be displayed in the bright portion LP.

[0079] Therefore, as the voltage drop of the first power supply voltage ELVDD is larger, mura may be more clearly seen. In addition, as the period (i.e., the off period) in which the first emission signal EM1 has an invalid level is longer, the mura caused by the voltage drop of the first power supply voltage ELVDD may be larger. Therefore, in order to reduce mura, it is necessary to reduce the off time of the first emission signal EM1.

[0080] Figure 7 It is a diagram of Figure 2 0 is a timing diagram of an example in which a sub-pixel is driven.

[0081] refer to Figure 2 and Figure 7 , the first period P1 and the second period P2 may be repeated alternately in one frame FR. In the present embodiment, it is illustrated that the first period P1 and the second period P2 are repeated four times. However, the present disclosure is not limited thereto.

[0082] The first period P1 may include a first sub-period SP1 in which a data voltage is written to the sub-pixel SP and a second sub-period SP2 different from the first sub-period SP1 .

[0083] Hereinafter, the operation in the first sub-period SP1 will be described.

[0084] First, the first emission signal EM1 having an inactive level may be applied to the sub-pixel SP. Accordingly, the first emission transistor T5 may be turned off, and an emission period based on a data voltage written in a previous frame may end.

[0085] Next, when the initialization gate signal GI having an effective level is applied to the sub-pixel SP, the first initialization transistor T4 may be turned on. Accordingly, the light emitting element LD may be initialized. Since the second emission transistor T6 is in a turned-on state, the first initialization voltage VINT1 may be applied to the second node N2. Therefore, the holding capacitor C2 may be initialized.

[0086] In addition, when the reference gate signal GR having an active level is applied to the sub-pixel SP, the reference transistor T3 may be turned on. Accordingly, the reference voltage VREF may be applied to the first node N1. Therefore, the storage capacitor C1 may be initialized.

[0087] Next, when the first emission signal EM1 having an effective level is applied to the sub-pixel SP, the first emission transistor T5 may be turned on. While the reference gate signal GR has an effective level, the voltage of the first electrode of the storage capacitor C1 may increase to correspond to the threshold voltage Vth of the driving transistor T1. Since the current flows through the first emission transistor T5 and the driving transistor T1, the voltage of the second node N2 may gradually increase. When the gate-source voltage of the driving transistor T1 reaches the threshold voltage Vth of the driving transistor T1, the driving transistor T1 may be turned off and the voltage of the second node N2 may be maintained. Accordingly, the storage capacitor C1 may store a voltage corresponding to the threshold voltage Vth of the driving transistor T1.

[0088] In a period in which the first emission signal EM1 and the reference gate signal GR have active levels, the initialization gate signal GI may have an active level. Accordingly, while the threshold voltage Vth of the driving transistor T1 is compensated, the first electrode (eg, anode electrode) of the light emitting element LD may be maintained at the first initialization voltage VINT1.

[0089] Next, when a write gate signal GW having an effective level is applied to the subpixel SP, the write transistor T2 may be turned on. In a state where the data voltage is applied to the data line DL, the data voltage may be written to the storage capacitor C1. The voltage of the second node N2 may vary according to the capacitance ratio of the capacitors C1 and C2 and the threshold voltage Vth of the driving transistor T1.

[0090] The initialization gate signal GI may have an active level in a period in which the write gate signal GW has an active level. Accordingly, while the data voltage is written, the first electrode (eg, anode electrode) of the light emitting element LD may be maintained at the first initialization voltage VINT1.

[0091] Next, in the second period P2 after the first sub-period SP1, when the first emission signal EM1 and the second emission signal EM2 having an effective level are applied to the sub-pixel SP, the first emission transistor T5 and the second emission transistor T6 may be turned on. Accordingly, the first power supply voltage ELVDD may be applied to the first electrode of the driving transistor T1, and the driving transistor T1 may be connected to the light emitting element LD. In addition, the driving transistor T1 may generate a driving current corresponding to the written data voltage, and the light emitting element LD may emit light by receiving the driving current.

[0092] The second emission signal EM2 may have an inactive level in at least a portion of the first sub-period SP1. In the second period P2 and the second sub-period SP2, the second emission signal EM2 may have an active level, and the reference gate signal GR and the write gate signal GW may have an inactive level.

[0093] In each of the first time periods P1, the first transmit signal EM1 may switch between an effective level and an ineffective level. For example, in each of the first time periods P1, the first transmit signal EM1 may include two ineffective periods and one effective period. The ineffective period is a period in which the first transmit signal EM1 has an ineffective level, and the effective period is a period in which the first transmit signal EM1 has an effective level.

[0094] The first emission signal EM1 may have an active level in the first part PP1 of the second sub-period SP2. Accordingly, the cut-off time of the first emission signal EM1 may be reduced. As described above, as the cut-off time of the first emission signal EM1 is reduced, mura caused by the voltage drop of the first power supply voltage ELVDD may be reduced.

[0095] In the second portion PP2 of at least one of the second sub-periods SP2 where the first emission signal EM1 has an inactive level, the initialization gate signal GI may have an active level. Accordingly, the light emitting element LD may be initialized between the second periods P2 where the light emitting element LD emits light.

[0096] In an embodiment, the initialization gate signal GI may have an inactive level in the first portion PP1 of the second sub-period SP2. Accordingly, in the first portion PP1, a driving current may flow through the light emitting element LD.

[0097] Figure 8 is a timing diagram illustrating an example in which a display device drives sub-pixels according to an embodiment of the present disclosure.

[0098] In addition to the initialization gate signal GI in the first part PP1, the display device according to this embodiment is Figure 1 The display device shown in FIG. 1 is substantially the same as that shown in FIG. 1 , and therefore, is similar to that shown in FIG. Figure 1 The same or similar components as those of the display device shown in FIG. 1 are denoted by the same reference numerals, and repeated description will be omitted.

[0099] refer to Figure 2 and Figure 8 , the initialization gate signal GI may have an active level in the first part PP1 of the second sub-period SP2. Accordingly, a certain current may flow through the light emitting element LD.

[0100] Fig. 9is a circuit diagram illustrating an example of a sub-pixel of a display device according to an embodiment of the present disclosure.

[0101] In addition to the second initialization transistor T7, the display device according to this embodiment is Figure 1 The display device shown in FIG. 1 is substantially the same as that shown in FIG. 1 , and therefore, is similar to that shown in FIG. Figure 1 The same or similar components as those of the display device shown in FIG. 1 are denoted by the same reference numerals, and repeated description will be omitted.

[0102] refer to Fig. 9 , the sub-pixel SP may further include a second initialization transistor T7 that supplies the second initialization voltage VINT2 supplied from the second initialization voltage line to the storage capacitor C1 in response to the initialization gate signal GI.

[0103] For example, the second initialization transistor T7 may include a control electrode receiving the initialization gate signal GI, a first electrode receiving the second initialization voltage VINT2, and a second electrode connected to the second node N2.

[0104] For example, when the initialization gate signal GI having an active level is applied to the subpixel SP, the second initialization transistor T7 may be turned on. Accordingly, the second initialization voltage VINT2 may be applied to the second node N2. Therefore, the storage capacitor C1 and the holding capacitor C2 may be initialized.

[0105] Fig.10 is a circuit diagram illustrating an example of a sub-pixel of a display device according to an embodiment of the present disclosure.

[0106] The display device according to this embodiment is similar to the display device according to the embodiment except that the display device according to this embodiment does not include the second emission transistor T6. Figure 1 The display device shown in FIG. 1 is substantially the same as that shown in FIG. 1 , and therefore, is similar to that shown in FIG. Figure 1 The same or similar components as those of the display device shown in FIG. 1 are denoted by the same reference numerals, and repeated description will be omitted.

[0107] refer to Fig.10 , the second electrode of the first initialization transistor T4 may be directly connected to the second node N2, and the first electrode of the light emitting element LD may be directly connected to the second node N2.

[0108] For example, when the initialization gate signal GI having an active level is applied to the subpixel SP, the first initialization transistor T4 may be turned on. Accordingly, the first initialization voltage VINT1 may be applied to the second node N2. Thus, the light emitting element LD, the storage capacitor C1, and the holding capacitor C2 may be initialized.

[0109] Fig.11is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure.

[0110] refer to Fig.11 In the method of driving a display device, a data voltage may be written to a sub-pixel in a first sub-period (step S100), a first emission signal having a valid level may be provided to the sub-pixel in a second period after the first sub-period, thereby allowing a light-emitting element of the sub-pixel to emit light (step S200), a first emission signal switched between a valid level and an invalid level may be provided to the sub-pixel in a second sub-period after the second period (step S300), and a first emission signal having a valid level may be provided to the sub-pixel in a second period after the second sub-period, thereby allowing the light-emitting element to emit light (step S400).

[0111] Can be used for reference Figure 2 as well as Figures 7 to 10 Any of the sub-pixels described performs Fig.11 Therefore, repeated description will be omitted.

[0112] Fig.12 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. Fig.13 It is a diagram of Fig.12 The electronic device shown in FIG. 1 is a diagram of an example in which the electronic device is implemented as a television.

[0113] refer to Fig.12 and Fig.13 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be Figure 1 In addition, the electronic device 1000 may further include several ports capable of communicating with a video card, a sound card, a memory card, a USB device, etc. or communicating with other systems. In an embodiment, as Fig.13 As shown in , the electronic device 1000 can be implemented as a TV. However, this is merely illustrative, and the electronic device 1000 is not limited thereto. For example, the electronic device 1000 can be implemented as a mobile phone, a videophone, a smart tablet, a smart watch, a tablet PC, a vehicle navigation system, a computer monitor, a notebook computer, or a head-mounted display device, etc.

[0114] The processor 1010 can perform specific calculations or tasks. In some embodiments, the processor 1010 can be a microprocessor, a central processing unit, or an application processor. The processor 1010 can be connected to other components through an address bus, a control bus, and a data bus. In some embodiments, the processor 1010 can be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0115] The memory device 1020 may store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include a nonvolatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, or a ferroelectric random access memory (FRAM) device, and / or a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, or a mobile DRAM device.

[0116] The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, and the like.

[0117] The I / O device 1040 may include an input tool such as a keyboard, a keypad, a touch screen, or a mouse, and an output tool such as a speaker or a printer. In some embodiments, the display device 1060 may be included in the I / O device 1040 .

[0118] The power supply 1050 may supply power required for the operation of the electronic device 1000. For example, the power supply 1050 may be a power management integrated circuit (PMIC).

[0119] The display device 1060 may display an image corresponding to the visual information of the electronic device 1000. The display device 1060 may be an organic light emitting display device or a quantum dot light emitting display device, but the present disclosure is not limited thereto. The display device 1060 may be connected to other components via a bus or another communication link.

[0120] The present disclosure may be applied to a display device and an electronic device including the display device. For example, the present disclosure may be applied to a digital TV, a 3D TV, a mobile phone, a smart phone, a tablet computer, a VR device, a PC, a home appliance, a notebook computer, a PDA, a PMP, a digital camera, a music player, a portable game console, and a navigation system, etc.

[0121] In the display device according to the present disclosure, the off time of the first emission signal is reduced, so that mura caused by the voltage drop (eg, IR Drop) of the first power supply voltage can be minimized.

[0122] Example embodiments have been disclosed herein, and although specific terms are used, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art upon filing this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless specifically indicated otherwise. Therefore, those skilled in the art will appreciate that various changes may be made in form and detail without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A display device, comprising: A display panel including sub-pixels; as well as A display panel driver is configured to drive the display panel. Wherein, the sub-pixel comprises: A driving transistor, generating a driving current, wherein the driving transistor comprises a control electrode, a first electrode, and a second electrode; a storage capacitor connected between the control electrode of the driving transistor and the second electrode of the driving transistor; a write transistor connected between a data line and the control electrode of the drive transistor, the write transistor writing a data voltage into the storage capacitor in response to a write gate signal; a first emission transistor connected between a first power supply voltage line providing a first power supply voltage and the first electrode of the driving transistor, the first emission transistor providing the first power supply voltage to the first electrode of the driving transistor in response to a first emission signal; a holding capacitor connected between the first power supply voltage line and the second electrode of the driving transistor; and a light emitting element connected to the driving transistor, and The first transmission signal has a valid level in a first part of each of the first time periods of a frame, and has the valid level in each of the second time periods respectively located after the first time period.

2. The display device according to claim 1, wherein: In each of the first time periods, the first transmission signal switches between the active level and the inactive level.

3. The display device according to claim 1, wherein: The first period includes a first sub-period in which the data voltage is written to the sub-pixel and a second sub-period different from the first sub-period.

4. The display device according to claim 3, wherein: The sub-pixel further includes a first initialization transistor connected between a first initialization voltage line providing a first initialization voltage and the light emitting element, the first initialization transistor providing the first initialization voltage to the light emitting element in response to an initialization gate signal, and The initialization gate signal has a valid level in a second portion of the second sub-period in which the first emission signal has an invalid level.

5. The display device according to claim 4, wherein: The initialization gate signal has an inactive level in the first portion of the second sub-period.

6. The display device according to claim 4, wherein: The initialization gate signal has the active level in the first portion of the second sub-period.

7. The display device according to claim 1, wherein: Each of the first periods includes a first sub-period in which the data voltage is written to the sub-pixel and a second sub-period different from the first sub-period, The sub-pixel further includes a first initialization transistor connected between a first initialization voltage line providing a first initialization voltage and the light-emitting element, the first initialization transistor providing the first initialization voltage to the light-emitting element in response to an initialization gate signal, and The initialization gate signal has a valid level in a second portion of at least one of the second sub-periods in which the first emission signal has an invalid level.

8. The display device according to claim 1, wherein: The first period includes a first sub-period in which the data voltage is written to the sub-pixel and a second sub-period different from the first sub-period, and The write gate signal has a valid level in at least a portion of the first sub-period, and has an invalid level in the second sub-period and the second period.

9. The display device according to claim 8, wherein: The sub-pixel further includes a first initialization transistor connected between a first initialization voltage line providing a first initialization voltage and the light emitting element, the first initialization transistor providing the first initialization voltage to the light emitting element in response to an initialization gate signal, and The initialization gate signal has a valid level in a period in which the write gate signal has the valid level.

10. The display device according to claim 1, wherein: The sub-pixel further includes a reference transistor connected between a reference voltage line supplying a reference voltage and the control electrode of the driving transistor, the reference transistor supplying the reference voltage to the storage capacitor in response to a reference gate signal.

11. The display device according to claim 10, wherein: The first period includes a first sub-period in which the data voltage is written to the sub-pixel and a second sub-period different from the first sub-period, and The reference gate signal has a valid level in at least a portion of the first sub-period, and has an invalid level in the second sub-period and the second period.

12. The display device according to claim 11, wherein: The sub-pixel further includes a first initialization transistor connected between a first initialization voltage line providing a first initialization voltage and the light emitting element, the first initialization transistor providing the first initialization voltage to the light emitting element in response to an initialization gate signal, and The initialization gate signal has the effective level in a period in which the first emission signal and the reference gate signal have the effective level.

13. The display device according to claim 1, wherein: The sub-pixel further includes a second emission transistor connected between the drive transistor and the light emitting element, the second emission transistor connecting the drive transistor to the light emitting element in response to a second emission signal.

14. The display device according to claim 13, wherein: The first period includes a first sub-period in which the data voltage is written to the sub-pixel and a second sub-period different from the first sub-period, and The second transmission signal has an invalid level in at least a part of the first sub-period, and has a valid level in the second sub-period and the second period.

15. The display device according to claim 1, wherein: The subpixel further includes a second initialization transistor connected between a second initialization voltage line providing a second initialization voltage and the second electrode of the driving transistor, the second initialization transistor providing the second initialization voltage to the storage capacitor in response to an initialization gate signal.

16. A method for driving a display device, the method comprising: Writing a data voltage into a sub-pixel in a first sub-period; providing a first emission signal having an effective level to the sub-pixel in a second period after the first sub-period, thereby allowing a light-emitting element of the sub-pixel to emit light; providing the first emission signal switched between the effective level and the ineffective level to the sub-pixel in a second sub-period after the second period; as well as The first emission signal having the active level is provided to the sub-pixel in a second period after the second sub-period, thereby allowing the light emitting element to emit light.

17. The method according to claim 16, wherein: The sub-pixel comprises: A driving transistor generates a driving current; a storage capacitor connected to the control electrode of the drive transistor; a write transistor that writes the data voltage into the storage capacitor in response to a write gate signal; a first emission transistor that supplies a first power supply voltage to a first electrode of the driving transistor in response to the first emission signal; and a holding capacitor including a first electrode receiving the first power supply voltage and a second electrode connected to the second electrode of the driving transistor, and The light emitting element emits light by receiving the driving current from the driving transistor.

18. The method according to claim 16, further comprising: In a portion of the second sub-period in which the first emission signal has the inactive level, a first initialization voltage is applied to the light emitting element.

19. The method according to claim 18, further comprising: In a portion of the second sub-period in which the first emission signal has the active level, the first initialization voltage is applied to the light emitting element.

20. The method according to claim 16, wherein: When the data voltage is written into the sub-pixel, a first initialization voltage is applied to the light emitting element.

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