Coding and decoding equipment and system

Abstract

The invention discloses a coding and decoding device and system in the technical field of computers. According to the coding and decoding device, all RAID algorithm actuators in the coding and decoding device are called according to the parallel and time division multiplexing principle to conduct coding calculation or decoding calculation, the coding and decoding device is suitable for various types of RAID algorithms, flexibility is high, application is wide, the data throughput rate and the hardware resource utilization rate can be increased, and therefore the execution efficiency of the RAID algorithms is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and particularly relates to an encoding and decoding device and system. Background Art

[0002] Currently, most RAID (Redundant Arrays of Independent Disks) algorithms are executed by software. The execution efficiency of software is limited by the performance of the host CPU (Central Processing Unit), and the execution process of the algorithm may also compete for resources with other services on the host, resulting in a large overhead of the host CPU and slowing down the execution efficiency of the RAID algorithm.

[0003] Therefore, how to improve the execution efficiency of the RAID algorithm is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide an encoding and decoding device and system to improve the execution efficiency of the RAID algorithm. The specific scheme is as follows:

[0005] In a first aspect, the present invention provides an encoding and decoding device, including: a first processing core, a first cache connected to the first processing core, a plurality of RAID algorithm executors connected to the first cache, a second cache connected to each RAID algorithm executor, and a second processing core connected to the second cache;

[0006] Among them, the first processing core is used for: obtaining a target task and the data to be processed of the target task; the target task is used to implement the encoding calculation or decoding calculation of at least one RAID algorithm;

[0007] Correspondingly, the first processing core is used for: dividing the data to be processed according to the time-division multiplexing principle and the type of the RAID algorithm implemented by the target task, to obtain a plurality of sub-data;

[0008] The first cache is used for: storing the plurality of sub-data;

[0009] Each RAID algorithm executor is used for: reading at least one sub-data matching the RAID algorithm engine in itself from the first cache, and performing encoding calculation or decoding calculation on the read sub-data by using the RAID algorithm engine;

[0010] The second cache is used for: storing the calculation results output by each RAID algorithm executor;

[0011] The second processing core is configured to: generate an address access command according to the calculation result stored in the second cache, and send a command generated message to the host to which the codec device belongs, so that the host obtains the address access command according to the command generated message, and directly reads the calculation result from the second cache according to the address access command; the address access command is used to access a storage address segment in the second cache.

[0012] Optionally, the first processing core includes:

[0013] The task parsing module is configured to: parse the target task to obtain a parsing result; the parsing result includes: the type of RAID algorithm implemented by the target task, the number of encoding calculations for encoding, the number of decoding calculations for decoding, the valid data bit information, parity bit information, address list pointer, and parameter list pointer associated with the data to be processed.

[0014] The task processing module is configured to: divide the data to be processed when it is determined that the parsing result is correct.

[0015] Optionally, the task processing module includes:

[0016] The time-division multiplexing control unit is configured to: determine a time-division multiplexing allocation rule according to the parsing result and the running conditions of each RAID algorithm executor.

[0017] The address information reading unit is configured to: read the storage address of the data to be processed in the host.

[0018] The data parameter reading unit is configured to: determine the row and column sizes of the data matrix to be read according to the time-division multiplexing allocation rule, read the data from the storage address of the data to be processed in the host, and write the read data into the first cache.

[0019] Optionally, the task processing module is further configured to: discard the target task and send a task error message to the host to which the codec device belongs when it is determined that the parsing result is incorrect.

[0020] Optionally, the first cache includes: a plurality of input cache units;

[0021] Correspondingly, each input cache unit is configured to: store at least one sub-data that matches the same RAID algorithm engine.

[0022] Optionally, each RAID algorithm executor includes: at least one RAID algorithm engine;

[0023] Accordingly, any RAID algorithm engine is used for: performing encoding calculation or decoding calculation using RAID1 algorithm, RAID2 algorithm, RAID3 algorithm, RAID5 algorithm, RAID6 algorithm or RAIDTP algorithm.

[0024] Optionally, each RAID algorithm executor is further used for: distributing at least one sub-data read to different RAID algorithm engines in itself according to the time-division multiplexing principle, so that different RAID algorithm engines in the same RAID algorithm executor operate according to the time-division multiplexing principle.

[0025] Optionally, the second cache includes: a plurality of output cache units;

[0026] Accordingly, each output cache unit is used for: storing the calculation results output by the same RAID algorithm executor.

[0027] Optionally, the second processing core includes:

[0028] The command generation module is used for: generating an address access command according to the calculation results stored in the second cache;

[0029] The trigger module is used for: sending a command generated message to the host to which the codec device belongs, so that the host obtains the address access command according to the command generated message, and directly reads the calculation results from the second cache according to the address access command.

[0030] Optionally, the command generation module is specifically used for: when detecting that a new calculation result is written into the second cache, generating a corresponding address access command based on the storage address of the new calculation result in the second cache, and recording the address access command in the circular command table.

[0031] Optionally, the trigger module is specifically used for: when detecting that there is an unprocessed address access command in the circular command table, sending a command generated message to the host to which the codec device belongs.

[0032] Optionally, the trigger module is specifically used for: detecting the valid flag information corresponding to each address access command in the circular command table, and determining whether there is an unprocessed address access command in the circular command table according to the valid flag information.

[0033] Optionally, the second processing core is further used for: performing row-column reorganization on the calculation results output by different RAID algorithm executors in the second cache according to the target task, so as to integrate the calculation results.

[0034] Optionally, each RAID algorithm executor includes: an enabling device;

[0035] Accordingly, the enabling device is used to enable or disable the corresponding RAID algorithm executor.

[0036] Optionally, the first processing core is further used to send a ready message to the host to which the encoding / decoding device belongs, so that the host sends the target task and the data to be processed to the first processing core according to the ready message.

[0037] Optionally, the first processing core further includes: a configuration register;

[0038] Accordingly, the configuration register is used to configure the number of encodings for encoding calculations and the number of decodings for decoding calculations in response to an externally input configuration operation, so as to adjust the type of RAID algorithm supported by the encoding / decoding device.

[0039] In a second aspect, the present invention provides an encoding / decoding system, including: a host and the encoding / decoding device according to any one of the foregoing items.

[0040] Optionally, there are multiple encoding / decoding devices; the host is communicatively connected to each encoding / decoding device.

[0041] Optionally, the host communicates with each encoding / decoding device through Remote Direct Memory Access (RDMA) technology and / or Direct Memory Access (DMA) technology.

[0042] Optionally, the host is connected to each encoding / decoding device through an expansion chip.

[0043] As can be seen from the above solution, the present invention provides an encoding and decoding device, including: a first processing core, a first cache connected to the first processing core, a plurality of RAID algorithm executors connected to the first cache, a second cache connected to each RAID algorithm executor, and a second processing core connected to the second cache; wherein, the first processing core is configured to: obtain a target task and the data to be processed of the target task; the target task is used to implement the encoding calculation or decoding calculation of at least one RAID algorithm; correspondingly, the first processing core is configured to: divide the data to be processed according to the time division multiplexing principle and the type of the RAID algorithm implemented by the target task, to obtain a plurality of sub-data; the first cache is configured to: store the plurality of sub-data; each RAID algorithm executor is configured to: read at least one sub-data matching the RAID algorithm engine in itself from the first cache, and perform encoding calculation or decoding calculation on the read sub-data by using the RAID algorithm engine; the second cache is configured to: store the calculation results output by each RAID algorithm executor; the second processing core is configured to: generate an address access command according to the calculation results stored in the second cache, and send a command generated message to the host to which the encoding and decoding device belongs, so that after the host obtains the address access command according to the command generated message, and directly reads the calculation results from the second cache according to the address access command; the address access command is used to access a segment of storage address in the second cache.

[0044] It can be seen that the present invention provides a hardware device dedicated to RAID encoding and decoding, and the beneficial effects are as follows: it can call RAID algorithm executors to perform encoding calculation or decoding calculation according to the parallel and time division multiplexing principles, and is applicable to various types of RAID algorithms, with high flexibility and wide application, and can improve data throughput rate and hardware resource utilization rate, and improve the execution efficiency of RAID algorithms.

[0045] Correspondingly, an encoding and decoding system provided by the present invention also has the above technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0047] Figure 1 Schematic diagram of an encoding and decoding device disclosed by the present invention;

[0048] Figure 2Another schematic diagram of the encoding and decoding device disclosed by the present invention;

[0049] Figure 3 A schematic diagram of a time-division multiplexing process disclosed by the present invention;

[0050] Figure 4 A communication schematic diagram among a command processor, an encoding and decoding device, and a host disclosed by the present invention;

[0051] Figure 5 A schematic diagram of a circular command shown by the present invention;

[0052] Figure 6 A schematic diagram of an encoding and decoding system disclosed by the present invention;

[0053] Figure 7 A structural diagram of the encoding and decoding device 1 provided by the present invention;

[0054] Figure 8 A structural diagram of the encoding and decoding device 2 provided by the present invention. Detailed implementation manners

[0055] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0056] Currently, most RAID algorithms are executed by software. The execution efficiency of software is limited by the performance of the host CPU, and the execution process of the algorithm may also compete for resources with other services on the host, resulting in a large overhead of the host CPU and slowing down the execution efficiency of the RAID algorithm. For this reason, the present invention provides an encoding and decoding scheme, which can be applied to various types of RAID algorithms, has high flexibility, wide application, can improve the data throughput rate and the utilization rate of hardware resources, and improve the execution efficiency of the RAID algorithm.

[0057] See Figure 1 As shown, an embodiment of the present invention discloses an encoding and decoding device, including: a first processing core, a first cache connected to the first processing core, a plurality of RAID algorithm executors connected to the first cache, a second cache connected to each RAID algorithm executor, and a second processing core connected to the second cache.

[0058] Among them, the first processing core is used to: obtain a target task and the data to be processed of the target task; the target task is used to implement the encoding calculation or decoding calculation of at least one RAID algorithm.

[0059] Accordingly, the first processing core is used to: divide the data to be processed according to the time-division multiplexing principle and the type of RAID algorithm implemented by the target task, so as to obtain a plurality of sub-data.

[0060] The first cache is used to: store a plurality of sub-data.

[0061] Each RAID algorithm executor is used to: read at least one sub-data matching the RAID algorithm engine in itself from the first cache, and perform encoding calculation or decoding calculation on the read sub-data by using the RAID algorithm engine.

[0062] The second cache is used to: store the calculation results output by each RAID algorithm executor.

[0063] The second processing core is used to: generate an address access command according to the calculation results stored in the second cache, and send a command generated message to the host to which the encoding / decoding device belongs, so that after the host obtains the address access command according to the command generated message, it directly reads the calculation results from the second cache according to the address access command; the address access command is used to access a segment of storage addresses in the second cache.

[0064] In this embodiment, each RAID algorithm executor can run in parallel and can also run alternately according to the time-division multiplexing principle. For example, when there are multiple target tasks, each RAID algorithm executor is allowed to process the input data of different target tasks; at the same time, different RAID algorithm engines in the same RAID algorithm executor can also run in parallel or run alternately according to the time-division multiplexing principle.

[0065] In one implementation, the first processing core includes: a task parsing module for: parsing the target task to obtain a parsing result; the parsing result includes: the type of RAID algorithm implemented by the target task, the number of encoding for encoding calculation, the number of decoding for decoding calculation, the valid data bit information, parity bit information, address list pointer and parameter list pointer associated with the data to be processed; a task processing module for: when it is determined that the parsing result is correct, dividing the data to be processed.

[0066] In one implementation, the task processing module includes: a time-division multiplexing control unit for: determining a time-division multiplexing allocation rule according to the parsing result and the running conditions of each RAID algorithm executor; an address information reading unit for: reading the storage address of the data to be processed in the host; a data parameter reading unit for: determining the row and column sizes of the data matrix to be read according to the time-division multiplexing allocation rule, and after reading the data from the storage address of the data to be processed in the host, writing the read data into the first cache.

[0067] In one implementation, the task processing module is further used to: when it is determined that the parsing result is incorrect, discard the target task and send a task error message to the host to which the encoding / decoding device belongs.

[0068] In one embodiment, the first cache includes: a plurality of input cache units; correspondingly, each input cache unit is configured to: store at least one sub-data that matches the same RAID algorithm engine.

[0069] In one embodiment, each RAID algorithm executor includes: at least one RAID algorithm engine; correspondingly, any RAID algorithm engine is configured to: perform encoding calculation or decoding calculation using RAID1 algorithm, RAID2 algorithm, RAID3 algorithm, RAID5 algorithm, RAID6 algorithm or RAIDTP algorithm.

[0070] RAID is a redundant disk array. A disk array is formed by combining multiple independent disks to obtain a disk group with a large capacity. By adopting RAID storage technology, the storage capacity can be increased, the request capacity of the system input and output can be improved, and the data reliability can be enhanced through data distributed storage technology, parallel access means and information redundancy technology. RAID mainly utilizes data striping, mirroring and data verification technologies to achieve high performance, reliability, high fault tolerance and scalability. Many RAID algorithms have been derived according to the strategies and architectures of applying or combining these technologies. Among them, the most widely used are RAID5, RAID6 and RAIDTP. TP (Triple Parity) represents triple parity check.

[0071] The data in RAID is distributed to each disk in units of blocks. RAID5 stores the data and its corresponding parity check information on each disk that makes up RAID5. When one disk data in RAID5 is damaged, the remaining data and the corresponding check information are used to recover the damaged data. RAID6 adds another check disk on the basis of RAID5, that is, RAID6 can recover the data lost on two disks. RAIDTP adds another check disk on the basis of RAID6, that is, RAIDTP can recover the data lost on three disks.

[0072] In one example, the distribution of the data included in a stripe corresponding to RAID5 on the disks can be seen in Table 1. In Table 1, D1, D2... Dn are n data included in a stripe and come from different disks, P is the check data included in the stripe, and the following operation relationship is satisfied: K1*D1⊕K2*D2⊕K3*D3⊕…⊕Kn*Dn⊕P = 0; * represents Galois field multiplication, K1, K2, K3... Kn are Galois multiplication operation parameters; ⊕ is the exclusive OR operator.

[0073] Table 1

[0074]

[0075] Accordingly, the encoding formula for RAID5 is as follows: The decoding formula is: It does not include the Dx term. If any one of the data included in a stripe of RAID5 is lost, it can be recovered through other data.

[0076] In one example, the distribution of the data included in a stripe corresponding to RAID6 on the disk can be seen in Table 2. In Table 2, D1, D2... Dn are n data included in a stripe and come from different disks, and P and Q are the parity data included in this stripe, and satisfy the following operation relationships: According to the principle of solving a system of binary linear equations, RAID6 can recover the data missing from at most two disks.

[0077] Table 2

[0078]

[0079] In one example, the distribution of the data included in a stripe corresponding to RAIDTP on the disk can be seen in Table 3. In Table 3, D1, D2... Dn are n data included in a stripe and come from different disks, and P, Q, and R are the parity data included in this stripe, and satisfy the following operation relationships: According to the principle of solving a system of ternary linear equations, RAIDTP can recover the data missing from at most three disks.

[0080] Table 3

[0081]

[0082] It can be seen that different RAID algorithms can calculate different amounts of parity data. Therefore, different RAID algorithms require different RAID algorithm engines for encoding or decoding.

[0083] Since there are the following three modes for writing to the disk:

[0084] Mode 1: Full stripe write. The new data to be written fills the entire stripe. In this case, the parity information of the data to be written can be calculated, and the entire stripe can be directly written to the disk. In this case, there is no old data, and the parity value can be directly calculated.

[0085] Mode 2: Read-modify-write. Read the old data (D) to be modified and the original parity data, and calculate the parity value together with the newly written data (D′).

[0086] Mode 3: Reconstructive writing. Read the data (D) on this stripe that does not need to be modified, calculate the checksum together with the new data (D′) to be written, and write it to the disk.

[0087] Under different writing modes, different engine circuits are also required for implementation. Among them, Mode 2 and Mode 3 also need to calculate PPL.

[0088] Suppose a RAID5 stripe as shown in Table 4 is formed. In Table 4, D1 to D7 are data blocks. If the data of D2 and D3 is updated to D2′ and D3′ at this time, it is necessary to consider that when the disk where the unmodified data (in this example, D1, D4, D5, D6, D7) is removed (the disk is pulled out or damaged) during the process of writing D2′ and D3′, RAID5 needs to protect any 1 disk where the unmodified data is located during this process can be recovered. In order to protect the unmodified data, PPL is introduced. PPL is the checksum of the unmodified data. In this example,

[0089] Table 4

[0090] D1 D2 D3 D4 D5 D6 D7 P

[0091] The following introduces the calculation methods of the check data P′ and PPL under the three modes: In Mode 1, the data on all disks will be modified, and the checksum is calculated using all the new data. Then there is: D1′~Dn′ are new data. Mode 2 is used for scenarios where the disk data to be modified is relatively small (less than half of the stripe); for example, among the n data D1~Dn of a stripe, only D2 and D3 are modified. Then the old data in this stripe satisfies: According to the principle of exclusive OR operation, it can be obtained that: Therefore, after the old data D2 and D3 are replaced by the new data D2′ and D3′, the calculation formula for the new checksum P′ is: Under Mode 2, the calculation formula for PPL is as follows: Mode 3 is applicable to scenarios where the disk data to be modified is relatively large (more than half of the stripe); for example, among the n data D1~Dn of a stripe, D2 and D3 are modified. Then the calculation formula for the new checksum P′ is: Among them, P′ is the newly calculated checksum, which can be omitted. Then the calculation formula for PPL under Mode 3 is as follows:

[0092] It should be noted that the RAID algorithm engine provided in this embodiment is used to calculate the respective calculation formulas of the foregoing examples. Thus, the RAID algorithm engine needs to have various types in order to meet the encoding and decoding requirements of different RAID algorithms in different modes.

[0093] In one implementation, each RAID algorithm executor is further configured to: distribute at least one sub-data read to different RAID algorithm engines in itself according to the time-division multiplexing principle, so that different RAID algorithm engines in the same RAID algorithm executor operate according to the time-division multiplexing principle.

[0094] In one implementation, the second cache includes: a plurality of output cache units; correspondingly, each output cache unit is configured to: store the calculation results output by the same RAID algorithm executor.

[0095] In one implementation, the second processing core includes: a command generation module configured to: generate an address access command according to the calculation results stored in the second cache; a trigger module configured to: send a command generated message to the host to which the codec device belongs, so that the host obtains the address access command according to the command generated message, and directly reads the calculation results from the second cache according to the address access command. Specifically, the command generation module is configured to: when detecting that a new calculation result is written into the second cache, generate a corresponding address access command based on the storage address of the new calculation result in the second cache, and record the address access command in the circular command table. Specifically, the trigger module is configured to: when detecting that there is an unprocessed address access command in the circular command table, send a command generated message to the host to which the codec device belongs.

[0096] In one implementation, the trigger module is specifically configured to: detect the valid flag information corresponding to each address access command in the circular command table, and determine whether there is an unprocessed address access command in the circular command table according to the valid flag information.

[0097] In one implementation, the second processing core is further configured to: perform row-column reorganization on the calculation results output by different RAID algorithm executors in the second cache according to the target task, so as to integrate the calculation results.

[0098] In one implementation, each RAID algorithm executor includes: an enabling device; correspondingly, the enabling device is configured to: enable or disable the corresponding RAID algorithm executor.

[0099] In one implementation, the first processing core is further configured to: send a ready message to the host to which the codec device belongs, so that the host sends a target task and data to be processed to the first processing core according to the ready message.

[0100] In one embodiment, the first processing core further includes: a configuration register; correspondingly, the configuration register is used for: in response to a configuration operation input externally, configuring the number of encodings for encoding calculations and the number of decodings for decoding calculations, so as to adjust the type of RAID algorithm supported by the encoding and decoding device.

[0101] The encoding and decoding device provided in this embodiment can perform task allocation and is a high-performance and high-concurrency RAID hardware system. It can be seen that this embodiment provides a hardware device dedicated to performing RAID encoding and decoding. This device can call the RAID algorithm executor to perform encoding calculations or decoding calculations according to the principles of parallelism and time-division multiplexing, and is applicable to various types of RAID algorithms, with high flexibility and wide application. It can improve the data throughput rate and the utilization rate of hardware resources, and improve the execution efficiency of the RAID algorithm.

[0102] Please refer to Figure 2 , the present invention provides another encoding and decoding device. This device can perform time-division multiplexing on the hardware from multiple dimensions and supports multi-channel concurrency. At the same time, time-division multiplexing is supported both between multiple channels and within a single channel. A channel refers to Figure 2 one of the data calculation units therein (i.e., Figure 1 the RAID algorithm executor therein).

[0103] For Figure 2 the device shown, the user can configure two modes: Mode 1 is the encoding processing process (the encoding process can also calculate PPL), and Mode 2 is the decoding processing process. The encoding process is used to calculate check data or PPL. The user can configure: the number of data blocks Dx, the number of check blocks Dy, the flag indicating the position of the check block in the disk, etc. Taking 16 disks as an example, when the flag is 16 bits, it can represent a maximum of 16 disks. The user can freely configure the position of the check bit in the disk according to the scenario. In fact, the number of disks of this hardware can be expanded arbitrarily. The decoding process is used to recover the missing data. The user can configure: the data block Dx, the total number of check blocks Dy, the flag indicating the position of the missing data block in the disk, etc. Taking 16 disks as an example, when the flag is 16 bits, it can represent a maximum of 16 disks. The user can freely configure the position of the missing data block in the disk according to the scenario. The maximum number of missing data for RAID5 is 1, the maximum number of missing data for RAID6 is 2, and the maximum number of missing data for RAIDTP is 3.

[0104] Data reading, address reading, etc. are completed through externally assisted hardware, such as DMA.

[0105] If Figure 2The device shown is configured as follows: 6 inputs and 6 outputs, and there are 8 data calculation units in the device. When the device is running, the 8 data calculation units are time-division multiplexed, and each calculation engine within a single data calculation unit is also time-division multiplexed to accelerate the encoding and decoding process of data processing. It also supports multi-channel simultaneous encoding or decoding.

[0106] The encoding and decoding device provided in this embodiment can calculate check values, encoding values, or each PPL value simultaneously on multiple channels. For different tasks, in order to maximize the execution rate of the system, time-division multiplexing between channels and time-division multiplexing within channels are used to accelerate the system performance from two levels of large data granularity and small data granularity. The execution of different tasks does not need to wait for each other, maximizing the utilization of the idle time that exists between tasks and task execution.

[0107] Among them, the time-division multiplexing between channels with large data granularity is as follows: when task A is executed, some idle channels are utilized through time-division multiplexing to execute task B. This method can greatly improve the execution rate of the system in complex task scenarios. At the large granularity, the idle channel resources and the resources required by tasks are detected in real time and dynamically, and tasks are reasonably allocated to idle channels for processing, which has a very large flexibility and performance improvement compared to the previous processing form of task-channel binding.

[0108] The time-division multiplexing within channels with small data granularity is as follows: when the task volume is relatively large, if all channels are running at full load, within a single channel, different calculation engines run in a time-division multiplexing mechanism to maximize the utilization of the idle time within a single channel and improve the performance of the entire system. The multiplexing of calculation engines within small-granularity channels can avoid the waste of time intervals. For example: when processing a two-dimensional matrix and a one-dimensional matrix, if the two-dimensional matrix is processed first and then the one-dimensional matrix, it is necessary to wait. If the time-division multiplexing principle is adopted, the two-dimensional matrix is split into multiple one-dimensional matrices, and the split one-dimensional matrices are processed in different time periods, so that the processing of the split one-dimensional matrices and the original one-dimensional matrix is parallel, thereby minimizing the overall time of the two tasks and achieving the purpose of improving the system efficiency.

[0109] As Figure 2 shown, the overall hardware structure of the device is divided into a control plane and a data plane. The control plane is mainly responsible for the scheduling of system addresses, control instructions, matrix allocation, time-division multiplexing granularity control, and the generation of its instructions. The data plane is mainly responsible for processing data input, output, calculation, and integration.

[0110] Among them, the task parsing module: parses the CB command information and task information dispatched by the NVME protocol to obtain information such as task type, number of processed data, number of decoded data, number of parity bits, address list pointer, address of the parameter list pointer, and valid data bits. Parses the NVME protocol and determines whether the information is correct. If it is incorrect, directly discard this task and report an error. If it is correct, the task processing module sorts out the instructions for each module based on the parsed information and configures the corresponding instructions for each module: the data parameter matrix reading unit (data parameter reading unit), output data controller, time-division multiplexing matrix control unit (i.e., time-division multiplexing control unit), input data dispatcher, data address information reading unit (i.e., address information reading unit), and processing result summarizing unit.

[0111] Among them, the task processing module includes: a data parameter matrix reading unit, an output data controller, a time-division multiplexing matrix control unit, an input data dispatcher, a data address information reading unit, and a processing result summarizing unit. The processing result summarizing unit can respond to the task processing progress externally, and the task calculation result reaches the outside through the command processor.

[0112] The data parameter matrix reading unit: reads the corresponding matrix parameters according to the mode issued by the system, and then adjusts the row and column sizes of the scheduling matrix variably according to time-division multiplexing control. The data parameter matrix reading unit and the data address information reading unit read the parameter matrix and the data address list into the internal address buffer and parameter matrix buffer according to the mode requirements and the amount of data to be calculated for consumption by the lower-level modules.

[0113] The time-division multiplexing matrix control unit: generates an encoding matrix or a decoding matrix for one-time processing according to the data transmission throughput requirement, and this matrix can be flexibly set according to the configuration. Calculates the time-division multiplexing task allocation rule according to the system task type (encoding, decoding, number of encoding and decoding, number of input data, and channel idle condition, etc.). For example: how much data each task should process, and different types of tasks reasonably arrange the corresponding channels to execute encoding, etc. according to the channel idle and the number of input data. After receiving the configuration, the input data dispatcher determines the encoding or decoding task, further determines the usage of each data calculation channel, and schedules the corresponding encoding and decoding matrix. Reads data from the outside into the multi-channel data input buffer (i.e., multiple input buffer units). The output data controller sends the address sequence and rule of the solution data to the data plane for use according to the number of encoding and decoding.

[0114] Input Data Dispatcher: According to the instructions of the task processing module, it reads external data into the data input buffer. Based on the instruction information of the time-division multiplexing matrix control unit and the channel execution information of data feedback, it generates time-division multiplexing control instructions and matrix distribution rules. According to the number of matrix rows and columns sent by the time-division multiplexing matrix control unit, the execution status of lower-level module tasks (information such as how many data caches are occupied, how many data calculation units are in use, and how many are idle), and the task types of the task parsing module, etc., it reads data and sends it into the matching data input buffer. For example: For the first 3+1 encoding task, both the data calculation unit and the data input buffer are idle, so the data is stored in data caches 1, 2, and 3. The time-division multiplexing input data dispatcher distributes the data to data calculation units 1, 2, and 3 for processing. For the second 3+1 decoding task, the data is sent into data input caches 4, 5, and 6, and the time-division multiplexing input data distribution control unit sends the data into data calculation units 4, 5, and 6 for processing. The time-division multiplexing input data distribution module will arbitrarily distribute the data to the data calculation units according to the idle situation of the data calculation units, thereby improving the system efficiency. Using the time-division multiplexing mechanism, it achieves no waiting in the data processing pipeline within a RAID algorithm task and no waiting in the data processing pipeline between tasks.

[0115] Output Data Dispatcher: According to the instructions of the task processing module, it outputs the processed data and generates time-division multiplexing integration output rule instructions.

[0116] Data Input Buffer (i.e., Input Buffer Unit): It has the function of data caching to improve the system efficiency.

[0117] Data Output Buffer (i.e., Output Buffer Unit): It has the function of data caching to improve the system efficiency.

[0118] The time-division multiplexing input data distribution control unit can be built into the first processing core: According to the instructions and task modes of the upper-level module, it sends data to the lower-level data calculation units. And it adjusts the direction of data distribution in real time according to the execution status of the calculation units to ensure that as much data as possible is processed per unit time.

[0119] The data calculation unit performs Galois field multiplication and exclusive OR operations on the input matrix to achieve the simultaneous calculation of the solution data and PPL. In one example, there are two calculation engines in the data calculation unit, and each calculation engine can implement the mixed calculation of the solution data and PPL data. Therefore, when task 1 is executed by calculation engine 1, the other calculation engine is idle, and the calculation unit will automatically identify and allocate the new task to the data of the idle calculation engine, achieving the purpose of time-division multiplexing different calculation engines, thereby improving the execution efficiency of the entire system. The data calculation unit performs corresponding matrix calculations according to the upper-level configured data volume, matrix size, granularity, and task type, dynamically adjusts the execution process of different tasks during the calculation, saves the task execution time in the calculation unit by the time-division multiplexing method, and can implement the simultaneous encoding and decoding functions of any RAID algorithm task.

[0120] The output data integration unit can be built into the second processing core, reorder the generated data according to the distribution order, the number of checks, the number of decodings, the block size information, and the time-division multiplexing rule, and output it to the time-division multiplexing output data distribution unit in the second processing core in sequence.

[0121] The time-division multiplexing output data distribution unit distributes the data from the upper level to the data output buffer in order according to the size of the data, the number of check or recovery data, and notifies the host that the task is completed. It can be seen that this device dynamically schedules various hardware resources in itself, realizes three-dimensional hierarchical time-division multiplexing, and supports two-way simultaneous processing of encoding and decoding. This unit reorganizes some out-of-order calculation data according to the instructions of the upper-level module and the dynamic real-time execution situation, and distributes the data to the data output buffer according to the task type and the task execution order.

[0122] If a single data calculation unit includes 2 calculation engines and executes three tasks: the 4 (number of data blocks) + 2 (number of check blocks) encoding task, the 4 (number of data blocks) + 1 (number of check blocks) encoding task, and the 3 (number of data blocks) + 1 (number of check blocks) decoding task according to the time-division multiplexing principle, then the data calculation unit can complete these three tasks in 2 cycles. Please refer to Figure 3 , in cycle T1, the 2 calculation engines simultaneously process different data in the 4+2 encoding task; in cycle T2, calculation engine 1 processes the 4+1 encoding task, and calculation engine 2 processes the 3+1 decoding task. It can be seen that by adopting the multi-engine concurrent and multi-dimensional three-dimensional time-division multiplexing method, the resource utilization rate can be improved, and thus the data throughput rate can be improved.

[0123] In addition, in this embodiment, considering that the codec device is located far from the host, if the codec device directly sends the calculation result to the host, it will not only occupy the bus for a long time, but also the transmission delay for each interruption is relatively large, which will drag down the performance of the entire system. Therefore, the present invention proposes a form of circular and continuous command list. After the host side reads and parses the command, it directly initiates a read data transfer to the codec device through an independent path, reducing the number of interactions between the host and the codec device and improving the system performance.

[0124] Please refer to Figure 4 , the codec device can be externally connected or internally provided with a command processor (i.e., the second processing core) as Figure 4 shown. Figure 4 The command processor shown has the following functions: Whenever the calculation result is stored in the output buffer, a data transmission command is sent to request the buffer, so that the data and the data transfer command (i.e., the address access command) of the host are generated and cached for the host to read. The circular command table formed by the interaction commands is as Figure 5 shown. Each command corresponds to a section of address and a valid flag bit, where 0 indicates invalid and 1 indicates valid. After the module forms the command, it will notify the host that the command is ready. After receiving it, the host reads the command and maintains the read command in itself. After obtaining the relevant data through a command read, the command is set to invalid in itself. The host also maintains a circular command table. In theory, as long as the commands are continuous, the codec device only needs to notify the host once to achieve the transmission of all subsequent calculation results. Thus, the number of interactions with the host is reduced, and the performance of the entire system is improved.

[0125] As Figure 5 shown, during initialization, the current valid field of the newly generated data transfer command is filled with 1, and the low flag of the table is inverted. The address in the ring indication command is filled with the head address of the list to link the command table into a ring. It can be seen that the entire command table consists of multiple data transfer commands and a ring indication command. The ring indication command represents that the command has reached the end and the command needs to be read from the head of the table.

[0126] It can be seen that this embodiment proposes a multi-dimensional and three-dimensional parallel time-division multiplexing strategy from the level of RAID algorithm task scheduling and processing, which can flexibly configure the coding and decoding matrix particles, improve the data throughput rate and resource utilization rate, has easy expandability, high efficiency and good compatibility, and can meet different RAID algorithm tasks.

[0127] Next, a codec system provided by an embodiment of the present invention will be introduced. The codec system described below can be referred to each other with other embodiments described in this article.

[0128] Refer to Figure 6As shown in the figure, an embodiment of the present invention discloses an encoding and decoding system, including: a host and at least one encoding and decoding device described in any one of the foregoing embodiments.

[0129] In one implementation, there are multiple encoding and decoding devices; the host is communicatively connected to each encoding and decoding device.

[0130] In one implementation, the host communicates with each encoding and decoding device through Remote Direct Memory Access (RDMA) technology and / or Memory Direct Access (MDA) technology.

[0131] In one implementation, the host is connected to each encoding and decoding device through an expansion chip.

[0132] In this embodiment, the encoding and decoding device includes: a first processing core, a first cache connected to the first processing core, a plurality of RAID algorithm executors connected to the first cache, a second cache connected to each RAID algorithm executor, and a second processing core connected to the second cache.

[0133] Among them, the first processing core is used to: obtain a target task and the data to be processed of the target task; the target task is used to implement the encoding calculation or decoding calculation of at least one RAID algorithm.

[0134] Correspondingly, the first processing core is used to: divide the data to be processed according to the time-division multiplexing principle and the type of RAID algorithm implemented by the target task, and obtain a plurality of sub-data;

[0135] The first cache is used to: store a plurality of sub-data.

[0136] Each RAID algorithm executor is used to: read at least one sub-data matching the RAID algorithm engine in itself from the first cache, and perform encoding calculation or decoding calculation on the read sub-data by using the RAID algorithm engine.

[0137] The second cache is used to: store the calculation results output by each RAID algorithm executor.

[0138] The second processing core is used to: generate an address access command according to the calculation results stored in the second cache, and send a command generated message to the host to which the encoding and decoding device belongs, so that after the host obtains the address access command according to the command generated message, and reads the calculation results directly from the second cache according to the address access command; the address access command is used to access a segment of storage addresses in the second cache.

[0139] In one embodiment, the first processing core includes: a task parsing module configured to: parse a target task to obtain a parsing result; the parsing result includes: the type of RAID algorithm implemented by the target task, the number of encoding calculations for encoding calculation, the number of decoding calculations for decoding calculation, valid data bit information, parity bit information, address list pointer, and parameter list pointer associated with the data to be processed; a task processing module configured to: when it is determined that the parsing result is correct, partition the data to be processed.

[0140] In one embodiment, the task processing module includes: a time-division multiplexing control unit configured to: determine a time-division multiplexing allocation rule according to the parsing result and the operating conditions of each RAID algorithm executor; an address information reading unit configured to: read the storage address of the data to be processed in the host; a data parameter reading unit configured to: determine the row and column sizes of the data matrix to be read according to the time-division multiplexing allocation rule, and after reading the data from the storage address of the data to be processed in the host, write the read data into the first cache.

[0141] In one embodiment, the task processing module is further configured to: when it is determined that the parsing result is incorrect, discard the target task and send a task error message to the host to which the encoding and decoding device belongs.

[0142] In one embodiment, the first cache includes: a plurality of input cache units; correspondingly, each input cache unit is configured to: store at least one sub-data that matches the same RAID algorithm engine.

[0143] In one embodiment, each RAID algorithm executor includes: at least one RAID algorithm engine; correspondingly, any one of the RAID algorithm engines is configured to: perform encoding calculation or decoding calculation using RAID1 algorithm, RAID2 algorithm, RAID3 algorithm, RAID5 algorithm, RAID6 algorithm, or RAIDTP algorithm.

[0144] In one embodiment, each RAID algorithm executor is further configured to: distribute at least one sub-data read to different RAID algorithm engines in itself according to the time-division multiplexing principle, so that different RAID algorithm engines in the same RAID algorithm executor operate according to the time-division multiplexing principle.

[0145] In one embodiment, the second cache includes: a plurality of output cache units; correspondingly, each output cache unit is configured to: store the calculation result output by the same RAID algorithm executor.

[0146] In one embodiment, the second processing core includes: a command generation module configured to: generate an address access command based on the calculation result stored in the second cache; a trigger module configured to: send a command generated message to the host to which the codec device belongs, so that the host obtains the address access command according to the command generated message and directly reads the calculation result from the second cache according to the address access command.

[0147] In one embodiment, the command generation module is specifically configured to: when detecting that a new calculation result is written into the second cache, generate a corresponding address access command based on the storage address of the new calculation result in the second cache, and record the address access command in the circular command table.

[0148] In one embodiment, the trigger module is specifically configured to: when detecting an unprocessed address access command in the circular command table, send a command generated message to the host to which the codec device belongs.

[0149] In one embodiment, the trigger module is specifically configured to: detect the valid flag information corresponding to each address access command in the circular command table, and determine whether there is an unprocessed address access command in the circular command table according to the valid flag information.

[0150] In one embodiment, the second processing core is further configured to: perform row-column recombination on the calculation results output by different RAID algorithm executors in the second cache according to the target task to integrate the calculation results.

[0151] In one embodiment, each RAID algorithm executor includes: an enabling device; correspondingly, the enabling device is configured to: enable or disable the corresponding RAID algorithm executor.

[0152] In one embodiment, the first processing core is further configured to: send a ready message to the host to which the codec device belongs, so that the host sends a target task and data to be processed to the first processing core according to the ready message.

[0153] In one embodiment, the first processing core further includes: a configuration register; correspondingly, the configuration register is configured to: in response to an externally input configuration operation, configure the number of encodings for encoding calculation and the number of decodings for decoding calculation to adjust the type of RAID algorithm supported by the codec device.

[0154] Wherein, for the more specific working processes of each module and unit in this embodiment, reference may be made to the corresponding content disclosed in the foregoing embodiments, and details are not described herein again.

[0155] As can be seen, the present embodiment provides an encoding and decoding system, which can be applicable to various types of RAID algorithms, has high flexibility, wide application, can improve data throughput rate and hardware resource utilization rate, and improve the execution efficiency of RAID algorithms.

[0156] Furthermore, the embodiment of the present invention also provides an electronic device. Among them, the above-mentioned electronic device can be either the encoding and decoding device 1 as shown in Figure 7 or the encoding and decoding device 2 as shown in Figure 8 . Figure 7 And Figure 8 are both structural diagrams of electronic devices shown according to an exemplary embodiment, and the content in the figure cannot be regarded as any limitation on the scope of use of the present invention.

[0157] Figure 7 FIG. is a schematic structural diagram of an encoding and decoding device 1 provided by an embodiment of the present invention. The encoding and decoding device 1 may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. Among them, the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the relevant steps in the encoding and decoding disclosed in any of the foregoing embodiments.

[0158] In this embodiment, the power supply is used to provide working voltage for each hardware device on the encoding and decoding device 1; the communication interface can create a data transmission channel between the encoding and decoding device 1 and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of the present invention, and no specific limitation is imposed on it here; the input / output interface is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application needs, and no specific limitation is made here.

[0159] In addition, as a carrier for resource storage, the memory can be a read-only memory, a random access memory, a disk, or an optical disc, etc. The resources stored thereon include an operating system, a computer program, and data, etc., and the storage method can be temporary storage or permanent storage.

[0160] Among them, the operating system is used to manage and control each hardware device on the encoding and decoding device 1 and the computer program to implement the operation and processing of data in the memory by the processor, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the encoding and decoding method disclosed in any of the foregoing embodiments, the computer program can further include a computer program that can be used to complete other specific tasks. In addition to data such as update information of the application program, the data can also include data such as developer information of the application program.

[0161] Figure 8Schematic diagram of the structure of an encoding and decoding device 2 provided by an embodiment of the present invention. The encoding and decoding device 2 may specifically include, but is not limited to, a smart phone, a tablet computer, a laptop computer, a desktop computer, etc.

[0162] Generally, the encoding and decoding device 2 in this embodiment includes: a processor and a memory.

[0163] Among them, the processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may further include an AI (Artificial Intelligence) processor, and the AI processor is used to process computing operations related to machine learning.

[0164] The memory may include one or more computer-readable storage media, and the computer-readable storage media may be non-transitory. The memory may further include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory is at least used to store the following computer programs. After the computer programs are loaded and executed by the processor, the relevant steps in the encoding and decoding method executed by the encoding and decoding device 2 disclosed in any of the foregoing embodiments can be implemented. In addition, the resources stored in the memory may further include an operating system and data, etc., and the storage method may be transient storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, update information of the application program.

[0165] In some embodiments, the encoding and decoding device 2 may further include a display screen, an input / output interface, a communication interface, a sensor, a power supply, and a communication bus.

[0166] Those skilled in the art can understand, Figure 8The structure shown does not constitute a limitation on the encoding / decoding device 2, and may include more or fewer components than those shown in the figure.

[0167] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference may be made to each other.

[0168] The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be implemented directly in hardware, software modules executed by a processing core, or a combination of both. The software modules may be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of readable storage medium known in the art.

[0169] Specific examples are used herein to illustrate the principles and implementation manners of the present invention. The description of the above embodiments is only for helping to understand the method of the present invention and its core idea. At the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation on the present invention.

Claims

1. A coding and decoding device, characterized in that: include: a first processing core, a first cache connected to the first processing core, a plurality of RAID algorithm executors connected to the first cache, a second cache connected to each of the RAID algorithm executors, and a second processing core connected to the second cache; Wherein, the first processing core is used to: obtain a target task and data to be processed of the target task; the target task is used to implement encoding calculation or decoding calculation of at least one RAID algorithm; Accordingly, the first processing core is used to: divide the data to be processed according to the time division multiplexing principle and the type of the RAID algorithm implemented by the target task to obtain a plurality of sub-data; The first cache is used to: store the plurality of sub-data; Each RAID algorithm executor is used to: read at least one sub-data matching the RAID algorithm engine in itself from the first cache, and use the RAID algorithm engine to perform encoding calculation or decoding calculation on the read sub-data; The second cache is used to: store the calculation results output by each RAID algorithm executor; The second processing core is used to: generate an address access command according to the calculation result stored in the second cache, and send a command generated message to the host to which the codec device belongs, so that the host obtains the address access command according to the command generated message, and directly reads the calculation result from the second cache according to the address access command; the address access command is used to access a storage address in the second cache.

2. The encoding and decoding device according to claim 1, characterized in that: The first processing core comprises: The task parsing module is used to: parse the target task to obtain a parsing result; the parsing result includes: the type of RAID algorithm implemented by the target task, the number of encodings calculated by encoding, the number of decodings calculated by decoding, the valid data bit information, check bit information, address list pointer and parameter list pointer associated with the data to be processed; The task processing module is used to: when it is determined that the analysis result is correct, divide the data to be processed.

3. The encoding and decoding device according to claim 2, characterized in that: The task processing module includes: The time-division multiplexing control unit is used to: determine the time-division multiplexing allocation rule according to the analysis result and the operation status of each RAID algorithm executor; The address information reading unit is used to: read the storage address of the data to be processed in the host; The data parameter reading unit is used to determine the row and column size of the read data matrix according to the time division multiplexing allocation rule, and after reading the data to be processed from the storage address of the host, write the read data into the first cache.

4. The encoding and decoding device according to claim 2, characterized in that: The task processing module is further used to: when determining that the parsing result is wrong, discard the target task and send a task error message to the host to which the encoding and decoding device belongs.

5. The encoding and decoding device according to claim 1, characterized in that: The first cache comprises: a plurality of input cache units; Correspondingly, each input buffer unit is used to store at least one sub-data matching the same RAID algorithm engine.

6. The encoding and decoding device according to claim 1, characterized in that: Each RAID algorithm executor includes: at least one RAID algorithm engine; Accordingly, any RAID algorithm engine is used to perform encoding calculation or decoding calculation using the RAID1 algorithm, the RAID2 algorithm, the RAID3 algorithm, the RAID5 algorithm, the RAID6 algorithm or the RAIDTP algorithm.

7. The coding and decoding device according to claim 6, characterized in that: Each RAID algorithm executor is also used to distribute the read at least one sub-data to different RAID algorithm engines in itself according to the time division multiplexing principle, so that different RAID algorithm engines in the same RAID algorithm executor operate according to the time division multiplexing principle.

8. The encoding and decoding device according to claim 1, characterized in that: The second cache includes: a plurality of output cache units; Correspondingly, each output cache unit is used to store the calculation results output by the same RAID algorithm executor.

9. The encoding and decoding device according to claim 1, characterized in that: The second processing core comprises: The command generation module is used to: generate an address access command according to the calculation result stored in the second cache; The trigger module is used to send a command generated message to the host to which the codec device belongs, so that the host obtains the address access command according to the command generated message and directly reads the calculation result from the second cache according to the address access command.

10. The coding and decoding device according to claim 9, characterized in that: The command generation module is specifically used to: when detecting that a new calculation result is written into the second cache, generate a corresponding address access command based on the storage address of the new calculation result in the second cache, and record the address access command in the ring command table.

11. The coding and decoding device according to claim 10, characterized in that: The trigger module is specifically configured to send a command generation message to a host to which the codec device belongs when detecting that there is an unprocessed address access command in the ring command table.

12. The coding and decoding device according to claim 11, characterized in that: The trigger module is specifically used to detect valid flag information corresponding to each address access command in the ring command table, and determine whether there is an unprocessed address access command in the ring command table according to the valid flag information.

13. The coding and decoding device according to any one of claims 1 to 12, characterized in that: The second processing core is further used for: reorganizing the calculation results output by different RAID algorithm executors in the second cache in rows and columns according to the target task, so as to integrate the calculation results.

14. The coding and decoding device according to any one of claims 1 to 12, characterized in that: Each RAID algorithm executor includes: an enabling device; Correspondingly, the enabling device is used to enable or disable the corresponding RAID algorithm executor.

15. The coding and decoding device according to any one of claims 1 to 12, characterized in that: The first processing core is further used to send a ready message to a host to which the codec device belongs, so that the host sends the target task and the data to be processed to the first processing core according to the ready message.

16. The coding and decoding device according to any one of claims 1 to 12, characterized in that: The first processing core also includes: configuration registers; Accordingly, the configuration register is used to configure the number of encodings of the encoding calculation and the number of decodings of the decoding calculation in response to an externally input configuration operation, so as to adjust the type of RAID algorithm supported by the encoding and decoding device.

17. A coding and decoding system, characterized in that: include: A host and a coding and decoding device as claimed in any one of claims 1 to 16.

18. The coding and decoding system according to claim 17, characterized in that: There are multiple codec devices; the host is communicatively connected with each codec device.

19. The coding and decoding system according to claim 18, characterized in that: The host communicates with each codec device via remote direct data access technology and / or memory direct access technology.

20. The coding and decoding system according to claim 18, characterized in that: The host is connected to each codec device via an expansion chip.

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