A device and method for detecting local partial discharge on the surface of a distribution network cable terminal

Abstract

The present application provides a device and method for detecting local partial discharge on the surface of a distribution network cable terminal, belonging to the technical field of local partial discharge detection; it solves the problem of mis-extraction of local partial discharge information caused by signal fluctuations due to various interferences existing in the on-site application of existing detection devices; the device includes a power supply module, a frequency division and filtering module, an analog-to-digital conversion module, and a CPU module; the frequency division and filtering module collects the original local partial discharge signals on the cable surface, separates the effective local partial discharge signals and phase signals in the original local partial discharge signals, and transmits the above-mentioned effective local partial discharge signals and phase signals to the CPU module after being converted into digital signals through the analog-to-digital conversion module. The CPU module is used for circularly collecting and signal processing of the digital signals, where the signal processing includes zero-phase detection of the trigger signal, peak seeking of the discharge amount in the phase window, and phase counting; the present application is applied to cable local partial discharge detection.

Description

Technical Field

[0001] This application relates to the technical field of partial discharge detection, and particularly relates to a device and method for detecting surface partial discharge of a cable terminal in a distribution network. Background Art

[0002] High-voltage switchgears are widely used in China's distribution network of 35 kV and below, and they are important bridge links in the power system's power transmission and distribution nodes. The internal structure of the switchgear is complex, and the components in different switchgears vary greatly, resulting in condensation and pollution in the switchgear, which can cause insulation surface discharge. In particular, the insulation surface discharge at the cable terminal will cause insulation corrosion. As the corrosion degree increases, carbonized grooves and compositional changes will appear on the insulation surface, the surface conductivity will gradually increase, and the surface hydrophobicity will weaken, ultimately leading to the failure of the cable insulation in the switchgear.

[0003] Therefore, how to detect the surface partial discharge of the cable insulation in the high-voltage switchgear has attracted wide attention. However, the existing devices for detecting the surface partial discharge of the cable insulation used in the switchgear still have certain limitations. This is mainly reflected in that when collecting partial discharge signals on-site, various interferences and noises will cause fluctuations in the partial discharge signals, which easily leads to inaccurate extraction of partial discharge phase information. If the phase information of the partial discharge cannot be accurately obtained, errors will occur when drawing the partial discharge phase angle resolution diagram, and the obtained graph cannot truly reflect the discharge type, resulting in difficulties in subsequent identification of the partial discharge type, or even the inability to distinguish the partial discharge type.

[0004] In the research results of partial discharge detection on the surface of cable insulation in a switchgear cabinet related to this application, patents such as "CN119375642A - A Method and System for On - line Monitoring of Partial Discharge in High - Voltage Switchgear Cabinets" introduce how to achieve early warning of partial discharge in the target part of high - voltage switchgear cabinets; the patent "CN119375641A - Partial Discharge and Location Device Based on the Phase - Checking Hole of Switchgear Cabinets" introduces a method of measuring partial discharge through the phase - checking hole of switchgear cabinets and realizing cable defect location using the PRPD spectrogram; the patent "CN119471261A - A Method, System and Medium for Detecting Partial Discharge in High - Voltage Cables" introduces a partial discharge detection system for high - voltage cables, which includes a detection and acquisition module and a diagnosis module; the partial discharge monitoring device designed in the patent "CN119125807A - An Intelligent On - line Monitoring System and Device for Partial Discharge in Switchgear Cabinets" includes a data temporary storage module, a data analysis module, a data real - time monitoring module, etc. To sum up, these existing patents tend to focus on the reuse of partial discharge data and the overall design of partial discharge detection devices or systems, and do not provide methods for specifically designing partial discharge zero - phase detection, discharge quantity peak seeking, and phase counting based on the developed device hardware. They cannot avoid the problem of mis - extraction of partial discharge information caused by signal fluctuations due to various interferences during on - site application, and cannot meet the requirements of partial discharge detection in switchgear cabinets on site. Summary of the Invention

[0005] To solve the above - mentioned technical problems, this application proposes a device and method for detecting partial discharge on the surface of a distribution network cable terminal.

[0006] The technical solution adopted in this application is as follows: A device for detecting partial discharge on the surface of a distribution network cable terminal includes a power supply module, a frequency - division filtering module, an analog - to - digital conversion module, and a CPU module. The input ports of the frequency - division filtering module are respectively connected to the partial discharge sensors sleeved on each phase of the cable to be measured in the switchgear cabinet. The phase output port of the frequency - division filtering module is connected to the low - speed port of the analog - to - digital conversion module, and the partial discharge output port of the frequency - division filtering module is connected to the high - speed port of the analog - to - digital conversion module; the parallel digital output port of the analog - to - digital conversion module is connected to the CPU module;

[0007] The frequency division filtering module collects the original partial discharge signals on the surface of the cable under test, separates the effective partial discharge signals and phase signals in the original partial discharge signals, converts the above-mentioned effective partial discharge signals and phase signals into digital signals through the analog-to-digital conversion module, and then transmits them to the CPU module. The CPU module is used for cyclic acquisition and signal processing of the digital signals, where the signal processing includes trigger signal zero-phase detection, discharge quantity peak search in the phase window, and phase counting. The trigger signal zero-phase detection completes the detection of the rising edge of the zero crossing point of the phase signal. After detecting the rising edge of the zero crossing point, the discharge quantity peak search in the phase window and phase counting are executed, and finally the phase-discharge quantity data starting from the zero point of the rising edge of the phase signal is output.

[0008] Further, the frequency division filtering module consists of three identical signal processing circuits, namely signal processing circuit A, signal processing circuit B, and signal processing circuit C. The input ports of signal processing circuit A, signal processing circuit B, and signal processing circuit C are respectively connected to the partial discharge sensors sleeved on the A-phase, B-phase, and C-phase of the cable under test. The input port of each signal processing circuit includes two branch circuits. One branch circuit uses two operational amplifiers and their connected capacitors and resistors to collect the phase signal, and this phase signal is used to provide a synchronous clock. The other branch circuit uses four operational amplifiers and their connected capacitors and resistors to collect the partial discharge pulse signal and record the occurrence of discharge events.

[0009] Further, the analog-to-digital conversion module consists of a low-speed analog-to-digital conversion unit and three high-speed analog-to-digital conversion units. The three input ports of the low-speed analog-to-digital conversion unit are respectively connected to the phase signal output terminals of signal processing circuit A, signal processing circuit B, and signal processing circuit C, and the three high-speed analog-to-digital conversion units are respectively connected to the partial discharge signal output terminals of signal processing circuit A, signal processing circuit B, and signal processing circuit C.

[0010] Further, it also includes a communication module, and the CPU module communicates bidirectionally with the communication module.

[0011] Further, it also includes a display module. The display module is connected to the CPU module. The CPU module is built-in with software for plotting the phase-discharge quantity data into a PRPD spectrogram corresponding to partial discharge, and the display module visually displays the plotted PRPD spectrogram.

[0012] Further, the CPU module is built-in with a data storage module, and the data storage module consists of two FIFO read-write control modules and an SDRAM storage area.

[0013] A method for detecting partial discharge on the surface of a distribution network cable terminal includes the following steps:

[0014] S1: First, the operator connects the partial discharge detection device on the surface of the distribution network cable terminal to the incoming cable in the switchgear according to the pulse current method, and then starts the discharge detection.

[0015] S2: The original partial discharge signals generated in the detection circuit are first input into the detection device through the frequency division and filtering module. After filtering and voltage conditioning, the partial discharge data originally coupled to the power frequency sine voltage is output to the analog-to-digital conversion module through two channels. One channel is the power frequency trigger voltage phase reference signal, which is used to provide a synchronous clock; the other channel is the partial discharge pulse signal, which is used to record the occurrence of discharge events. Then, the two signals are converted into binary digital quantities in the analog-to-digital conversion module and input into the CPU module. The trigger signal zero-phase detection, phase window discharge quantity peak seeking, and phase counting programs in the CPU module process and calculate the partial discharge data to obtain the partial discharge data with phase information and the peak value of the single-phase window discharge quantity, that is, the phase-discharge quantity data.

[0016] S3: After being processed by the software in the CPU module, the collected phase-discharge quantity data is finally visually displayed on the display module in the form of a PRPD spectrogram and presented to the operator.

[0017] Further, the process of trigger signal zero-phase detection is as follows: First, clear the phase signal rising edge flag flag_start to 0 for initialization, and adjust the phase signal data range after analog-to-digital conversion to -512 to 511. Name the adjusted phase signal data as ad0_data. Then, sample ad0_data for two beats along the rising edge of the clock signal. The first beat is named zero_st1, and the second beat is named zero_st2, that is, zero_st1 lags behind zero_st2 by one clock cycle. Next, judge whether the result of the exclusive NOR operation of the highest bits of zero_st1 and zero_st2 data is 1. If it is 1, then proceed to the next step; if it is not 1, clear the phase signal rising edge flag flag_start to 0 and end the process. Subsequently, after a time delay of 5 clock cycles, judge whether the result of the logical AND operation of the highest bit of zero_st1 being 0 and the highest bit of zero_st2 being 1 is 1. If the result is 1, it means that the process of the phase signal digital quantity changing from negative to positive, that is, the phase zero point, is detected. Immediately set the phase signal rising edge flag flag_start to 1 and end; otherwise, clear the phase signal rising edge flag flag_start to 0 and end the process.

[0018] Further, the process of finding the peak discharge quantity in the phase window is as follows: First, determine whether the phase signal is the zero point of the rising edge. After detecting the zero point of the rising edge, initialize the maximum discharge quantity in the phase window, the sampling point ordinal number, and the phase window ordinal number to 0. Then, determine whether the current discharge quantity is greater than the maximum discharge quantity in the phase window. If it is greater, assign the current discharge quantity to the maximum discharge quantity in the phase window and increment the sampling point ordinal number by 1; otherwise, directly increment the sampling point ordinal number by 1. Next, loop the above comparison process until all sampling points in the current phase window are traversed. When a phase window is looped and compared, save the maximum discharge quantity in the phase window and increment the phase window ordinal number by 1.

[0019] Further, the process of phase counting is as follows: First, determine whether the rising edge zero point of the phase signal is reached. If it is reached, initialize the phase window number, the phase span of a single phase window, the current phase, and the current phase window ordinal number. If the phase signal does not reach the rising edge zero point, continue to detect until the rising edge zero point arrives. Then, wait for the peak finding of the discharge quantity to traverse each partial discharge sampling point in the phase window. After traversing, update the current phase window ordinal number and the current phase. Then, repeat the above process for the next phase window until the phase calculation is completed for all phase windows within the entire trigger period.

[0020] The beneficial effects of this application compared with the prior art are as follows: This application adopts a high-sampling-rate hardware design and a refined processing method for partial discharge data, and can accurately capture and analyze the partial discharge signals occurring on the surface of the cable insulation inside the switchgear. By real-time monitoring of the partial discharge situation, abnormal conditions on the surface of the cable insulation can be discovered in a timely manner, and corresponding maintenance measures can be taken to ensure the safe operation of the cable. Compared with traditional partial discharge detection methods, this application has a higher sampling rate and detection accuracy, and can effectively improve the cable insulation performance and service life of the switchgear. Description of the Drawings

[0021] The following further describes this application with reference to the drawings:

[0022] Figure 1 It is the overall block diagram of the partial discharge detection device provided by the embodiment of this application;

[0023] Figure 2 It is the circuit schematic diagram of the frequency division filtering module provided by the embodiment of this application;

[0024] Figure 3 It is the circuit schematic diagram of the AD conversion module provided by the embodiment of this application;

[0025] Figure 4 It is the flow chart of the zero-phase detection program of the trigger signal provided by the embodiment of this application;

[0026] Figure 5 It is the flow chart of finding the peak of the discharge quantity in the phase window provided by the embodiment of this application;

[0027] Figure 6 It is the flowchart of phase counting provided by the embodiment of the present application;

[0028] Figure 7 It is the PRPD spectrogram of surface discharge detected by this device provided by the embodiment of the present application. Detailed implementation manners

[0029] As Figures 1 to 7 shown, the present application provides a device for detecting partial discharge on the surface of a distribution network cable terminal, which can accurately detect partial discharge on the insulation surface of the cable in the switch cabinet. It includes a power supply module, a frequency division and filtering module, an analog-to-digital conversion module, a CPU module, a communication module, and a display module. The input ports of the frequency division and filtering module are respectively connected to the partial discharge sensors sleeved on each phase of the cable under test in the switch cabinet. The phase output port of the frequency division and filtering module is connected to the low-speed port of the analog-to-digital conversion module, and the partial discharge output port of the frequency division and filtering module is connected to the high-speed port of the analog-to-digital conversion module. The parallel digital output port of the analog-to-digital conversion module is connected to the SPI port and GPIO port of the CPU module. The display module is connected to the I 2 C port of the CPU module; the communication module is connected to the Ethernet interface of the CPU module, which can realize the communication between the CPU module and the upper computer. The power supply module is used to supply power to the frequency division and filtering module, the analog-to-digital conversion module, the CPU module, the communication module, and the display module.

[0030] Among them, the CPU module can use FPGA. In this embodiment, the CPU module uses a minimum system with XC7Z020-2CLG400C as the processor, which is used to read, analyze, and store partial discharge signals. It has a built-in data storage module, which can be used to store partial discharge signals.

[0031] Among them, the frequency division and filtering module is used to collect the original partial discharge signals on the cable surface and separate the effective partial discharge signals and phase signals in the original partial discharge signals. As Figure 2 shown, the frequency division and filtering module consists of three identical signal processing circuits, namely signal processing circuit A, signal processing circuit B, and signal processing circuit C. The input ports of signal processing circuit A, signal processing circuit B, and signal processing circuit C U PDA , U PDB , U PDC are respectively connected to the partial discharge sensors sleeved on phase A, phase B, and phase C of the cable under test. In this embodiment, signal processing circuit A is taken as an example for illustration. One end of the input capacitor C 0 of signal processing circuit A is used as the input port of signal processing circuit A U PDA, the input capacitance C The other end of 0 is connected to the resistor R 0, R 1, R One end of 5. The resistor R The other end of 0 is connected to the ground terminal of the power supply module. The resistor R The other end of 1 is connected to the capacitor C One end of 1, the resistor R One end of 2. The capacitor C The other end of 1 is connected to the inverting input terminal, output terminal of the operational amplifier U 1 and the resistor R One end of 3. The resistor R The other end of 2 is connected to the operational amplifier U The non-inverting input terminal of 1 and the capacitor C One end of 2. The capacitor C The other end of 2 is connected to the ground terminal of the power supply module. The resistor R The other end of 3 is connected to the capacitor C One end of 3, the resistor R One end of 4. The capacitor C The other end of 3 is connected to the operational amplifier U The inverting input terminal and output terminal of 2, and serves as the phase signal output terminal of the frequency division and filtering module U φAo , output the phase signal of the original partial discharge signal of phase A. The resistor R The other end of 4 is connected to the operational amplifier U The non-inverting input terminal of 2 and the capacitor C One end of 4. The capacitor C The other end of 4 is connected to the ground terminal of the power supply module. The resistor R The other end of 5 is connected to the capacitor C One end of 5, the resistor R One end of 6. The capacitor C The other end of 5 is connected to the operational amplifier U The inverting input terminal, output terminal of 3 and the resistor R One end of 7. The resistor R The other end of 6 is connected to the operational amplifier U The non-inverting input terminal of 3 and the capacitor C One end of 6. The capacitor C The other end of 6 is connected to the ground terminal of the power supply module. The resistor R The other end of 7 is connected to the capacitor C One end of 7, the resistor R One end of 8. The capacitor C The other end of 7 is connected to the operational amplifier U The inverting input terminal, output terminal of 4 and the capacitor COne end of 9 is connected. Resistor R The other end of 8 is connected to the operational amplifier U The non-inverting input terminal of 4 and capacitor C One end of 8 are connected. Capacitor C The other end of 8 is connected to the ground terminal of the power supply module. Capacitor C The other end of 9 is connected to resistor R 12 One end, capacitor C 10 One end are connected. Resistor R 12 The other end is connected to the operational amplifier U The output terminal of 5, resistor R 11 One end and capacitor C 11 One end are connected. Resistor R 11 The other end is connected to the operational amplifier U The inverting input terminal of 5, resistor R One end of 9 are connected. Resistor R The other end of 9 is connected to the ground terminal of the power supply module. Capacitor C 10 The other end is connected to the operational amplifier U The non-inverting input terminal of 5 and resistor R 10 One end are connected. Resistor R 10 The other end is connected to the ground terminal of the power supply module. Capacitor C 11 The other end is connected to resistor R 13 One end, capacitor C 12 One end, capacitor C 13 One end are connected. Resistor R 13 The other end is connected to the operational amplifier U The inverting input terminal and the output terminal of 6, and is used as the partial discharge signal output terminal of the frequency division and filtering module U PDAo . Capacitor C 12 The other end is connected to the operational amplifier U The non-inverting input terminal of 5 and resistor R 14 One end are connected. Resistor R 14 The other end, capacitor C 13 The other end is connected to the ground terminal of the power supply module.

[0032] In this embodiment, the operational amplifier U 1、 U 2、 U 3、 U 4、 U 5、 U 6 are all TLV9361. The output terminals of the signal processing circuit B and the signal processing circuit C of the frequency division and filtering module are respectively: the partial discharge signal output terminal U PDBo and U PDCo , and the phase signal output terminal U φBo and U φCo .

[0033] The analog-to-digital conversion module is used to convert analog signals into digital signals, that is, to convert the partial discharge signal and the phase signal of the frequency division and filtering module into digital signals. As Figure 3 shown, the analog-to-digital conversion module consists of a low-speed analog-to-digital conversion unit U 7 and three high-speed conversion units U 9、 U 11 、 U 13 . In this embodiment, the low-speed analog-to-digital conversion unit uses AD7606-4, and the high-speed conversion unit uses 3PA1030. U φAo 、 U φBo and U φCo are respectively connected to the input ports U 7 of the low-speed analog-to-digital conversion unit V 1、 V 2 and V 3. The SPI port of the low-speed analog-to-digital conversion unit U 7 outputs the digital quantities of the A, B, and C phase signals D φo . U PDAo is connected to one end of the capacitor C 14 and the resistor R 15 , and the non-inverting input terminal of the operational amplifier U 8. The other end of the capacitor C 14 is connected to one end of the capacitor C 15 , the other end of the resistor R 15 , and one end of the resistor R 16 . The capacitorC 15 The other end of and the resistor R 16 The other ends of are all connected to the ground terminal of the power supply module. The operational amplifier U The inverting input terminal of 8 is connected to the resistor R 17 One end of, and the resistor R 17 The other end of is connected to the output terminal of the operational amplifier U 8 and is connected to the input port AIN of the high-speed conversion unit U 9. The high-speed conversion unit U The output port of 9 D 1~9 Outputs the digital quantity of the partial discharge signal of phase A D PDAo . U PDBo Is connected to the capacitor C 16 One end of, the resistor R 18 One end of, and the in-phase input terminal of the operational amplifier U 10 Is connected. The capacitor C 16 The other end of is connected to the capacitor C 17 One end of, the resistor R 18 One end of, the capacitor R 19 One end of is connected. The capacitor C 17 The other end of and the resistor R 19 The other ends of are all connected to the ground terminal of the power supply module. The operational amplifier U 10 The inverting input terminal of is connected to the resistor R 20 One end of, and the resistor R 20 The other end of is connected to the output terminal of the operational amplifier U 10 And is connected to the input port AIN of the high-speed conversion unit U 11 9. The high-speed conversion unit U 11 The output port D 1~9 Outputs the digital quantity of the partial discharge signal of phase B D PDBo . U PDCo Is connected to the capacitor C18 One end of, resistor R 21 One end of, and operational amplifier U 12 The non-inverting input terminal of is connected. Capacitor C 18 The other end of is connected to capacitor C 19 One end of, resistor R 21 One end of, resistor R 22 One end of, resistor C 19 The other end of and resistor R 22 The other ends of are all connected to the ground terminal of the power supply module. Operational amplifier U 12 The inverting input terminal of is connected to resistor R 23 One end of, resistor R 23 The other end of is connected to the output terminal of operational amplifier U 12 And is connected to the input port AIN of the high-speed conversion unit U 13 The high-speed conversion unit U 13 The output port of D 1~9 Outputs the digital quantity of the C-phase partial discharge signal D PDCo . D φo Is connected to the SPI port of the CPU module, D PDAo , D PDBo , D PDCo Is connected to the GPIO port of the CPU module.

[0034] The logic operation unit in the CPU module is used to complete digital signals D φo , D PDAo , D PDBo , D PDCoOperations and processing include two parts: signal acquisition and signal processing. The function of signal acquisition is to cyclically acquire the phases and partial discharge signals of three phases A, B, and C. Signal processing includes zero-phase detection of the trigger signal, peak seeking of the discharge quantity in the phase window, and phase counting. Zero-phase detection of the trigger signal is used to complete the detection of the rising edge of the zero crossing of the phase signal. After detecting the rising edge of the zero crossing, peak seeking of the discharge quantity in the phase window and phase counting are executed. The existence of the phase counting program is to provide a reference phase for the above-mentioned peak seeking process of the discharge quantity in the phase window, ensuring that there is a corresponding phase point for each piece of discharge data refined by peak seeking of the discharge quantity in the phase window, so as to draw the PRPD spectrogram of the insulation surface discharge in the subsequent host computer. The specific design processes of the above-mentioned parts of the program are as follows respectively.

[0035] As Figure 4 shown is the flowchart of the zero-phase detection program of the trigger signal provided by the embodiment of the present application. In this process, first, the rising edge flag flag_start of the phase signal is cleared to 0 for initialization, and the 10-bit phase signal data interval after analog-to-digital conversion is adjusted from the original 0-1023 to -512-511. The adjusted phase signal data is named ad0_data. Then, ad0_data is sampled twice along the rising edge of the clock signal. The first sample is named zero_st1, and the second sample is named zero_st2, which means that zero_st1 lags behind zero_st2 by one clock cycle. Next, it is judged whether the result of the exclusive NOR operation of the highest bits of zero_st1 and zero_st2 data (0 indicates negative data, 1 indicates positive data) is 1. If it is 1, then proceed to the next step; if it is not 1, the rising edge flag flag_start of the phase signal is cleared to 0 and the process ends. The purpose of this step is to judge whether the phase signals at two adjacent moments before detecting the rising edge zero point are in the same positive or negative half cycle. Subsequently, after a delay of 5 clock cycles, it is judged whether the result of the logical AND operation of "the highest bit of zero_st1 is 0" and "the highest bit of zero_st2 is 1" is 1. If the result is 1, it means that the process of the digital quantity of the phase signal changing from negative to positive, that is, the phase zero point, is detected. Immediately, the rising edge flag flag_start of the phase signal is set to 1 and the process ends. Otherwise, the rising edge flag flag_start of the phase signal is cleared to 0 and the process ends. In this process, the phase signal undergoes two judgments with an interval of 5 clock cycles in the middle, which can avoid misjudgment caused by signal fluctuations to a certain extent and increase the error tolerance rate of the program.

[0036] As Figure 5 shown is the flowchart of peak seeking of the discharge quantity in the phase window provided by the embodiment of the present application. In this process, first, it is judged whether the phase signal is the rising edge zero point. After detecting the rising edge zero point, for the maximum discharge quantity PD imax in the phase window and the sampling point ordinal numberβ i and the phase window sequence number i are both initialized to 0. Then, it is judged whether the current discharge amount PD in_data is greater than the maximum discharge amount PD imax of this phase window. If it is greater, the current discharge amount PD in_data is assigned to the maximum discharge amount PD imax of this phase window, and the sampling point sequence number β i is incremented by 1; otherwise, the sampling point sequence number β i is directly incremented by 1. Then, the above comparison process is looped 2000 times until all sampling points of the current phase window are traversed. After a phase window is looped and compared, the maximum discharge amount PD imax of this phase window is saved, and the phase window sequence number i is incremented by 1. In this embodiment, the sampling rate of the analog-to-digital conversion module is set to 50 Msps, and each sampling channel generates 50 million partial discharge data per second. Therefore, the above process will be executed 500 times within a trigger period to ensure that all phase windows within the trigger period participate in the peak seeking of the discharge amount. The trigger period is related to the frequency. Currently, the AC power grid frequency in China is 50 Hz, and a period is fixed at 20 milliseconds. Therefore, the entire trigger period in this embodiment can be 20 ms. If it is other frequencies, the trigger period can be modified accordingly according to the specific frequency.

[0037] As Figure 6 shown is the phase counting flow chart provided by the embodiment of the present application. In this process, it is first judged whether the rising edge zero point of the phase signal is reached. If it is reached, the phase window number n , the single-phase window phase span a , the current phase p ( i ), and the current phase window sequence number i are initialized; if the phase signal does not reach the rising edge zero point, the detection continues until the rising edge zero point arrives. The number of phase windows for phase counting should be consistent with that for peak seeking of the discharge amount. Therefore, the phase window number n is uniformly set to 500. Then, wait for the peak seeking of the discharge amount to traverse each partial discharge sampling point in the phase window. After traversing, the current phase window sequence number i and the current phase p ( i ) are updated, and the update of the phase p ( i ) is calculated according to formula (1). Then, the above process is repeated for the next phase window until the phase calculation for all phase windows within the entire trigger period is completed.

[0038] (1).

[0039] After being processed through the above processes of zero-phase detection of the trigger signal, peak-seeking of the discharge quantity in the phase-splitting window, and phase counting, when the partial discharge digital signal outputs from the CPU module, it has been transformed into phase-discharge quantity data starting from zero at the rising edge of the phase signal. Therefore, by simply transmitting this data back to the host computer, the PRPD spectrogram corresponding to the partial discharge can be obtained, and then the discharge phenomenon can be analyzed.

[0040] The data storage module is used to save some phase-discharge quantity data and can calculate certain partial discharge parameters in the offline state, such as calculating the average discharge quantity per minute, discharge frequency, etc. This module consists of two FIFO read-write control modules and a 256Mbit SDRAM storage area. The two FIFO read-write control modules cooperate with each other, with one writing while the other reads, enabling uninterrupted data storage; the 256Mbit SDRAM storage area can store approximately 671s of partial discharge data in the phase-splitting window under the condition that the sampling rate of the analog-to-digital conversion module is 50Msps.

[0041] The communication module is used to transmit the phase-discharge quantity data to the host computer or server connected externally to the device. This module communicates based on the UDP protocol, with a maximum transmission rate of 10Mbps, and the maximum transmission capacity of a single packet of data can reach 1472Byte. When communicating, the communication module must cooperate with the physical interface transceiver PHY chip to complete the data transmission and reception. The PHY chip is responsible for establishing a signal transmission channel and converting the serial analog signal into a physical-layer signal for output through the RJ45 network interface; the communication module is responsible for packing the partial discharge data to make the transmitted data conform to the UDP protocol and thus complete the batch transmission of data.

[0042] The display module is used to receive the phase-discharge quantity data collected by this device and realizes the visual display and analysis of the partial discharge event by drawing the PRPD spectrogram corresponding to the partial discharge and the trigger sine signal in the software of the CPU module. As Figure 7 shown is the surface discharge PRPD spectrogram drawn in the display module after being collected by this device. Analyzing the above figure, the drawn PRPD spectrogram conforms to the characteristics of typical surface discharge and has a good drawing effect, which can be used for the analysis of the insulation state and discharge degree of the switch cabinet. Therefore, it is considered that the discharge detection function of this device is normal and the display effect is good.

[0043] The embodiment of this application also proposes a method for detecting partial discharge on the surface of a distribution network cable terminal. Using the above device, it mainly includes the following steps:

[0044] S1: The operator first connects this device to the incoming cable in the switch cabinet according to the partial discharge detection circuit of the pulse current method, and then starts the partial discharge detection.

[0045] S2: The original partial discharge signals generated in the detection circuit are first input into this detection device through the frequency division and filtering module. After filtering and voltage conditioning, the partial discharge data originally coupled to the power frequency sine voltage is output to the analog-to-digital conversion module through two channels. One of them is the power frequency trigger voltage phase reference signal, which is used to provide a synchronous clock to ensure the accuracy of data acquisition; the other is the partial discharge pulse signal, which is used to record the occurrence of discharge events. Then, the two signals are converted into 10-bit binary digital quantities in the analog-to-digital conversion module and input into the CPU module. Programs such as zero-phase detection of the trigger signal, peak seeking of the discharge quantity in the phase window, and phase counting in the CPU module process and calculate the partial discharge data to obtain the partial discharge data with phase information and the peak value of the single-phase window discharge quantity, that is, the phase-discharge quantity data, and then output it to the FIFO read-write control module in the data storage module. Under the read and write of the FIFO read-write control module, the phase-discharge quantity data is respectively written into the actual data storage area, that is, the SDRAM storage area and the communication module.

[0046] S3: After being processed by the software in the CPU module, the collected phase-discharge quantity data is finally visually displayed on the display module in the form of a PRPD spectrogram and presented to the operator. The operator can analyze and judge the characteristics of the discharge spectrogram, and then timely evaluate the operating status of the switchgear equipment or issue a device failure warning. The communication module can also send the phase-discharge quantity data to the external host computer or server of the device according to the UDP protocol for further processing.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for detecting partial discharge on the surface of a distribution network cable terminal, characterized in that: It includes the following steps: S1: The operator first connects the partial discharge detection device on the surface of the distribution network cable terminal to the incoming cable in the switch cabinet according to the pulse current method, and then starts the discharge detection; S2: The original partial discharge signals generated in the detection circuit are first input into the detection device through the frequency division filter module. After filtering and voltage conditioning, the partial discharge data originally coupled to the power frequency sinusoidal voltage is output to the analog-to-digital conversion module through two channels. One is the power frequency trigger voltage phase reference signal, which is used to provide a synchronous clock; the other is the partial discharge pulse signal, which is used to record the occurrence of discharge events. Then, the two signals are converted into binary digital quantities in the analog-to-digital conversion module and input into the CPU module. The trigger signal zero-phase detection, phase window discharge quantity peak seeking, and phase counting programs in the CPU module process and calculate the partial discharge data to obtain the partial discharge data with phase information and the peak value of the single-phase window discharge quantity, that is, the phase-discharge quantity data; S3: After being processed by the software in the CPU module, the collected phase-discharge quantity data is finally visually displayed on the display module in the form of a PRPD spectrogram and presented to the operator; The partial discharge detection device on the surface of the distribution network cable terminal includes a power supply module, a frequency division filter module, an analog-to-digital conversion module, and a CPU module. The input ports of the frequency division filter module are respectively connected to the partial discharge sensors sleeved on each phase of the cable under test in the switch cabinet. The phase output port of the frequency division filter module is connected to the low-speed port of the analog-to-digital conversion module, and the partial discharge output port of the frequency division filter module is connected to the high-speed port of the analog-to-digital conversion module; the parallel digital output port of the analog-to-digital conversion module is connected to the CPU module; The frequency division filter module collects the original partial discharge signals on the surface of the cable under test, separates the effective partial discharge signals and phase signals in the original partial discharge signals, converts the above effective partial discharge signals and phase signals into digital signals through the analog-to-digital conversion module and then transmits them to the CPU module. The CPU module is used for cyclic acquisition and signal processing of the digital signals. The signal processing includes trigger signal zero-phase detection, phase window discharge quantity peak seeking, and phase counting. The trigger signal zero-phase detection completes the detection of the rising edge of the zero crossing point of the phase signal. After detecting the rising edge of the zero crossing point, the phase window discharge quantity peak seeking and phase counting are executed, and finally the phase-discharge quantity data starting from the zero point of the rising edge of the phase signal is output; The process of zero-phase detection of the trigger signal is as follows: First, clear and initialize the rising-edge flag flag_start of the phase signal, and adjust the data range of the phase signal after analog-to-digital conversion to -512 to 511. Name the adjusted phase signal data as ad0_data. Then, sample ad0_data for two clock cycles along the rising edge of the clock signal. The first sample is named zero_st1, and the second sample is named zero_st2, that is, zero_st1 lags zero_st2 by one clock cycle. Next, judge whether the exclusive-NOR operation result of the most significant bits of zero_st1 and zero_st2 data is 1. If it is 1, then proceed to the next step; If it is not 1, clear the rising-edge flag flag_start of the phase signal and end the process; Subsequently, after a time delay of 5 clock cycles, judge whether the logical AND operation result of the most significant bit of zero_st1 being 0 and the most significant bit of zero_st2 being 1 is 1. If the result is 1, it means that the process of the digital quantity of the phase signal changing from negative to positive, that is, the phase zero point, is detected. Then, set the rising-edge flag flag_start of the phase signal to 1 and end; Otherwise, clear the rising-edge flag flag_start of the phase signal and end the process.

2. A method for detecting local surface discharge of a distribution network cable terminal according to claim 1, characterized in that: The process of peak seeking for the discharge amount in the phase window is as follows: First, judge whether the phase signal is the rising-edge zero point. After detecting the rising-edge zero point, initialize the maximum discharge amount in the phase window, the sampling point ordinal number, and the phase window ordinal number to 0. Then, judge whether the current discharge amount is greater than the maximum discharge amount in the phase window. If it is greater, assign the current discharge amount to the maximum discharge amount in the phase window and increment the sampling point ordinal number by 1; Otherwise, directly increment the sampling point ordinal number by 1; Then, loop the above comparison process until all sampling points in the current phase window are traversed; After looping and comparing a phase window, save the maximum discharge amount in the phase window and increment the phase window ordinal number by 1.

3. A method for detecting local partial discharge on the surface of a distribution network cable terminal according to claim 1, characterized in that: The process of phase counting is as follows: First, judge whether the rising-edge zero point of the phase signal is reached. If it is reached, initialize the phase window number, the phase span of a single phase window, the current phase, and the current phase window ordinal number; If the phase signal does not reach the rising-edge zero point, continue to detect until the rising-edge zero point arrives; Then, wait for the peak seeking of the discharge amount to traverse each partial discharge sampling point in the phase window. After traversing, update the current phase window ordinal number and the current phase. Then, repeat the above process for the next phase window until the phase calculation of all phase windows within the entire trigger period is completed.

4. A method for detecting partial discharge on the surface of a distribution network cable terminal according to claim 1, characterized in that: The frequency division filtering module consists of three identical signal processing circuits, namely signal processing circuit A, signal processing circuit B, and signal processing circuit C. The input ports of signal processing circuit A, signal processing circuit B, and signal processing circuit C are respectively connected to the partial discharge sensors sleeved on the A-phase, B-phase, and C-phase of the cable under test. The input port of each signal processing circuit includes two branch circuits. One branch circuit uses two operational amplifiers and their connected capacitors and resistors to collect the phase signal, which is used to provide a synchronous clock. The other branch circuit uses four operational amplifiers and their connected capacitors and resistors to collect the partial discharge pulse signal and record the occurrence of discharge events.

5. A method for detecting partial discharge on the surface of a distribution network cable terminal according to claim 4, characterized in that: The analog-to-digital conversion module consists of a low-speed analog-to-digital conversion unit and three high-speed analog-to-digital conversion units. The three input ports of the low-speed analog-to-digital conversion unit are respectively connected to the phase signal output ends of signal processing circuit A, signal processing circuit B, and signal processing circuit C. The three high-speed analog-to-digital conversion units are respectively connected to the partial discharge signal output ends of signal processing circuit A, signal processing circuit B, and signal processing circuit C.

6. A method for detecting local partial discharge on the surface of a distribution network cable terminal according to any one of claims 1-5, characterized in that: It also includes a communication module, and the CPU module communicates bidirectionally with the communication module.

7. A method for detecting local partial discharge on the surface of a distribution network cable terminal according to claim 6, characterized in that: It also includes a display module. The display module is connected to the CPU module. The CPU module is built-in with software for plotting the phase-discharge amount data into a PRPD spectrogram corresponding to partial discharge, and the display module visually displays the plotted PRPD spectrogram.

8. A method for detecting local partial discharge on the surface of a distribution network cable terminal according to claim 7, characterized in that: The CPU module is built-in with a data storage module, and the data storage module consists of two FIFO read-write control modules and a SDRAM storage area.

Images