Data access method and memory

Abstract

According to the data access method and the memory, in the application, the memory can receive a write-in request from a processor, and the write-in request is used for requesting to write in data. The memory obtains data carried in the write-in request, after data compression is performed, EEC operation is performed on the compressed data to generate a first check code, the compressed data, the first check code and a first identifier are stored, and the first identifier is used for indicating that the stored data is compressed. Due to the fact that the data is compressed, the storage space occupied by the reduced data in the memory is allowed to generate the first check code with the larger length, the larger the length of the first check code is, the better the error correction capability of the first check code is, the reliability of the memory can be improved by compressing the data, and in the process, the error correction capability of the memory is improved. Storage particles do not need to be added in the memory, so that the cost of the memory is ensured, and the reliability of the memory is ensured.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a data access method and a memory. Background Art

[0002] In a computing device, the memory of the computing device includes multiple storage particles for storing user data, and also includes one or more storage particles for storing check codes of the user data. In the event of an error in the user data, the check code can provide a certain error correction capability to correct the erroneous data.

[0003] When designing the memory of a computing device, it is necessary to consider the error probability of the memory at different periods throughout its life cycle. If the memory is designed only based on the low error probability during the initial use period, then the memory will only include a small number of storage particles for storing verification codes of user data. The error probability of the memory designed in this way will increase in the later stages of its life cycle, and its reliability will deteriorate. If the memory is designed only based on the high error probability during the later stages of its use, then the memory will include more storage particles for storing verification codes of user data. The memory designed in this way has a high cost, and the advantages of the multiple storage particles cannot be fully utilized in the early stages of its life cycle. Summary of the invention

[0004] The embodiments of the present application provide a data access method and a memory, which are used to improve the error correction capability of the memory without increasing the cost of the memory.

[0005] In a first aspect, an embodiment of the present application provides a data access method, which can be executed by a memory. The memory can receive a write request from a processor, and the write request is used to request to write data.

[0006] The memory obtains the data carried in the write request, and after compressing the data, performs an ECC operation on the compressed data to generate a first check code. For example, the memory may call a first ECC error correction algorithm to generate a first check code for the compressed data. After generating the first check code, the memory may store the compressed data, the first check code, and a first flag bit, where the first flag bit is used to indicate that the stored data has been compressed.

[0007] Through the above method, when writing data into the memory, the memory can compress the data and generate a first check code for the compressed data. Since the data is compressed, the storage space occupied by the data in the memory is reduced, allowing the generation of a first check code with a longer length. The longer the length of the first check code is, the better its error correction capability is. By compressing the data, the reliability of the memory can be improved. In this process, there is no need to increase storage particles in the memory, which not only ensures the cost of the memory, but also ensures the reliability of the memory.

[0008] In a possible implementation, the storage medium of the memory is divided according to the wear status of different areas in the storage medium. The storage medium of the memory may include multiple first areas with different wear status. When the memory stores compressed data, a first check code, and a first mark bit, the memory determines a first area for storing the compressed data, the first check code, and the first mark bit according to the wear status of the multiple first areas, and stores the compressed data, the first check code, and the first mark bit in the determined first area. The memory may determine a first area according to the wear status of the multiple first areas, allocate a first physical address to the compressed data, the first check code, and the first mark bit in the first area, and store the compressed data, the first check code, and the first mark bit at the first physical address.

[0009] Through the above method, the memory can assign a first physical address to the compressed data, the first check code and the first mark bit in combination with the wear status of different areas in the storage medium, and store the compressed data and the first check code to ensure that the compressed data, the first check code and the first mark bit can be stored in a more suitable first area.

[0010] In a possible implementation, since the first check code has a higher error correction capability, it may be considered to store the compressed data, the first check code, and the first mark bit in an area with more wear. For example, the first area storing the compressed data, the first check code, and the first mark bit is the first area with the most wear among the first areas with free space. This can ensure the error correction capability of the memory and improve the utilization rate of each first area in the storage medium.

[0011] In a possible implementation, the storage medium of the memory is divided according to the error rate ranges of different areas in the storage medium, and the storage medium of the memory includes multiple second areas, and the error rate ranges of different second areas are different. When the memory stores compressed data, the first check code, and the first mark bit, the memory determines the second area for storing the compressed data, the first check code, and the first mark bit according to the error rate ranges of the multiple second areas, and stores the compressed data, the first check code, and the first mark bit in the determined second area. The memory can determine a second area from the multiple second areas, allocate a first physical address to the compressed data and the first check code in the second area, and store the compressed data and the first check code at the first physical address.

[0012] Through the above method, the memory can allocate a first physical address to the compressed data, the first check code and the first mark bit in combination with the error rate range of different areas in the storage medium, and store the compressed data, the first check code and the first mark bit to ensure that the compressed data, the first check code and the first mark bit can be stored in the second area with a suitable error rate range.

[0013] In a possible implementation, since the first check code has a higher error correction capability, it may be considered to store the compressed data, the first check code, and the first mark bit in an area with a larger error rate range. For example, the second area storing the compressed data, the first check code, and the first mark bit is the first area with the largest error rate range in the second area with free space. In the embodiment of the present application, the size of the error rate range refers to the size of the boundary value of the error rate range. This can not only ensure the error correction capability of the memory, but also improve the utilization rate of each area in the storage medium.

[0014] In a possible implementation, after the memory compresses the data, if the ratio of the compressed data to the data is less than or equal to the compression rate threshold, the memory may perform an ECC operation on the compressed data to generate a first check code.

[0015] Through the above method, when the ratio of compressed data to data meets the compression rate threshold, it means that more storage space can be reserved for the first check code, effectively ensuring that the first check code is longer and has better error correction capability.

[0016] In one possible implementation, if the ratio of compressed data to data is greater than a compression rate threshold, the memory performs an ECC operation on the data to generate a second check code, stores the data and the second check code, wherein the length of the first check code is greater than the length of the second check code, and stores the data and the second check code.

[0017] Through the above method, if the ratio of compressed data to data does not meet the certain compression rate threshold, and more storage space cannot be reserved for the first check code, in this case, the second check code can be directly generated for the data. When storing data and the second check code, a first area with less wear (such as the first area with the least wear in the first area with free space) and / or a second area with a smaller error rate range (such as the second area with the smallest error rate range in the second area with free space) can be selected.

[0018] In a possible implementation, when the memory stores compressed data and the second check code, the memory may store the second check code and the second marker, where the second marker is used to indicate that the stored data is not compressed.

[0019] Through the above method, the second mark bit can be used to conveniently determine whether the data is compressed, so as to facilitate processing of the data when the data is read again later.

[0020] In a possible implementation, the memory receives a read request sent by the processor, where the read request is used to request to read data. The memory obtains the compressed data and the first check code. The memory first verifies the compressed data using the first check code. If the verification is successful, it means that there is no error data in the compressed data. The compressed data is decompressed, and data is obtained and fed back to the processor. If the verification fails, it means that the compressed data is wrong. The compressed data is corrected using the first check code. After the error correction is successful, the corrected data is decompressed, and data is obtained and fed back to the processor.

[0021] Through the above method, the memory can decompress the compressed data when the processor needs to read the data, thereby ensuring that the memory can accurately feed back the data to the processor.

[0022] In a second aspect, the present application further provides a memory, which has the function of implementing the behavior in the method example of the first aspect, and the beneficial effects can be found in the description of the first aspect and will not be repeated here. The storage device includes a controller and a storage medium.

[0023] Storage media, used to store data.

[0024] The controller may receive a write request sent by the processor, the write request being used to request writing data, and after receiving the write request, the controller compresses the data carried in the write request. After compressing the data, the controller performs an ECC operation on the compressed data to generate a first check code, and stores the compressed data, the first check code, and a first flag bit in a storage medium, the first flag bit being used to indicate that the stored data has been compressed.

[0025] In one possible implementation, the storage medium includes multiple first areas. When storing the compressed data, the first check code, and the first mark bit, the controller determines the first area to store the compressed data, the first check code, and the first mark bit according to the wear status of the multiple first areas, and stores the compressed data, the first check code, and the first mark bit in the determined first area.

[0026] In a possible implementation manner, the first area storing the compressed data, the first check code and the first mark bit is the first area with the greatest wear among the first areas with free space.

[0027] In one possible implementation, the storage medium includes multiple second areas, and different second areas have different error rate ranges. When storing the compressed data, the first check code, and the first mark bit, the controller determines the second area for storing the compressed data, the first check code, and the first mark bit according to the error rate ranges of the multiple second areas, and stores the compressed data, the first check code, and the first mark bit in the determined second area.

[0028] In a possible implementation manner, the second region storing the compressed data, the first check code and the first mark bit is the first region with the largest error rate range among the second regions with free space.

[0029] In a possible implementation, the ratio of compressed data to data is less than a compression rate threshold.

[0030] In one possible implementation, if the ratio of compressed data to data is greater than a compression rate threshold, the controller can perform an ECC operation on the data to generate a second check code, store the data and the second check code, wherein the length of the first check code is greater than the length of the second check code, and store the data and the second check code.

[0031] In a possible implementation, when the controller stores the data and the second check code in the storage medium, the controller may store the data, the second check code, and a second marker, wherein the second marker is used to indicate that the stored data is not compressed.

[0032] In a possible implementation, the controller may receive a read request sent by the processor, where the read request is used to request to read data. The controller obtains compressed data and a first check code from a storage medium, and then verifies the compressed data using the first check code. If the verification succeeds, the controller decompresses the compressed data, obtains data, and feeds back data to the processor. If the verification fails, the controller uses the first check code to correct errors in the compressed data, and after the error correction succeeds, the controller decompresses the corrected data, obtains data, and feeds back data to the processor.

[0033] In the third aspect, the present application also provides a storage device, the functions of which can be implemented by hardware or by executing corresponding software through hardware. The hardware or software includes one or more units corresponding to the above functions. In one possible design, the structure of the storage device includes a compression module, a first encoding module, and a storage module, and optionally, a second encoding module. These modules can perform the corresponding functions of the storage device in the method example of the first aspect above. For details, please refer to the detailed description in the method example, which will not be repeated here.

[0034] In a fourth aspect, the present application further provides a computer-readable storage medium, in which instructions are stored, and when the computer-readable storage medium is run on a computer, the computer executes the method in the above-mentioned first aspect and various possible implementations of the first aspect.

[0035] In a fifth aspect, the present application also provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method in the above-mentioned first aspect and various possible implementations of the first aspect.

[0036] In a sixth aspect, the present application also provides a computer chip, which is connected to a memory, and the chip is used to read and execute a software program stored in the memory to execute the methods in the above-mentioned first aspect and various possible implementation methods of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A structural diagram of a data access system provided for this application;

[0038] Figure 2 A schematic diagram of the structure of a memory provided by this application;

[0039] Figure 3 A schematic diagram of the structure of a storage particle provided in this application;

[0040] Figure 4 A schematic diagram of a data access method provided for this application;

[0041] Figure 5 A schematic diagram of a storage device provided in this application. DETAILED DESCRIPTION

[0042] like Figure 1 , which is a schematic diagram of the structure of a data access system 10 provided in an embodiment of the present application, the system includes a processor 100 and a memory 200 .

[0043] The processor 100 is the computing core of the system. The processor 100 can perform major data computing operations. When performing data computing operations, the processor 100 can access the memory 200 to read data or write data in the memory 200. For example, the processor 100 can read data from the memory 200 and perform data computing on the read data; the processor 100 can also store data generated after data computing in the memory 200.

[0044] When accessing the memory 200 , the processor 100 sends a read request or a write request to the memory 200 . The read request or the write request carries a logical address of data to instruct the memory 200 to read or write data at the logical address.

[0045] The embodiment of the present application does not limit the specific type of the processor 100. The processor 100 may be a central processing unit (CPU) or other specific integrated circuits. The processor 100 may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0046] The memory 200 has a data storage function. The memory 200 can store data required by the processor 100 for data calculation, and can also store data generated after the processor 100 performs data calculation. Exemplarily, the memory 200 receives and processes a read request or a write request from the processor 100, reads and writes data according to the logical address of the data, writes the data calculated by the processor 100 to the logical address, or reads the data required by the processor 100 for data calculation from the logical address, and feeds the read data back to the processor 100.

[0047] In the embodiment of the present application, the memory 200 has the following capabilities:

[0048] Capability 1. ECC capability.

[0049] The memory 200 with the ECC capability can perform ECC operations on the data and generate a check code for the data when it is necessary to write data into the memory 200 (such as the processor 100 initiating a write request). Exemplarily, the memory 200 can call an ECC error correction algorithm (such as the first ECC error correction algorithm and the second ECC error correction algorithm mentioned in the embodiment of the present application) to generate a check code for the data, and store the data and the check code for the data. Correspondingly, when it is necessary to read the data (such as the processor 100 initiating a read request), the memory 200 will read the data and the check code for the data, and use the check code for the data to check and correct the data. After checking or correcting, subsequent operations are performed, for example, the data that is successfully checked or corrected is transmitted to the processor 100, and for example, after the error correction fails, the processing data is notified of an error. Among them, checking refers to determining whether there is an error in the data, and error correction refers to correcting the erroneous data in the data. Here, the ECC algorithm represents a type of algorithm that can be used to generate a check code. The embodiments of the present application do not limit the specific type of the ECC algorithm, for example, Hamming code, Reed-Solomon (RS), BCH (Bose-Chaudhuri-Hocquenghem) algorithm.

[0050] The memory 200 with the ECC capability can correct erroneous data in the internally stored data to ensure the accuracy of the data.

[0051] Ability 2: Data compression and decompression capabilities.

[0052] The memory 200 with compression and decompression capabilities can compress the data before writing the data into the memory, and if the compression is successful, the compressed data is written into the memory 200. If the compression fails, the data is written into the memory 200. The compression success means that the ratio of the compressed data to the data before compression (referred to as the data compression rate) is less than or equal to the compression rate threshold, and the compression failure means that the ratio of the compressed data to the data before compression (referred to as the data compression rate) is greater than the compression rate threshold.

[0053] Correspondingly, when data needs to be read, if the data is compressed successfully when being written into the memory 200, the memory 200 will read the compressed data and decompress the compressed data.

[0054] In addition, the memory 200 may also set a first flag bit for the data that has been compressed successfully, and the first flag bit is used to indicate that the data has been compressed. The embodiment of the present application does not limit the setting method of the first flag bit. For example, the first flag bit may be stored in the memory 200 together with the compressed data. For another example, the first flag bit may be added to the mapping relationship between the logical address and the physical address of the data. When the data is subsequently read, when the physical address of the data is queried, it can be determined that the data has been compressed through the first flag bit recorded in the mapping relationship.

[0055] For data that fails to be compressed, the memory 200 may also set a second flag bit for the data, and the second flag bit is used to indicate that the data is not compressed. Similar to the first flag bit, the embodiment of the present application does not limit the setting method of the second flag bit. For example, the second flag bit may be stored in the memory 200 together with the data. For another example, the second flag bit may be added to the mapping relationship between the logical address and the physical address of the data. When reading the data later, when querying the physical address of the data, the second flag bit recorded in the mapping relationship may be used to determine that the data is not compressed.

[0056] The memory 200 with compression and decompression capabilities can reduce redundant data in the data, thereby reducing the storage space occupied by the data.

[0057] In view of the fact that the memory 200 has both of the above-mentioned capabilities, when storing data, the memory 200 can generate a check code for the compressed data after compressing the data, that is, perform an ECC operation on the compressed data to generate a check code, and the check code for the compressed data is the check code generated for the compressed data (such as the first check code mentioned in the embodiment of the present application), and store the compressed data and the check code for the compressed data (optionally, the first mark bit can also be stored). The memory 200 may also not compress the data, generate a check code for the data, store the data and the check code for the data (optionally, the second mark bit can also be stored).

[0058] Correspondingly, when it is necessary to obtain data in the memory 200, the memory 200 can obtain the compressed data and the check code of the compressed data, and after the compressed data is successfully checked using the check code of the compressed data, the compressed data is decompressed. The memory 200 can also obtain data and the check code of the data, and use the check code of the data to check the data.

[0059] Ability 3: Assign physical addresses to data.

[0060] The processor 100 specifies the storage location of the data in the memory 200 through the logical address of the data. The logical address can be understood as the address provided by the memory 200 to the external device (such as the processor 100) to locate the data storage location. As for the memory 200, the memory 200 can allocate the actual storage location (physical address) to the data according to the logical address of the data, that is, the memory 200 can realize the conversion between the logical address and the physical address. The physical address is the address used inside the memory 200 to locate the storage location of the data.

[0061] In the memory 200, the memory 200 realizes data writing and reading by changing the voltage of the internal circuit of the memory 200. The number of times or frequency of reading and writing will cause the storage medium 220 in the memory 200 to form wear. Different degrees of wear will also lead to different actual error rates of data in the region. In the storage medium 220, the number of times of reading and writing in different regions is different, and the wear state of different regions is also different. The number of times of reading and writing in the region is large, the actual error rate in the region is large, and the wear state is poor; the number of times of reading and writing in the region is small, the actual error rate in the region is small, and the wear state is good. The actual error rate indicates the probability of erroneous data appearing when reading and writing data at this position or region. In the embodiment of the present application, the specific calculation method of the actual error rate is not limited. The actual error rate of a certain position or a certain region can be equal to the ratio of the number of bits that have errors in the data reading and writing operations performed for a set number of times to the total number of bits read and written by the data reading and writing operations for a set number of times, or it can be equal to the ratio of the number of bits that have errors in multiple data reading and writing operations performed per unit time to the total number of bits read and written by the data reading and writing operations for a set number of times.

[0062] In the embodiment of the present application, the memory 200 can monitor the wear state of each area in the storage medium 220 in the memory 200. When the memory 200 converts the logical address into the physical address, it allocates the physical address to the data according to the wear state of each area in the storage medium 220, and establishes a mapping relationship between the logical address and the physical address. The wear state of a certain area represents the number of reads and writes in the area or its actual error rate.

[0063] For example, the memory 200 may preferentially write compressed data into an area with a worse wear state, and write uncompressed data into an area with a better wear state.

[0064] Due to the influence of factors such as the wiring method of the internal circuit of the memory 200 and the design method of the driving voltage inside the memory 200, the error rates of different areas in the storage medium 220 will be different, that is, the storage medium 220 is further divided based on the error rate of the data to form multiple different areas. The range of the error rate in each area is the same, while the range of the error rate in different areas is different. The error rate here is different from the error rate involved in the description of the wear state. The error rate involved in the description of the wear state refers to the error rate calculated by recording the errors in the reading and writing process of the memory 200 during the working process (after leaving the factory), which is the actual error rate of the memory 200. The error rate here is caused by the influence of factors such as the wiring mode of the internal circuit of the memory 200 and the design mode of the driving voltage inside the memory 200. The error rate of different areas in the storage medium 220 is an error rate determined based on the properties of the memory 200 itself. This error rate is an error rate determined based on the hardware characteristics of the memory 200 itself. It is an error rate that can be estimated before the memory 200 leaves the factory or obtained through professional evaluation software testing, and is not an error obtained by actual measurement of the memory 200 during operation. For the sake of convenience, this error rate is called an estimated error rate.

[0065] When converting a logical address into a physical address, the memory 200 may allocate a physical address to the data in combination with the error rate ranges of different regions and the state of the data itself.

[0066] For example, the memory 200 may preferentially write compressed data into an area with a higher error rate, and write uncompressed data into an area with a lower error rate.

[0067] It should be noted that the area division standard mentioned in "the memory 200 monitors the wear status of each area in the storage medium 220 in the memory 200" may be different from the area division standard mentioned in "the error rate range of different areas in the storage medium 220". For example, when dividing areas according to the wear status, the memory 200 can monitor the number of read and write times or the actual error rate at each physical address in the storage medium 220 in the memory 200, and divide it into multiple areas according to the number of read and write times or the actual error rate at each physical address in the storage medium 220. Assume that the memory 200 is divided into multiple areas according to the number of read and write times at each physical address in the storage medium 220. The number of read and write times of physical addresses in different areas is different. Each area corresponds to a read and write number range, that is, for any area, the number of read and write times of the physical addresses in the area belongs to the read and write number range corresponding to the area.

[0068] The areas referred to in the “error rate ranges of different areas in the storage medium 220” may be areas determined based on specific values ​​of the estimated error rate range.

[0069] In order to conveniently distinguish between these two different areas, in an embodiment of the present application, the area mentioned in "the memory 200 monitors the wear status of each area in the storage medium 220 in the memory 200" is referred to as the first area, and the storage medium 220 may include multiple first areas, and the number of read and write times at each physical address in each first area belongs to the range of read and write times corresponding to the first area. The wear status of different first areas is different. The embodiment of the present application does not limit the division method of the first area and the number of first areas. For example, the memory 200 can be divided according to the number of read and write times at different physical addresses in the storage medium 220, and the storage medium 220 is divided into ten first areas, each of which corresponds to a range of read and write times. As the memory 200 interacts with the processor 100, the number of read and write times at different physical addresses in the storage medium 220 will change, and the coverage of the first area (that is, the physical address covered by the first area) will also change.

[0070] The area mentioned in "the error rate range of different areas in the storage medium 220" is referred to as the second area. The storage medium 220 may include multiple second areas, each of which corresponds to an error rate range, and the error rate ranges of different second areas are different. The second area division of different error rate ranges in the storage medium 220 is related to multiple factors such as the routing of the circuit inside the memory 200 and the design of the driving voltage in the memory 200. The number of second areas included in the storage medium 220 and the error rate range of each second area are related to the circuit structure inside the memory 200. In addition, when using dedicated evaluation software to test its estimated error rate, the number of second areas with different error rate ranges in the memory 200 and the error rate range of each second area will also change due to the setting of the test parameters. For example, in a specific test, when a higher accuracy or more error rate gears can be selected, the second area included in the storage medium 220 may also increase.

[0071] From the above definitions of the two areas, it can be seen that there is no direct relationship between the first area and the second area. The first area may include one or more second areas, and the first area may also include part of the second area. The second area may include one or more first areas, and the second area may also include part of one or more first areas.

[0072] The embodiment of the present application does not limit the specific type of the memory 200. The memory 200 may be a phase change memory 200 (PCM), a dynamic random access memory 200 (DRAM), or other types of memory.

[0073] like Figure 2 FIG. 2 is a schematic diagram of a memory structure provided in an embodiment of the present application. The memory 200 includes a controller 210 and a storage medium 220.

[0074] In the memory 200, the storage medium 220 is the main component for storing data. The embodiment of the present application does not limit the specific type of the storage medium 220. The specific type of the storage medium 220 is related to the type of the memory 200. For example, when the memory 200 is PCM or DRAM, the storage medium 220 is the storage particle 230 of the PCM or DRAM.

[0075] The following describes the structure of the storage medium 220 by taking the memory 200 as PCM or DRAM as an example. Figure 3 As shown, the storage medium 220 includes a plurality of storage particles (chips) 230. From the hardware structure, the storage particle 230 is the smallest physical unit for storing data in the memory 200. The storage space inside any storage particle 230 can be further divided. Each storage particle 230 includes a plurality of BANKs. Each BANK can be regarded as a storage matrix, which is like a grid array. This "grid array" has many columns and many rows. When it is necessary to retrieve certain data in the memory 200, it is only necessary to specify the BANK, the row in the BANK, and the column. The size, number of rows, and number of columns of each BANK are relatively fixed, that is, the logical address range covered by each BANK is fixed.

[0076] In a memory 200 such as PCM or DRAM, multiple storage particles 230 included in the memory 200 share the same set of logical addresses. That is, after the memory 200 receives a read / write request carrying a logical address, the controller 210 inside the memory 200 converts the logical address into a physical address, sends the physical address to each storage particle 230, and each storage particle 230 parses the physical address to parse out the information pointing to the BANK, column, and row, and reads and writes data to the BANK, column, and row pointed to by the information.

[0077] When there are multiple storage particles 230 in the memory 200, each storage particle 230 can contribute part of the data, such as each storage particle 230 contributes 8 bytes of data, so that the amount of data read and written in each data read and write operation inside the memory 200 is the sum of the amount of data contributed by each storage particle 230, such as the amount of data read and written in one data read and write operation is the product of the number of storage particles 230 and 8. The data at the logical address is distributed in each storage particle 230 of the memory 200 from the physical position.

[0078] The controller 210 is the control center of the memory 200, and manages or controls the storage medium 220. For example, the controller 210 writes or reads data in the storage medium 220, or implements data compression or decompression, or implements conversion between logical addresses and physical addresses.

[0079] The controller 210 can support various capabilities of the memory 200. The following describes the control methods for supporting various capabilities of the memory 200:

[0080] Capability 1. ECC capability.

[0081] Inside the memory 200, after receiving a write request for writing data sent by a device outside the memory 200 (such as the processor 100) to the memory 200, the controller 210 determines that the data needs to be written to the storage medium 220, performs an ECC operation on the data, generates a check code for the data, and stores the data and the check code for the data. Exemplarily, the controller 210 calls an ECC error correction algorithm to generate a check code for the data, and writes the data and the check code for the data to the storage medium 220.

[0082] After receiving a read request for reading data sent by a device other than the memory 200 to the memory 200, the controller 210 will not only read the data from the storage medium 220, but also read the check code of the data from the storage medium 220, and call the ECC error correction algorithm to check the read data according to the check code to determine whether the data read from the storage medium 220 is erroneous. If the data is found to be free of errors through verification, the controller 210 will feed back the data to the device requesting the data; if the data is found to be erroneous through verification, the controller 210 will use the check code to correct the read data; when the error correction is successful, the controller 210 can feed back the corrected data to the device requesting the data; when the error correction fails, the controller 210 notifies the device that an error has occurred in the data reading.

[0083] Ability 2: Data compression and decompression capabilities.

[0084] Inside the memory 200, after the controller 210 receives a write request for writing data sent by a device outside the memory 200 (such as the processor 100) to the memory 200, the controller 210 determines that the data needs to be written to the storage medium 220, compresses the data, and if the compression is successful, stores the compressed data in the storage medium 220. If the compression fails, the data is stored in the storage medium 220. After the controller 210 receives a read request for reading data sent by a device outside the memory 200 to the memory 200, the controller 210 needs to read the data from the storage medium 220. If the data is successfully compressed when written to the storage medium 220, the controller 210 reads the compressed data from the storage medium 220, decompresses the compressed data, obtains the data, and feeds the data back to the device requesting the data; if the data fails to be compressed when written to the storage medium 220, the controller 210 reads the data from the storage medium 220 and feeds the data back to the device requesting the data.

[0085] Inside the memory 200, the controller 210 can realize the setting and storage of the first mark bit and the second mark bit. The setting and storage of the first mark bit and the second mark bit can be referred to the above description, which will not be repeated here.

[0086] Since the memory 200 has both of the above two capabilities, when storing data, the memory 200 can generate a check code for the compressed data after the data is compressed successfully. The memory 200 can also generate a check code for the data without compressing the data.

[0087] Inside the memory 200, if data needs to be written to the storage medium 220, the controller 210 may first compress the data. If the compression is successful, the controller 210 obtains the compressed data, and the controller 210 performs an ECC operation on the compressed data to generate a check code for the compressed data, and stores the compressed data and the check code for the compressed data in the storage medium 220. If the compression fails, the controller 210 performs an ECC operation on the data to generate a check code for the data, and stores the data and the check code for the data in the storage medium 220.

[0088] Correspondingly, when it is necessary to obtain data in the memory 200, inside the memory 200, if it is necessary to read data from the storage medium 220, if the data is compressed successfully when writing, the controller 210 reads the compressed data and the check code of the compressed data from the storage medium 220, and calls the ECC error correction algorithm to check the read data according to the check code. If it is found through verification that there is no error in the compressed data, the controller 210 can decompress the compressed data, obtain the data, and feed the data back to the device requesting the data. If it is found through verification that there is an error in the compressed data, the controller 210 will use the check code of the compressed data to correct the compressed data; when the error correction is successful, the controller 210 continues to decompress the data obtained after the error correction, obtain the data, and feed the data back to the device requesting the data; when the error correction fails, the controller 210 notifies the device requesting the data that an error has occurred in the data reading.

[0089] Ability 3: Assign physical addresses to data.

[0090] Inside the memory 200, the controller 210 can realize the conversion between the logical address and the physical address. When the controller 210 converts the logical address into the physical address, the controller 210 can allocate the physical address to the data according to the wear status of each first area in the storage medium 220, and establish a mapping relationship between the logical address and the physical address. The controller 210 can also allocate the physical address to the data in combination with the error rate range of different second areas and the status of the data itself.

[0091] Combine the following Figure 4 A data access method provided in an embodiment of the present application is described. The method includes two parts, one part is a data writing process, see step 401 to step 408, and the other part is a data reading process, see step 409 to step 411.

[0092] Step 401: The processor 100 sends a write request to the memory 200. The write request is used to request to write data. The write request includes the data and the logical address of the data.

[0093] Step 402: After receiving the write request, the memory 200 compresses the data carried in the write request. If the data compression is successful, step 403 is executed. If the data compression fails, step 406 is executed. This step can be executed by the controller 210.

[0094] When compressing data, the compression rate of the data (i.e., the ratio between the compressed data and the data before compression) is related to the data compression method and the data itself. For example, for data with less repeated data such as images and videos, the data compression rate is low and the amount of data that can be compressed is small. For file and text data, such data usually has more repeated data, the compression rate of such data is higher, and the amount of data that can be compressed is larger. In addition, in the embodiment of the present application, the data compression method adopted by the memory 200 is not limited, and any method that can compress data is applicable to the embodiment of the present application.

[0095] The memory 200 is provided with a compression rate threshold. After compressing the data, the memory 200 determines the ratio of the compressed data to the data before compression, that is, the compression rate of the data, and compares the compression rate of the data with the compression rate threshold. If the compression rate of the data is less than or equal to the compression rate threshold, the compression is successful, and the memory 200 executes step 403. If the compression rate of the data is greater than the compression rate threshold, the compression fails, and the memory 200 executes step 406.

[0096] The embodiment of the present application does not limit the number of compression rate thresholds set inside the memory 200. One compression rate threshold may be set inside the memory 200, or multiple compression rate thresholds may be set. When multiple compression rate thresholds are set inside the memory 200, when the compression rate of the data is less than or equal to any compression rate threshold, the compression is considered to be successful. When the compression rate of the data is greater than all compression rate thresholds, the compression is considered to have failed. Among them, the situation where the compression rate of the data is equal to the compression rate threshold can be considered as a special case. In practical applications, it can be considered that the compression is successful when the compression rate of the data is equal to the compression rate threshold, and it can also be considered that the compression fails when the compression rate of the data is equal to the compression rate threshold.

[0097] Each compression rate threshold corresponds to an ECC operation, and the ECC operation refers to a method of generating a check code of the data based on the data. The ECC operations corresponding to different compression rate thresholds may be different, and the check codes generated by different ECC operations for the same data may be different, such as different lengths of the check codes. The ECC operation can be understood as an ECC error correction algorithm. To put it another way. Each compression rate threshold corresponds to a first ECC error correction algorithm, and the first ECC error correction algorithms corresponding to different compression rate thresholds may be different. When the compression rate of the data is less than or equal to one of the compression rate thresholds among the multiple compression rate thresholds, there may be a situation where the compression rate of the data is less than other compression rate thresholds among the multiple compression rate thresholds, that is, there are multiple compression rate thresholds that are greater than or equal to the compression rate of the data. For example, five compression rate thresholds are set, from large to small, compression rate threshold A, compression rate threshold B, compression rate threshold C, compression rate threshold D, and compression rate threshold E. When the compression rate of the data is less than or equal to the compression rate threshold B, the compression rate of the data must also be less than the compression rate threshold A. In the subsequent step 403, step 403 may be performed by an ECC operation (or a first ECC error correction algorithm) corresponding to a minimum compression rate threshold among a plurality of compression rate thresholds greater than the compression rate of the data.

[0098] Step 403: After the data is successfully compressed, the memory 200 performs an ECC operation on the compressed data to generate a check code for the compressed data. For the convenience of description, in the embodiment of the present application, the check code generated for the compressed data is referred to as a first check code.

[0099] In the embodiment of the present application, the ECC error correction algorithm called to generate the first check code is called the first ECC error correction algorithm, and the embodiment of the present application does not limit the specific type of the first ECC error correction algorithm. That is, step 403 can be understood as the memory 200 calling the first ECC error correction algorithm for the compressed data to generate the first check code.

[0100] For any ECC error correction algorithm, the ECC error correction algorithm can encode data to generate a check code for the data. Different types of ECC error correction algorithms or different parameter values ​​in the ECC error correction algorithm can generate different lengths of the check code for the data.

[0101] In the embodiment of the present application, for the first ECC error correction algorithm corresponding to any compression rate threshold, when the compression rate of the data is equal to the compression rate threshold, the first checksum generated by the first ECC error correction algorithm for the compressed data and the total data length of the compressed data are not greater than the data length written by the controller 210 to the storage medium 220 at one time. Taking PCM as an example, the data length written by the controller 210 to the storage medium 220 at one time is equal to the product of the number of storage particles 230 in the storage medium 220 and the bit width of each storage particle 230, and the bit width of the storage particle 230 is equal to the data length that can be written by the storage particle 230 at one time.

[0102] When the memory 200 executes step 403, if the data compression rate is less than the compression rate threshold corresponding to the first ECC error correction algorithm, then the first check code generated by calling the first ECC error correction algorithm for the compressed data and the total data length of the compressed data may be less than the data length that the controller 210 writes to the storage medium 220 at one time. In this case, the controller 210 may first pad the compressed data with 0, that is, add one or more 0 bits to the compressed data to ensure that the first check code generated by calling the first ECC error correction algorithm for the zero-padded data and the total data length of the zero-padded data are equal to the data length that the controller 210 writes to the storage medium 220 at one time. The controller 210 may also first call the first ECC error correction algorithm to generate the first check code for the compressed data, and then pad the compressed data and the first check code with zero, and the total data length of the compressed data and the first check code after the zero padding is equal to the data length that the controller 210 writes to the storage medium 220 at one time.

[0103] For the memory 200, when the storage space that the storage medium 220 in the memory 200 can provide is fixed (such as the size and number of the storage particles 230 are fixed), when the memory 200 performs a data read and write operation, the total amount of data written by the memory 200 in the storage medium 220 and its check code (that is, the length of data that the controller 210 can write to the storage medium 220 at one time) is usually fixed. For example, under the double data rate (DDR) 4 standard, 8 or 16 storage particles 230 are allowed to store data, and 1 or 2 storage particles 230 are allowed to store the check code of the data. When 8 storage particles 230 store data and 1 storage particle 230 stores the check code of the data, each storage particle 230 provides 8 bytes of space for storing data or the check code of the data. When 16 storage particles 230 store data and 2 storage particles 230 store the check code of the data, each storage particle 230 provides 4 bytes of space for storing data or the check code of the data. Regardless of which method is used, the total amount of data read and written in the memory 200 in one data read and write operation is 64 bytes of data and 8 bytes of check code, that is, the total amount of data is 72 bytes of data.

[0104] In the embodiment of the present application, when the memory 200 executes step 403, since the data has been compressed successfully, the memory 200 can generate a first check code with a longer data length for the compressed data. For example, still taking the DDR4 standard as an example, for 64 bytes of data, when not compressed, the maximum data length of the check code of the data allowed inside the memory 200 is 8 bytes. If the 64 bytes of data are compressed and become 56 bytes of data, the maximum data length of the check code of the data allowed inside the memory 200 is 16 bytes. The increase in the check code can effectively improve the error correction capability of the memory 200.

[0105] Step 404: The memory 200 allocates a first physical address to the compressed data and the first check code, and records a mapping relationship between the first physical address and the logical address.

[0106] After the memory 200 obtains the compressed data and generates the first check code, the memory 200 can execute step 404. The embodiment of the present application does not limit the way in which the memory 200 executes step 404. The following lists several ways in which the memory 200 provided in the embodiments of the present application allocates the first physical address to the compressed data and the first check code.

[0107] Method 1: The memory 200 allocates a first physical address to the compressed data and the first check code according to the wear status of each first area in the storage medium 220 .

[0108] Since the data length of the first check code is relatively long, the error correction performance of the first check code is relatively good. When the memory 200 allocates the first physical address for the compressed data and the first check code, it can select the first physical address in the first area with more wear (that is, the wear state is poor) from multiple first areas. The embodiment of the present application does not limit the manner in which the memory 200 selects the first area where the first physical address is located from the multiple first areas. For example, the memory 200 can select the first area with the greatest wear from the first area with free space, and allocate the first physical address to the compressed data and the first check code from the first area. For another example, the memory 200 can select the first area with medium wear (that is, the wear is between the maximum wear and the minimum wear) from the first area with free space, and allocate the first physical address to the compressed data and the first check code from the first area.

[0109] For example, the memory 200 divides the area in the storage medium 220 into two first areas, the first area A and the first area B, based on the number of read and write times at each physical address, and the number of read and write times of the physical address in the first area A is greater than the number of read and write times of the physical address in the first area B. If there is an unoccupied physical address in the first area A, the memory 200 allocates the first physical address in the first area A to the compressed data and the first check code. If there is no unoccupied physical address in the first area A, the memory 200 allocates the first physical address in the first area B to the compressed data and the first check code.

[0110] For example, based on the number of read and write times at each first physical address, the memory 200 divides the area within the storage medium 220 into three first areas, namely, the first area A1, the first area A2, and the first area A3. The number of read and write times of the first physical address of each first area is sorted from large to small as follows: the first area A1, the first area A2, and the first area A3.

[0111] If there is an unoccupied physical address in the first area A1, the memory 200 allocates the first physical address in the first area A1 to the compressed data and the first check code. If there is no unoccupied physical address in the first area A1, and there is an unoccupied physical address in the first area A2, the memory 200 allocates the first physical address in the first area A2 to the compressed data and the first check code. If there is no unoccupied physical address in the first area A1 and the first area A2, and there is an unoccupied physical address in the first area A3, the memory 200 allocates the first physical address in the first area A3 to the compressed data and the first check code.

[0112] Method 2: The memory 200 allocates a first physical address to the compressed data and the first check code according to the error rate range of each second area in the storage medium 220 .

[0113] Since the data length of the first check code is relatively long and the error correction performance of the first error correction code is relatively good, the memory 200 can select the first physical address in the second area with a higher error rate range from multiple second areas when allocating the first physical address for the compressed data and the first check code. The embodiment of the present application does not limit the manner in which the memory 200 selects the second area where the first physical address is located from the multiple second areas. For example, the memory 200 can select the second area with the largest error rate range from the second area where there is free space, and allocate the first physical address to the compressed data and the first check code from the second area. For another example, the memory 200 can select the second area with the middle error rate range from the second area where there is free space, and allocate the first physical address to the compressed data and the first check code from the second area.

[0114] For example, for each BANK in the storage particle 230 in the memory 200, each BANK is divided into two second areas, the second area A and the second area B, and the error rate range of the first area A is greater than the error rate range in the first area B (that is, the lower limit of the error rate range of the first area A is greater than the upper limit of the error rate range in the first area B). If there is an unoccupied physical address in the second area A, the memory 200 allocates the first physical address in the second area A to the compressed data and the first check code. If there is no unoccupied physical address in the second area A, the memory 200 allocates the first physical address in the second area B to the compressed data and the first check code.

[0115] For example, the memory 200 divides each BANK in the storage particle 230 into three second areas, namely, the second area A1, the second area A2, and the second area A3. The error rate ranges of the second areas are arranged from large to small as follows: the second area A1, the second area A2, and the second area A3.

[0116] If there is an unoccupied physical address in the second area A1, the memory 200 allocates the first physical address in the second area A1 to the compressed data and the second check code. If there is no unoccupied physical address in the second area A1, and there is an unoccupied physical address in the second area A2, the memory 200 allocates the physical address in the second area A2 to the compressed data and the second check code. If there is no unoccupied physical address in the second area A1 and the second area A2, and there is an unoccupied physical address in the second area A3, the memory 200 allocates the first physical address in the second area A3 to the compressed data and the second check code.

[0117] Method three: the memory 200 allocates a first physical address to the compressed data and the first check code according to the wear state of each first area in the storage medium 220 and the error rate range of each second area.

[0118] Since the data length of the first check code is longer and the error correction performance of the first error correction code is better, when the memory 200 allocates the first physical address to the compressed data and the first check code, it can select a first area with more wear (that is, worse wear status) from multiple first areas, such as selecting the first area with the most wear. After selecting the first area, if the first area includes one or more second areas (or partial areas in the second area), the memory 200 can further select a second area with a larger error rate range (partial area in the second area) from the first area. For example, if the second area with the largest error rate range is selected, the memory 200 can allocate the first physical address to the compressed data and the first check code from within the second area.

[0119] When allocating the first physical address to the compressed data and the first check code, the memory 200 may also select a second area with a larger error rate range from multiple second areas, such as selecting the second area with the largest error rate range. After selecting the second area, if the second area includes one or more first areas (or partial areas in the first area), the memory 200 may further select a first area (partial area in the first area) with a worse wear state (i.e., more wear) from the second area. For example, if the first area with the most wear is selected, the memory 200 can allocate a first physical address to the compressed data and the first check code from within the first area.

[0120] The embodiment of the present application does not limit the manner in which the memory 200 selects the second region where the first physical address is located from the plurality of second regions and the manner in which the first region where the first physical address is located is selected from the plurality of first regions. Any manner in which the first physical address can be allocated to the compressed data and the first check code in combination with the wear state of each first region in the storage medium 220 and the error rate range of each second region is applicable to the embodiment of the present application.

[0121] For example, the area in the storage medium 220 is divided into two first areas, the first area A and the first area B, and the number of read and write times of the physical address in the first area A is greater than the number of read and write times of the first physical address in the first area B. If there is an unoccupied first physical address in the first area A, and the first area A covers one or more second areas (or part of the second areas), the memory 200 determines a second area with a minimum error rate range and an unoccupied physical address in the first area A, and the memory 200 allocates the first physical address in the second area to the compressed data and the first check code.

[0122] Step 405: The memory 200 stores the compressed data and the first check code according to the first physical address.

[0123] After determining the first physical address, the memory 200 stores the compressed data and the first check code at the location indicated by the first physical address. Taking the memory 200 as a PCM as an example, since each storage particle 230 inside the memory 200 shares the same physical address, the controller 210 transmits the first physical address and the data to be stored in each storage particle 230 to each storage particle 230. Any storage particle 230 locates the row and column of the BANK in the storage particle 230 based on the first physical address, and inputs a control voltage to the device or circuit on the row and column of the BANK in the storage particle 230, so that data is written to the row and column of the BANK in the storage particle 230.

[0124] Optionally, the memory 200 can set and store a first flag bit for the compressed data, and the first flag bit is used to indicate that the stored data has been compressed. The embodiment of the present application does not limit the setting method of the first flag bit. For example, after generating the first check code, the memory 200 can add a first flag bit to the compressed data to characterize that the data has been compressed, and the compressed data, the first check code and the first flag bit can be stored on the first physical address. For another example, when the memory 200 records the mapping relationship between the physical address (such as the first physical address) and the logical address, the memory 200 can add a first flag bit to the mapping relationship to indicate that the data is not compressed, and the first flag bit is stored in the mapping relationship.

[0125] Step 406: After the memory 200 fails to compress the data, it performs an ECC operation on the data to generate a check code for the data. For the convenience of explanation, the check code generated for the data in the embodiment of the present application is referred to as a second check code. The ECC operation performed in step 406 is different from the ECC operation performed in step 404, and the check code generated is also different.

[0126] In the embodiment of the present application, the ECC error correction algorithm called to generate the second check code is called the second ECC error correction algorithm, and the embodiment of the present application does not limit the specific type of the second ECC error correction algorithm. That is, step 403 can be understood as the memory 200 calling the second ECC error correction algorithm for the compressed data to generate the second check code.

[0127] The way in which the memory 200 executes step 406 is similar to the way in which the memory 200 executes step 403, except that the data for which the check code needs to be generated is different, that is, the data in step 406 is uncompressed data, and that in step 403 is compressed data.

[0128] Step 407: The memory 200 allocates a second physical address to the data and the second check code.

[0129] After the memory 200 obtains the data and generates the second check code, the memory 200 can execute storage of the data and the second check code. The embodiment of the present application does not limit the way in which the memory 200 executes step 407. Similar to the way in which the memory 200 executes step 404, the memory 200 can allocate a second physical address to the data and the second check code by any of the methods listed below.

[0130] Method 1: The memory 200 allocates the second physical address for the data and the second check code according to the wear status of each first area in the storage medium 220 .

[0131] Compared with the first check code, the data length of the second check code is smaller, and the error correction performance of the second check code is poor. When the memory 200 allocates the second physical address for the data and the second check code, it can select the second physical address in the first area with less wear (that is, better wear state) from multiple first areas. The embodiment of the present application does not limit the way in which the memory 200 selects the first area where the second physical address is located from the multiple first areas. For example, the memory 200 can select the first area with the least wear from the first area with free space, and allocate the second physical address to the data and the second check code from the first area.

[0132] Method 2: The memory 200 allocates the second physical address to the data and the second check code according to the error rate range of each second area in the storage medium 220 .

[0133] When the memory 200 allocates the second physical address for the data and the second check code, it can select the second physical address in the second area with a lower error rate range from the multiple second areas. The embodiment of the present application does not limit the manner in which the memory 200 selects the second area where the second physical address is located from the multiple second areas. For example, the memory 200 can select the second area with the smallest error rate range from the second area with free space, and allocate the second physical address for the data and the second check code from the second area.

[0134] Method three: allocating a second physical address to the compressed data and the first check code according to the wear status of each area in the storage medium 220 and the error rate range of each area.

[0135] When allocating a second physical address to the data and the second check code, the memory 200 can select a first area with less wear from multiple second areas, such as selecting the first area with the least wear. After selecting the first area, if the first area includes one or more second areas (or partial areas in the second area), the memory 200 can further select a second area with a smaller error rate range (partial area in the second area) from the first area. For example, if the second area has the smallest error rate range, the memory 200 can allocate a second physical address to the data and the second check code from within the second area.

[0136] When the memory 200 allocates a second physical address to the data and the second check code, it may also select a second area with a smaller error rate range from multiple second areas. After selecting the second area, if the second area includes one or more first areas (or partial areas in the first area), the memory 200 may further select a first area (partial area in the first area) with a better wear state (i.e., less wear) from the second area, and the memory 200 may allocate a second physical address to the data and the second check code from within the first area.

[0137] The embodiment of the present application does not limit the manner in which the memory 200 selects the second region where the first physical address is located from the plurality of second regions and the manner in which the first region where the first physical address is located is selected from the plurality of first regions. Any manner in which the second physical address can be allocated to the data and the second check code in combination with the wear state of each first region in the storage medium 220 and the error rate range of each second region is applicable to the embodiment of the present application.

[0138] Step 408: The memory 200 stores the data and the second check code according to the second physical address, and records the mapping relationship between the second physical address and the logical address. The memory 200 performs step 405 in a similar manner to the memory 200 performs step 408. For details, please refer to the above content and will not be repeated here.

[0139] Optionally, the memory 200 can set and store a second flag bit for the data, and the second flag bit is used to indicate that the stored data is not compressed. The embodiment of the present application does not limit the setting method of the second flag bit. For example, after generating the first check code, the memory 200 can add a second flag bit to the data to characterize that the data is not compressed, and the data, the second check code and the second flag bit can be stored at the second physical address. For another example, when the memory 200 records the mapping relationship between the physical address (such as the second physical address) and the logical address, the memory 200 can add a second flag bit to the mapping relationship to indicate that the data is not compressed, and the second flag bit is stored in the mapping relationship.

[0140] Steps 403 to 405 describe the process of writing data in the memory 200 after the data compression is successful, and steps 406 to 408 describe the process of writing data in the memory 200 after the data compression fails. It can be seen from the above steps that the memory 200 provides two different data writing methods. For data whose compressed data meets the compression rate threshold, the memory 200 can compress such data and generate a first check code with better error correction performance based on the compressed data to ensure that when subsequent data errors occur, the data can be effectively corrected. The memory 200 can also store the compressed data and the first check code at the first physical address with a high error rate or a poor wear state. Even if the data stored at the first physical address is wrong, the first check code can be used to achieve error correction. For data whose compressed data does not meet the compression rate threshold, the memory 200 may not compress such data, but directly generate a second check code for the data. And the data and the second check code are stored at the second physical address with a low error rate or a good wear state, reducing the probability of errors in the data stored at the second physical address.

[0141] Step 409: The processor 100 sends a read request to the memory 200. The read request is used to request to read data, and the read request includes a logical address of the data.

[0142] Step 410: After receiving the read request, the memory 200 reads the data according to the logical address of the data.

[0143] If the data is compressed successfully when written, the memory 200 determines the first physical address according to the logical address of the data, reads the compressed data and the first check code from the first physical address, and the memory 200 can determine that the data is compressed successfully when written by identifying the first mark bit set for the data. The compressed data is checked using the first check code, and if the check is successful, the memory 200 decompresses the compressed data. If the check fails, the memory 200 uses the first check code to correct the compressed data, and if the error correction is successful, the corrected data is decompressed to obtain the data. If the error correction fails, the data reading fails, and the memory 200 can inform the processor 100 that the data reading fails.

[0144] If the data fails to be compressed when being written, the memory 200 determines the second physical address according to the logical address of the data, reads the data and the second check code from the second physical address, and the memory 200 can determine that the data is not compressed when being written by identifying the second mark bit set for the data. The memory 200 uses the second check code to check the compressed data. If the check succeeds, the memory 200 obtains the data and executes step 411. If the check fails, the memory 200 uses the second check code to correct the data. If the error correction succeeds, the corrected data is the data. If the error correction fails, the data reading fails, and the memory 200 can inform the processor 100 that the data reading fails.

[0145] Step 411 : The memory 200 feeds back the data to the processor 100 .

[0146] Based on the same inventive concept as the method embodiment, the embodiment of the present application further provides a storage device, which is used to execute the above-mentioned Figure 5 The method executed by the memory in the method embodiment shown in the figure, the relevant features can be found in the above method embodiment, and will not be repeated here. Figure 5 As shown, the storage device 500 includes a compression module 501 , a first encoding module 502 , a storage module 503 , and a second encoding module 504 .

[0147] The compression module 501 is used to receive a write request sent by the processor, where the write request is used to request to write data, and compress the data.

[0148] The first encoding module 502 is used to perform an ECC operation on the compressed data to generate a first check code.

[0149] The storage module 503 is used to store the compressed data, the first check code and the first mark bit in the storage medium, where the first mark bit is used to indicate that the stored data has been compressed.

[0150] In a possible implementation, the storage medium includes multiple first areas, and the storage module 503 determines the first area for storing compressed data and a first check code according to the wear status of the multiple first areas, and stores the compressed data, the first check code, and the first mark bit in the determined first area.

[0151] In a possible implementation manner, the first area storing the compressed data, the first check code, and the first mark bit is the first area with the greatest wear among the first areas with free space.

[0152] In a possible implementation, the storage medium includes multiple second areas, and different second areas have different error rate ranges. The storage module 503 determines the second area for storing compressed data and the first check code based on the error rate ranges of the multiple second areas, and stores the compressed data, the first check code, and the first mark bit in the determined second area.

[0153] In a possible implementation manner, the second region storing the compressed data, the first check code and the first mark bit is the first region with the largest error rate range among the second regions with free space.

[0154] In a possible implementation, the ratio of compressed data to data is less than or equal to a compression rate threshold.

[0155] In a possible implementation, if the ratio of the compressed data to the data is greater than the compression rate threshold, the storage device further includes a second encoding module 504, the second encoding module performs an ECC operation on the data to generate a second check code, wherein the length of the first check code is greater than the length of the second check code. The storage module 503 stores the data and the second check code.

[0156] In a possible implementation, when the storage module 503 stores data and the second check code, the storage module 503 stores the data, the second check code and the second marker, and the second marker is used to indicate that the stored data is not compressed.

[0157] In a possible implementation, the compression module 501 receives a read request sent by the processor, where the read request is used to request to read data. The storage module 503 obtains the compressed data and the first check code from the storage medium. The first encoding module 502 uses the first check code to check or correct the compressed data. The compression module 501 decompresses the compressed data after the first encoding module 502 successfully checks or corrects the compressed data using the first check code, obtains and feeds back the data to the processor.

[0158] It should be noted that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. The functional modules in the embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0159] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid state drive (SSD).

[0160] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0161] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0162] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0163] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0164] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A data access method, It is characterized in that include: The memory receives a write request sent by the processor, wherein the write request is used to request to write data; After compressing the data, the memory performs an ECC operation on the compressed data to generate a first check code, and stores the compressed data, the first check code and a first flag bit, where the first flag bit is used to indicate that the stored data has been compressed.

2. The method according to claim 1, It is characterized in that The storage medium of the memory includes a plurality of first areas, and the memory stores the compressed data and the first check code, including: The memory determines a first area for storing the compressed data and the first check code according to the wear status of the multiple first areas, and stores the compressed data, the first check code and the first mark bit in the determined first area.

3. The method according to claim 2, It is characterized in that The first area storing the compressed data, the first check code and the first mark bit is the first area with the most wear among the first areas with free space.

4. The method according to any one of claims 1 to 3, It is characterized in that The storage medium of the memory includes a plurality of second areas, and different second areas have different error rate ranges. The memory stores the compressed data, the first check code, and the first flag bit, including: The memory determines a second area for storing the compressed data, the first check code and the first mark bit according to the error rate range of the multiple second areas, and stores the compressed data, the first check code and the first mark bit in the determined second area.

5. The method according to claim 4, It is characterized in that The second area storing the compressed data, the first check code and the first flag bit is the first area with the largest error rate range in the second area with free space.

6. The method according to any one of claims 1 to 5, It is characterized in that The ratio of the compressed data to the data is less than or equal to a compression rate threshold.

7. The method according to claim 6, It is characterized in that If the ratio of the compressed data to the data is greater than the compression rate threshold, the method further includes: The memory performs an ECC operation on a second check code for the data, stores the data and the second check code, wherein the length of the first check code is greater than the length of the second check code, and stores the data and the second check code.

8. The method according to claim 7, It is characterized in that The memory stores the data and the second check code, and further includes: The memory stores the data, the second check code and a second marker, wherein the second marker is used to indicate that the stored data is not compressed.

9. The method according to any one of claims 1 to 8, It is characterized in that The method further comprises: The memory receives a read request sent by the processor, where the read request is used to request to read the data; The memory acquires the compressed data and the first check code; After successfully verifying or correcting the compressed data using the first verification code, the memory decompresses the compressed data, obtains the data, and feeds it back to the processor.

10. A memory, It is characterized in that The memory includes a controller and a storage medium; The storage medium is used to store data; The controller is used to receive a write request sent by the processor, wherein the write request is used to request writing data; after compressing the data, an ECC operation is performed on the compressed data to generate a first check code, and the compressed data, the first check code and a first mark bit are stored, wherein the first mark bit is used to indicate that the stored data has been compressed.

11. The memory according to claim 10, It is characterized in that The storage medium includes a plurality of first areas, and the controller is configured to: The memory determines a first area for storing the compressed data and the first check code according to the wear status of the multiple first areas, and stores the compressed data, the first check code and the first mark bit in the determined first area.

12. The memory according to claim 11, It is characterized in that The first area storing the compressed data, the first check code and the first mark bit is the first area with the most wear among the first areas with free space.

13. The memory according to any one of claims 10 to 12, It is characterized in that The storage medium includes a plurality of second areas, and different second areas have different error rate ranges. The controller is used to: A second area for storing the compressed data, the first check code and the first mark bit is determined according to the error rate range of the multiple second areas, and the compressed data, the first check code and the first mark bit are stored in the determined second area.

14. The memory as claimed in claim 13, It is characterized in that The second area storing the compressed data, the first check code and the first flag bit is the first area with the largest error rate range in the second area with free space.

15. The memory according to any one of claims 10 to 14, It is characterized in that The ratio of the compressed data to the data is less than or equal to a compression rate threshold.

16. The memory as claimed in claim 15, It is characterized in that If the ratio of the compressed data to the data is greater than the compression rate threshold, the controller is further configured to: An ECC operation is performed on the data to generate a second check code, and the data and the second check code are stored, wherein the length of the first check code is greater than the length of the second check code, and the data and the second check code are stored.

17. The memory according to claim 16, It is characterized in that The controller is used to: The data, the second check code and a second marker are stored, wherein the second marker is used to indicate that the stored data is not compressed.

18. The memory according to any one of claims 10 to 17, It is characterized in that The controller is further used for: receiving a read request sent by the processor, wherein the read request is used to request to read the data; Acquire the compressed data and the first check code from the storage medium; After the compressed data is successfully verified or error-corrected using the first verification code, the compressed data is decompressed, and the data is acquired and fed back to the processor.

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