Expander device channel switching for memory devices

Abstract

The invention relates to expander device channel switching for memory devices. A method includes receiving, by a memory device interface, a signal including a header from a host; decoding, by the memory device interface, the header to determine an instruction; selecting, by the memory device interface, a first channel associated with a first memory resource based on the instruction; sending, by the memory device interface, the tag to a second channel associated with a second memory resource; and sending, by the memory device interface, subsequent packets of the header to the first channel.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to expander device channel switching of memory devices. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. For example, the memory devices may be non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present disclosure provides a method for expander device channel switching, comprising: receiving, by a memory device interface, a signal including a header; decoding, by the memory device interface, the header to determine an instruction; selecting, by the memory device interface, a first channel associated with a first memory resource based on the instruction; sending, by the memory device interface, the header to a second channel associated with a second memory resource; and sending, by the memory device interface, a subsequent packet of the header to the first channel.

[0004] On the other hand, the present disclosure provides an apparatus for expander device channel switching, comprising: a plurality of memory dies; and a memory device interface for transmitting communications between a host that can be coupled to the memory device interface and the plurality of memory dies, wherein the memory device interface comprises a controller configured to: identify a first header associated with a first signal received at the memory device interface; allow the first header to pass through a first channel to a first memory resource; switch from the first channel to a second channel associated with a second memory resource in response to allowing the first header to pass through the first channel; allow a plurality of packets associated with the first header to pass through the second channel to the second memory resource; identify a second header associated with a second signal; and switch from the second channel to the first channel in response to identifying the second header.

[0005] On the other hand, the present disclosure provides a system for expander device channel switching, comprising: a memory subsystem comprising a non-volatile memory device; and a host that can be coupled to the memory subsystem through a memory device interface, the memory device interface comprising a processing device, the processing device being configured to: receive a first signal including a first header from the host; allow the first header to pass through a first channel of the memory device interface to a first memory resource of the non-volatile memory device; switch from the first channel to a second channel in response to the first header passing through the first channel; receive a plurality of simple content access (SCA) packets from the host; allow the plurality of SCA packets to pass through the second channel of the memory device interface to a second memory resource of the non-volatile memory device; receive a second signal including a second header; allow the second header to pass through the second channel of the memory device interface to the second memory resource of the non-volatile memory device; and switch from the second channel to the first channel in response to the second header passing through the second channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 A system including a multi-channel input / output expander according to some embodiments of the present disclosure is described.

[0009] Figure 3 A timing diagram illustrating expander device channel switching for a memory device according to some embodiments of the present disclosure.

[0010] Figure 4 is a flowchart corresponding to a channel switching method according to some embodiments of the present disclosure.

[0011] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0012] Aspects of the present disclosure relate to signal locking, and in particular, to a memory subsystem including a signal locking component. The memory subsystem may be a storage system, a storage device, a memory module, or a combination thereof. An example of a memory subsystem is a storage system, such as a solid state drive (SSD). Figure 1and others to describe examples of storage devices and memory modules. In general, a host system may utilize a memory subsystem that includes one or more components, such as a memory device that stores data. The host system may provide data stored at the memory subsystem and may request data retrieved from the memory subsystem.

[0013] The memory device may be a non-volatile memory device. One example of a non-volatile memory device is a NAND memory device (also known as flash technology). As used herein, a NAND memory device may include a set of flash memory dies or a combination of a flash memory die and a non-volatile memory (NVM) controller. The NVM controller may include circuitry for performing read / write operations, as described herein. Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may be composed of one or more planes. Planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. A block hereinafter refers to a cell of a memory device for storing data and may include a group of memory cells, a group of word lines, a word line, or an individual memory cell. For some memory devices, a block (hereinafter also referred to as a "memory block") is the smallest area that can be erased. Pages cannot be erased individually and only entire blocks can be erased.

[0014] Each of the memory devices may include one or more memory cell arrays. Depending on the cell type, a cell may be written so as to store one or more binary bits of information and have various logic states related to the number of stored bits. The logic state may be represented by a binary value such as "0" and "1" or a combination of such values. There are various types of cells such as single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC). For example, an SLC may store one bit of information and have two logic states.

[0015] Some NAND memory devices employ a floating gate architecture in which memory access is controlled based on relative voltage changes between a bit line and a word line. Other examples of NAND memory devices may employ a replacement gate architecture, which may include using a word line layout that may allow a charge corresponding to a data value to be trapped within a memory cell based on the properties of the material used to construct the word line.

[0016] In some previous approaches, an input / output (IO) expander (IOE) device may be placed between a host and a memory die. For example, an IOE device may be placed between a host device and multiple NAND dies (or "LUNs"). The host side of the IOE device may be referred to as the front end (front side) and the memory die side of the IOE device may be referred to as the back end (back side). The IOE device may allow the host to view a single die load at the front side (FS) of the IOE device. The NAND die load may be distributed across multiple IOE back side channels. These previous IOE devices may implement a crossbar switch to route the intended traffic to the target NAND die. As used herein, a crossbar switch includes a set of switches arranged in a matrix configuration. The crossbar switch may have multiple input and output lines that form a cross pattern of interconnect lines, and connections between the interconnect lines may be established by closing switches (elements of the matrix) positioned at each intersection.

[0017] In some previous approaches, the IOE device may be implemented with a buffer architecture to allow the crossbar switch to work. In this implementation, all signals from the host to the NAND and from the NAND to the host are buffered within the IOE device and distributed to the desired ports of the crossbar switch. In these approaches, as more NAND dies are added to the system, the load or load average between the host and the NAND can be reduced. That is, as more NAND dies are added to the system, the previous IOE device will have a lower load capacity between the host and the NAND.

[0018] In some previous approaches, an IOE device may receive communications from a host device at the front end and provide the communications to a memory resource at the back end. In these previous approaches, the host device may utilize headers (e.g., vendor specific (VSP) headers, etc.) during the SCA mode of operation. In these previous embodiments, the headers may be passed to the same memory resource as the payload or other portion of the communication. In some previous embodiments, there may be a risk that the headers will cause a memory resource failure. In some embodiments, it may be difficult or impossible to filter the headers provided to the memory resource, which may cause delays or failures associated with the host communicating with the memory resource.

[0019] Aspects of the present disclosure address the above and other shortcomings by adopting an IOE device that utilizes channel switching. For example, aspects of the present disclosure may utilize a channel switching component that can be configured to switch channels in response to receiving a header. For example, in some embodiments, the header may include instructions for switching and / or selecting a back-end channel of the IOE device. In some embodiments, the header may be used to select and / or switch the back-end channel for the payload of the communication associated with the header. For example, in a specific embodiment, a communication packet may be sent to the IOE device. The communication packet may include a header that includes instructions for switching the back-end channel from a first back-end channel to a second back-end channel. In this example, the header may be sent to the first back-end channel and the payload or other portion of the communication packet may be sent to the second back-end channel. In this way, the header does not negatively affect the memory resources coupled to the second back-end channel. In this way, the header can be used to trigger the back-end channel switching of the IOE device and does not potentially affect the performance of the memory resources associated with the memory resources to be used to receive the communication.

[0020] Figure 1 An example computing system including a memory subsystem 110 according to some embodiments of the present disclosure is illustrated. Memory subsystem 110 may include media such as one or more volatile memory devices (such as memory device 140), one or more non-volatile memory devices (such as memory device 130), or a combination thereof.

[0021] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0022] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (such as an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (such as an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0023] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0024] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0025] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0026] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0027] Some examples of non-volatile memory devices (e.g., memory device 130) include non-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on body resistance changes in conjunction with a stacked cross-gate data access array. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0028] Each of the memory devices 130, 140 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, and / or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory, such as NAND, pages may be grouped to form blocks.

[0029] Although nonvolatile memory components such as a three-dimensional cross-point array of nonvolatile memory cells and NAND-type memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0030] As described above, the memory component may be a memory die or a memory package that forms at least a portion of the memory device 130. In some embodiments, a block of memory cells may form one or more "super blocks". As used herein, a "super block" generally refers to a group of data blocks that span multiple memory dies and are written in an interleaved manner. For example, in some embodiments, each of several interleaved NAND blocks may be deployed across multiple memory dies having multiple planes and / or pages associated therewith. In view of the context of the present disclosure, the terms "super block", "block", "memory cell block" and / or "interleaved NAND block" and variations thereof may be used interchangeably.

[0031] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0032] The memory subsystem controller 115 may be a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0033] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 is illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0034] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system that communicates with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140 and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0035] In some embodiments, memory subsystem 110 may include a cache or buffer such as DRAM and address circuitry such as a row decoder and a column decoder that may receive addresses from memory subsystem controller 115 and decode the addresses to access memory device 130 and / or memory device 140. For example, in some embodiments, memory device 140 may be a DRAM and / or SRAM configured to operate as a cache for memory device 130. In such examples, memory device 130 may be NAND.

[0036] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local media controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. Memory subsystem 110 may also include additional circuitry or components not illustrated.

[0037] The memory subsystem 110 may include a channel switching component 113, which may alternatively be referred to herein as a "controller." Although Figure 11 so as not to obscure the diagram, but channel switch component 113 may include various circuitry that facilitates aspects of media management, as described in detail herein. In some embodiments, channel switch component 113 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry that may allow channel switch component 113 to orchestrate and / or perform the operations described herein.

[0038] In some embodiments, the memory subsystem controller 115 includes at least a portion of the channel switching component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, the channel switching component 113 is part of the memory subsystem 110, an application, or an operating system.

[0039] In a non-limiting example, a device (e.g., computing system 100) may include a channel switching component 113. Channel switching component 113 may reside on memory subsystem 110. As used herein, the term "resides on" refers to something being physically located on a particular component. For example, channel switching component 113 "resides on memory subsystem 110" refers to a condition in which a hardware circuit system including channel switching component 113 is physically located on memory subsystem 110. In this document, the term "resides on" may be used interchangeably with other terms such as "deployed on" or "located on".

[0040] As further described herein, computing system 100 may include an IOE device that can be used to connect a host (e.g., host system 120, etc.) to a memory device (e.g., memory device 130, etc.). In some embodiments, the IOE device can be coupled to the host at the front end and to the memory device at the back end. The host can configure the IOE device based on the properties of the memory device. For example, a configuration signal from the host can be received at a chip enable pin of the IOE device. In previous methods, the configuration signal can be provided to the memory device even if the configuration signal is not desired to be received by the memory device. As described herein, the configuration signal may be detrimental to the performance of the memory device. In some embodiments, channel switching component 113 can be used to filter or prevent headers from being provided to a specific memory device or a specific channel.

[0041] The channel switching component 113 may be configured to identify a first header associated with a first signal received at a memory device interface. As used herein, a memory device interface may be an IOE device that can communicatively couple a host device or a host system 120 to a plurality of memory dies. In some embodiments, the first header is received from a host controller and / or a host system 120. In some embodiments, the first header is a first vendor specific (VSP) header. In some embodiments, the host controller may use the first VSP header as a first instruction and the second VSP header as a second instruction different from the first instruction. In this way, the host controller may utilize the VSP header to cause back-end channel switching of the IOE device.

[0042] In these embodiments, the host controller or host system 120 may use the first header as a command or instruction to the memory device interface and / or the IOE device. For example, the first header may be decoded by the IOE device. Decoding the first header may include analyzing the header to determine the instructions encoded within the first header. In some embodiments, the first header may be associated with multiple data packets. In these embodiments, the first header may include instructions for providing the multiple data packets to a specific backend channel and / or a specific memory resource.

[0043] In some embodiments, the channel switching component 113 may be configured to allow the first header to pass through the first channel to the first memory resource. In some embodiments, the channel switching component 113 may send or direct the first header through the first channel to the first memory resource coupled to the first channel. As described herein, the first channel may be a backend channel of the IOE device. In these embodiments, the first channel may be the currently selected channel and the first header may include instructions for switching the channel to a channel different from the selected channel. In this way, the first header may be sent to the first channel before switching from the first channel to the second channel and sending the communication packet to the second channel.

[0044] In some embodiments, the channel switching component 113 may be configured to decode the first header to determine the instruction for switching from the first channel to the second channel. As described herein, the first header may be a VSP header encoded with instructions to the IOE device for back-end channel switching. For example, the first header may be encoded with instructions for back-end channel selection. In this example, the IOE device may decode the first header to determine the instruction. In this way, the channel switching component 113 of the host device may utilize the VSP header to instruct the IOE device to switch back-end channels.

[0045] The channel switching component 113 can be configured to switch from the first channel to a second channel associated with the second memory resource in response to allowing the first header to pass through the first channel. As described herein, the first channel can be a first back-end channel of the IOE device. In this way, the second channel can be a second back-end channel of the IOE device that is different from the first channel.

[0046] In some embodiments, the channel switching component 113 may perform a switch from the first channel to the second channel in response to a decoded instruction from the first header. In some embodiments, the first channel is a currently selected channel of the IOE device and the second channel is an unselected channel of the IOE device. As further described herein, the first header may be transmitted to the first channel before switching from the first channel to the second channel. In this way, the first header is sent to a different backend channel than the signals or packets (e.g., SCA packets, etc.) that make up the remainder of the communication session. In this way, the first header does not interrupt or alter the function of the memory resource to receive the signals and / or packets of the communication session.

[0047] The channel switching component 113 can be configured to allow a plurality of packets associated with the first header to pass through the second channel to the second memory resource. As described herein, the IOE device can send the first header to the first channel to the first memory resource and send the plurality of packets associated with the first header to the second backend channel. In some embodiments, the plurality of packets include simple content access (SCA) packets. In this way, the first header does not affect the performance of the second memory resource to receive the plurality of SCA packets or other signals associated with the first header.

[0048] The channel switching component 113 may be configured to identify a second header associated with the second signal. In some embodiments, the second header is received from the host controller. In some embodiments, the second header may be decoded by the channel switching component 113. The second header may be encoded with instructions to switch back from the second channel to the first channel. In some embodiments, when the IOE device includes channels other than the first channel and the second channel, the second header may be encoded with instructions to switch from the second channel to a different backend channel. In this way, the second header may include the same or similar instructions as the first header.

[0049] The channel switching component 113 may be configured to switch from the second channel to the first channel in response to identifying the second header. As described herein, the second header may include instructions similar to the first header. When the channel switching component 113 decodes the second header, the channel switching component 113 may switch the backend channel to a channel different from the second channel. As further described herein, the channel switching component 113 may send the second header to the second channel and send packets and / or other signals associated with the second header to a different backend channel, such as (but not limited to) the first channel.

[0050] In some embodiments, the channel switching component 113 can be configured to allow the second header to pass through the second channel to the second memory resource. In some embodiments, the first header is a first vendor-specific header and the second header is a second vendor-specific header. In some embodiments, the first header and the second header are not recognizable by the plurality of memory dies. As described herein, the first header and the second header are not recognizable by the plurality of memory dies, such that the memory dies can ignore the first header and / or the second header.

[0051] However, in some embodiments, the first header and / or the second header may cause multiple memory dies to fail or cause a change in performance of the multiple memory dies. For this reason, the first header and / or the second header may be sent to a different backend channel than the multiple packets, so that the multiple packets are sent to a different memory resource than the corresponding header to avoid any failure or change in performance of the memory resource that is receiving the multiple packets.

[0052] Figure 2 A system 221 including a multi-channel input / output expander device 222 according to some embodiments of the present disclosure is described. The IOE device 222 may include a device utilizing a first input channel 223-1 and a second input channel 223-2 that may be connected to a host device or a host system. In some embodiments, the IOE device 222 may operate in a single channel mode and / or a dual channel mode. In these embodiments, the IOE device 222 may utilize only the first input channel 223-1 in the single channel mode and may utilize both the first input channel 223-1 and the second input channel 223-2 in the dual channel mode. In some embodiments, the second input channel 223-2 is disabled to perform the single channel mode using the first input channel 223-1.

[0053] In some embodiments, the IOE device 222 may include a first plurality of output channels 224-1, 224-2 and a second plurality of output channels 224-3, 224-4. In some embodiments, the first output channel 224-1 may be coupled to a first portion of LUNs 225-1, the second output channel 224-2 may be coupled to a second portion of LUNs 225-2, the third output channel 224-3 may be coupled to a third portion of LUNs 225-3, and the fourth output channel 224-4 may be coupled to a fourth portion of LUNs 225-4. In single channel mode, the first input channel 223-1 may be used to access multiple LUNs 225-1, 225-2, 225-3, 225-4. In dual channel mode, the first input channel 223-1 can be used to access the first portion of LUN 225-1 and the second portion of LUN 225-2 through the first plurality of output channels 224-1, 224-2, and the second input channel 223-2 can be used to access the third portion of LUN 225-3 and the fourth portion of LUN 225-4 through the second plurality of output channels 224-3, 224-4.

[0054] In some previous methods, the host may provide a signal to the IOE device 222 through one of the first input channel 223-1 and the second input channel 223-2. In these previous methods, the signal intended for the IOE device 222 may be transmitted to one or more of the multiple LUNs 225-1, 225-2, 225-3, 225-4. As further described herein, the signal intended for the IOE device 222 may cause unexpected or unintended changes to the multiple LUNs 225-1, 225-2, 225-3, 225-4. The present disclosure may utilize a signal locking component (e.g., Figure 1 IOE device 222 of the channel switching component 113 referenced in the figure).

[0055] The channel switching component may be configured to receive a first signal including a first header from the host. In some embodiments, the host may provide the first signal to one of the first front-end channel 223-1 or the second front-end channel 223-2 of the IOE device 222. In some embodiments, the first signal may include a first header, which is a VSP header encoded with an instruction from one of the plurality of back-end channels 224-1, 224-2, 224-3, 224-4 to a different one of the plurality of back-end channels 224-1, 224-2, 224-3, 224-4. The channel switching component may be configured to decode the first header to determine an instruction for switching from the first channel to the second channel.

[0056] The channel switching component can be configured to allow a first header to pass through a first channel of the memory device interface to a first memory resource of the non-volatile memory device. As described herein, the first channel can be a first back-end channel of the plurality of back-end channels 224-1, 224-2, 224-3, 224-4. For example, the first channel can be back-end channel 224-1. In this example, the first header can be sent or directed to LUN 225-1.

[0057] The channel switching component may be configured to switch from the first channel to the second channel in response to the first header passing through the first channel. As described herein, the channel switching component may direct the first header through the first channel and then switch the backend channel of the IOE device 222 from the first channel to the second channel. In a specific example, the channel switching component may be configured to allow the first header to pass through the backend channel 224-1 and then switch from the backend channel 224-1 to the backend channel 224-2. In this way, if the first header changes the performance of the LUN 225-1, it will not affect the packets provided to the LUN 225-2 through the backend channel 224-2.

[0058] The channel switching component may be configured to assert the second channel and de-assert the first channel when switching from the first channel to the second channel. In some embodiments, the IOE device 222 may execute instructions or signals to assert the second channel and de-assert the first channel. In this way, the second channel may be activated and the first channel may be deactivated.

[0059] The channel switching component may be configured to receive a plurality of simple content access (SCA) packets from a host. As described herein, a first header may be associated with the plurality of SCA packets. For example, the first header may be followed by a plurality of SCA packets provided to one of the plurality of LUNs 225-1, 225-2, 225-3, 225-4. In a specific example, the first header may be provided to the backend channel 224-1 and the plurality of SCA packets may be provided to the backend channel 224-2 and provided to the LUN 225-2.

[0060] The channel switching component may be configured to allow the plurality of SCA packets to pass through the second channel of the memory device interface to the second memory resource of the non-volatile memory device. As described herein, the plurality of SCA packets may be provided to LUN 225-2 through the back-end channel 224-2. In this manner, the first header is provided to LUN 225-1 and the plurality of SCA packets are provided to LUN 225-2.

[0061] The channel switching component may be configured to receive a second signal including a second header. In some embodiments, the second header may be a second VSP header different from the first header. In some embodiments, the second header may be decoded to determine instructions for switching the backend channel of the IOE device 222. The channel switching component may be configured to allow the second header to pass through the second channel of the memory device interface to the second memory resource of the non-volatile memory device.

[0062] The channel switching component may be configured to switch from the second channel to the first channel in response to the second header passing through the second channel. In some embodiments, the channel switching component may decode the second header to determine that the IOE device 222 is to be switched from the second channel to a different channel. For example, the second header may include an encoded instruction that can be decoded by the channel switching component to switch from the backend channel 224-2 to the backend channel 224-1. In this way, a plurality of packets associated with the second header will be provided to a different backend channel than the second header. In this way, any performance changes caused by the second header can be avoided when providing a plurality of packets associated with the second header to the memory resource.

[0063] Figure 3 A timing diagram 331 illustrating channel switching according to some embodiments of the present disclosure. In some embodiments, the timing diagram 331 may represent how a plurality of front-end signals 332, 333, 334, 335 correspond to a plurality of back-end signals 336, 337, 338, 339, 350. That is, the plurality of front-end signals 332, 333, 334, 335 may be signals received from a host at a plurality of corresponding signal pins of an IOE device. The timing diagram 331 may illustrate how the IOE device transmits the plurality of front-end signals 332, 333, 334, 335 from the host to the plurality of back-end signals 336, 337, 338, 339, 350 provided to a memory resource. In addition, the timing diagram 331 includes a channel selection signal 354.

[0064] In some embodiments, the plurality of front-end signals 332, 333, 334, 335 may include a front-end chip enable signal 332, a front-end (data) command signal 333, a front-end command clock signal 334, and / or a front-end read enable signal 335. In a similar manner, the plurality of back-end signals 336, 337, 338, 339, 350 may include signals corresponding to the plurality of front-end signals 332, 333, 334, 335. For example, the plurality of back-end signals 336, 337, 338, 339, 350 may include a back-end chip enable (A) signal 336, a back-end chip enable (B) signal 337, a back-end command signal 338, a back-end clock signal 339, and / or a back-end read enable signal 350.

[0065] As described herein, the IOE device may receive a header signal 351-1 on the front end command signal 333. The header signal 351-1 may be a VSP header associated with a plurality of data packets 352-1 subsequently received on the front end command signal 333. In these embodiments, the front end clock signal 334 may include the header signal 351-1 and a corresponding clock signal for the plurality of data packets 352-1. As described herein, the header signal 351-1 may be used to cause a switch from a first back end channel (e.g., channel A, etc.) to a second back end channel (e.g., channel B, etc.).

[0066] In some embodiments, the timing diagram 331 may include a backend chip enable (A) signal 336 and a backend chip enable signal (B) 337. In these embodiments, the backend chip enable (A) signal 336 may be used to assert or de-assert a first backend channel, referred to as backend channel (A). In a similar manner, the backend chip enable signal (B) 337 may be used to assert and / or de-assert a second backend channel, referred to as backend channel (B). Although two backend channels are referenced in the timing diagram 331, additional backend channels may be utilized without departing from the present disclosure.

[0067] In some embodiments, the back-end command signal 338 may receive a header 351-2 provided to the front-end command signal 333. In some embodiments, the header 351-2 may be provided to the back-end channel (B). In these embodiments, the back-end chip enable signal (B) 337 may receive a de-assertion signal 353-1 to de-assert the back-end channel (B). In these embodiments, the back-end chip enable signal (A) 336 may receive an assertion signal 353-2 to assert the back-end channel (A). In this manner, the timing diagram 331 illustrates switching from the back-end channel (B) to the back-end channel (A) after receiving the header 351-2.

[0068] In these embodiments, the plurality of packets 352-2 may be received at the backend command signal 338 and provided to the asserted backend channel (A). As described herein, switching the backend channel after receiving the header 351-2 may ensure that the header 351-2 is provided to a different memory resource than the plurality of packets 352-2. In some embodiments, the header 351-2 includes a deassertion signal 353-1 and / or an assertion signal 353-2 that causes a switch from backend channel (B) to backend channel (A). Additionally, the channel select signal 354 may indicate a channel switch 355 or when the backend channel is switched from backend channel (B) to backend channel (A).

[0069] Figure 44 is a flow chart corresponding to a channel switching method 441 according to some embodiments of the present disclosure. The method 441 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 441 is performed by Figure 1 The channel switching component 113 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiment should be understood as only an example, and the illustrated process can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not every embodiment requires all processes. Other process flows are possible.

[0070] At operation 442, method 441 may be performed to receive a signal including a header by a memory device interface. As described herein, the memory device interface may be an IOE device (e.g., Figure 2 222, etc.). For example, the memory device interface may include one or more front-end channels (e.g., input channels, etc.) and multiple back-end channels (e.g., output channels, etc.). In some embodiments, the one or more front-end channels may be coupled to the host device and the multiple back-end channels may be coupled to the corresponding memory resources. In this way, the host device may utilize one of the multiple back-end channels to send a signal to the memory device interface for transmission to a specific memory device.

[0071] At operation 443, method 441 may be performed to decode the header by the memory device interface to determine the instruction. As described herein, the memory device interface may decode the header associated with the signal to determine the instruction. In some embodiments, the header of the communication session may be encoded with instructions that specify a particular back-end channel and / or a particular memory resource associated with the particular back-end channel. In this manner, the header of the communication may be used by the host device to send the instruction to the memory device interface. As described herein, the header may be a VSP header that may be used by the host to encode instructions that may be decoded by the memory device interface.

[0072] At operation 444, method 441 may be performed to select, by the memory device interface, a first channel associated with the first memory resource based on the instruction. As described herein, the memory device interface may utilize the instruction to select a particular channel (e.g., a back-end channel, etc.) for providing signals associated with the communication session. In some embodiments, the first channel selected by the memory device interface is different from a currently selected channel of the memory device interface. In this manner, the selected channel is a channel that forces the memory device interface to switch from a particular back-end channel to a different back-end channel.

[0073] At operation 445, method 441 may be performed to send, by the memory device interface, a header to a second channel associated with a second memory resource. In some embodiments, the second channel is a channel previously selected by the memory device interface. For example, the second channel may be the currently selected channel when the signal is received, such that the header may be directed to the currently selected channel before switching to indicate the channel selected by the header. That is, the second channel is the selected channel of the memory device interface after receiving the signal from the host.

[0074] In some embodiments, method 441 may be performed to send the header to the second channel before switching from the second channel to the first channel. As described herein, the header may be sent to the second channel when the data packet associated with the header is sent to the first channel. In some embodiments, method 441 may be performed to maintain the low power mode by the second memory resource after receiving the header from the second channel. In some embodiments, the second memory resource cannot recognize the header. In these embodiments, the header does not change or affect the power state of the second memory resource. In this way, when the second memory resource is in the low power state, the header does not change the power state to leave the low power state.

[0075] In some embodiments, method 441 may be performed to ignore the header by the second memory resource after receiving the header from the second channel. As described herein, the header may be a VSP header that is ignored by the second memory resource so that the header does not affect or change the state of the second memory resource. Additionally, the second memory resource does not receive the data packet associated with the header because the data packet is provided to the first memory resource associated with the first channel.

[0076] At operation 446, method 441 may be executed to send, by the memory device interface, a subsequent packet of the header to the first channel. In some embodiments, method 441 may be executed to send a subsequent packet of the header to the first channel in response to switching from the second channel to the first channel. As described herein, the subsequent packet may be a data packet, such as, but not limited to, an SCA packet. The subsequent packet of the header may be a data packet associated with the header. In this way, the host device may utilize the header to indicate where the memory device interface is to direct the subsequent packet. In addition, the performance of directing the packet is not affected by the header or instructions associated with the header because the header is provided to the second memory resource and the subsequent packet is provided to the first memory resource.

[0077] Figure 5 is a block diagram of an example computer system 500 in which embodiments of the present disclosure may operate. For example, Figure 5An example machine illustrating a computer system 500 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 500 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110) or can be used to perform operations of the controller (for example, to execute an operating system to execute a corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0078] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0079] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0080] The processing device 502 represents one or more general purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or multiple processors implementing a combination of instruction sets. The processing device 502 may also be one or more special purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. The computer system 500 may further include a network interface device 508 to communicate over a network 520.

[0081] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methodologies or functions described herein. The instructions 526 may also reside completely or at least partially within the main memory 504 and / or the processing device 502 during execution thereof by the computer system 500, the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0082] In one embodiment, the instructions 526 include instructions for implementing a command corresponding to a channel switching component (eg, Figure 1 113 of the channel switching component 113). Although the machine-readable storage medium 524 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more of the methodologies of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0083] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is generally conceived here to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0084] It should be remembered, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve the actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0085] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0086] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with the programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of various of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that various programming languages ​​may be used to implement the teachings of the present disclosure described herein.

[0087] The present disclosure may be provided as a computer program product or software that may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer).

[0088] In some embodiments, machine-readable (e.g., computer-readable) media include machine (e.g., computer) readable storage media, such as read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc. In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It should be understood that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings should be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A method (441) for channel switching of an expander device, comprising: Receiving a signal including a header (351-1, 351-2) by a memory device interface (222); decoding the header (351-1, 351-2) by the memory device interface (222) to determine the instruction; The memory device interface (222) selects a first memory resource (225-1, 225-2, 225-3, 225-4) associated with the first channel (224-1, 224-2, 224-3, 224-4); sending, by the memory device interface (222), the header to a second channel (224-1, 224-2, 224-3, 224-4) associated with a second memory resource (225-1, 225-2, 225-3, 225-4); and Subsequent packets of the header are sent by the memory device interface (222) to the first lane (224-1, 224-2, 224-3, 224-4). 2 . The method of claim 1 , wherein the second channel is a channel previously selected by the memory device interface.

3. The method of claim 1, further comprising sending the header to the second channel before switching from the second channel to the first channel, wherein the second channel is a selected channel of the memory device interface after receiving the signal from a host. 4 . The method of claim 3 , further comprising sending the subsequent packet of the header to the first lane in response to switching from the second lane to the first lane.

5. The method according to claim 1, further comprising: after receiving the header from the second channel, ignoring the header by the second memory resource; and After receiving the header from the second channel, a low power mode is maintained by the second memory resource.

6. An apparatus for channel switching of an expander device, comprising: a plurality of memory dies (225-1, 225-2, 225-3, 225-4); and A memory device interface (222) for transmitting communications between a host (120) that may be coupled to the memory device interface (222) and the plurality of memory dies (225-1, 225-2, 225-3, 225-4), wherein the memory device interface (222) includes a controller (115) configured to: identifying a first header (351-1, 351-2) associated with a first signal received at the memory device interface (222); allowing the first header (351-1, 351-2) to pass through the first channel (224-1, 224-2, 224-3, 224-4) to the first memory resource (225-1, 225-2, 225-3, 225-4); In response to allowing the first header (351-1, 351-2) to pass through the first channel (224-1, 224-2, 224-3, 224-4) and switching from the first channel (224-1, 224-2, 224-3, 224-4) to a second channel (224-1, 224-2, 224-3, 224-4) associated with a second memory resource (225-1, 225-2, 225-3, 225-4); allowing a plurality of packets associated with the first header (351-1, 351-2) to pass through the second channel (224-1, 224-2, 224-3, 224-4) to the second memory resource (225-1, 225-2, 225-3, 225-4); identifying a second header (351-1, 351-2) associated with a second signal; and In response to identifying the second header (351-1, 351-2), the second channel (224-1, 224-2, 224-3, 224-4) switches to the first channel (224-1, 224-2, 224-3, 224-4).

7. The apparatus of claim 6, further comprising the controller configured to allow the second header to pass through the second channel to the second memory resource.

8. The apparatus of claim 6, further comprising the controller configured to decode the first header to determine instructions for switching from the first lane to the second lane.

9. The apparatus of claim 6, wherein the plurality of packets comprise Simple Content Access (SCA) packets.

10. The apparatus of claim 6, wherein the first header is a first vendor specific header and the second header is a second vendor specific header.

11. The apparatus of claim 6, wherein the first header and the second header are received from a host controller and are not discernible by the plurality of memory dies, wherein the first header and the second header are ignored by the plurality of memory dies.

12. A system for channel switching of an expander device, comprising: a memory subsystem (115) comprising a non-volatile memory device (130); and A host (120) may be coupled to the memory subsystem (115) via a memory device interface (222), the memory device interface (222) including a processing device (117), the processing device (117) being configured to: receiving a first signal including a first header (351-1, 351-2) from the host (120); allowing the first header (351-1, 351-2) to pass through a first channel (224-1, 224-2, 224-3, 224-4) of the memory device interface (222) to a first memory resource (225-1, 225-2, 225-3, 225-4) of the non-volatile memory device (130); In response to the first header (351-1, 351-2) passing through the first channel (224-1, 224-2, 224-3, 224-4), the first channel (224-1, 224-2, 224-3, 224-4) is switched from the first channel (224-1, 224-2, 224-3, 224-4) to the second channel (224-1, 224-2、224-3、224-4)； Receiving a plurality of simple content access (SCA) packets (352-1, 352-2) from the host (120); allowing the plurality of SCA packets (352-1, 352-2) to pass through the second channel (224-1, 224-2, 224-3, 224-4) of the memory device interface (222) to a second memory resource (225-1, 225-2, 225-3, 225-4) of the non-volatile memory device (130); receiving a second signal including a second header (351-1, 351-2); allowing the second header (351-1, 351-2) to pass through the second channel (224-1, 224-2, 224-3, 224-4) of the memory device interface (222) to the second memory resource (225-1, 225-2, 225-3, 225-4) of the non-volatile memory device (130); and Switching from the second lane (224-1, 224-2, 224-3, 224-4) to the first lane (224-1, 224-2, 224-3, 224-4) in response to the second header (351-1, 351-2) passing through the second lane (224-1, 224-2, 224-3, 224-4).

13. The system of claim 12, wherein the first channel and the second channel are backend channels of the memory device interface.

14. The system of claim 12, wherein the processing device is further configured to decode the first header to determine instructions for switching from the first lane to the second lane, wherein the instructions identify that the first header is to be provided to the first lane and the plurality of SCA packets are to be provided to the second lane.

15. The system of claim 12, wherein the processing device is further configured to assert the second channel and de-assert the first channel when switching from the first channel to the second channel.

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