Low-power-consumption FLASH architecture based on dual-core system
By adopting an independent FLASH subsystem and multiple power consumption control module design in a dual-core system, the problem that existing FLASH memory is difficult to maintain performance when reducing power consumption is solved, and efficient power consumption management and ability to adapt to complex application scenarios is achieved.
Patent Information
- Application Number
- CN202510109772.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2025-05-23
AI Technical Summary
While reducing power consumption, existing FLASH memories are difficult to maintain memory performance, and the low-power management mechanism is difficult to adapt to complex application scenario needs.
The low-power FLASH architecture based on dual-core systems is adopted, and access and power consumption management of the FLASH subsystem is achieved through independent FLASH subsystem, FLASH controller and flash storage. This architecture includes FLASH access control module, SLEEP control module, dual-core erase low-power control module and LPM system power control module, realizing control and conversion of multiple power consumption modes.
It effectively realizes the power consumption management of the FLASH memory of dual-core system, reduces power consumption, improves energy efficiency and reliability, and adapts to the needs of complex application scenarios.
Smart Images
Figure CN120029545A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a low-power FLASH architecture based on a dual-core system. Background Art
[0002] In today's digital age, digital storage has become an indispensable function of various electronic devices. As a type of non-volatile memory, FLASH memory is widely used in mobile devices such as smartphones, tablets, solid-state drives, etc. due to its high speed, high density and low power consumption. However, with the popularity and enhanced functions of mobile devices, users' demand for battery life is also increasing, which makes the low-power design of FLASH memory particularly important.
[0003] In order to reduce the power consumption of FLASH memory, a common method is to use power gating technology, which controls the power supply of FLASH memory so that it enters a low-power sleep state when not needed, thereby reducing unnecessary energy consumption.
[0004] However, in practical applications, low-power design still faces some challenges: further reducing power consumption while ensuring memory performance; designing a more reasonable low-power management mechanism to adapt to more complex application scenarios. These are two issues that need to be solved urgently. Therefore, how to further reduce the power consumption of FLASH memory and improve its energy efficiency and reliability is a topic worth studying. Summary of the invention
[0005] The object of the present invention is to provide a low-power FLASH architecture based on a dual-core system to solve the problems in the background technology.
[0006] In order to solve the above technical problems, the present invention provides a low-power FLASH architecture based on a dual-core system, comprising:
[0007] Each core system has an independent FLASH subsystem, each FLASH subsystem contains an independent FLASH controller and flash storage, and independently implements access to the FLASH subsystem and power consumption management;
[0008] The low-power FLASH architecture includes a FLASH0 subsystem, a FLASH0 access control module of the FLASH0 subsystem, a FLASH0 SLEEP control module, and a FLASH1 subsystem, a FLASH1 access control module of the FLASH1 subsystem, a FLASH1 SLEEP control module, a dual-core erasable low-power control module, an LPM_0 system power consumption control module, and an LPM_1 system power consumption control module;
[0009] The FLASH0 access control module implements access control to the flash memory 0 and control of its own power consumption mode state; the FLASH0SLEEP control module implements entry and wake-up control of the flash memory 0 sleep mode state; the FLASH1 access control module implements access control to the flash memory 1 and control of its own power consumption mode state; the FLASH1 SLEEP control module implements entry and wake-up control of the flash memory 1 sleep mode state;
[0010] The LPM_0 system power consumption control module and the LPM_1 system power consumption control module realize the switch control of the corresponding FLASH subsystem clocks; the dual-core erase low power consumption control module realizes the control of the dual-core system erase enable.
[0011] In one embodiment, the FLASH0 access control module and the FLASH1 access control module respectively include a FLASH power consumption mode state machine, and each of the FLASH power consumption mode state machines controls three power consumption modes and three working states of the corresponding flash memory; the three power consumption modes are activation mode ACTIVE, sleep mode SLEEP, and standby mode STANDBY; the three working states are programming state PROGRAM, erasure state ERASE, and read state READ.
[0012] In one implementation, the FLASH0 SLEEP control module and the FLASH1 SLEEP control module each include a SLEEP mode state machine, and each of the SLEEP mode state machines controls the conversion and control of the sleep state, wake-up state, and idle state of the corresponding flash memory.
[0013] In one embodiment, the LPM_0 system power consumption control module controls the power consumption mode of the circuit system. When CPU0 initiates a low power consumption mode request, it waits until the FLASH0 subsystem completely enters a sleep state, the clock enable of the clock gating circuit of the LPM_0 system power consumption control module fails, and the FLASH0 subsystem clock is turned off. At this time, the power consumption of FLASH controller 0 and flash memory 0 is the lowest, wherein FLASH controller 0 includes a flash memory 0 access control module and a flash memory 0 SLEEP control module; the LPM_1 system power consumption control module controls the power consumption mode of the circuit system. When CPU1 initiates a low power consumption mode request, it waits until the FLASH1 subsystem completely enters a sleep state, the clock enable of the clock gating circuit of the LPM_1 system power consumption control module fails, and the FLASH1 subsystem clock is turned off. At this time, the power consumption of FLASH controller 1 and flash memory 1 is the lowest, wherein FLASH controller 1 includes a flash memory 1 access control module and a flash memory 1 SLEEP control module.
[0014] In one embodiment, the dual-core erase low power control module includes an erase enable control register for resetting the erase enable shutdown; in the dual-core system activation mode, the FLASH priority control module is shared by the two CPU systems, and the FLASH priority control module controls the programming and erasing functions of the flash memory, so that only one flash memory of the dual-core system is programmed or erased at the same time, and the other flash memory turns off the write / erase pump, thereby reducing the power consumption of the dual-core system.
[0015] The present invention provides a low-power FLASH architecture based on a dual-core system, which achieves control and conversion of multiple power consumption modes of the dual-core system FLASH through the design of the FLASH controller power consumption mode, the control design of the flash memory low power consumption mode, the control of the dual-core erase low power consumption mode and the control of the LPM power consumption mode, and effectively realizes the power consumption management of the dual-core system FLASH memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 A schematic diagram of the dual-core system FLASH low-power architecture provided by the present invention;
[0017] Figure 2 This is a schematic diagram of the FLASH power consumption mode state machine;
[0018] Figure 3 This is a schematic diagram of the SLEEP mode state machine. DETAILED DESCRIPTION
[0019] The following is a further detailed description of a low-power FLASH architecture based on a dual-core system proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0020] The present invention provides a low-power FLASH architecture based on a dual-core system. Through the design of the FLASH controller power consumption mode, the control design of the flash memory low power consumption mode, the control of the dual-core erase low power consumption mode and the control of the LPM power consumption mode, the power consumption management of the dual-core system FLASH is achieved, so that the FLASH supports multiple power consumption modes to adapt to various complex scene application requirements.
[0021] like Figure 1 FIG. 1 is a schematic diagram of a low-power FLASH architecture based on a dual-core system proposed by the present invention.
[0022] Each CPU corresponds to a FLASH subsystem and an LPM system power consumption control module. Figure 1In the example, CPU0 corresponds to the FLASH subsystem flash_sys_0 and LPM_0 system power consumption control module, and CPU1 corresponds to the FLASH subsystem flash_sys_1 and LPM_1 system power consumption control module; and the FLASH architecture also includes a dual-core erase low power consumption control module. Each FLASH subsystem includes a FLASH controller and a flash memory, that is, the FLASH subsystem flash_sys_0 includes a flash memory 0 access control module, a flash memory 0 SLEEP control module, a SLEEP module state machine, a flash memory 0, and a FLASH power consumption mode state machine; the FLASH subsystem flash_sys_1 includes a flash memory 1 access control module, a flash memory 1 SLEEP control module, a SLEEP module state machine, a flash memory 1, and a FLASH power consumption mode state machine.
[0023] The LPM system power consumption control module of each FLASH subsystem controls the power consumption mode of the corresponding FLASH controller (flash memory access control module, flash memory SLEEP control module) and flash memory. The power consumption levels from high to low are active mode, standby mode, and sleep mode.
[0024] Sleep mode: This mode is the default state after the FLASH subsystem is reset. When the CPU initiates a system low-power mode request, the FLASH subsystem completely enters the sleep mode, the FLASH controller and flash memory are in sleep state, and flash_clk (flash0_clk and flash1_clk) are turned off. In this mode, the FLASH subsystem is in the lowest power state. When the CPU has a data read operation on the flash memory, the flash memory will automatically switch from sleep mode to standby state, and then enter the active state.
[0025] Standby mode: This mode consumes more power than the sleep mode, but it takes less time to switch to the active state. In this mode, the FLASH controller and flash memory are in standby state, and flash_clk (flash0_clk and flash1_clk) are not turned off. When the CPU has a data read operation on the flash memory, the flash memory automatically switches from standby mode to active state.
[0026] Active mode: This mode is the mode with the highest power consumption of the FLASH subsystem. In this mode, the FLASH controller and flash memory are both in active state, LPM clock control is enabled, and flash_clk (flash0_clk and flash1_clk) is turned on. The dual-core erase low power control module contains an erase enable control register, which configures the CPU erase enable and turns on the programming / erase enable of the corresponding flash memory. In the dual-core system active mode, the FLASH priority control module is shared by the two CPU systems. The FLASH priority control module controls the programming and erasing functions of the flash memory, so that only one flash memory of the dual-core system can be programmed or erased at the same time, and the other flash memory turns off the write / erase pump, thereby reducing the power consumption of the dual-core system.
[0027] The LPM_0 system power consumption module controls the system clock switch of the FLASH subsystem flash_sys_0. When CPU0 initiates a system low power mode request, the LPM_0 system power consumption module will determine whether Flash 0 has entered the sleep state, that is, whether ef_sleep_0 or ef_sleep_1 is high. If Flash 0 has entered the low power mode, the system turns off the FLASH0 subsystem clock. Otherwise, it indicates that the corresponding FLASH0 subsystem is not ready to enter low power consumption, and the clock cannot be turned off. External GPIO or interrupt will wake up the CPU from the sleep state, and the system clock will be turned on. When the CPU has a data read operation on the flash memory, the flash memory will exit the SLEEP mode and automatically switch the power consumption mode to the active state. Correspondingly, the LPM_1 system power consumption control module controls the clock switch of Flash 1 with the same working principle.
[0028] like Figure 2 As shown, it is a schematic diagram of the FLASH power consumption mode state machine.
[0029] The flash memory access control module contains a FLASH power mode state machine, which controls the three power modes and three working states of FLASH. The three power modes include ACTIVE (active mode), SLEEP (sleep mode), STANDBY (standby mode), and the three working states include PROGRAM (programming state), ERASE (erasing state), and READ (reading state). Figure 2 The working relationship between the state machine power mode states is shown, with programming, erasing, and reading as active working modes.
[0030] The default reset of the state machine is sleep mode. The sleep mode state can jump to standby state, idle state or active state under certain conditions. When the power mode control bit BANKPWR is configured to 2'b10, it can switch from sleep mode to standby mode; when the power mode control bit BANKPWR is configured to 2'b11 or the CPU has data reading or other activation requests, the state machine will jump from sleep mode to active mode. The standby mode and sleep mode are switched by configuring the mode control bit BANKPWR. When the FLASH is in standby mode and the CPU has an activation request, the state machine will spend less time jumping into active mode.
[0031] The active mode of the state machine is the working mode, which includes three working states: PROGRAM, ERASE, and READ. When the FLASH completes the above work, the state machine jumps to the IDLE state. During the transition from active mode to sleep mode, if the FLASH has unfinished work, the CPU will automatically stop and wait until the current operation of the FLASH is completed and jumps to the idle state, and the CPU's sleep request will continue to execute.
[0032] like Figure 3 The figure shows a schematic diagram of the sleep mode state machine. The FLASH can enter the sleep mode only when it is in the IDLE state, not the programming or erasing state. To fully enter the sleep mode, the SLEEP signal of the FLASH flash memory needs to meet certain waiting time requirements, that is, a certain number of waiting cycles must be met before the flash memory can enter the sleep mode.
[0033] When FLASH completely enters sleep mode, an external access request can initiate a wake-up operation on FLASH. At this time, the SLEEP state machine will jump from the SLEEP state to the Wakeup state. After the wake-up wait cycle delay, FLASH jumps to the IDLE state. At this time, FLASH is ready to be accessed at any time.
[0034] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A low-power FLASH architecture based on a dual-core system, characterized in that: Each core system has an independent FLASH subsystem, each FLASH subsystem contains an independent FLASH controller and flash storage, and independently implements access to the FLASH subsystem and power consumption management; The low-power FLASH architecture includes a FLASH0 subsystem, a FLASH0 access control module of the FLASH0 subsystem, a FLASH0 SLEEP control module, and a FLASH1 subsystem, a FLASH1 access control module of the FLASH1 subsystem, a FLASH1 SLEEP control module, a dual-core erasable low-power control module, an LPM_0 system power consumption control module, and an LPM_1 system power consumption control module; The FLASH0 access control module implements access control to the flash memory 0 and control of its own power consumption mode state; the FLASH0SLEEP control module implements entry and wake-up control of the flash memory 0 sleep mode state; the FLASH1 access control module implements access control to the flash memory 1 and control of its own power consumption mode state; the FLASH1 SLEEP control module implements entry and wake-up control of the flash memory 1 sleep mode state; The LPM_0 system power consumption control module and the LPM_1 system power consumption control module realize the switch control of the corresponding FLASH subsystem clocks; the dual-core erase low power consumption control module realizes the control of the dual-core system erase enable.
2. The low-power FLASH architecture based on a dual-core system as claimed in claim 1, characterized in that: The FLASH0 access control module and the FLASH1 access control module respectively include a FLASH power consumption mode state machine, each of which controls three power consumption modes and three working states of the corresponding flash memory; the three power consumption modes are activation mode ACTIVE, sleep mode SLEEP, and standby mode STANDBY; the three working states are programming state PROGRAM, erasing state ERASE, and reading state READ.
3. The low-power FLASH architecture based on a dual-core system as claimed in claim 1, characterized in that: The FLASH0 SLEEP control module and the FLASH1 SLEEP control module each include a SLEEP mode state machine, and each of the SLEEP mode state machines controls the conversion and control of the sleep state, wake-up state, and idle state of the corresponding flash memory.
4. The low-power FLASH architecture based on a dual-core system as claimed in claim 1, characterized in that: The LPM_0 system power consumption control module controls the power consumption mode of the circuit system. When CPU0 initiates a low power consumption mode request, it waits until the FLASH0 subsystem completely enters a sleep state, the clock enable of the clock gating circuit of the LPM_0 system power consumption control module fails, and the FLASH0 subsystem clock is turned off. At this time, the power consumption of FLASH controller 0 and flash memory 0 is the lowest, wherein FLASH controller 0 includes a flash memory 0 access control module and a flash memory 0 SLEEP control module; the LPM_1 system power consumption control module controls the power consumption mode of the circuit system. When CPU1 initiates a low power consumption mode request, it waits until the FLASH1 subsystem completely enters a sleep state, the clock enable of the clock gating circuit of the LPM_1 system power consumption control module fails, and the FLASH1 subsystem clock is turned off. At this time, the power consumption of FLASH controller 1 and flash memory 1 is the lowest, wherein FLASH controller 1 includes a flash memory 1 access control module and a flash memory 1 SLEEP control module.
5. The low-power FLASH architecture based on a dual-core system as claimed in claim 1, characterized in that: The dual-core erase low power control module includes an erase enable control register for resetting the erase enable shutdown; in the dual-core system activation mode, the FLASH priority control module is shared by the two CPU systems, and the FLASH priority control module controls the programming and erasing functions of the flash memory, so that only one flash memory of the dual-core system is programmed or erased at the same time, and the other flash memory turns off the write / erase pump, thereby reducing the power consumption of the dual-core system.