Memory and control method thereof

Abstract

The invention provides a memory and a control method thereof, the memory comprises a storage medium, the storage medium comprises a plurality of data areas, and host data are stored in the data areas; the auxiliary decoding area is filled with preset data, and the preset data and the host data are synchronously written in; the data filling module is connected with the auxiliary decoding area and is used for generating and writing preset data; the voltage switching module comprises a multi-stage adjustable output voltage and is used for triggering a voltage changing rereading operation of the host data when the host data fails to be read; the error analysis module is connected with the auxiliary decoding area and the voltage switching module, and obtains the error bit number of the preset data and the error bit number of the storage page under each read voltage; and the decoding control module is connected with the voltage switching module and the error analysis module, and takes the read voltage corresponding to the minimum storage page error bit number as the intermediate voltage of the soft decoding process when the host data is not read by traversing the read voltage.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory and a control method thereof. Background Art

[0002] With the development of flash memory technology, storage solutions using flash memory as storage media have gradually surpassed mechanical hard disks and become mainstream storage products. Flash memory represents data by the amount of charge in the storage unit. However, with the increase in the number of uses, temperature changes, and frequent reading, the amount of charge in the storage unit will change, resulting in errors in the stored data. Therefore, the use of error correction technology in flash memory devices is inevitable.

[0003] When error correction fails and triggers data rereading, the system usually needs to perform multiple read operations to try to recover the data. This process not only continues to occupy the bandwidth and computing resources of the storage system, but also faces the contradiction between error correction accuracy and processing efficiency. If the error correction efficiency is given priority, it may lead to insufficient error correction capability, and then the storage unit errors that could be repaired will be marked as bad blocks, resulting in a waste of storage resources. If higher error correction accuracy is pursued, the resource overhead will be significantly increased, which will not only reduce the decoding speed, but also may affect the overall performance of the storage system due to resource competition. This lack of balance makes it difficult for the error correction process to meet the requirements of high reliability and high efficiency at the same time. Summary of the invention

[0004] The object of the present invention is to provide a memory and a control method thereof, which can improve both data read capability and data read efficiency and maximize the use of storage resources.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions: The present invention provides a memory, comprising: A storage medium, wherein a plurality of storage pages are provided in the storage medium, and the storage pages include: a plurality of data areas, wherein host data is stored in the data areas; and at least one auxiliary decoding area, wherein the auxiliary decoding area is filled with preset data, and the preset data is written synchronously with the host data; A data filling module, connected to the auxiliary decoding area, and executing generation and writing of the preset data; A voltage switching module, the voltage switching module includes a multi-level adjustable output voltage and is used to trigger a voltage-switching re-reading operation of the host data when the host data reading fails; an error analysis module connected to the auxiliary decoding area and the voltage switching module, and acquiring the number of error bits of the preset data and the number of error bits of the storage page under each read voltage; and The decoding control module is connected to the voltage switching module and the error analysis module, and when the host data is still not read out after traversing the read voltage, the read voltage corresponding to the minimum number of storage page error bits is used as the intermediate voltage of the soft decoding process.

[0006] In one embodiment of the present invention, the storage page further includes a plurality of check areas, in which check codes are stored, and the check codes are synchronously written and read out with the host data, wherein the check codes are redundant data generated by LDPC encoding the host data.

[0007] In one embodiment of the present invention, the storage page is divided into at least one decoded unit, and the decoded unit is the minimum storage unit for obtaining the intermediate voltage, wherein the decoded unit includes the data area, the check area and the auxiliary decoding area, and the number of the data area, the check area and the auxiliary decoding area is equal, wherein in the storage page, multiple auxiliary decoding areas are evenly and discontinuously distributed in the storage page.

[0008] In one embodiment of the present invention, the check area is adjacent to the associated data area, wherein the storage page is a minimum storage unit for obtaining the intermediate voltage, and the auxiliary decoding area is a continuous storage area in the decoded unit.

[0009] In one embodiment of the present invention, the memory stores a check bit capacity table, and the check bit capacity table stores multiple standard capacity data. The memory also includes an initialization module, and the initialization module is triggered when the memory is powered on for the first time. The initialization module selects one of the standard capacity data as the capacity of the check area in the storage page according to the capacity of the storage page and the capacity of the data area, and makes the capacity of the auxiliary decoding area in the storage page greater than zero.

[0010] In one embodiment of the present invention, the data filling module stores at least one preset data format for generating the preset data, and the data filling module includes: a data generating unit, generating at least one set of data according to the preset data format and using the set of data as the preset data; and A data writing unit is connected to the auxiliary decoding area and performs continuous writing of the preset data until the auxiliary decoding area is filled up.

[0011] In one embodiment of the present invention, the error analysis module includes a first calculation unit, which is connected to the auxiliary decoding area, the voltage switching module and the data area, and the first calculation unit is triggered to output when reading the host data, wherein the first calculation unit outputs a first error bit number of the preset data compared to the original data, wherein the original data is backup data of the data generated by the data generation unit, and the original data is stored in a storage area with a fixed and known address in the data area.

[0012] In one embodiment of the present invention, the error analysis module includes a second calculation unit, which is connected to the first calculation unit and outputs a second error bit number of the storage page according to the number of the auxiliary decoding areas in the storage page and the first error bit number.

[0013] In one embodiment of the present invention, the memory also includes an error correction module, and the error correction module is started in the hard decoding process and the soft decoding process, wherein the error correction module is started when risk data appears in the soft decoding process, wherein the risk data is soft data adjacent to a decision threshold in the soft decoding process.

[0014] The present invention provides a memory control method, based on the memory as described above, comprising the following steps: While writing the host data into the data area, generating preset data, and writing the preset data into the auxiliary decoding area; When reading the host data fails, switching the read voltage of the host data and re-reading the host data; While reading out the host data, reading out the preset data, and obtaining the number of error bits of the preset data, and obtaining the number of error bits of the storage page according to the number of error bits of the preset data; and When the read voltage is traversed and the host data is still not read, the read voltage corresponding to the minimum number of storage page error bits is used as the intermediate voltage of the soft decoding process.

[0015] As described above, the present invention provides a memory and a control method thereof, which effectively solves the reliability challenges faced by high-density flash memory through innovative storage architecture and intelligent error correction mechanism. The present invention achieves a balance between error correction accuracy and system performance through the coordinated optimization of the three-zone division structure of the storage page and the dynamic voltage regulation technology, as well as the hierarchical error correction strategy, and provides key technical support for the new generation of high-density storage devices. The memory and control method thereof provided by the present invention not only have high verification efficiency, but also the optimized design of the decoded unit realizes the improvement of error location accuracy, thereby reducing the number of voltage retries by an average of 40% and the bad block misjudgment rate by 60%. This technology uses a hardware-accelerated parallel processing architecture to control the error correction delay within 50μs in the typical working scenario of QLC flash memory, and improves the read and write bandwidth utilization by 35%. Even in the case of decoding failure, the present invention can estimate the number of error bits, thereby accurately judging the degree of wear of the current storage page, which is conducive to subsequent product optimization and problem tracing.

[0016] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0018] Figure 1 The figure is a schematic diagram of a distribution structure of the auxiliary decoding area in one embodiment of the present invention.

[0019] Figure 2 FIG. 4 is a schematic diagram of another distribution structure of the auxiliary decoding area in one embodiment of the present invention.

[0020] Figure 3 Schematic diagram of the structure of a controller in one embodiment of the present invention.

[0021] Figure 4 It is a structural diagram of a data filling module in one embodiment of the present invention.

[0022] Figure 5 FIG. 4 is a schematic diagram of the structure of an error analysis module in an embodiment of the present invention.

[0023] Figure 6 FIG. 4 is a schematic diagram of the structure of a decoding control module in an embodiment of the present invention.

[0024] Figure 7 FIG. 4 is a schematic diagram of the structure of a soft decoding unit in an embodiment of the present invention.

[0025] Figure 8 FIG. 4 is a schematic diagram of the structure of a scrambling code control module in an embodiment of the present invention.

[0026] Fig. 9 FIG. 4 is a flow chart of a method for controlling a memory in an embodiment of the present invention.

[0027] In the figure: D1, host data; 100, storage medium; 110, storage block; 120, storage page; 121, data area; 122, check area; 123, auxiliary decoding area; E, decoded unit; 200, controller; 210, initialization module; 220, timing control module; 230, data filling module; 231, data generation unit; 232, data writing unit; 240, voltage switching module; 250, error analysis module; 251, first calculation unit; 252, second calculation unit; 260, decoding control module; 261, hard decoding unit; 262, soft decoding unit; 2621, left bias module; 2622, right bias module; 2623, reread module; 2624, logic processing module; 270, error correction module; 280, scrambling code control module; 281, scrambling unit; 282, descrambling unit. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] The storage medium 100 of the memory provided by the present invention is a flash memory. Specifically, the memory provided by the present invention can be a NAND flash memory, or an eMMC storage chip, a UFS storage chip, etc. Figure 1 and Figure 3As shown, the host data is user data or system data of the memory, wherein the user data may be data that the host wants to write into the memory. In a storage device using a flash memory as the storage medium 100, the host data has a writing process and a reading process. In the writing process, the host data is first scrambled, and the data sequence is disrupted in a regular manner. The scrambled host data is encoded and a check bit is added. In this embodiment, the encoding method may be an LDPC code. The host data is the information bit of the LDPC code, and a check bit is added to the host data after encoding and processing the host data. The host data and the check bit are written into the storage medium 100 together. In the process of reading out the host data, the host data read out from the storage medium 100 is first decoded, the check bit is parsed, and it is determined whether the read host data is wrong. If there is an error, such as a bit flip, the host data read out is corrected by the check bit. After the host data error correction is successful, the host data is then descrambled by the inverse scrambling process, and the host data is successfully read out after descrambling.

[0030] The memory provided by the present invention, please refer to Figure 1 and Figure 2 As shown, the memory includes a storage medium 100. The storage medium 100 is a NAND flash memory. The storage medium 100 includes a plurality of storage blocks 110. The storage block 110 includes a plurality of storage pages 120. The storage page 120 includes a plurality of data areas 121, a plurality of check areas 122 and at least one auxiliary decoding area 123. The data area 121 is used to store host data. The check area 122 is used to store the check code of the host data. The auxiliary decoding area 123 stores preset data, and the preset data is written synchronously with the host data. The check code is redundant data generated by LDPC encoding the host data, and is specifically a check bit of LDPC encoding. The check code and the host data are written and read synchronously. The data format of the preset data is pre-designed by the designer, for example, the preset data is 0×A5. In the present invention, the check area 122 and the associated data area 121 are adjacently distributed in the storage page 120. The association between the check area 122 and the data area 121 means that the check code in the check area 122 is generated by encoding the host data of the data area 121. In the present invention, the auxiliary coding area is distributed in the storage page 120 in a preset manner. In the present invention, a plurality of decoded units E are set in the memory, and the decoded unit E is the minimum storage unit for obtaining the intermediate voltage. That is, for different decoded units E, the intermediate voltage is re-obtained once. The decoded unit E includes at least one data area 121, at least one check area 122 and at least one auxiliary decoding area 123.

[0031] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, there are multiple auxiliary coding areas, and the auxiliary coding areas are evenly and non-continuously distributed in the storage page 120. In this embodiment, in the decoded unit E, the number of data areas 121, check areas 122 and auxiliary decoding areas 123 is equal. Figure 1 As shown, for example, the decoded unit E includes one data area 121, one check area 122 and one auxiliary decoding area 123. In another embodiment of the present invention, the decoded unit E includes one auxiliary coding area, multiple data areas 121 and multiple check areas 122, and the auxiliary decoding area 123 is a continuous storage area in the decoded unit E. For example, Figure 2 As shown, the decoded unit E is a storage page 120. The decoded unit E includes four data areas 121, four check areas 122 and one auxiliary decoding area 123.

[0032] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the capacity of the data area 121 is a fixed capacity, and the capacity of the data area 121 can be determined during the manufacturing process of the memory. For example, the capacity of the data area 121 is 4KB. In this embodiment, a data area 121 with a fixed and known address is set to store a check bit capacity table. The check bit capacity table stores multiple standard capacity data. For example, the check bit capacity table stores capacity data such as 296byte, 362byte, 390byte, 448byte, 462byte, 484byte, and 530byte. In this embodiment, the capacity of the check area 122 is any capacity data stored in the check bit capacity table. Specifically, when the memory is powered on for the first time, the memory can be initialized, and a capacity data can be selected from the check bit capacity table as the capacity of the check area 122. It should be noted that in the present invention, the capacity of each data area 121 is equal, and the capacity of each check area 122 is set after the first power-on, and the capacity of each check area 122 is not limited to be equal. In this embodiment, the capacity of the check area 122 is set based on the auxiliary decoding area 123 that can form a non-zero storage capacity in the decoded unit E. In the present invention, the capacity of the storage page 120 is formed during the product manufacturing process and is a fixed parameter of the memory. Figure 1 As shown, the capacity of the storage page 120 is 18976 bytes. For example, 4 check areas 122 and 4 data areas 121 are set in the storage page 120. Among them, the capacity of the data area 121 is 4KB, and the capacity of the check area 122 can be selected to be 530 bytes. Therefore, the total capacity of the data area 121 and the check area 122 in the storage page 120 is 18504 bytes. The remaining space in the storage page 120 is 18976 bytes minus 18504 bytes, specifically 472 bytes. For example, Figure 1The layout structure of the auxiliary decoding area 123 shown in FIG. 1 is shown in FIG. 1 , and the storage capacity of each auxiliary decoding area 123 is 118 bytes. Figure 2 The layout structure of the auxiliary decoding area 123 is shown, and the storage capacity of the auxiliary decoding area 123 is 472 bytes. In this embodiment, each storage page 120 is provided with at least one auxiliary decoding area 123, and the capacity of the auxiliary decoding area 123 is greater than zero.

[0033] See also Figures 1 to 3 As shown, in one embodiment of the present invention, the memory further includes a controller 200, and the controller 200 is electrically connected to the storage medium 100. The controller 200 includes an initialization module 210, a timing control module 220, a data filling module 230, a voltage switching module 240, an error analysis module 250, a decoding control module 260, an error correction module 270 and a scrambling control module 280. The initialization module 210 is used to set the capacity of the check area 122 in the decoded unit E, and to obtain the capacity of the auxiliary decoding area 123 in the decoded unit E. The timing control module 220 is used to generate the working clock signal of each module and each unit in the controller 200, and adjust the working timing of each operation in the controller 200. The data filling module 230 is used to write preset data to the auxiliary decoding area 123 in the decoded unit E while writing the host data. The voltage switching module 240 is used to control the read voltage for re-reading the host data. The error analysis module 250 is used to obtain the number of error bits of the preset data, the decoded unit E and even the storage page 120 during error correction decoding. The decoding control module 260 is used to perform hard decoding and soft decoding processes on the host data reading process. The error correction module 270 is used to further correct and analyze the soft data with low reliability in the soft decoding process. The scrambling control module 280 is used to execute and control the scrambling process and descrambling process of the host data.

[0034] See also Figures 1 to 3As shown, in one embodiment of the present invention, the initialization module 210 is triggered when the memory is powered on for the first time. The initialization module 210 selects a standard capacity data from the check bit capacity table as the capacity of the check area 122 in the storage page 120 according to the capacity of the storage page 120 and the capacity of the data area 121, and makes the capacity of the auxiliary decoding area 123 in the storage page 120 greater than zero. In the step of obtaining the storage capacity of the check area 122, the capacity of the check area 122 can be set according to the decoded unit E, or the capacity of the check area 122 can be set according to the storage page 120. For setting the capacity of the check area 122 according to the decoded unit E, for example, 2 decoded units E are set in the storage page 120, and the capacity of the storage page 120 is 18000 bytes, then the total capacity of one decoded unit E is 9000 bytes. Among them, in the same decoded unit E, the capacity of multiple check areas 122 is equal. It should be noted that the capacity of multiple decoded units E in the storage page 120 is equal. The capacity of the check area 122 satisfies that the capacity of the auxiliary decoding area 123 in the decoded unit E is greater than zero. For setting the capacity of the check area 122 in units of storage pages 120, the capacities of multiple check areas 122 are equal, and the capacity of the check area 122 satisfies that the capacity of the auxiliary decoding area 123 in the decoded unit E is greater than zero. It should be noted that if the capacity of the auxiliary decoding area 123 is not an integer, the calculation result can be rounded to make the capacity of any auxiliary decoding area 123 an integer.

[0035] See also Figures 1 to 3As shown, in one embodiment of the present invention, the timing control module 220 outputs timing signals for data filling, reading host data, switching voltage to reread host data, hard decoding process and soft decoding process, scrambling process, etc. Specifically, in the process of writing host data, the scrambling process is first performed on the host data. Then the scrambled host data is encoded to generate a check code. Then the preset data is generated. Then the host data is written into the data area 121, the check code is written into the check area 122, and the preset data is written into the auxiliary decoding area 123. In the process of reading the host data, the host data and the check code are first read out, and it is determined whether the host data conforms to the information recorded by the check code. If it conforms to the information of the check code, the host data is successfully read out. If it does not conform to the information of the check code, the host data reading fails. Then the read host data is corrected. If the number of error bits of the host data exceeds the error correction capability of the error correction module 270, the hard decoding process is started. In the hard decoding process, the read voltage of the host data is switched, and the host data is reread until all the read voltages are traversed or the host data is read out. While switching the read voltage and rereading the host data, the preset data is read out and the number of error bits of the preset data is obtained. Then, the number of error bits of the storage page 120 is obtained according to the number of error bits of the preset data. When the host data is not read out after traversing all the read voltages, the soft decoding process is started. In the soft decoding process, the unreliable soft data is corrected according to the reliability of the soft data in the soft decoding process. When the soft data error correction is successful, the host data is successfully read out. When the soft data error correction fails, the decoding fails, and the current storage page 120 is a bad page. In this embodiment, the timing control module 220 provides a working timing signal for each process and control component of the host data reading and writing.

[0036] See also Figures 1 to 4As shown, in one embodiment of the present invention, the data filling module 230 is connected to the auxiliary decoding area 123, and performs the generation and writing of preset data. In this embodiment, the data filling module 230 stores at least one preset data format for generating preset data. The data sequence in the preset data format is determined. Specifically, the preset data format can be a data sequence of determined content, for example, the preset data format is 0×5A. The preset data format can also be a format requirement for determining the data sorting method, for example, the preset data format satisfies the interval distribution of 0 and 1, the interval distribution of 00 and 11, and so on. In this embodiment, the data filling module 230 includes a data generation unit 231 and a data writing unit 232. The data generation unit 231 generates at least one set of data according to the preset data format and serves as the preset data. The data writing unit 232 is connected to the auxiliary decoding area 123 and performs continuous writing of the preset data until the auxiliary decoding area 123 is filled. It should be noted that in this embodiment, the preset data refers to all the data that fills the auxiliary decoding area 123. The preset data can be composed of a set of data that conforms to the preset data format, or it can be composed of multiple sets of data that conform to the preset data format. Subsequent acquisition of the number of error bits of the preset data refers to acquiring the number of error bits of the data stored in the auxiliary decoding area 123. In this embodiment, after the preset data is generated, while the preset data is filled into the auxiliary decoding area 123, the preset data is also filled into the backup area as the original data backed up for the preset data. The address of the backup area is fixed and known.

[0037] See also Figures 1 to 3 , Figure 6As shown, in one embodiment of the present invention, when the controller 200 receives a read instruction from the host, the host data is read from the corresponding address. When the number of error bits of the host data exceeds the error correction capability of the error correction module 270, the hard decoding process is enabled. In this embodiment, the decoding control module 260 includes a hard decoding unit 261 and a soft decoding unit 262. The hard decoding unit 261 is connected to the voltage switching module 240, and re-reads the host data according to the read voltage output by the voltage switching module 240. The voltage switching module 240 is enabled when an error that cannot be corrected occurs. Specifically, a read voltage table is stored in the data area 121 of the determined address, and a plurality of read voltage data are stored in the read voltage table. In this embodiment, the error correction method of the error correction module 270 can be error correction according to the LDPC code. The voltage switching module 240 selects a read voltage from the re-read voltage table as a new read voltage for the host data, and re-performs the read process of the host data. If the readout is successful, the hard decoding process of the host data is terminated. If the readout fails, the readout voltage is continuously changed and the readout process of the host data is repeated. Each time the host data is read out, the number of error bits of the current storage page 120 or the current decoded unit E is obtained and recorded. Specifically, the number of error bits of the current storage page 120 or the current decoded unit E is obtained respectively when the data is read for the first time and each subsequent change of the readout voltage. In this embodiment, the reading of the host data and the acquisition of the number of error bits can be coordinated by establishing a task queue and timing coordination. The coordination and activation of various tasks can also be achieved by transmitting a signal after completing the task.

[0038] See also Figures 1 to 3 As shown, it should be noted that when the host data is read out for the first time, the read voltage of the data can be the default voltage in the read voltage table, or it can be the most suitable read voltage calculated by the system itself when the memory is in an offline state. Factors that affect whether the read voltage is the most suitable read voltage include temperature and the degree of wear of the storage medium 100. Specifically, the voltage for reading the host data for the first time can be obtained by machine training when the memory is in an offline state, or a comparison table of voltage parameters can be generated by verification testing before leaving the factory to obtain the read voltage that should be used in each temperature range and the degree of wear of the storage medium 100. According to the temperature and the degree of wear of the storage medium 100, the most suitable read voltage for reading the host data for the first time is determined.

[0039] See also Figures 1 to 3 , Figure 5As shown, in one embodiment of the present invention, the error analysis module 250 includes a first calculation unit 251 and a second calculation unit 252. The first calculation unit 251 is connected to the auxiliary decoding area 123, the voltage switching module 240 and the data area 121, and the first calculation unit 251 triggers an output when the host data is read out. Specifically, the first calculation unit 251 outputs a first error bit number of preset data compared to the original data, wherein the original data is backup data of the data generated by the data generation unit 231, and the original data is stored in a storage area with a fixed and known address in the data area 121. The second calculation unit 252 is connected to the first calculation unit 251, and outputs a second error bit number of the storage page 120 based on the number of auxiliary decoding areas 123 in the storage page 120 and the first error bit number. Regarding the distribution uniformity of the auxiliary decoding area 123 in the storage page 120, as shown in FIG. Figure 1 and Figure 2 As shown, for example, 4 decoded units E are set in the storage page 120, and the second number of error bits is the sum of the number of error bits of the multiple decoded units E. According to the first number of error bits and the space occupancy ratio of the auxiliary decoding area 123 in the decoded unit E, the number of error bits of the decoded unit E can be obtained. In some embodiments of the present invention, multiple auxiliary decoding areas 123 can also be set in the decoded unit E. When calculating the number of error bits of the decoded unit E, the sum of the first number of error bits of the multiple auxiliary decoding areas 123 and the space occupancy ratio of the multiple auxiliary decoding areas 123 in the decoded unit E are used for calculation.

[0040] See also Figures 1 to 3 , Figure 5 As shown, it should be noted that in the hard decoding process, when the host data of the decoded unit E is read out, the error analysis module 250 obtains the number of error bits of the decoded unit E. Specifically, when the preset data is filled into the auxiliary decoding area 123, the original data is read out, and the preset data and the original data are compared to obtain the number of error bits of the preset data. Then, according to the number of error bits of the preset data, the number of error bits of the storage page 120 is obtained. In this embodiment, Figure 1 As shown, the storage units in the decoded unit E have the same storage medium 100 and the same storage environment, so the situation of the decoded unit E is simulated according to the situation of the auxiliary decoding area 123. Specifically, for example, the number of error bits in the auxiliary decoding area 123 is 10, then Figure 1 The storage page 120 structure of the decoded unit E is used to obtain the number of error bits of the decoded unit E according to the byte ratio of the auxiliary decoding area 123 in the decoded unit E. For example, if the auxiliary decoding area 123 occupies one tenth of the storage area of ​​the decoded unit E, the number of error bits of the decoded unit E is 100. Figure 1As shown, for example, four decoded units E are set in a storage page 120, and the number of error bits of each decoded unit E is obtained respectively. Finally, the number of error bits of the storage page 120 is the sum of the number of error bits of all decoded units E. In another embodiment of the present invention, Figure 2 In the structure of the storage page 120 shown, one storage page 120 is a decoded unit E, for example, the number of error bits in the auxiliary decoding area 123 is 50. The auxiliary decoding area 123 accounts for, for example, one fifth of the decoded unit E. Then the number of error bits in the decoded unit E is 250. For the first embodiment, the number of error bits of the storage page 120 can be simulated with higher accuracy. For the second embodiment, the number of error bits of the storage page 120 can be simulated with less resource occupancy. After traversing all the read voltages, the number of error bits of the storage page 120 is calculated under each read voltage, where the read voltage corresponding to the minimum number of error bits is the intermediate voltage of the soft decoding process.

[0041] See also Figures 1 to 3 , Figure 6 and Figure 7As shown, in an embodiment of the present invention, the soft decoding unit 262 is connected to the error analysis module 250 and performs the soft decoding process of the memory based on the intermediate voltage. The soft decoding unit 262 includes a left bias module 2621, a right bias module 2622, a rereading module 2623, and a logic processing module 2624. In this embodiment, the left bias module 2621 outputs at least one left bias according to the intermediate voltage, where the left bias is less than the intermediate voltage. The right bias module 2622 outputs at least one right bias according to the intermediate voltage, where the right bias is greater than the intermediate voltage. For example, if the intermediate voltage is 3V, the left bias module 2621 can output a voltage of 0 to 3V, and the right bias module 2622 can output a voltage greater than 3V. The bias amount of the bias module is fixed, and the bias amounts of the left bias module 2621 and the right bias module 2622 are equal. Specifically, the left bias and the right bias can be symmetrically arranged. When the intermediate voltage is 3V, the left bias is 2.7V, 2.4V, and the right bias is 3.3V, 3.6V. The bias amount is fixed at, for example, 0.3V to avoid introducing additional delay due to dynamic adjustment. The rereading module 2623 is connected to the left bias module 2621 and the right bias module 2622, and rereads the host data under the left bias and the right bias respectively, and outputs the left-biased data under the left bias and the right-biased data under the right bias. The logic processing module 2624 is connected to the rereading module 2623, and performs exclusive-OR processing on the left-biased data and the right-biased data to obtain the soft data of the soft decoding process. If the soft data is 1, it means that the bit voltage is sensitive and the data needs to be key corrected. If the soft data is 0, it means that the bit is stable and the data has high credibility. Specifically, if the reread data is read as "1" under the intermediate voltage but read as "0" under the left bias, it indicates that the charge amount of the corresponding storage unit is close to the critical value and the reliability is low. For data with low reliability, the data can be further corrected by LDPC decoding. If the first soft decoding fails, the bias range can be extended or the bias amount can be adjusted to cover a wider voltage drift range. In an embodiment of the present invention, when the minimum number of error bits is greater than the decoding ability of the soft decoding unit 262, the soft decoding process can be directly skipped, a decoding failure is reported, and the corresponding storage page 120 is scrapped.

[0042] Please refer to Figures 1 to 3 As shown, in an embodiment of the present invention, in the hard decoding process and the soft decoding process, the error correction module 270 is started. The error correction module 270 is configured to implement the data decoding function through the low-density parity-check (LDPC) algorithm. In the soft decoding process, the decision threshold is, for example, 1. When the soft data is 1 or a value close to 1, it means that the soft data is at risk and is risk data. At this time, the error correction module 270 can perform targeted error correction on the risk data. In the soft decoding process, if any risk data error correction fails, a decoding failure is reported to the host, and the current host data cannot be read out.

[0043] Please refer to Figures 1 to 3 and Figure 8 As shown, in one embodiment of the present invention, the scrambling control module 280 includes a scrambling unit 281 and a descrambling unit 282. The scrambling unit 281 performs scrambling processing on the data sequence of the host data before the host data is written into the storage medium 100, and specifically before generating a check bit for the host data. After the host data is successfully read out from the storage medium 100, the descrambling unit 282 performs a descrambling processing on the read data that is opposite to the scrambling processing, so that the host can read accurate host data.

[0044] See also Figures 1 to 3 and Fig. 9 As shown, the present invention provides a memory control method, and the control method includes steps S100 to S400.

[0045] S100 , while writing host data into the data area 121 , generating preset data, and writing the preset data into the auxiliary decoding area 123 .

[0046] S200 , when the host data reading fails, switching the host data reading voltage and re-reading the host data.

[0047] S300 , while reading out the host data, read out the preset data and obtain the number of error bits of the preset data, and simultaneously obtain the number of error bits of the storage page 120 according to the number of error bits of the preset data.

[0048] S400 , when the read voltage is traversed and the host data is still not read out, the read voltage corresponding to the minimum number of error bits of the storage page 120 is used as the intermediate voltage of the soft decoding process.

[0049] See also Figures 1 to 3 and Fig. 9As shown, in one embodiment of the present invention, in step S100, preset data is generated according to a preset data structure, and while the preset data is written into the auxiliary decoding area 123, the preset data is written into the backup area. The preset data fills the auxiliary decoding area 123. In step S200, the host data is read out for the first time according to the default voltage or the voltage of offline training. If the host data readout fails, the readout voltage is switched from the readout voltage table, and the host data is reread at the switched readout voltage. In step S300, while reading out the host data, the error analysis module 250 obtains the number of error bits of the current decoded unit E, and then obtains the number of error bits of the current storage page 120. In one embodiment of the present invention, in step S400, after the hard decoding process fails, the soft decoding process is started with the readout voltage corresponding to the minimum number of error bits as the intermediate voltage. When the soft decoding process fails, the memory reports the decoding failure. In another embodiment of the present invention, in step S400, when the hard decoding process fails, the minimum second error bit number is obtained. When the minimum second error bit number exceeds the decoding capability of the soft decoding process, the decoding is terminated and the memory directly reports the decoding failure.

[0050] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A memory, characterized in that: include: A storage medium, wherein a plurality of storage pages are provided in the storage medium, and the storage pages include: a plurality of data areas, wherein host data is stored in the data areas; and at least one auxiliary decoding area, wherein the auxiliary decoding area is filled with preset data, and the preset data is written synchronously with the host data; A data filling module, connected to the auxiliary decoding area, and executing generation and writing of the preset data; A voltage switching module, the voltage switching module includes a multi-level adjustable output voltage and is used to trigger a voltage-switching re-reading operation of the host data when the host data reading fails; an error analysis module connected to the auxiliary decoding area and the voltage switching module, and acquiring the number of error bits of the preset data and the number of error bits of the storage page under each read voltage; and The decoding control module is connected to the voltage switching module and the error analysis module, and when the host data is still not read out after traversing the read voltage, the read voltage corresponding to the minimum number of storage page error bits is used as the intermediate voltage of the soft decoding process.

2. A memory according to claim 1, characterized in that: The storage page further includes a plurality of check areas, in which check codes are stored, and the check codes are synchronously written and read out with the host data, wherein the check codes are redundant data generated by LDPC encoding the host data.

3. A memory according to claim 2, characterized in that: The storage page is divided into at least one decoded unit, which is the minimum storage unit for obtaining the intermediate voltage, wherein the decoded unit includes the data area, the check area and the auxiliary decoding area, and the number of the data area, the check area and the auxiliary decoding area is equal, wherein in the storage page, multiple auxiliary decoding areas are evenly and discontinuously distributed in the storage page.

4. A memory according to claim 3, characterized in that: The check area is adjacent to the associated data area, wherein the storage page is a minimum storage unit for obtaining the intermediate voltage, and the auxiliary decoding area is a continuous storage area in the decoded unit.

5. A memory according to claim 2, characterized in that: The memory stores a check bit capacity table, wherein the check bit capacity table stores a plurality of standard capacity data. The memory further comprises an initialization module, wherein the initialization module is triggered when the memory is powered on for the first time, and the initialization module selects one of the standard capacity data as the capacity of the check area in the storage page according to the capacity of the storage page and the capacity of the data area, and makes the capacity of the auxiliary decoding area in the storage page greater than zero.

6. A memory according to claim 1, characterized in that: The data filling module stores at least one preset data format for generating the preset data, and the data filling module includes: a data generating unit, generating at least one set of data according to the preset data format and using the set of data as the preset data; and A data writing unit is connected to the auxiliary decoding area and performs continuous writing of the preset data until the auxiliary decoding area is filled up.

7. A memory according to claim 6, characterized in that: The error analysis module includes a first calculation unit, which is connected to the auxiliary decoding area, the voltage switching module and the data area, and the first calculation unit is triggered to output when the host data is read out, wherein the first calculation unit outputs a first error bit number of the preset data compared to the original data, wherein the original data is backup data of the data generated by the data generation unit, and the original data is stored in a storage area with a fixed and known address in the data area.

8. A memory according to claim 7, characterized in that: The error analysis module includes a second calculation unit, which is connected to the first calculation unit and outputs a second error bit number of the storage page according to the number of the auxiliary decoding areas in the storage page and the first error bit number.

9. The memory according to claim 1, characterized in that: The memory also includes an error correction module, which is started in the hard decoding process and the soft decoding process, wherein the error correction module is started when risk data appears in the soft decoding process, wherein the risk data is soft data adjacent to a decision threshold in the soft decoding process.

10. A memory control method, based on the memory according to claim 1, characterized in that: The following steps are involved: While writing the host data into the data area, generating preset data, and writing the preset data into the auxiliary decoding area; When reading the host data fails, switching the read voltage of the host data and re-reading the host data; While reading out the host data, reading out the preset data, and obtaining the number of error bits of the preset data, and obtaining the number of error bits of the storage page according to the number of error bits of the preset data; as well as When the read voltage is traversed and the host data is still not read, the read voltage corresponding to the minimum number of storage page error bits is used as the intermediate voltage of the soft decoding process.

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