Task scheduling method and device for heterogeneous multi-core processor

Abstract

The invention discloses a task scheduling method and device for a heterogeneous multi-core processor, and relates to the technical field of resource scheduling. The method is based on a heterogeneous multi-core processor and comprises the steps that 1, a directed acyclic graph (DAG) task model is established and expressed as G = (V, E, P, c), 2, the directed acyclic graph (DAG) task model is converted into a triple time sequence model, 3, all nodes are traversed, the nodes are distributed to a corresponding set Setk according to the type of the processor, blocked segment detection is conducted in each Setk through a triple, and blocked nodes are screened; 4, iterative reconstruction is carried out on the blocking segment of the directed acyclic graph DAG, and task scheduling is carried out through the reconstructed directed acyclic graph DAG; the scheduling efficiency of the heterogeneous multi-core processor is improved, and the task scheduling time is shortened.

Description

Technical Field

[0001] The invention discloses a task scheduling method and device for a heterogeneous multi-core processor, and relates to the technical field of resource scheduling. Background Art

[0002] A heterogeneous multi-core processor is a processor architecture composed of processor cores of different types and computing capabilities. The task scheduling algorithm can be used to coordinate the scheduling order of these processor cores, and the tasks can be reasonably divided and assigned to the corresponding processor cores for execution. The task scheduling algorithm directly determines the execution efficiency of the heterogeneous multi-core processor. Existing scheduling algorithms, such as HEFT and MCP, still have some problems: for example, non-self-sustainability, that is, when the number of cores increases, the worst response time may increase, resulting in insufficient resource utilization; another example is blocking node redundancy, that is, introducing too many blocking nodes, and the response time calculation is too pessimistic. Summary of the invention

[0003] In view of the problems of the prior art, the present invention provides a task scheduling method and device for a heterogeneous multi-core processor, which solves the problems of non-self-sustainability and excessive introduction of blocked nodes in the existing DAG task scheduling algorithm, improves the scheduling efficiency of the heterogeneous multi-core processor, and reduces the time of task scheduling.

[0004] The specific scheme proposed by the present invention is: The present invention provides a task scheduling method for a heterogeneous multi-core processor, based on the heterogeneous multi-core processor, comprising: Step 1: Establish a directed acyclic graph DAG task model, expressed as G=(V,E,P,c): V is the task node set, each node in the task node set v i Represents an atomic computing task, E⊆V×V is an edge set, and each edge in the edge set e ij Indicates the dependencies between tasks. P:V→Π is the mapping function from node to processor type P (v i ), P (v i )definition v i Can only be executed on specified types of processors, c:V→R^+ is the worst response time function c (v i ), c (v i )definition v i the maximum execution time on a processor of a specified type; Step 2: Convert the directed acyclic graph DAG task model into a triple time series model: For each node v i Represented as a triple ( s i ,e i ,d i ), which provides that: s i It's a task v i Earliest start time, s i =max{e j |v j ∈ Predecessor(v i )}, front drive (v i ) indicates a task v i The set of all predecessor tasks of e j It is a precursor task v j The earliest completion time, e i It's a task v i Earliest completion time, e i =s i +c(v i ), indicating the earliest execution time s i Start executing, after c ( v i ) time to complete the task, d i It's a task v i The latest deadline, d i =min{s j |v j ∈ Successor(v i )}, followed by ( v i ) indicates a task v i The set of all successor tasks of s j It is a subsequent task v j The earliest start time, d i Used to ensure that all subsequent tasks start on time. v i existd i Completed before; Step 3: Traverse all nodes and assign them to the corresponding Set according to the processor type k In each Set, use the triple k Perform blocking segment detection and filter out blocking nodes; Step 4: Iteratively reconstruct the blocked segment of the directed acyclic graph DAG, and use the reconstructed directed acyclic graph DAG to schedule tasks.

[0005] Furthermore, in step 2 of the task scheduling method for a heterogeneous multi-core processor, when converting the directed acyclic graph DAG task model into a triple timing model, it is stipulated that: The source node is v 0 , corresponding to s 0 =0,e 0 =d 0 =c(v 0 )=0, The target node is v end , corresponding to d end =e end , Intermediate nodes: They are divided into four categories according to the number of predecessors / successors, namely single-input single-output nodes, multi-input single-output nodes, single-input multi-output nodes, and multi-input multi-output nodes.

[0006] Furthermore, in step 3 of the task scheduling method for heterogeneous multi-core processors, blocking segment detection is performed to screen blocking nodes, including: In each set Set k In the process of blocking segment detection, when the following conditions are met: Some nodes have the same s i , and the number of processors of each type is m k A number smaller than the number of nodes in the part forms a blocking segment; Filtering blocked nodes: Prioritizing buffer window Δ i =d i -e i The largest node, when Δ i If the same, select d i Larger nodes, if d i If they are the same, select the successor node d i A larger node, if the successor node d i If they are the same, they will be selected in descending order of node numbers. Add execution edges to blocking nodes to force blocking nodes to form a serial relationship with non-blocking nodes.

[0007] Furthermore, step 4 of the task scheduling method for a heterogeneous multi-core processor is iteratively reconstructed, including: Path analysis: calculate the length of all complete paths and sort them in descending order, Transformation triples: traverse the nodes to generate ( s i ,e i ,d i ), Δ i Nodes with values ​​> 0 are marked as bufferable nodes. Blocking segment reconstruction loop: When there is a blocking segment Seg kt , select (m k -|Seg kt |) blocked nodes, add execution edges to the earliest completed non-blocking nodes, and recalculate the ( s i ,e i ,d i ), update the node triple.

[0008] The present invention also provides a task scheduling device for a heterogeneous multi-core processor, based on the heterogeneous multi-core processor, comprising a model management module, a conversion module, a blocking detection module and a reconstruction scheduling module. The model management module establishes a directed acyclic graph DAG task model, which is represented by G=(V,E,P,c): V is the task node set, each node in the task node set v i Represents an atomic computing task, E⊆V×V is an edge set, and each edge in the edge set e ij Indicates the dependencies between tasks. P:V→Π is the mapping function from node to processor type P (v i ), P (v i )definition v i Can only be executed on specified types of processors, c:V→R^+ is the worst response time function c (v i ), c (v i )definition v i the maximum execution time on a processor of a specified type; The conversion module converts the directed acyclic graph DAG task model into a triple time series model: For each node v i Represented as a triple ( s i ,e i ,d i ), which provides that: s i It's a task v i Earliest start time, s i =max{e j |v j ∈ Predecessor(v i )}, front drive (v i ) indicates a task v i The set of all predecessor tasks of e j It is a precursor task v j The earliest completion time, e i It's a task v i Earliest completion time, e i =s i +c(v i ), indicating the earliest execution time s i Start executing, after c ( v i ) time to complete the task, d i It's a task v i The latest deadline, d i =min{s j |v j ∈ Successor(v i )}, followed by ( v i ) indicates a task v i The set of all successor tasks of s j It is a subsequent task v j The earliest start time, d i Used to ensure that all subsequent tasks start on time. v i exist d i Completed before; The blocking detection module traverses all nodes and assigns them to the corresponding set Set according to the processor type. k In each Set, use the triple k Perform blocking segment detection and filter out blocking nodes; The reconstruction scheduling module iteratively reconstructs the blocked segments of the directed acyclic graph DAG and uses the reconstructed directed acyclic graph DAG for task scheduling.

[0009] Furthermore, when the conversion module of the task scheduling device of the heterogeneous multi-core processor converts the directed acyclic graph DAG task model into a triple timing model, it is stipulated that: The source node is v 0 , corresponding to s 0 =0,e 0 =d 0 =c(v 0 )=0, The target node is v end , corresponding to d end =e end , Intermediate nodes: They are divided into four categories according to the number of predecessors / successors, namely single-input single-output nodes, multi-input single-output nodes, single-input multi-output nodes, and multi-input multi-output nodes.

[0010] Furthermore, the blocking detection module of the task scheduling device of the heterogeneous multi-core processor performs blocking segment detection and screens blocking nodes, including: In each set Set k In the process of blocking segment detection, when the following conditions are met: Some nodes have the same s i , and the number of processors of each type is m k A number smaller than the number of nodes in the part forms a blocking segment; Filtering blocked nodes: Prioritizing buffer window Δ i =d i -e i The largest node, when Δ i If the same, select d i Larger nodes, if d i If they are the same, select the successor node d i A larger node, if the successor node d i If they are the same, they will be selected in descending order of node numbers. Add execution edges to blocking nodes to force blocking nodes to form a serial relationship with non-blocking nodes.

[0011] Furthermore, the reconfiguration scheduling module of the task scheduling device of the heterogeneous multi-core processor performs iterative reconfiguration, including: Path analysis: calculate the length of all complete paths and sort them in descending order, Transformation triples: traverse the nodes to generate ( s i ,e i ,d i ), Δ i Nodes with values ​​> 0 are marked as bufferable nodes. Blocking segment reconstruction loop: When there is a blocking segment Seg kt , select (m k -|Seg kt |) blocked nodes, add execution edges to the earliest completed non-blocking nodes, and recalculate the ( s i ,e i ,d i ), update the node triple.

[0012] The benefits of the present invention are: (1) Improved accuracy: Compared with the existing DTF algorithm, through comparative experiments, the accuracy of task schedulability judgment is significantly improved after task graph reconstruction; (2) Time optimization: After the number of blocked nodes is reduced, the average task scheduling time is reduced by 15%-20%; the load balancing degree of heterogeneous processors is improved by 25%, and the system throughput is significantly enhanced; (3) Resource utilization: The reconstructed DAG task graph shortens the critical path length and reduces processor idle time. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic flow chart of the method of the present invention. DETAILED DESCRIPTION

[0014] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0015] Usually, a heterogeneous multi-core processor consists of M types of processing cores, denoted as Π={π 1 ,π 2 ,...,π M}, where π k represents the kth type of processor core, and the number of processors in each type is m k = |π k |, for example, when Π={π 1 ,π 2}, π 1 Number of class processors m1 =2,π 2 Class Processor m 2 = 1. Each type of processor has heterogeneous computing capabilities. The computing performance of the same type of processor cores is the same, but the response time of different types of processors to perform the same task varies.

[0016] Embodiment 1: The present invention provides a task scheduling method for a heterogeneous multi-core processor, based on a heterogeneous multi-core processor, comprising: Step 1: Establish a directed acyclic graph DAG task model, expressed as G=(V,E,P,c): V is the set of task nodes, V={ v 1 ,v 2 ,...,v n}, each node in the task node set v i Represents an atomic computing task, that is, an indivisible minimum computing unit. E⊆V×V is an edge set, and each edge in the edge set e ij Represents the dependency relationship between tasks, that is, edge e ij Representation Task v i After completion, you can start v j , P:V→Π is the mapping function from node to processor type P (v i ), P (v i )definition v i Can only be executed on specified types of processors, c:V→R^+ is the worst response time function c (v i ), c (v i )definition v i the maximum execution time on a processor of a specified type; Step 2: Convert the directed acyclic graph DAG task model into a triple time series model: For each node v i Represented as a triple ( s i ,e i ,d i ), which provides that: si It's a task v i Earliest start time, s i =max{e j |v j ∈ Predecessor(v i )}, front drive (v i ) indicates a task v i The set of all predecessor tasks of e j It is a precursor task v j The earliest completion time, e i It's a task v i Earliest completion time, e i =s i +c(v i ), indicating the earliest execution time s i Start executing, after c ( v i ) time to complete the task, d i It's a task v i The latest deadline, d i =min{s j |v j ∈ Successor(v i )}, followed by ( v i ) indicates a task v i The set of all successor tasks of s j It is a subsequent task v j The earliest start time, d i Used to ensure that all subsequent tasks start on time. v i exist d i Completed before.

[0017] It provides: The source node is v 0 , corresponding to s 0 =0,e 0 =d 0 =c(v 0 )=0, that is, the execution time of the source node is 0, The target node is v end , corresponding to d end =e end , Intermediate nodes: They are divided into four categories according to the number of predecessors / successors, namely single-input single-output node SD, multiple-input single-output node MI, single-input multiple-output node MO and multiple-input multiple-output node MIMO.

[0018] Step 3: Traverse all nodes and assign them to the corresponding Set according to the processor type k In each Set, use the triple k Perform blocking segment detection and filter out blocking nodes.

[0019] The blocked section detection and blocked node screening include: In each set Set k In the process of blocking segment detection, when the following conditions are met: Some nodes have the same s i , and the number of processors of each type is m k A number smaller than the number of nodes in the part forms a blocking segment; Filtering blocked nodes: Prioritizing buffer window Δ i =d i -e i The largest node, when Δ i If the same, select d i Larger nodes, if d i If they are the same, select the successor node d i A larger node, if the successor node d i If they are the same, they will be selected in descending order of node numbers. Add execution edges to blocking nodes to force blocking nodes to form a serial relationship with non-blocking nodes.

[0020] Step 4: Iteratively reconstruct the blocked segment of the directed acyclic graph DAG, and use the reconstructed directed acyclic graph DAG to schedule tasks.

[0021] Iterative reconstruction is performed, including: Path analysis: calculate the length of all complete paths and sort them in descending order, Transformation triples: traverse the nodes to generate ( s i ,e i ,d i ), Δ i Nodes with values ​​> 0 are marked as bufferable nodes. Blocking segment reconstruction loop: When there is a blocking segment Seg kt , select (mk -|Seg kt |) blocked nodes, add execution edges to the earliest completed non-blocking nodes, and recalculate the ( s i ,e i ,d i ), update the node triple.

[0022] Analysis of the improvement of scheduling accuracy by the method of the present invention: Define the schedulable decision error rate: η = DWCRT old − WCRT new D is the deadline, when the heterogeneous multi-core processor system meets: ∃ k , ts . t . ⌈ m k ∣ Hello kt ∣⌉< Lcpk ∑ v i ∈ Hello kt c ( v i ) Then the error rate exists: η ≥ D ∑ k =1 M ∑ t =1 Nk Δ blocks ⋅(1−∑ v i ∈ V k c ( v i ) m k Lcpk ) In a typical configuration (M=3,m k =2), the reconstruction process Δblock of the method of the present invention is reduced by about 18.7%, and the corresponding schedulable misjudgment rate is reduced: Δη=D 0.187⋅∑Δ block =10.69% This shows that the present invention eliminates the pessimistic estimation caused by linear superposition in the traditional method by accurately identifying the real blocking segment, so that the accuracy of dispatchable judgment is improved as guaranteed by theory. The consistency between the experimental results and the theoretical derivation verifies the effectiveness of the analysis method.

[0023] Embodiment 2: The present invention also provides a task scheduling device for a heterogeneous multi-core processor, based on a heterogeneous multi-core processor, comprising a model management module, a conversion module, a blocking detection module and a reconstruction scheduling module. The model management module establishes a directed acyclic graph DAG task model, which is represented by G=(V,E,P,c): V is the task node set, each node in the task node set v i Represents an atomic computing task, E⊆V×V is an edge set, and each edge in the edge set e ij Indicates the dependencies between tasks. P:V→Π is the mapping function from node to processor type P (v i ), P (v i )definition v i Can only be executed on specified types of processors, c:V→R^+ is the worst response time function c (v i ), c (v i )definition v i the maximum execution time on a processor of a specified type; The conversion module converts the directed acyclic graph DAG task model into a triple time series model: For each node v i Represented as a triple ( s i ,e i ,d i ), which provides that: s i It's a task v i Earliest start time, s i =max{e j |v j ∈ Predecessor(v i )}, front drive (v i ) indicates a task v i The set of all predecessor tasks ofe j It is a precursor task v j The earliest completion time, e i It's a task v i Earliest completion time, e i =s i +c(v i ), indicating the earliest execution time s i Start executing, after c ( v i ) time to complete the task, d i It's a task v i The latest deadline, d i =min{s j |v j ∈ Successor(v i )}, followed by ( v i ) indicates a task v i The set of all successor tasks of s j It is a subsequent task v j The earliest start time, d i Used to ensure that all subsequent tasks start on time. v i exist d i Completed before; The blocking detection module traverses all nodes and assigns them to the corresponding set Set according to the processor type. k In each Set, use the triple k Perform blocking segment detection and filter out blocking nodes; The reconstruction scheduling module iteratively reconstructs the blocked segments of the directed acyclic graph DAG and uses the reconstructed directed acyclic graph DAG for task scheduling.

[0024] As the information interaction and execution process between the modules in the above-mentioned device are based on the same concept as the embodiment of the method of the present invention, the specific contents can be found in the description of the embodiment of the method of the present invention and will not be repeated here.

[0025] Likewise, the device of the present invention is beneficial in that: (1) Improved accuracy: Compared with the existing DTF algorithm, through comparative experiments, the accuracy of task schedulability judgment is significantly improved after task graph reconstruction; (2) Time optimization: After the number of blocked nodes is reduced, the average task scheduling time is reduced by 15%-20%; the load balancing degree of heterogeneous processors is improved by 25%, and the system throughput is significantly enhanced; (3) Resource utilization: The reconstructed DAG task graph shortens the critical path length and reduces processor idle time.

[0026] It should be noted that not all steps and modules in the above-mentioned processes and device structures are necessary, and some steps or modules can be ignored according to actual needs. The execution order of each step is not fixed and can be adjusted as needed. The system structure described in the above-mentioned embodiments can be a physical structure or a logical structure, that is, some modules may be implemented by the same physical entity, or some modules may be implemented by multiple physical entities, or some components in multiple independent devices may be implemented together.

[0027] The above-described embodiments are only preferred embodiments for fully illustrating the present invention, and the protection scope of the present invention is not limited thereto. Equivalent substitutions or changes made by those skilled in the art based on the present invention are within the protection scope of the present invention. The protection scope of the present invention shall be subject to the claims.

Claims

1. A task scheduling method for a heterogeneous multi-core processor, characterized in that Based on heterogeneous multi-core processors, including: Step 1: Establish a directed acyclic graph DAG task model, expressed as G=(V,E,P,c): V is the task node set, each node in the task node set v i Represents an atomic computing task, E⊆V×V is an edge set, and each edge in the edge set e ij Indicates the dependencies between tasks. P:V→Π is the mapping function from node to processor type P (v i ), P (v i )definition v i Can only be executed on specified types of processors, c:V→R^+ is the worst response time function c (v i ), c (v i )definition v i the maximum execution time on a processor of a specified type; Step 2: Convert the directed acyclic graph DAG task model into a triple time series model: For each node v i Represented as a triple ( s i ,e i ,d i ), which provides that: s i It's a task v i Earliest start time, s i =max{e j |v j ∈ Predecessor(v i )}, front drive (v i ) indicates a task v i The set of all predecessor tasks of e j It is a precursor task v j The earliest completion time, e i It's a task v i Earliest completion time, e i =s i +c(v i ), indicating the earliest execution time s i Start executing, after c ( v i ) time to complete the task, d i It's a task v i The latest deadline, d i =min{s j |v j ∈ Successor(v i )}, followed by ( v i ) indicates a task v i The set of all successor tasks of s j It is a subsequent task v j The earliest start time, d i Used to ensure that all subsequent tasks start on time. v i exist d i Completed before; Step 3: Traverse all nodes and assign them to the corresponding Set according to the processor type k In each Set, use the triple k Perform blocking segment detection and filter out blocking nodes; Step 4: Iteratively reconstruct the blocked segment of the directed acyclic graph DAG, and use the reconstructed directed acyclic graph DAG to schedule tasks.

2. The task scheduling method for a heterogeneous multi-core processor according to claim 1, characterized in that When converting the directed acyclic graph DAG task model to a triplet time series model in step 2, it is stipulated that: The source node is v0, corresponding to s0=0, e0=d0=c(v0)=0, The target node is v end , corresponding to d end =e end , Intermediate nodes: They are divided into four categories according to the number of predecessors / successors, namely single-input single-output nodes, multi-input single-output nodes, single-input multi-output nodes, and multi-input multi-output nodes.

3. The task scheduling method for a heterogeneous multi-core processor according to claim 1 is characterized in that the blocked segment detection and the blocked node screening in step 3 include: In each set Set k In the process of blocking segment detection, when the following conditions are met: Some nodes have the same s i , and the number of processors of each type is m k A number smaller than the number of nodes in the part forms a blocking segment; Filtering blocked nodes: Prioritizing buffer window Δ i =d i -e i The largest node, when Δ i If the same, select d i Larger nodes, if d i If they are the same, select the successor node d i A larger node, if the successor node d i If they are the same, they will be selected in descending order of node numbers. Add execution edges to blocking nodes to force blocking nodes to form a serial relationship with non-blocking nodes.

4. The task scheduling method for a heterogeneous multi-core processor according to claim 1, characterized in that Step 4 performs iterative reconstruction, including: Path analysis: calculate the length of all complete paths and sort them in descending order, Transformation triples: traverse the nodes to generate ( s i ,e i ,d i ), Δ i Nodes with values ​​> 0 are marked as bufferable nodes. Blocking segment reconstruction loop: When there is a blocking segment Seg kt , select (m k -|Seg kt |) blocked nodes, add execution edges to the earliest completed non-blocking nodes, and recalculate the ( s i ,e i ,d i ), update the node triple.

5. A task scheduling device for a heterogeneous multi-core processor, characterized in that Based on heterogeneous multi-core processors, it includes model management module, conversion module, blocking detection module and reconstruction scheduling module. The model management module establishes a directed acyclic graph DAG task model, which is represented by G=(V,E,P,c): V is the task node set, each node in the task node set v i Represents an atomic computing task, E⊆V×V is an edge set, and each edge in the edge set e ij Indicates the dependencies between tasks. P:V→Π is the mapping function from node to processor type P (v i ), P (v i )definition v i Can only be executed on specified types of processors, c:V→R^+ is the worst response time function c (v i ), c (v i )definition v i the maximum execution time on a processor of a specified type; The conversion module converts the directed acyclic graph DAG task model into a triple time series model: For each node v i Represented as a triple ( s i ,e i ,d i ), which provides that: s i It's a task v i Earliest start time, s i =max{e j |v j ∈ Predecessor(v i )}, front drive (v i ) indicates a task v i The set of all predecessor tasks of e j It is a precursor task v j The earliest completion time, e i It's a task v i Earliest completion time, e i =s i +c(v i ), indicating the earliest execution time s i Start executing, after c ( v i ) time to complete the task, d i It's a task v i The latest deadline, d i =min{s j |v j ∈ Successor(v i )}, followed by ( v i ) indicates a task v i The set of all successor tasks of s j It is a subsequent task v j The earliest start time, d i Used to ensure that all subsequent tasks start on time. v i exist d i Completed before; The blocking detection module traverses all nodes and assigns them to the corresponding set Set according to the processor type. k In each Set, use the triple k Perform blocking segment detection and filter out blocking nodes; The reconstruction scheduling module iteratively reconstructs the blocked segments of the directed acyclic graph DAG and uses the reconstructed directed acyclic graph DAG for task scheduling.

6. The task scheduling device for a heterogeneous multi-core processor according to claim 5, characterized in that When the conversion module converts the directed acyclic graph DAG task model into a triple time series model, it stipulates: The source node is v0, corresponding to s0=0, e0=d0=c(v0)=0, The target node is v end , corresponding to d end =e end , Intermediate nodes: They are divided into four categories according to the number of predecessors / successors, namely single-input single-output nodes, multi-input single-output nodes, single-input multi-output nodes, and multi-input multi-output nodes.

7. The task scheduling device for a heterogeneous multi-core processor according to claim 5, characterized in that The blocking detection module detects blocking segments and filters blocking nodes, including: In each set Set k In the process of blocking segment detection, when the following conditions are met: Some nodes have the same s i , and the number of processors of each type is m k A number smaller than the number of nodes in the part forms a blocking segment; Filtering blocked nodes: Prioritizing buffer window Δ i =d i -e i The largest node, when Δ i If the same, select d i Larger nodes, if d i If they are the same, select the successor node d i A larger node, if the successor node d i If they are the same, they will be selected in descending order of node numbers. Add execution edges to blocking nodes to force blocking nodes to form a serial relationship with non-blocking nodes.

8. The task scheduling device for a heterogeneous multi-core processor according to claim 5, characterized in that Refactor the scheduling module for iterative refactoring, including: Path analysis: calculate the length of all complete paths and sort them in descending order, Transformation triples: traverse the nodes to generate ( s i ,e i ,d i ), Δ i Nodes with values ​​> 0 are marked as bufferable nodes. Blocking segment reconstruction loop: When there is a blocking segment Seg kt , select (m k -|Seg kt |) blocked nodes, add execution edges to the earliest completed non-blocking nodes, and recalculate the ( s i ,e i ,d i ), update the node triple.

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