Task Scheduling Method and Device for a Heterogeneous Multi-Core Processor

Abstract

The present invention discloses a task scheduling method and device for a heterogeneous multi-core processor, relating to the technical field of resource scheduling; based on a heterogeneous multi-core processor, including: Step 1: Establish a directed acyclic graph (DAG) task model, denoted as G=(V, E, P, c), Step 2: Convert the directed acyclic graph (DAG) task model into a triple timing model, Step 3: Traverse all nodes, and allocate the nodes to the corresponding set Set according to the processor type k . In the set, use the triple to perform blocking segment detection in each Set k to screen for blocking nodes; Step 4: Iteratively reconstruct the blocking segments of the directed acyclic graph (DAG), and use the reconstructed directed acyclic graph (DAG) for task scheduling; the present invention improves the scheduling efficiency of the heterogeneous multi-core processor and reduces the time of task scheduling.

Description

Technical Field

[0001] The present invention discloses a task scheduling method and device for a heterogeneous multi-core processor, which relates to the technical field of resource scheduling. Background Art

[0002] A heterogeneous multi-core processor is a processor architecture composed of multiple types of processor cores with different computing capabilities. Task scheduling algorithms can be used to coordinate the scheduling order of these processor cores, reasonably divide tasks, and allocate them to the corresponding processor cores for execution. The task scheduling algorithm directly determines the execution efficiency of the heterogeneous multi-core processor. Existing scheduling algorithms, such as HEFT, MCP, etc., still have some problems: for example, non-self-sustainability, that is, when the number of cores increases, the worst-case response time may increase, resulting in insufficient resource utilization; another example is the redundancy of blocking nodes, that is, introducing too many blocking nodes, and the response time calculation is too pessimistic, etc. Summary of the Invention

[0003] Aiming at the problems of the existing technology, the present invention provides a task scheduling method and device for a heterogeneous multi-core processor, which solves the problems of non-self-sustainability and excessive introduction of blocking nodes in the existing DAG task scheduling algorithm, and improves the scheduling efficiency of the heterogeneous multi-core processor and reduces the task scheduling time.

[0004] The specific solution proposed by the present invention is as follows:

[0005] The present invention provides a task scheduling method for a heterogeneous multi-core processor, based on the heterogeneous multi-core processor, including:

[0006] Step 1: Establish a directed acyclic graph (DAG) task model, denoted as G=(V, E, P, c):

[0007] V is a set of task nodes, and each node in the set of task nodes v i represents an atomic computing task,

[0008] E⊆V×V is a set of edges, and each edge in the set of edges e ij represents the dependency relationship between tasks,

[0009] P:V→Π is a mapping function from nodes to processor types P (v i ), P (v i ) is defined as v i can only be executed on a specified type of processor,

[0010] c:V→R^+ is the worst-case response time function c (v i ),c (v i ) defines v i the maximum execution time on a processor of a specified type;

[0011] Step 2: Convert the directed acyclic graph (DAG) task model into a triple timing model:

[0012] Represent each node v i as a triple ( s i ,e i ,d i ), where it is specified that:

[0013] s i is the v i earliest start execution time, s i = max{e j | v j ∈ predecessor(v i ), predecessor(v i ) represents the set of all predecessor tasks of the task v i , e j is the earliest completion time of the predecessor task v j ,

[0014] e i is the v i earliest completion time, e i = s i + c(v i ), indicating that starting from the earliest start execution time s i , after c ( v i ) time, the task is completed,

[0015] d i is the v i latest deadline, d i = min{s j | v j ∈ successor(v i ), successor( v i ) represents the task v iThe set of all successor tasks s j is the successor task v j The earliest start time of d i To ensure that all successor tasks start on time, task v i is completed before d i ;

[0016] Step 3: Traverse all nodes, and allocate the nodes to the corresponding set Set according to the processor type k and use the triple to detect the blocking segments in each Set k to screen out the blocking nodes;

[0017] Step 4: Iteratively reconstruct the blocking segments of the directed acyclic graph DAG, and use the reconstructed directed acyclic graph DAG for task scheduling.

[0018] Furthermore, when converting the directed acyclic graph DAG task model to the triple time series model in step 2 of the task scheduling method for a heterogeneous multi-core processor, it is stipulated that:

[0019] The source node is v0, corresponding to s0 = 0, e0 = d0 = c(v0) = 0,

[0020] The target node is v end , corresponding to d end = e end ,

[0021] Intermediate nodes: Divided into four categories according to the number of predecessors / successors, namely single-input single-output nodes, multi-input single-output nodes, single-input multi-output nodes, and multi-input multi-output nodes.

[0022] Furthermore, in step 3 of the task scheduling method for a heterogeneous multi-core processor, when detecting the blocking segments and screening out the blocking nodes, it includes:

[0023] In each set Set k , detect the blocking segments. When the following conditions are met:

[0024] Some nodes have the same s i , and the number m of each type of processor k is less than the number of the said part of nodes, then a blocking segment is formed;

[0025] Screen out the blocking nodes: Give priority to selecting the node with the largest buffer window Δ i = d i - e i When Δ i is the same, select di Larger nodes, if d i is the same, select the successor node d i Larger nodes, if the successor node d i is the same, finally select in descending order according to the node numbers,

[0026] Add execution edges to the blocking nodes, forcing the blocking nodes and non-blocking nodes to form a serial relationship.

[0027] Furthermore, step 4 of the task scheduling method for the heterogeneous multi-core processor is iteratively reconstructed, including:

[0028] Path analysis: Calculate the lengths of all complete paths and sort them in descending order,

[0029] Convert triples: Traverse the nodes to generate ( s i ,e i ,d i ), mark the nodes with Δ i >0 as bufferable nodes,

[0030] Blocking segment reconstruction loop: When there is a blocking segment Seg kt , select (m k -|Seg kt |) blocking nodes, add execution edges to the earliest completed non-blocking nodes, and recalculate the ( s i ,e i ,d i ) of the blocking nodes, and update the triples of the nodes.

[0031] The present invention also provides a task scheduling device for a heterogeneous multi-core processor, based on the heterogeneous multi-core processor, including a model management module, a conversion module, a blocking detection module, and a reconstruction scheduling module,

[0032] The model management module establishes a directed acyclic graph DAG task model, denoted as G=(V,E,P,c):

[0033] V is the set of task nodes, and each node in the set of task nodes v i represents an atomic computing task,

[0034] E⊆V×V is the set of edges, and each edge in the set of edges e ij represents the dependency relationship between tasks,

[0035] P:V→Π is a mapping function from nodes to processor types P(v i ), P (v i ) defines v i to be executable only on processors of a specified type.

[0036] c: V → R^+ is the worst-case response time function c (v i ), c (v i ) defines v i the maximum execution time on a processor of a specified type;

[0037] The conversion module converts the directed acyclic graph (DAG) task model into a triple timing model:

[0038] Each node v i is represented as a triple ( s i ,e i ,d i ), where it is specified that:

[0039] s i is the earliest start time of task v i s i = max{e j | v j ∈ predecessors(v i ), predecessors(v i ) represents the set of all predecessor tasks of task v i ; e j is the earliest completion time of predecessor task v j ;

[0040] e i is the earliest completion time of task v i e i = s i + c(v i ), indicating that starting from the earliest start time s i and after c ( v i ) time, the task is completed.

[0041] d i is the taskv i The latest deadline, d i = min{s j | v j ∈ succ(v i )}, where succ( v i ) represents the set of all successor tasks of task v i , s j s is the earliest start time of the successor task v j to ensure that all successor tasks start on time. Task d i is completed before v i ; d i The blocking detection module traverses all nodes and assigns the nodes to the corresponding set Set

[0042] according to the processor type, and uses triples to detect blocking segments in each Set k to screen for blocking nodes; k The restructuring scheduling module iteratively restructures the blocking segments of the directed acyclic graph DAG and uses the restructured directed acyclic graph DAG for task scheduling.

[0043] Furthermore, when the conversion module of the task scheduling device for a heterogeneous multi-core processor converts the directed acyclic graph DAG task model into a triple time series model, it is stipulated that:

[0044] The source node is v0, corresponding to s0 = 0, e0 = d0 = c(v0) = 0,

[0045] The target node is v

[0046] , corresponding to d end = e end , end ;

[0047] Intermediate nodes: Divided into four categories according to the number of predecessors / successors, namely single-input single-output nodes, multi-input single-output nodes, single-input multi-output nodes, and multi-input multi-output nodes.

[0048] Furthermore, the blocking detection module of the task scheduling device for a heterogeneous multi-core processor performs blocking segment detection and screens for blocking nodes, including:

[0049] In each set Set k , perform blocking segment detection. When the following conditions are met:

[0050] Some nodes have the same si and the number m of each type of processor k is less than the number of the partial nodes, thus forming a blocking segment;

[0051] Filter blocking nodes: preferentially select the node with the largest buffer window Δ i =d i -e i When Δ i is the same, select the node with a larger d i If d i is the same, select the successor node with a larger d i If the successor node d i is the same, finally select in descending order according to the node number,

[0052] Add an execution edge to the blocking node to force a serial relationship between the blocking node and the non-blocking node.

[0053] Furthermore, the reconstruction scheduling module of the task scheduling device for the heterogeneous multi-core processor performs iterative reconstruction, including:

[0054] Path analysis: calculate the lengths of all complete paths and sort them in descending order,

[0055] Convert triples: traverse the nodes to generate ([[]] s i ,e i ,d i ), mark the nodes with Δ i >0 as bufferable nodes,

[0056] Blocking segment reconstruction loop: when there is a blocking segment Seg kt , select (m k -|Seg kt |) blocking nodes, add execution edges to the earliest completed non-blocking nodes, and recalculate the ([[]] s i ,e i ,d i ) of the blocking nodes, and update the triples of the nodes.

[0057] The advantages of the present invention are:

[0058] (1) Precision improvement: Compared with the existing DTF algorithm, through comparative experiments, the accuracy of task schedulability judgment is significantly improved after task graph reconstruction;

[0059] (2) Time optimization: After the number of blocking nodes is reduced, the average task scheduling time is reduced by 15%-20%; the load balancing degree of the heterogeneous processor is increased by 25%, and the system throughput is significantly enhanced;

[0060] (3) Resource utilization rate: The reconstructed DAG task graph shortens the critical path length and reduces the processor idle time. Description of the Drawings

[0061] Figure 1 It is a schematic flowchart of the method of the present invention. Specific Embodiments

[0062] The present invention will be further described below in conjunction with the drawings and specific embodiments, so that those skilled in the art can better understand the present invention and be able to implement it, but the embodiments cited do not limit the present invention.

[0063] Usually, a heterogeneous multi-core processor is composed of M types of processing cores, denoted as Π = {π1, π2,..., π M}, where π k represents the kth type of processor core, and the number of each type of processor is m k = |π k |. For example, when Π = {π1, π2}, the number of π1 type processors m1 = 2, and the number of π2 type processors m2 = 1. Each type of processor has heterogeneous computing capabilities. The computing performance of the same type of processor core is the same, and there are differences in the response time of different types of processors when executing the same task.

[0064] Embodiment 1: The present invention provides a task scheduling method for a heterogeneous multi-core processor, based on a heterogeneous multi-core processor, including:

[0065] Step 1: Establish a directed acyclic graph DAG task model, denoted as G = (V, E, P, c):

[0066] V is a set of task nodes, V = { v 1 ,v 2 ,...,v n}, and each node in the set of task nodes v i represents an atomic computing task, that is, an indivisible minimum computing unit.

[0067] E ⊆ V × V is a set of edges, and each edge in the set of edges e ij represents the dependency relationship between tasks, that is, the edge e ij represents that task v i can only be started after v j is completed.

[0068] P: V → Π is a mapping function from nodes to processor types P (v i ) P (v i ) is defined v i to be executable only on processors of the specified type

[0069] c: V → R^+ is the worst-case response time function c (v i ) c (v i ) is defined v i as the maximum execution time on a processor of the specified type

[0070] Step 2: Convert the directed acyclic graph (DAG) task model to a triple timing model

[0071] Represent each node v i as a triple( s i ,e i ,d i ) where it is stipulated that

[0072] s i is the earliest start execution time of task v i s i = max{e j | v j ∈ predecessors(v i )}, predecessors(v i ) represents the set of all predecessor tasks of task v i e j is the earliest completion time of the predecessor task v j

[0073] e i v i is the earliest completion time of task v i e i = s i + c(v i ) indicating that starting from the earliest start execution time s i after c ( v i ) time, the task is completed

[0074] d i is the task v i 's latest deadline, d i = min{s j | v j ∈ succ(v i )}, where succ( v i ) represents the set of all successor tasks of task v i , s j is the earliest start time of the successor task v j , which is used to ensure that all successor tasks start on time. Task d i is completed before v i . d i

[0075] It is stipulated that:

[0076] The source node is v0, corresponding to s0 = 0, e0 = d0 = c(v0) = 0, that is, the execution time of the source node is 0,

[0077] The target node is v end , corresponding to d end = e end ,

[0078] Intermediate nodes: Classified into four categories according to the number of predecessors / successors, namely single-input single-output nodes SD, multi-input single-output nodes MI, single-input multi-output nodes MO, and multi-input multi-output nodes MIMO.

[0079] Step 3: Traverse all nodes and allocate the nodes to the corresponding set Set k according to the processor type, and use triples to perform blocked segment detection in each Set k to screen out blocked nodes.

[0080] Among them, performing blocked segment detection and screening out blocked nodes includes:

[0081] In each set Set k , perform blocked segment detection. When the following conditions are met:

[0082] Some nodes have the same s i , and the number m k of each type of processor is less than the number of the said part of nodes, then a blocked segment is formed;

[0083] Screening out blocked nodes: Give priority to selecting the buffer window Δ​i = d i - e i The largest node, when Δ i is the same, select d i The larger node, if d i is the same, select the successor node d i The larger node, if the successor node d i is the same, finally select in descending order according to the node numbers,

[0084] Add execution edges to the blocking nodes to force the blocking nodes and non-blocking nodes to form a serial relationship.

[0085] Step 4: Iteratively reconstruct the blocking segments of the directed acyclic graph DAG, and use the reconstructed directed acyclic graph DAG for task scheduling.

[0086] Among them, the iterative reconstruction includes:

[0087] Path analysis: Calculate the lengths of all complete paths and sort them in descending order,

[0088] Convert triples: Traverse the nodes to generate ( s i ,e i ,d i ), mark the nodes with Δ i > 0 as bufferable nodes,

[0089] Blocking segment reconstruction loop: When there is a blocking segment Seg kt , select (m k - |Seg kt |) blocking nodes, add execution edges to the earliest completed non-blocking nodes, and recalculate the ( s i ,e i ,d i ) of the blocking nodes and update the triples of the nodes.

[0090] Analysis of improving the scheduling accuracy of the method of the present invention:

[0091] Define the schedulable decision error rate:

[0092] η = DWCRT old − WCRT new

[0093] D is the deadline. When the heterogeneous multi-core processor system satisfies:

[0094] ∃k , ts . t . ⌈ m k ∣ Seg kt ∣⌉< Lcpk ∑ v i ∈ Seg kt c ( v i )

[0095] Then the error rate exists:

[0096] η ≥ D ∑ k =1 M ∑ t =1 Nk Δ blockt ⋅(1−∑ v i ∈ V k c ( v i ) m k Lcpk )

[0097] In a typical configuration (M = 3, m k = 2), the reconstruction process Δblock of the method of the present invention is reduced by about 18.7%, and the corresponding reduction in the schedulable misjudgment rate is:

[0098] Δη=D 0.187⋅∑Δ block = 10.69%

[0099] It shows that the present invention eliminates the pessimistic estimation caused by linear superposition in the traditional method by accurately identifying the real blocking segment, so that the accuracy of schedulable determination is theoretically guaranteed to be improved. The consistency between the experimental results and the theoretical derivation verifies the effectiveness of the analysis method.

[0100] Embodiment 2: The present invention also provides a task scheduling device for a heterogeneous multi-core processor. Based on the heterogeneous multi-core processor, it includes a model management module, a conversion module, a blocking detection module, and a reconstruction scheduling module.

[0101] The model management module establishes a directed acyclic graph DAG task model, denoted as G=(V, E, P, c):

[0102] V is a set of task nodes, and each node in the set of task nodes v iRepresents an atomic computing task,

[0103] E ⊆ V × V is the edge set, and each edge in the edge set e ij Represents the dependency relationship between tasks,

[0104] P: V → Π is the mapping function from nodes to processor types P (v i ) P (v i ) is defined v i Can only be executed on processors of the specified type,

[0105] c: V → R^+ is the worst-case response time function c (v i ) c (v i ) is defined v i The maximum execution time on processors of the specified type;

[0106] The conversion module converts the directed acyclic graph (DAG) task model into a triple timing model:

[0107] Each node v i Is represented as a triple( s i ,e i ,d i ), where it is stipulated that:

[0108] s i Is the earliest start execution time of task v i s i = max{e j | v j ∈ predecessor(v i ), predecessor(v i ) represents all predecessor task sets of task v i , e j Is the earliest completion time of the predecessor task v j ,

[0109] e i Is the earliest completion time of task v i e i = s i + c(v i) indicates the earliest start execution time s i starts execution and after c ( v i ) time, the task is completed.

[0110] d i is the latest deadline of the task v i , d i = min{s j | v j ∈ successors(v i )}, successors( v i ) represents the set of all successor tasks of the task v i , s j is the earliest start time of the successor task v j , d i is used to ensure that all successor tasks start on time, and the task v i is completed before d i ;

[0111] The blocking detection module traverses all nodes and allocates the nodes to the corresponding set Set k according to the processor type, and uses the triple to detect the blocking segments in each Set k to screen the blocking nodes;

[0112] The reconstruction scheduling module iteratively reconstructs the blocking segments of the directed acyclic graph DAG and uses the reconstructed directed acyclic graph DAG for task scheduling.

[0113] For the information interaction and execution process among the modules in the above device, since they are based on the same concept as the method embodiment of the present invention, the specific content can be referred to the description in the method embodiment of the present invention and will not be elaborated here.

[0114] Similarly, the advantages of the device of the present invention are:

[0115] (1) Precision improvement: Compared with the existing DTF algorithm, through comparative experiments, the task schedulability judgment precision is significantly improved after the task graph is reconstructed;

[0116] (2) Time optimization: After the blocking nodes are reduced, the average task scheduling time is reduced by 15%-20%; the load balancing degree of heterogeneous processors is increased by 25%, and the system throughput is significantly enhanced;

[0117] (3)Resource utilization rate: The reconstructed DAG task graph shortens the critical path length and reduces the processor idle time.

[0118] It should be noted that not all steps and modules in the above-mentioned processes and device structures are necessary, and some steps or modules can be ignored according to actual needs. The execution order of each step is not fixed and can be adjusted according to needs. The system structure described in the above embodiments can be a physical structure or a logical structure, that is, some modules may be implemented by the same physical entity, or some modules may be implemented by multiple physical entities respectively, or some components in multiple independent devices can be jointly implemented.

[0119] The above-mentioned embodiments are only preferred embodiments given to fully illustrate the present invention, and the protection scope of the present invention is not limited thereto. Equivalent substitutions or transformations made by those skilled in the art on the basis of the present invention are all within the protection scope of the present invention. The protection scope of the present invention shall be subject to the claims.

Claims

1. A task scheduling method for a heterogeneous multi-core processor, characterized in that Based on a heterogeneous multi-core processor, including: Step 1: Establish a directed acyclic graph (DAG) task model, denoted as G=(V, E, P, c): V is a set of task nodes, and each node in the set of task nodes v i represents an atomic computing task E ⊆ V × V is the edge set, and each edge in the edge set e ij represents the dependency relationship between tasks P: V → Π is a mapping function from nodes to processor types P (v i ) P (v i ) is defined v i to be executable only on processors of a specified type c: V → R^+ is the worst-case response time function c (v i ) c (v i ) is defined v i as the maximum execution time on a processor of a specified type; Step 2: Convert the directed acyclic graph (DAG) task model into a triple timing model: Represent each node v i as a triple ( s i ,e i ,d i ), where it is stipulated that: s i is the task v i Earliest start execution time, s i = max{e j | v j ∈ Predecessors(v i )}, Predecessors(v i ) represents the set of all predecessor tasks of the task v i and e j is the earliest completion time of the predecessor task v j ​ e i is the task v i earliest completion time, e i = s i + c(v i ), indicating that starting from the earliest start execution time s i starting to execute, after passing c ( v i ) time, the task is completed d i is the task v i 's latest deadline, d i = min{s j | v j ∈ succ(v i )}, where succ( v i ) represents the set of all successor tasks of task v i ; s j is the earliest start time of the successor task v j ; to ensure that all successor tasks start on time, task d i must be completed before v i ; d i ; Step 3: Traverse all nodes and allocate the nodes to the corresponding set Set according to the processor type k In, use triples in each Set k to perform blocked segment detection and screen blocked nodes; Step 4: Iteratively reconstruct the blocked segments of the directed acyclic graph (DAG), and use the reconstructed DAG for task scheduling.

2. The task scheduling method of a heterogeneous multi-core processor according to claim 1, characterized in that When converting the DAG task model into a triple timing model in Step 2, it is stipulated that: The source node is v0, corresponding to s0 = 0, e0 = d0 = c(v0) = 0, The target node is v end , corresponding to d end = e end , Intermediate nodes: Classified into four categories according to the number of predecessors / successors, namely single-input single-output nodes, multi-input single-output nodes, single-input multi-output nodes, and multi-input multi-output nodes.

3. A task scheduling method for a heterogeneous multi-core processor according to claim 1, characterized in that in Step 3, blocked segment detection is performed to screen blocked nodes, including: In each set Set k a blocked segment detection is performed, when the following conditions are met: Some nodes are the same s i , and when the number m of each type of processor k is less than the number of the said partial nodes, a blocking segment is formed; Screen blocked nodes: preferentially select buffer window Δ i =d i -e i The largest node, when Δ i is the same, select d i The larger node, if d i is the same, select successor node d i The larger node, if the successor node d i is the same, finally select in descending order of node numbers Add execution edges to the blocked nodes to force the blocked nodes and non-blocked nodes to form a serial relationship.

4. The task scheduling method of a heterogeneous multi-core processor according to claim 1, characterized in that Step 4 performs iterative reconstruction, including: Path analysis: Calculate the lengths of all complete paths and sort them in descending order. Convert triples: Traverse nodes to generate ( s i ,e i ,d i ), and mark the nodes with Δ i > 0 as bufferable nodes. Blocking segment reconstruction loop: When there is a blocking segment Seg kt , select (m k - |Seg kt |) blocking nodes, add execution edges to the earliest completed non-blocking nodes, and recalculate the ([[]] s i ,e i ,d i ) of the blocking nodes, and update the triple of the nodes.

5. A task scheduling device for a heterogeneous multi-core processor, characterized in that Based on a heterogeneous multi-core processor, including a model management module, a conversion module, a blocked detection module, and a reconstruction scheduling module, The model management module establishes a DAG task model, denoted as G=(V, E, P, c): V is a set of task nodes, and each node in the set of task nodes v i represents an atomic computing task E ⊆ V × V is the edge set, and each edge in the edge set e ij represents the dependency relationship between tasks P: V → Π is a mapping function from nodes to processor types P (v i ) P (v i ) is defined v i to be executable only on processors of a specified type c: V → R⁺ is the worst-case response time function c (v i ), c (v i ) defines v i the maximum execution time on a processor of a specified type; The conversion module converts the DAG task model into a triple timing model: Represent each node v i as a triple ( s i ,e i ,d i ), where it is stipulated that: s i is the task v i Earliest start execution time, s i = max{e j | v j ∈ Predecessors(v i ))}, Predecessors(v i ) represents the set of all predecessor tasks of the task v i e j is the predecessor task v j Earliest completion time of​ e i is the task v i earliest completion time, e i = s i + c(v i ), indicating that starting from the earliest start execution time s i start to execute, after passing through c ( v i ) time, the task is completed d i is the task v i 's latest deadline, d i = min{s j | v j ∈ succ(v i )}, where succ( v i ) represents the set of all successor tasks of task v i ; s j is the earliest start time of successor task v j ; to ensure that all successor tasks start on time, task d i must be completed before v i ; d i ; The blocking detection module traverses all nodes and allocates the nodes to the corresponding set Set according to the processor type k . In it, use triples in each Set k to perform blocking segment detection and screen blocking nodes; The reconstruction scheduling module iteratively reconstructs the blocked segments of the DAG and uses the reconstructed DAG for task scheduling.

6. The task scheduling device for a heterogeneous multi-core processor according to claim 5, characterized in that When the conversion module converts the DAG task model into a triple timing model, it is stipulated that: The source node is v0, corresponding to s0 = 0, e0 = d0 = c(v0) = 0, The target node is v end , corresponding to d end = e end , Intermediate nodes: Classified into four categories according to the number of predecessors / successors, namely single-input single-output nodes, multi-input single-output nodes, single-input multi-output nodes, and multi-input multi-output nodes.

7. The task scheduling device of a heterogeneous multi-core processor according to claim 5, characterized in that The blocked detection module performs blocked segment detection to screen blocked nodes, including: In each set Set k a blocked segment detection is performed, when the following conditions are met: Some nodes are the same s i , and when the number m of each type of processor k is less than the number of said partial nodes, a blocking segment is formed; Screen blocked nodes: preferentially select the buffer window Δ i =d i -e i The largest node, when Δ i is the same, select d i The larger node, if d i is the same, select the successor node d i The larger node, if the successor node d i is the same, finally select in descending order of node numbers Add execution edges to the blocked nodes to force the blocked nodes and non-blocked nodes to form a serial relationship.

8. The task scheduling device of a heterogeneous multi-core processor according to claim 5, characterized in that The reconstruction scheduling module performs iterative reconstruction, including: Path analysis: Calculate the lengths of all complete paths and sort them in descending order. Convert triples: Traverse nodes to generate ( s i ,e i ,d i ), and mark the nodes with Δ i > 0 as bufferable nodes. Blocking segment reconstruction loop: When there is a blocking segment Seg kt , select (m k - |Seg kt |) blocking nodes, add execution edges to the earliest completed non-blocking nodes, and recalculate the ([[]] s i ,e i ,d i ) of the blocking nodes, and update the triples of the nodes.

Images