Method, apparatus, and system for serial bus transactions with selectable data transaction sizes

Abstract

A method may include receiving, at a serial input / output (IO) of a memory device, at least a command value, an address value, and metadata in synchronization with a serial clock, the metadata including an encoded length value. From at least the command value, the address value, and the encoded length value, a memory access operation, a memory array location, and one data length value (LEN) of a plurality of different data length values (LENs) corresponding to the memory access operation may be determined. During performing a memory access operation, at the serial IO, data having at least a length corresponding to one of the plurality of different LENs may be transferred in synchronization with the serial clock. Corresponding devices and systems are also disclosed.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Patent Application No. 63 / 602,186, filed on November 22, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates generally to authentication of memory device transactions, and more particularly to enabling memory device transactions with selectable extended data sizes, where the extended data is in addition to read data, write data, program data, or erase data. Background Art

[0004] Currently, many electronic platforms that use memory storage devices are concerned about the security of data access operations. Many specifications, including some automotive specifications, require authentication of code and data stored in memory devices before execution.

[0005] Traditionally, systems may employ "shadow" memory to improve security. In this arrangement, the code to be executed may be transferred from non-volatile memory (NVM) to volatile memory. A host (e.g., the device that will execute the code) may authenticate the code that has been transferred to volatile memory. The shadow memory approach is incompatible with execute-in-place (XiP) designs, where code is advantageously executed directly from NVM, as only code residing on volatile memory is authenticated.

[0006] In a conventional Serial Peripheral Interface Bus (SPI) transaction, the number of bytes transferred can be determined by the host deasserting the chip select signal (CS). Alternatively, such a transaction (e.g., a read operation) operates on a fixed data length (e.g., the amount of data read). Some conventional memory devices may include a configuration register by which a "wrap length" may be used to specify a fixed transaction length outside of the SPI protocol.

[0007] It would be desirable to have a protocol that specifies the size of a data transfer before it begins. This would allow for efficient implementation of security features such as authentication tags. Summary of the invention

[0008] A method may include receiving at least a command value, an address value, and metadata at a serial input / output (IO) of a memory device synchronously with a serial clock, the metadata including an encoded length value. Based on at least the command value, the address value, and the encoded length value, a memory access operation, a memory array location, and one of a plurality of different data length values ​​(LEN) corresponding to the memory access operation may be determined. During execution of the memory access operation, at the serial IO, data having at least a length corresponding to one of the plurality of different LENs may be transmitted synchronously with the serial clock. Corresponding devices and systems are also disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram of a memory device according to an embodiment.

[0010] Figure 2-0 and Figure 2-1 is a timing diagram of memory device transactions shown according to an embodiment.

[0011] Figure 3 is a block diagram of a system according to an embodiment.

[0012] Figure 4-0 , Figure 4-1 and Figure 4-2 is a state diagram illustrating a decoder device and operation according to an embodiment.

[0013] Figure 5-0 , Figure 5-1 and Figure 5-2 is a diagram illustrating memory device transactions according to an embodiment. Figure 5-3 is a table of memory device commands shown according to an embodiment. Figure 5-4 is a table showing encoded data length (LEN) values ​​according to an embodiment.

[0014] Figure 6-0 , Figure 6-1 and Figure 6-2 is a diagram of memory device transactions shown according to additional embodiments. Figure 6-3 is a table of address values ​​and encoded LEN values ​​shown according to an embodiment.

[0015] Figure 7-0 , Figure 7-1 and Figure 7-2 is a diagram illustrating a memory device transaction according to another embodiment. Figure 7-3 is a table of encoded LEN values ​​shown according to another embodiment.

[0016] Figure 8 is a flow chart of a method according to an embodiment.

[0017] Fig. 9is a flow chart showing the operation of a memory device according to an embodiment.

[0018] Fig.10 is a flow chart showing the operation of a memory device according to another embodiment.

[0019] Fig.11 is a diagram illustrating the operation of a memory device according to another embodiment.

[0020] Fig.12 is a flow chart showing the operation of a memory controller according to an embodiment.

[0021] Fig.13 is a flow chart showing an extended data operation of a memory controller according to another embodiment.

[0022] Fig.14 is a diagram showing the operation of a memory controller according to another embodiment.

[0023] Fig.15 is a table showing commands that may be received at a memory device serial interface, according to an embodiment.

[0024] Figure 16-0 and Figure 16-1 is a diagram of a memory array that may be included in an embodiment.

[0025] Fig.17 is a diagram of an integrated circuit (IC) device according to an embodiment.

[0026] Figure 18-0 and Figure 18-1 is a diagram of a memory controller shown according to an embodiment.

[0027] Fig.19 is a diagram illustrating system address spaces that may be included in an embodiment.

[0028] Fig. 20 is a flow chart of system operation according to an embodiment.

[0029] Fig.21 is a block diagram of a vehicle system according to an embodiment.

[0030] Fig. 22 is a diagram of a vehicle system according to an embodiment. DETAILED DESCRIPTION

[0031] According to an embodiment, a memory device may receive an encoded data length (LEN) value having a command value and an address value received in a transaction. The encoded LEN value may indicate one of the many possible lengths of the data included in the transaction. In a read operation, the LEN value may indicate the size of the corresponding read data. In a write operation or a programming operation, the LEN value may indicate the size of the corresponding write data or programming data. In this way, the amount of data transmitted in a memory device transaction may be controlled by the bit value transmitted together with the command value and the address value. The LEN value may correspond to the number of serial clock cycles required to transmit the data, and therefore may vary according to the serial bus size.

[0032] In some embodiments, a memory device transaction may include additional data beyond the LEN value, such as "tag" data used to authenticate the transaction.

[0033] In some embodiments, in addition to the data length, the LEN value may also include metadata for the transaction. Such metadata may include, but is not limited to, encryption of the indicated data or included authentication data.

[0034] According to an embodiment, in a read transaction, the memory device can provide any one of a plurality of possible read data sizes determined by the LEN value received with the command data and the address data. Similarly, in a write or programming operation, the memory device can determine the amount of data being received based on the LEN value received with the command data and the address data.

[0035] In some embodiments, the encoded LEN value may be received after the command value and the address value.

[0036] In some embodiments, the LEN value may be received with the command value, and then the address value.

[0037] In some embodiments, a LEN value may be received along with an address value following the command value.

[0038] In some embodiments, the LEN value may include additional metadata that may indicate characteristics of the corresponding transaction.

[0039] In some embodiments, transactions with selectable data length values ​​may occur between a non-volatile memory device and a host device. The host device may read and execute code directly from the non-volatile memory device using a command address (CMD / ADD) sequence including an encoded LEN value (i.e., an execute-in-place (XiP) operation).

[0040] Figure 11 is a block diagram of a memory device 100 according to an embodiment. The memory device 100 may include a memory array 102, an input / output (IO) circuit 104, a control logic 106, an array decoder circuit 108-0 / 108-1, a programming and erasing circuit 110, a data latch 112, and a data path 114. The memory array 102 may include any suitable type of memory cells, including non-volatile memory cells, volatile memory cells, and combinations thereof. The IO circuit 104 may be connected to a serial bus 118, which may carry a control signal CS#, a serial clock SCK, and one or more serial inputs and / or outputs SIO0 to SIOn. It will be appreciated that a command value and an address value sequence may be received as serial data on a serial IO (e.g., SIO0) in synchronization with SCK. In addition, an encoded LEN value may be received as part of a command address sequence.

[0041] The control logic 106 may receive a command value, an address value, and a LEN value received at the IO circuit 104. In response to these values, the control logic 106 may generate a control signal 116 that may control access to the memory array 102. Unlike conventional memory devices, the control logic 106 may include a LEN decoding circuit 106-0 that may generate a LEN value to determine the size (e.g., length) of the data that is the object of the memory access transaction. It will be appreciated that the LEN decoding circuit 106-0 may determine one of a plurality of possible different LEN values ​​from the received command / address (CMD / ADD) sequence. This is in contrast to conventional devices, which may require programming of configuration registers to establish a data length size for transactions that exceed a default or initially configured size.

[0042] The array decoder may include an X decoder 108-0 and a Y decoder 108-1. The X decoder 108-0 may select a row of memory cells, and in some embodiments, may select a higher organization (e.g., a block) of memory cells. The Y decoder 108-1 may select a column of memory cells. In some embodiments, the data may be stored with corresponding extended data within the memory array 102. Thus, in response to the decoded LEN value, the decoder circuits (108-0 and / or 108-1) may access the appropriate number of memory locations at the address provided in the CMD / ADD sequence. In addition, as described herein, the LEN value may include metadata related to the operation.

[0043] In the illustrated embodiment, the memory device 100 may include programming and erasing circuitry 110 for programming and erasing data in non-volatile memory cells within the memory array 102. In some embodiments, such data programming may vary depending on the LEN value. In some embodiments, metadata in the LEN value may also control characteristics of the erase operation. In some embodiments, the control logic 106 may process authenticated transactions. In this case, additional data (referred to herein as "tag" data) may be received after data having a length indicated by the LEN value is transmitted. The tag data may authenticate the data of the transaction and / or the transaction itself (e.g., authenticate command / address data). Although Figure 1 Program and erase circuits 110 are shown as being compatible with nonvolatile memory cells, but alternative embodiments may include volatile memory cells, in which case program / erase circuits 110 may be (or include) write circuits (e.g., write amplifiers, refresh circuits, etc.) appropriate for the memory cell type.

[0044] The data latch 112 circuit may latch data for programming / writing the memory array 102. The data path 114 may transfer data between the control logic 108 and the data latch 112 and / or the memory array 102.

[0045] In this manner, the memory device can decode the values ​​received in the command address sequence on the serial input to determine the variable data length size. The operation of transmitting and / or receiving data can be adjusted to meet the data length size.

[0046] Figure 2-0 and Figure 2-1 2 is a timing diagram illustrating a memory device transaction 225 - 0 and a memory device transaction 225 - 1 according to an embodiment. The memory device transactions 225 - 0 / 225 - 1 may occur over the serial bus 218 . Figure 2-0 and Figure 2-1 The waveforms of the serial clock signal SCK and the serial IO (SIO) are shown. The SIO can be a single IO or a combination of SIOs including multiple other IOs for receiving / sending transaction data (e.g., quad SPI (QSPI), octal SPI (OSPI)). In addition, in some embodiments, the SIO can be divided into one or more serial inputs dedicated to receiving serial data, and one or more serial outputs dedicated to sending serial data.

[0047] Figure 2-0 A transaction is shown in which the CMD / ADD sequence includes a LEN value. Figure 2-1 Another transaction is shown in which the CMD / ADD sequence includes another different LEN value.

[0048] refer to Figure 2-0 , at time t0, the device may begin receiving a command / address sequence 220-0. The CMD / ADD sequence 220 may include command data (C), address data (A), and data indicating that the LEN value is n+1, which is different from a conventional transaction. In some embodiments, such a value may be an encoded LEN value. The LEN data may be included separately in the command data and the address data (shown as 221), or may be included in the command data, in the address data, or in a combination thereof.

[0049] Command data may be received (e.g., latched) at both the rising and falling edges of SCK. In some embodiments, the command data received at both the rising and falling edges may be the same data (i.e., a repeated command). However, in other embodiments, command data may be received at the rising edge, and command data received at the falling edge may include LEN data. Figure 2-0 Command data is shown as being received within a single cycle of SCK, but in other embodiments, command data may be received within more cycles, and such command data may include LEN data.

[0050] At time t1, after the command data, address data may be received at the rising and falling edges of SCK. In some embodiments, the address data may include LEN data. In some embodiments, the LEN data may occupy the least significant address bit. In some embodiments, LEN (and possibly other data) may be received in extended command data 221 that may follow the command data and address data.

[0051] At time t2, transaction data having a length LEN 220-0 may be sent or received according to transaction 225-0. In the illustrated embodiment, the LEN value indicates n+1. Thus, the length of transaction data 220-0 may be n+1. Such data may be sent after a CMD / ADD sequence (e.g., a read operation) or may be received using a CMD / ADD sequence (e.g., a write / program operation).

[0052] Reference now Figure 2-1 ,and Figure 2-0 As in the case of , at time t0, the device may begin receiving command / address sequence 220-1. However, such CMD / ADD sequence 220 may include a different LEN value m+1. Therefore, the corresponding transaction data 220-1 may have a length of m+1.

[0053] Figure 2-1Also shown is extended data 223 that may be included in some transactions. Extended data 223 may be received after transaction data of length m+1. Extended data 223 may represent any suitable data in addition to transaction data, including but not limited to authentication data, error detection data (e.g., CRC), and / or error correction data (ECC code).

[0054] It is worth noting that, according to the embodiment, Figure 2-0 and Figure 2-1 The command data and address data of the two transactions 225-0 / 225-1 can be the same, but the difference in LEN values ​​will cause the size of the data transferred in the transaction to change.

[0055] In this manner, a memory device transaction may include a selectable data length value in a CMD / ADD sequence, and the transaction data may be transferred in a number of clock cycles corresponding to the selected data length.

[0056] Figure 3 3 is a block diagram of a system 330 according to an embodiment. The system 330 may include a memory device 300 and a memory controller 340 communicating via a serial bus 318. In some embodiments, the memory device 300 may be Figure 1 An implementation shown in .

[0057] The memory device 300 may include one or more memory cell arrays 302, IO circuits 304, CMD / ADD decoder circuits 306-0, access control circuits 306-1, data output circuits 324-0, data input circuits 324-1, and optional extended data operation circuits 306-2. The memory cell array 302 may include one or more memory cell arrays as described herein or equivalent. The IO circuits 304 may be connected to the serial bus 318 and receive control signals 342-0 and receive command values, address values, and LEN values, as well as receive or send data values ​​through one or more SIOs.

[0058] In the illustrated embodiment, the CMD / ADD decoder circuit 306-0 can receive command data and address data, as well as encoded LEN data 334-0. Based on these data, the CMD / ADD decoder circuit 306-0 can determine the type of transaction, the address corresponding to the transaction, and the LEN value of the transaction. These values ​​can be provided to the access control circuit 306-1. The access control circuit 306-1 can control access to the memory cell array 302 based on the determined transaction type and LEN size. The access control circuit 306-1 may include an extended transaction control circuit 332 to handle extended data included in the transaction. For example, the extended control circuit 332 can operate on data received after the data of length LEN (i.e., after the transaction data), which will be understood as extended data rather than transaction data.

[0059] The optional extended data operation circuit 306-2 can perform the extended data operation indicated by the CMD / ADD sequence. The extended data operation may include any appropriate operation that utilizes the extended data and the command, address and / or other data associated with the transaction. In some embodiments, the extended operation may include, but is not limited to, authentication, error detection or error correction. The authentication operation may include any of the following: an authenticated read operation, an authenticated write operation or a programming operation, and an authenticated erase operation. In an authenticated read operation, the extended data may be used to authenticate the read data transmitted with the extended data. In an authenticated programming or write operation, the extended data may be sent together with the CMD / ADD sequence and used to authenticate the programming / writing data and / or the CMD / ADD data. In addition or alternatively, the authenticated programming operation or the write operation may write the extended data to the memory device together with the corresponding write / programming data. When the programmed / written data is read out as read data, this extended data may be output together with the read data. In a verified erase operation, the extended data may be transmitted using the CMD / ADD sequence, and the CMD / ADD data may be authenticated using the data. The error detection operation may use the extended data to detect errors in data (eg, write data or program data) using the extended data received along with such data.

[0060] In the illustrated embodiment, the extended operation circuit 306-2 may include an extended function circuit 328-0 and an extended value generation circuit 328-1. The extended function circuit 328-0 may perform the extended operations described herein, including but not limited to writing / programming data using corresponding extended data authentication and / or writing / programming or erasing commands (and possibly addresses) using corresponding extended data authentication. Although the host may generate the extended value, in some embodiments, the memory device 300 may include the extended value generation circuit 328-1. In some embodiments, such a circuit may include generating an extended value from read data, e.g., an authentication value, EDC, or ECC.

[0061] The data output circuit 324-0 may provide a path from the memory cell array 302 to the extended operation circuit 306-2. The data input circuit 324-1 may provide a path from the extended operation circuit 306-2 to the memory cell array 302.

[0062] The memory controller 340 may perform transactions with the memory device 300 and may be part of a host device in some embodiments. The memory controller 340 may include a controller IO circuit 340-0, a controller CMD / ADD generator circuit 340-1, and an optional controller extended function circuit 340-2. The controller CMD / ADD generator 340-1 may receive request data 348 and LEN data 350. The request data may indicate the type of operation (read memory, write memory, erase memory). The LEN data may indicate the LEN value of the transaction. In response to such inputs, the controller CMD / ADD generator 340-1 may generate a CMD / ADD value with an encoded LEN value for the controller IO circuit 340-0. Different from a conventional controller, the CMD / ADD generator circuit 340-1 may include a LEN encoder circuit 344, which may encode the LEN value into a bit combination to be included in the CMD / ADD sequence. It can be understood from the embodiments herein that different encoded LEN bit combinations may correspond to different LEN sizes.

[0063] The optional controller extended function circuit 340-2 can perform functions related to extended data transactions. The extended check circuit 346-0 can receive data from the memory device 300, and can perform one or more functions associated with the received extended data, including but not limited to authenticating the read data using the corresponding extended data, performing error detection and / or error correction on the read data using the corresponding extended data. The authenticated read data can be output from the extended check circuit 346-0 as a data output 352-0. The read data that cannot be authenticated can be discarded. The read data that has been corrected can be output from the extended check circuit 346-0 as a data output 352-0. The read data that has only detected an error but not corrected can be discarded, and the read operation can be repeated.

[0064] The extended data generation circuit 346-1 may generate extended data values ​​for transmission to the memory device 300. In the illustrated embodiment, the data in 352-1 may be received and extended data (e.g., any of authentication data, EDC, ECC) may be generated therefrom. The received data in 352-1 and the corresponding generated extended data may then be provided to the controller IO circuit 340-0 for output on the serial bus 318. In some embodiments, command and / or address data may also be included in the generation of the extended data (e.g., for authentication CMD / ADD values).

[0065] The controller IO circuit 340-0 can drive a signal on the control line 342-0 to control the transmission on the serial bus 318. Such control signals 342-0 may include, but are not limited to, SCK signals and CS signals. The controller circuit 340-0 can also send CMD / ADD sequences with extended data and receive read data with extended data through one or more SIO lines 342-1.

[0066] In this manner, the controller device can encode the length size of the transaction data and include these values ​​in the CMD / ADD sequence to the memory device. The memory device can decode the encoded length value to determine the data size of the transaction indicated by the CMD / ADD sequence.

[0067] Figure 4-0 , Figure 4-1 and Figure 4-2 is a state diagram of a CMD / ADD decoder of a memory device according to an embodiment. Figure 4-0 to Figure 4-2 Similar items referred to by the same reference characters may be included.

[0068] Figure 4-0A CMD / ADD decoder 406-0 is shown, which can derive an encoded LEN value after receiving command data and address data. After activating the CS signal, the CMD / ADD decoder 406-0 can be converted from an idle state 454 to a decoding operation that varies according to a serial bus cycle 456-0. From bus cycle "i" to "j-1", the received value can be decoded into a command value 458. From cycle "j" to "k-1", the received value can be decoded into an address value 460. From cycle "k" to "l", the received value can be decoded into a LEN value 462. It is understood that clock cycles "i", "j", "k" and "l" can be parts of a cycle (e.g., half a cycle). In addition, the value of such a clock cycle (i1) can vary according to device configuration (e.g., the number of SIOs, memory device address space, memory device IO size, etc.). In some embodiments, according to the standard (e.g., SPI standard) of the operation of the memory device 300, cycles i to j-1 can be dedicated to command data, while cycles j to k-1 can be dedicated to address data.

[0069] Figure 4-1 is CMD / ADD decoder 406-1, which can derive the encoded LEN value included in the address value. In some embodiments, this configuration can be generated by replacing the LSB of the address with the LEN bit. Figure 4-1 and Figure 4-0 The difference is that after receiving the command value, the values ​​received from cycles j to k-1 can be decoded into address values ​​and LEN values. In some embodiments, cycles i to j-1 can be dedicated to addressing data according to the standard in which the memory device 300 operates.

[0070] Figure 4-2 is a CMD / ADD decoder 406-1, which can derive an encoded LEN value included in the command value. This configuration can utilize time periods (eg, falling clock edges) and / or unassigned bit value combinations in the command value space as encoded LEN values. Figure 4-2 and Figure 4-0 The difference is that the values ​​received from cycles i to j-1 can be decoded into commands and LEN values. In some embodiments, cycles i to j-1 can be dedicated to command data according to the standard in which the memory device 300 operates.

[0071] It is worth noting that embodiments may include Figure 4-0 to Figure 4-1 A combination of LEN decoding presented in .

[0072] In this way, the CMD / ADD decoder of the memory device can decode bits indicating the transaction data length size, which are included in any of the following bits: bits after the clock cycle assigned to the command value and the address value, bits included in the clock cycle assigned to the address value, and / or bits included in the clock cycle assigned to the command value.

[0073] Figure 5-0 to Figure 5-2 , Figure 6-0 to Figure 6-2 and Figure 7-0 to Figure 7-2 1 is a timing diagram of a memory device transaction according to an embodiment. Each timing diagram includes a CS# waveform, an SCK waveform, and an SIO waveform. The SIO waveform may include eight SIO[7:0] (eg, OSPI).

[0074] Figure 5-0 to Figure 5-2 A data transaction is shown where, in addition to the command value and address value, LEN and / or metadata may be included as data at the end of the CMD / ADD sequence.

[0075] refer to Figure 5-0 , the timing diagram shows a data read operation according to an embodiment. Before time t0, CS# may be converted to active (i.e., become low). At time t0, command data (C) may be latched at least on the rising edge of SCK. In the illustrated embodiment, the command data (C) may indicate an extended read operation. The extended read operation may return the read data at the indicated address and the corresponding extended data to the requesting device. Unlike a conventional read operation, the amount of read data (i.e., LEN) may be determined by the encoded LEN value included in the CMD / ADD sequence within L1, L0. After the command data (C), at time t1, the address data (A) may be latched at least on the rising edge of SCK. Unlike a conventional serial memory read operation, after the address data (A), at time t2, the encoded LEN data extended data (shown as L0, L1) may be latched at least on the rising edge of SCK. In some embodiments, a second set of command data (C) (i.e., Figure 5-0 The falling edge of SCK in ) can indicate the presence of LEN data (L1, L0) following the address data (A).

[0076] Still refer to Figure 5-0 , around time t3, after a number of dummy cycles, read data (shown as cD0 to cD31) corresponding to the extended data read operation may be output synchronously with the rising and falling edges of SCK (i.e., at double data rate). In the illustrated embodiment, the length of the read data may be indicated by the encoded LEN value, which in the illustrated embodiment may be 32 bytes output within 16 SCK cycles (i.e., at double data rate).

[0077] Note that CS# can remain active after the read data is transferred at time t4. However, since the controller device that issued the read command knows LEN, the controller device can distinguish the end position of the read data and the start position of the extended data.

[0078] At around time t4, after the read data (cD0 to cD31) is read, extended data (shown as eT0 to eT15) can be output at the rising and falling edges of SCK. In the illustrated embodiment, the extended data can be a 128-bit burst length output within 8 SCK cycles. At around time t5, CS# can be driven inactive, thus ending the extended data read transaction.

[0079] Figure 5-1 An extended data write / program operation according to an embodiment is shown. From time t0 to t2, the extended data write / program operation can follow the actions described for Figure 5-0 but the command value (C) indicates an extended data write / program operation. At around time t3, after the encoded LEN data (L0, L1), write / program data corresponding to the extended data write / program operation can be output at the rising and falling edges of SCK. Different from the conventional write / program operation, the amount of write data can be determined by the encoded LEN value included in the CMD / ADD sequence in L1, L0. In the illustrated embodiment, the write / program data can be a 256-bit burst length output within 16 SCK cycles. At around time t4, after the write / program data (cD0 to cD31), extended data (shown as eT0 to eT15) can be output at the rising and falling edges of SCK. In the illustrated embodiment, the extended data can be a 128-bit burst length output within 8 SCK cycles. At around time t5, CS# can end the extended data write / program transaction. Due to the LEN value received using L1, L0, the memory device receiving the data can determine the position where the write / program ends and the start position of the extended data.

[0080] Figure 5-2 An extended data erase operation according to an embodiment is shown. From time t0 to t2, the extended data erase operation can follow the actions described for Figure 5-0 but the command value (C) indicates an extended data erase operation. At around time t3, after the encoded LEN data (L0, L1), extended data (eT0 to eT15) can be output at the rising and falling edges of SCK. In the illustrated embodiment, the extended data can be a 128-bit burst length output within 8 SCK cycles. At around time t4, CS# can end the extended data erase transaction. In some embodiments, the LEN data can include metadata related to the erase operation.

[0081] Figure 5-3 is a table of command values ​​according to an embodiment. In some embodiments, the command value can be a hexadecimal value, so it can be sent on the rising and falling edges of SCK, such as Figure 5-0 to Figure 5-2 In some embodiments, such a command value can be latched at the first falling edge of SCK.

[0082] Figure 5-4 is a table of encoded LEN values ​​(L1, L0) according to one embodiment. In the illustrated embodiment, the encoded LEN value may be 16 bits, where bits [0:12] may indicate the length of the transaction data in bytes. Bits [13:15] may provide any other suitable data, including but not limited to other data related to the corresponding extended data operation (e.g., indicating authentication without encryption).

[0083] It should be understood that alternative embodiments may include operations without extension data, which may provide transaction data (eg, read data, write / program data) having a length indicated by L0, L1.

[0084] In this way, the memory device can decode the length data received after the command value and address value on the serial bus to determine the transaction data length value. For extended data transactions, the memory device can determine where the transaction data ends and where the extended data begins. The decoded length data can also indicate additional information (e.g., metadata) for indicating the operation.

[0085] Figure 6-0 to Figure 6-2 An extended data transaction is shown where LEN and other data may be included in the CMD / ADD sequence along with the command value. Figure 6-0 An extended data read operation according to an embodiment is shown. Prior to time t0, CS# may transition to active (i.e., go low). At time t0, command data (C) 620 may be latched on the rising edge of SCK. Unlike some conventional serial read operations, instead of repeating the command data (C) on the falling edge, the encoded LEN data 621 is latched on the falling edge of SCK. In some embodiments, the command data (C) 620 and / or the encoded data 621 may indicate an extended read operation. In the illustrated embodiment, the encoded LEN data 621 may include data on all eight SIO lines, with the three LSBs L[2:0] indicating the LEN value, and the remaining bits C[7:3] indicating additional features of the extended data operation. Following the extended data 621, at time t2, the address data (A) may be latched on at least the rising edge of SCK. At approximately time t3, after several dummy cycles, the extended data read operation may be performed according to Figure 5-0 Perform the operations shown in .

[0086] Figure 6-1 The extended data write / program operation according to the embodiment is shown. From time t0 to t2, the extended data write / program operation can follow the Figure 6-0 The actions described above are the same, but the command value (C) 620 and / or the encoded value 621 indicate an extended data write / program operation. At approximately time t3, the extended data write / program operation may follow Figure 5-1 The operations shown in .

[0087] Figure 6-2 According to the embodiment, the extended data erasure operation is shown. From time t0 to t2, the extended data erasure operation can follow the Figure 6-0 The actions described above are the same, but the command value (C) 620 and / or the encoded value 621 indicate an extended data erase operation. At approximately time t3, the extended data write / program operation may follow Figure 5-2 The operations shown in .

[0088] Figure 6-3 is a table of encoded LEN values ​​received with command data according to an embodiment. In the illustrated embodiment, the encoded LEN value may be 8 bits, where bits [2:0] may indicate the length of the extended data in bytes. Bits [7:3] may provide other data related to the corresponding transaction (e.g., authentication without encryption).

[0089] In this way, the memory device can decode the length data received on the serial bus before the command value and the address value. Based on the data length value, the memory device can determine the size of the transaction data. The decoded extended length data can also indicate additional information of the extended operation using the extended data.

[0090] Figure 7-0 to Figure 7-2 An extended data transaction is shown where LEN and other data may be included in the CMD / ADD sequence along with the address value. Figure 7-0An extended data read operation is shown according to an embodiment. Before time t0, CS# can be converted to an active state. At time t0, command data (C) 720 can be latched on at least one rising edge of SCK. After command data (C), at time t1, address data (A) can be latched on the edge of SCK. Different from some conventional serial read operations, at time t2, a mixture of address value and encoded LEN data 721 can be latched, rather than treating the data received after command data as only address data. In some embodiments, command data (C) can indicate an extended data read operation. In the embodiment shown, the data latched at time t2 can include A[7:5] of three MSB address data, and the remaining five LSB L[4:0] are encoded LEN data. In some embodiments, in addition to the transaction data length LEN, LSB L[4:0] can also indicate additional features of an extended data operation. In some embodiments, the number of bits dedicated to encoded LEN data can be based on the data size of the transaction and the granularity of the address value. For example, if the application's memory device accesses are aligned along 32-byte boundaries and the minimum data size is one byte, then the 5 LSBs of the address may not be needed and can be dedicated to encoding LEN data. At around time t3, after a number of dummy cycles, the extended data read operation can follow Figure 5-0 The operations described in .

[0091] Figure 7-1 The extended data write / program operation according to the embodiment is shown. From time t0 to t2, the extended data write / program operation can follow the Figure 7-0 The actions described above, but the command value (C) indicates an extended data write / program operation. At about time t3, the extended data write / program operation can follow the Figure 5-1 Describes the operation.

[0092] Figure 7-2 The extended data erase operation is shown according to an embodiment. From time t0 to t2, the extended data write / program operation may follow the Figure 7-0 The actions described above, but the command value (C) indicates an extended data erase operation. At about time t3, the extended data write / program operation can follow the Figure 5-2 The operation described.

[0093] Figure 7-3 is a table of encoded LEN values ​​according to an embodiment. In the illustrated embodiment, the encoded LEN value may be 4 bits, where bits [1:0] may indicate the length of the transaction data in bytes. Bits [5:2] may provide other data related to the corresponding operation (e.g., no encryption authentication).

[0094] In this way, the memory device can decode the data length value contained in the address data to determine the transaction data length. Based on the data length value, the memory device can determine the number of clock cycles for the transaction data to be sent or received. In an extended data operation, LEN can also indicate the boundary between transaction data and extended data.

[0095] Although the systems and devices described herein illustrate various methods, additional methods will now be described with reference to flow charts. Such methods may be performed by circuits of the devices and / or systems described herein.

[0096] Figure 8 870 is a flow chart of a method 870 according to an embodiment. The method may be performed by a memory device. The method 870 may include receiving a command value, an address value, and an encoded data length value 870-0 at a serial IO in synchronization with a serial clock. Such actions may include receiving a CMD / ADD sequence according to any embodiment described herein or an equivalent.

[0097] The received value may be decoded to determine one of many possible data length values ​​870-1. Such action may include decoding to determine a LEN value according to any embodiment described herein, or an equivalent. In some embodiments, such action may also determine information other than the LEN value that indicates other features (e.g., metadata) of the extended data operation.

[0098] A transaction data value having at least length LEN may be transmitted 870-2 on the serial IO in synchronization with the serial clock. Such an action may include sending transaction data from a memory device or receiving transaction data at a memory device. In some embodiments, extended data having a length exceeding LEN may be sent with the transaction data.

[0099] In this manner, one of many transaction data length values ​​may be encoded and included in a command address sequence, and transaction data indicating the length may be included in a memory transaction.

[0100] Fig. 9970 is a flowchart of another method 970 according to an embodiment. Method 970 may be executed by a memory device to perform any read, write / program or erase operation, including a version of such operation that includes extended data. In response to the CS signal becoming active 970-0, at the serial IO, command data 970-1 may be received synchronously with the clock signal. Such an action may include receiving command data on one or more serial IO lines. At the serial IO, after the command data, address data 970-2 may be received synchronously with the clock signal. At the serial IO, after the address data, a LEN value and possible other data 970-3 may be received synchronously with the clock signal. In some embodiments, the LEN value may be encoded as described herein or an equivalent. Actions 970-0 to 970-3 may constitute a received CMD / ADD sequence. The LEN value may include data other than the transaction data length value, as described herein or an equivalent. In some embodiments, part of the CMD data and / or the ADD data may indicate that LEN data is added after the address data.

[0101] Still refer to Fig. 9 , after receiving CMD / ADD and LEN data (970-0, 970-1, 970-2), command 970-4 can be executed. CMD data can be decoded. If the CMD data indicates a read transaction (Y from 970-5), data of length LEN stored at the address indicated by ADD can be output as read data 970-6 in synchronization with the clock signal. If the read operation is an extended data read operation (Y from 970-7), extended data 970-8 corresponding to the read data can be output in synchronization with the clock signal. In some embodiments, the extended data can follow (e.g., append to) the read data.

[0102] If the CMD data indicates a write or program transaction (Y from 970-9), the write or program data and the extended data 970-10 of length LEN may be received synchronously with the clock signal. If the write or program transaction includes extended data (Y from 970-7), the extended data 970-11 may be output together with the write or program data.

[0103] Optionally, the write or programming transaction 970-12 may be evaluated with extended data. Such actions may include any of the extended evaluations described herein or equivalents, including but not limited to authenticating the received write or programming data with extended data, authenticating the received write or programming command with extended data, performing error detection and / or correction on the write or programming data, or possibly corresponding command and address data. If the write or programming transaction does not pass the extended evaluation (N from 970-12), the received data may not be written or programmed at the address indicated by ADD. If the write or programming transaction passes the extended evaluation (Y from 970-12) or the write or programming transaction does not include extended data, the received data 970-13 may be written or programmed at the address indicated by ADD.

[0104] If the CMD data indicates an erase transaction (Y from 970-14) and the erase transaction includes extended data (Y from 970-7), the erase transaction 970-15 may be evaluated using the extended data. Such actions may include, but are not limited to, performing authentication, error detection, or error correction on the erase transaction command and / or address data. If the erase transaction does not pass the extended evaluation (N from 970-14), the data at the address indicated by ADD may not be erased. If the erase transaction passes the extended evaluation (Y from 970-14) or the erase transaction does not include extended data (N from 970-7), the data at the address indicated by ADD may be erased 970-15.

[0105] In this manner, the method may include receiving LEN data after the CMD and ADD data, and performing a read operation or a write operation or a program operation using the data of length LEN.

[0106] Fig.10is a flow chart of another method 1070 according to another embodiment. The method 1070 may be executed by a memory device to perform any read, write / program, or erase operation. In response to the CS signal becoming active 1070-0, at the serial IO, CMD data 1070-1 including a LEN value may be received synchronously with the clock signal. In some embodiments, such an action may include receiving CMD at one edge (e.g., rising or falling) of the serial clock and receiving LEN data at the opposite edge (e.g., falling or rising) of the same clock. In some embodiments, the LEN value may be encoded and include additional data regarding an extended operation described herein or an equivalent. At the serial IO, after the command data, ADD data 1070-2 may be received synchronously with the clock signal. Actions 1070-0 to 1070-2 may be a CMD / ADD sequence. After receiving the CMD / LEN / ADD data (1070-0, 1070-1, 1070-2), an extended command 1070-4 may be executed. Such an action 1070-4 may be as Fig. 9 The occurrence described in 970-4 occurs.

[0107] In this manner, the method may include receiving LEN data having CMD data followed by ADD data, and performing a read operation, a write operation, or a program operation using the LEN-sized data.

[0108] Fig.11 1170 is a flow chart of another method 1170 according to another embodiment. The method 1170 may be executed by a memory device to perform any read, write / program or erase operation. In response to the CS signal becoming active 1170-0, at the serial IO, CMD data 1170-1 may be received synchronously with the clock. Such actions may be as follows: Fig. 9 The occurrence described in 970-1, or its equivalent.

[0109] After the CMD data, at the serial IO, ADD data 1170-2 including the LEN value can be received synchronously with the clock signal. In some embodiments, such an action can include receiving the ADD data on one edge of the serial clock and receiving the LEN data on the opposite edge (e.g., falling or rising) of the same clock. In some embodiments, the data latched at the clock edge can include both the ADD data and the LEN data. After receiving the CMD / ADD / LEN data (1170-0, 1170-1, 1170-2), a command 1170-4 can be executed. Such an action 1170-4 can be as shown in FIG. Fig. 9 occurs as described for 970-4.

[0110] In this manner, the method may include receiving CMD data followed by ADD data with LEN data, and performing a read, write, or program operation using the LEN-sized data.

[0111] Fig.12 1 is a flow chart of another method 1270 according to an embodiment. The method 1270 may be executed by a memory controller device to perform any of a read, write, program, or erase operation. The method 1270 may be generally performed as follows: Fig. 9 , but represents the memory controller side.

[0112] Method 1270 may include driving a CS signal activity 1270-0. CMD data may be sent 1270-1 on the serial IO in synchronization with the clock signal. On the serial IO, after the command data, ADD data may be transmitted 1270-2 in synchronization with the clock signal. The LEN value and possibly other data may be sent 1270-3 at the serial IO after the address data in synchronization with the clock signal. The LEN value may be encoded as described herein, or an equivalent. Actions 1270-0 to 1270-2 may send a CMD / ADD sequence to a memory device. The LEN value may include data in addition to an extended data length value, as described herein, or an equivalent. In some embodiments, portions of the CMD data and / or ADD data may indicate that LEN data is added after the address data.

[0113] Still refer to Fig.12 , after receiving CMD / ADD and LEN data (1270-0, 1270-1, 1270-2), command 1270-4 can be executed. If the sent CMD data indicates a read operation (Y from 1270-5), read data 1270-6 of length LEN can be received at the serial IO in synchronization with the clock signal. In some embodiments, the read data can be received after some delay (e.g., a dummy cycle or other delay). If the read operation is an extended read operation (Y from 1270-7), at the serial IO, extended data 1270-8 of the length can be received in synchronization with the clock signal. In some embodiments, the extended data can follow (e.g., appended to) the read data. If the CMD data indicates a write or programming transaction (Y from 1270-9), at the serial IO, write or programming data 1270-10 of length LEN can be sent in synchronization with the clock signal. If the write or program operation is an extended data operation (Y from 1270-7), then at the serial IO, the extended data can be sent 1270-12 synchronously with the clock signal. If the erase operation is an extended data operation (Y from 1270-7), then at the serial IO, the extended data can be sent 1270-12 synchronously with the clock signal.

[0114] After executing any command 1270 - 4 , the CS signal may be driven to an inactive state 1270 - 14 .

[0115] In this manner, a method may include sending LEN data after CMD and ADD data, and performing a read, write, program, or erase operation that includes transferring transaction data having a length of LEN.

[0116] Fig.13 and Fig.14 are flow diagrams of additional methods 1370 and 1470 according to an embodiment. Fig.13 can include corresponding to Fig.10 Controller action. Fig.14 can include corresponding to Fig.11 Controller action.

[0117] refer to Fig.13 , method 1370 may include CS signal becoming active 1370-0. At the serial IO, CMD data including LEN value may be sent synchronously with the clock signal 1370-1. Such data may be used for Fig.10 1370-2. At the serial IO, after the CMD data, the ADD data 1370-2 may be sent synchronously with the clock signal. Actions 1370-0 to 1370-2 may be a CMD / ADD sequence. After receiving the CMD / LEN / ADD data (1370-0, 1370-1, 1370-2), an extended command 1370-4 may be executed. Such an action 1370-4 may be as follows: Fig.12 After any extended data command has been executed 1370-4, the CS signal may be driven inactive 1370-12.

[0118] In this manner, the method may include sending LEN data with CMD data followed by sending ADD data, and performing an extended data read operation, write operation, program operation, or erase operation including the extended data of the transfer length LEN.

[0119] Fig.14 The CS signal may be included to become active 1470-0. At the serial IO, CMD data may be sent 1470-1 in synchronization with the clock. Following the CMD data, at the serial IO, ADD data including a LEN value may be sent 1470-2 in synchronization with the clock signal. Such a combination of ADD and LEN values ​​may be as follows: Fig.11After the CMD / ADD / LEN data (1470-0, 1470-1, 1470-2) is transmitted, an extended command 1470-4 may be executed. Such an action 1470-4 may be as follows Fig.12 After any extended data command has been executed 1470-4, the CS signal may be driven inactive 1470-12.

[0120] In this manner, the method may include sending CMD data followed by sending ADD data with LEN data, and performing an extended data read, write, program, or erase operation including the extended data of the transfer length LEN.

[0121] Fig.15 is a table showing commands received at a serial interface of a memory device according to an embodiment. The received commands may include standard commands, including but not limited to: a read command (READ), a fast read command (FAST_READ), a page programming command (PP), and a sector erase command (SE). However, unlike conventional memory devices, such standard commands may have corresponding variable length corresponding commands, where the transaction amount may be established by the encoded LEN value included in the CMD / ADD sequence described herein, or an equivalent. In the illustrated embodiment, a variable length read command 1572-0 may establish the amount of read data using a LEN value. A variable length program command 1572-1 may establish the amount of program data using a LEN value. Fig.15 An advanced sector erase command 1572-2 is also shown. Such a command can utilize metadata in the LEN value to control various aspects of the sector erase operation.

[0122] In this manner, in response to a particular received command, a memory device may perform a memory access transaction that may select the amount of data sent in the transaction. Additionally or alternatively, the particular received command may include metadata. The metadata may include, but is not limited to, data for indicating characteristics of the transaction or controlling characteristics of the transaction.

[0123] While embodiments may include any suitable type of memory array, some embodiments may include a 1-transistor (1T) NOR type array. Figure 16-0is a schematic diagram of a 1T NOR array 1602-0 that may be included in an embodiment. The array 1602-0 may include a plurality of memory cells (one shown as 1674) arranged in rows and columns, wherein memory cells in the same row are connected to the same word line (one shown as 1676), and memory cells in the same column are connected to the same bit line (one shown as 1678). In some embodiments, the memory cell (1674) may be formed with a single transistor structure having a charge storage structure 1674-0 between the control gate and the channel. The charge storage structure 1674-0 may store one or more data bits as a charge (including no charge) without using power to maintain the data. The charge storage structure 1674-0 may take any suitable form, including but not limited to: a floating gate, a charge storage dielectric (e.g., a replacement gate), or a combination thereof. However, embodiments may include any other suitable non-volatile memory cell type.

[0124] In some embodiments, as described herein and their equivalents, commands with embedded LEN values ​​may be used to access non-volatile storage cells, thereby enabling reading data from NOR-type memory devices with selectable data transaction sizes (e.g., lengths), including execute-in-place (XiP) code read operations.

[0125] Embodiments may also include any suitable volatile array structures or volatile memory cell types. Figure 16-1 is a schematic diagram of a possible volatile memory cell array that may be included in an embodiment. Figure 16-1 An array 1602-1 is shown, which may include a plurality of volatile memory cells (one shown as 1680) arranged in rows and columns and connected to one or more bit lines (e.g., 1678) and word lines (e.g., 1676). The volatile memory cells (1680) may take any suitable form, including, but not limited to, DRAM cells 1680-0 and / or SRAM cells 1680-1. The SRAM cells 1680-1 may include, but are not limited to, 4-transistor (4T), 6T, and / or 8T variations.

[0126] Although embodiments may include devices and systems with various interconnected components, embodiments may also include unit devices that can perform the extended data storage device transactions described herein, and equivalents. In some embodiments, such unit devices may be advantageously compact single integrated circuits (i.e., chips). Fig.17Shown is a packaged memory IC device 1700 that can perform extended data transactions in accordance with embodiments described herein. A CMD / ADD sequence with embedded LEN data can be received, and a selected number of transaction data can be input or output on one or more external connections (shown as a 1782). However, a memory device according to an embodiment can include any other suitable integrated circuit package type, as well as directly bonding the device chip to a circuit board or substrate.

[0127] In this way, the IC memory device can perform extended data memory transactions.

[0128] Although embodiments can include a memory device that performs memory access transactions with selectable transaction data sizes, embodiments can also include a memory controller circuit that can perform such transactions through an interface compatible with the memory device. Such a memory controller can be part of a host device. Figure 18-0 Shown is a memory controller 1840 according to an embodiment. The memory controller 1840 can include a processing circuit 1842, an IF circuit 1844, a command queue 1846-0, a write queue 1846-1, and a read queue 1846-2. The processing circuit 1842 can include a LEN command generation circuit 1842-0 and a LEN data operation circuit 1842-1.

[0129] The command queue 1846-0, the write queue 1846-1, and the read queue 1846-2 can be connected to a controller IF 1848, which can be part of a larger host device or connected to the host device via a communication path. The command queue 1846-0 can receive memory requests through the controller IF 1848 to access a memory device connected to a bus 1818. The write data queue 1846-1 can receive write data or programming data associated with the memory request (e.g., data to be stored in the memory device). The read data queue 1846-2 can provide read data generated by the memory request (e.g., data read from the memory device).

[0130] In some embodiments, LEN data command generation circuit 1842-0 can distinguish memory access requests received through command queue 1846-0, some of which generate CMD / ADD sequences with encoded LEN data values, while other requests generate standard CMD / ADD sequences (i.e., sequences without encoded LEN bits). However, in other embodiments, such a distinction cannot be made, and all memory access requests can generate CMD / ADD sequences with encoded LEN values. Transactions can take any form or equivalent described herein. LEN data operation circuit 1842-1 can perform operations according to any embodiment or equivalent described herein, including but not limited to distinguishing transaction data and extended data according to LEN values. Interface 1844 and corresponding bus 2818 can be any suitable bus, including but not limited to a bidirectional serial bus.

[0131] In this manner, the memory controller may generate a CMD / ADD sequence with a transaction data length value for the memory device to process in response to a memory access request.

[0132] While embodiments may include a system having a memory device operating in cooperation with a host device, embodiments may also include a standalone host device having LEN command generation and operation circuitry and one or more memory device IFs formed in a single IC package. Figure 18-1 Such an embodiment is shown in . Figure 18-1 A perspective top view 1840-0 and a bottom view 1840-1 of a packaged host device are shown. The host device 1840-0 / 1840-1 may include a plurality of physical connections (e.g., 1850), all or part of which may be connected to a memory device IF as described herein. Such an IF may perform data transactions for processing, as described herein, and equivalents. In some embodiments, the host device may be a system-on-chip (SoC) type device. It is understood that the host device may include any other suitable package type.

[0133] In this manner, the IC host device may generate a data transaction having a selectable transaction data size in response to a request received via the controller IF.

[0134] Fig.19 1984 is a table showing a memory address space 1984 of a system according to an embodiment. The memory address space 1984 may include physical addresses (ADDRESS) in which various data are stored, including firmware 1984-0. In some embodiments, an optional transaction data size 1985 may be used to access some or all of the addresses assigned to firmware (e.g., 0x4000000 to 0x4005000), as described herein, or an equivalent.

[0135] In this manner, the system can assign memory device access transactions of selectable data sizes to one or more regions of the system memory space.

[0136] Fig. 20 2090-0. In some embodiments, such actions may include, but are not limited to, sending a program CMD / ADD sequence with a selected program data size, as described herein or an equivalent. Subsequently, if a firmware access occurs (Y from 2090-1), such memory access may be a data transaction 2090-2 directly accessing non-volatile memory with a selectable data transaction size (e.g., in LEN size). In some embodiments, such access may be a XiP type access and therefore does not include the time or additional components involved in copying the firmware to volatile memory, as in some conventional methods.

[0137] In this manner, in response to a firmware access, the host device may perform a data transaction having a selectable data transaction size.

[0138] Embodiments may include any suitable system that can benefit from fast, secure, flexible access to memory (e.g., non-volatile memory). Embodiments may be advantageously used in systems that access code from high-reliability, secure memory devices (e.g., automotive systems). Fig.21 An automotive system 2130 according to an embodiment is shown. The system 2130 may include a first NVM device 2100-0, a second NVM device 2100-1, a SoC 2140-0, an automotive microcontroller (MCU) 2140-1, a sensor 2192, an automotive control 2194-0, an automotive communication system 2194-1, an automotive power system 2194-2, and an optional dynamic random access memory (DRAM) device 2186. The NVM devices 2100-0 / 2100-1 are capable of performing transactions of variable data size (LENOps) 2106-20 / 2106-21. The SoC 2140-0 and the MCU 2140-1 are capable of generating CMD / ADD sequences with LEN values ​​(LEN Ops) 2140-20 / 2140-21.

[0139] The SoC 2140-0 and the first NVM device 2100-0 may be a host device and a corresponding NVM device according to any of the embodiments described herein. Thus, the SoC 2304-0 may securely execute code 2188-0 stored in the NVM device using data transactions with variable data length sizes, thereby eliminating the need to copy such code to a "shadow" volatile memory for authentication prior to execution. The transaction may include a read operation of the authentication code using extended data, where a LEN value may be used to demarcate the end position of the read data and the start position of the corresponding authentication data. Similarly, the MCU 2140-1 and the second NVM device 2100-1 may be a host device and a corresponding NVM device according to any of the embodiments described herein, or equivalent. Thus, the MCU 2140-1 may include a XiP operation 2188-1 using a data transaction with a LEN value for accessing code and any other suitable operation.

[0140] Although a DRAM device 2188 may be included, such a device may be used for purposes other than shadow code, as the SoC / MCU 2140-0 / 2140-1 may execute code in-place from the NVM device 2100-0 / 2100-1.

[0141] In this manner, an automotive control system may include one or more non-volatile memory devices that perform data transactions of variable data transaction sizes with a controller device.

[0142] refer to Fig. 22 , an automotive system 2296 according to an embodiment is shown. The automotive system 2296 may have multiple subsystems (shown as two subsystems 2300-0 and 2300-1) that operate using firmware accessed from an NVM device. Such subsystems (2230-0, 2230-1) may include an electronic control unit (ECU) and / or an advanced driver assistance system (ADAS). However, in other embodiments, such subsystems may include a dashboard display / control subsystem and / or an infotainment subsystem, which are just two of many possible examples. Each subsystem (2230-0, 2230-1) may include at least one host device and one or more NVM devices that may perform extended data transactions, as described herein or equivalent. Such transactions may include, but are not limited to, optional data transaction size, authentication, error correction, or error detection.

[0143] In this way, the car can benefit from variable data size transactions with the NVM device.

[0144] Embodiments may include methods, devices, and systems, including receiving at least a command value, an address value, and an encoded length value at a serial IO of a memory device synchronously with a serial clock; determining a memory access operation, a memory array location, and a LEN value of a plurality of different LEN values ​​corresponding to the memory access operation based on at least the command value, the address value, and the encoded length value. During execution of the memory access operation, data of at least a length of LEN may be sent at the serial IO synchronously with the serial clock.

[0145] Embodiments may include methods, devices, and systems having a memory cell array and a decoder circuit configured to determine a memory access operation based on a command value, a memory cell array location based on an address value, and one of a plurality of different data length values ​​(LEN) based on an encoded data length value. The control circuit may be configured to access the memory cell array location based on the memory access operation. The IO circuit may include a serial clock input configured to receive a serial clock, and at least one serial IO configured to receive a command value, an address value, and an encoded extended data length value synchronously with the serial clock, and transmit data of at least length LEN.

[0146] Embodiments may include methods, devices, and systems having a memory device including a memory cell array and a control circuit configured to determine a memory access operation and a location based on a command value and an address value, determine one of a plurality of data length values ​​(LEN) based on an encoded data length value, and access the memory cell array location based on the memory access operation. The IO circuit may be configured to receive the command value, the address value, and the encoded extended data length value at a serial IO in synchronization with a serial clock, and transmit data of at least the length LEN. A serial bus may be coupled to at least the IO circuit.

[0147] Methods, devices, and systems according to embodiments may include receiving a command bit in synchronization with a serial clock, receiving an address bit in synchronization with the serial clock after the command bit, and receiving a LEN bit in synchronization with the serial clock after the address bit.

[0148] Methods, devices, and systems according to embodiments may include: receiving a first set of command bits synchronously with a serial clock; receiving a second set of command bits and LEN bits synchronously with the serial clock after the first set; and receiving address bits synchronously with the serial clock after the second set.

[0149] Methods, devices, and systems according to embodiments may include: receiving command bits synchronously with a serial clock; receiving a first group of address bits synchronously with the serial clock after the command bits; and receiving a second group of address bits and LEN bits synchronously with the serial clock after the first group.

[0150] Methods, devices, and systems according to embodiments may include a selectable transaction data size that is a multiple of X, where X is an integer.

[0151] Methods, devices, and systems according to embodiments may include determining that the memory access operation is a read operation; and transmitting at least one length LEN of data includes transmitting the length LEN of read data stored at an address of the serial IO.

[0152] Methods, devices, and systems according to embodiments may include determining that a memory access operation is an authenticated read operation; and transmitting data of at least one length LEN includes transmitting read data of length LEN stored at the address, followed by transmitting authentication data for authenticating the read data from the memory device at the serial IO.

[0153] Methods, devices, and systems according to embodiments may include determining that a memory access is a program operation or a write operation; and transmitting at least one length LEN of data includes receiving program data or write data of length LEN at a serial IO of the memory device.

[0154] Methods, devices, and systems according to embodiments may include determining that a memory access is an authenticated programming or writing operation; and transmitting data of at least one length LEN includes receiving programming data or write data of length LEN at a serial IO of a memory device, followed by receiving authentication data, the authentication data being used to authenticate at least the write data or the programming data.

[0155] Methods, devices, and systems according to embodiments may include determining, through operation of a host device, a LEN for a memory access operation, and sending at least a command value, an address value, and a LEN value to a serial IO in synchronization with a serial clock in response to a request to access a memory space corresponding to a memory device.

[0156] Methods, devices, and systems according to embodiments may include a memory cell array including nonvolatile memory cells.

[0157] Methods, devices, and systems according to embodiments may include a serial clock input and at least one serial IO compatible with at least one Serial Peripheral Interface (SPI) standard.

[0158] Methods, devices, and systems according to embodiments may include an IO circuit configured to receive command data bits synchronously with a serial clock, receive address data bits synchronously with the serial clock following the command bits, and receive encoded LEN bits synchronously with the serial clock following the address bits.

[0159] Methods, devices, and systems according to embodiments may include an IO circuit configured to receive a first group of command data bits synchronously with a serial clock, receive a second group of command data bits and encoded LEN bits synchronously with the serial clock after the first group, and receive address data bits synchronously with the serial clock after the second group.

[0160] Methods, devices, and systems according to embodiments may include an IO circuit configured to receive command data bits synchronously with a serial clock, receive a first group of address data bits synchronously with the serial clock after the command bits, and receive a second group of address bits and encoded LEN bits synchronously with the serial clock after the first group.

[0161] Methods, devices, and systems according to embodiments may include an IO circuit configured to receive a command value, an address value, and an encoded extended length value in a format selected from the group consisting of: receiving a command bit, followed by an address bit, followed by an encoded extended length bit, and receiving a command bit, followed by an encoded extended length bit, followed by an address bit.

[0162] Methods, devices, and systems according to embodiments may include a host device having a command address generator circuit configured to generate a first command value, a first address value, and an encoded extended length value in an authenticated read operation, an authentication circuit configured to authenticate at least read data using corresponding extended data, and a host IO circuit. The host IO circuit may be coupled to a serial bus and configured to send the first command value, the first address value, and the first encoded extended data length value at the host serial IO in synchronization with a serial clock, and receive read data of length LEN and the corresponding extended data.

[0163] Methods, devices, and systems according to embodiments may include: a memory device having a memory cell array including non-volatile memory cells configured to store code; and a host device including a processor circuit configured to execute code directly from the memory device using an authenticated read operation.

[0164] It should be understood that references to "one embodiment" or "an embodiment" in this specification mean that the specific features, structures, or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. Therefore, it should be emphasized that two or more references to "one embodiment" or "an embodiment" or "an alternative embodiment" in various parts of this specification do not necessarily all refer to the same embodiment. In addition, specific features, structures, or characteristics may be appropriately combined in one or more embodiments of the present invention.

[0165] Similarly, it should be understood that in the description of the exemplary embodiments of the present invention described above, various features of the present invention are sometimes combined in a single embodiment, figure or description, with the purpose of simplifying the disclosure and helping to understand one or more of the various creative aspects. However, this disclosure method should not be interpreted as reflecting the intention that the claims require more features than those explicitly stated in each claim. Instead, creative aspects exist in less than all the features in a single previously disclosed embodiment. Therefore, the claims attached to the detailed description are hereby expressly incorporated into this detailed description, and each claim itself independently serves as a separate embodiment of the present invention.

[0166] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art after reference to this description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A method comprising: receiving at a serial input / output (IO) of a memory device, synchronously with a serial clock, at least a command value, an address value, and metadata, the metadata including an encoded length value; Determine the following based on at least the command value, the address value, and the encoded length value: Memory access operations, memory array location, and a data length value (LEN) of a plurality of different data length values ​​(LEN) corresponding to the memory access operation; as well as During execution of the memory access operation, at the serial IO, data having at least a length corresponding to one LEN of the plurality of different LENs is transmitted in synchronization with the serial clock.

2. The method according to claim 1, wherein: Receiving at least the command value, the address value, and the metadata comprises: receiving command bits synchronously with the serial clock, After the command bit, address bits are received synchronously with the serial clock, and Following the address bits, the LEN bit is received synchronously with the serial clock.

3. The method according to claim 1, wherein: Receiving at least the command value, the address value, and the metadata comprises: receiving a first set of command bits synchronized with the serial clock, receiving a second set of command bits and LEN bits synchronously with the serial clock after the first set, and After the second group, address bits are received synchronously with the serial clock.

4. The method according to claim 1, wherein: Receiving at least the command value, the address value, and the metadata comprises: receiving command bits synchronously with the serial clock, After the command bits, receiving a first set of address bits synchronously with the serial clock, and Following the first group, a second group of address bits and LEN bits are received synchronously with the serial clock.

5. The method according to claim 1, wherein: The plurality of different data length values ​​are multiples of X, where X is an integer.

6. The method according to claim 1, wherein: determining that the memory access operation is a read operation; as well as Transmitting the data having at least a length corresponding to one LEN of the plurality of LENs includes transmitting, at the serial IO, read data having a length LEN from the memory device stored at an address corresponding to an address value.

7. The method according to claim 1, wherein: determining that the memory access operation is an authenticated read operation; as well as Transmitting the data having at least a length corresponding to one LEN of the plurality of LENs comprises transmitting, at the serial IO, read data having a length LEN stored at an address corresponding to the address value followed by authentication data for authenticating the read data from the memory device.

8. The method according to claim 1, wherein: determining whether the memory access operation is a programming operation or a writing operation; as well as Transmitting the data having at least a length corresponding to one LEN of the plurality of LENs includes receiving program data or write data having a length LEN at the serial IO of the memory device.

9. The method according to claim 1, wherein: determining that the memory access operation is a verified program operation or a write operation; as well as Transmitting the data having at least a length corresponding to one LEN of the plurality of LENs comprises receiving program data or write data having a length of LEN at the serial IO of the memory device followed by receiving authentication data for authenticating at least the write data or program data.

10. The method according to claim 1, further comprising: The host device performs the following operations: Determine the LEN for memory access operations, and In response to a request to access a memory space corresponding to the memory device, at least the command value, the address value, and metadata are sent to the serial IO in synchronization with the serial clock, wherein the metadata includes the encoded length value.

11. A device comprising: A memory cell array; A decoder circuit, the decoder circuit being configured to: Determine the memory access operation based on the command value, Determine the memory cell array location based on the address value, and determining a data length value (LEN) from a plurality of different data length values ​​(LEN) based on the encoded data length value included in the metadata; a control circuit configured to access the memory cell array location in accordance with the memory access operation; as well as An input / output (IO) circuit, the input / output (IO) circuit comprising: a serial clock input configured to receive a serial clock, and At least one serial IO, the at least one serial IO being configured to: receiving a command value, an address value, and the metadata synchronously with the serial clock, and Data having at least the length LEN is transmitted.

12. The device according to claim 11, wherein The memory cell array includes: a non-volatile memory cell.

13. The device according to claim 11, wherein: The serial clock input and at least one serial IO are compatible with at least one Serial Peripheral Interface (SPI) standard.

14. The apparatus of claim 11, wherein: The IO circuit is configured as: receiving command data bits synchronously with the serial clock, After the command bit, address data bits are received synchronously with the serial clock, and Following the address bits, encoded LEN bits are received synchronously with the serial clock.

15. The apparatus of claim 11, wherein: The I / O circuit is configured as: receiving a first set of command data bits synchronously with the serial clock, receiving a second set of command data bits and encoded LEN bits in synchronization with the serial clock after the first set, and After the second group, address data bits are received synchronously with the serial clock.

16. The apparatus of claim 11, wherein: The I / O circuit is configured as: receiving command data bits synchronously with the serial clock, After the command bit, receiving a first set of address data bits synchronously with the serial clock, and Following the first group, a second group of address bits and encoded LEN bits are received synchronously with the serial clock.

17. A system comprising: A memory device, the memory device comprising: Memory cell array, A control circuit, the control circuit being configured to: Determine the memory access operation and location based on the command value and address value, determining a data length value (LEN) from a plurality of data length values ​​(LEN) based on an encoded data length value included in the metadata, accessing a memory cell array location according to the memory access operation, and An input / output (IO) circuit, the input / output (IO) circuit being configured to: receiving, at a serial IO, a command value, an address value, and the metadata in synchronization with the serial clock, and Transmit data having at least length LEN; and A serial bus is coupled to at least the I / O circuit.

18. The system of claim 17, wherein: The IO circuit is configured to receive a command value, an address value, and an encoded extended length value in a format selected from the group consisting of: receiving a command bit, followed by an address bit, followed by an encoded extended length bit, and The command bits are received, followed by the encoded length bits, followed by the address bits.

19. The system of claim 17, further comprising: A host device, the host device comprising: a command address generator circuit configured to generate a first command value, a first address value, and metadata in an authenticated read operation, the metadata including an encoded length value, an authentication circuit configured to authenticate at least the read data using corresponding authentication data, and a host IO circuit coupled to the serial bus and configured to: at a host serial IO, sending the first command value, the first address value, and the metadata synchronously with the serial clock, and Read data having the length LEN and corresponding authentication data are received.

20. The system of claim 19, further comprising: The memory device includes a memory cell array including non-volatile memory cells configured to store code; as well as The host device includes a processor circuit configured to execute the code directly from the memory device using an authenticated read operation.

Images