Storage device and method for managing data security therein

Abstract

The invention provides a storage device and a method for managing data security therein. In one aspect, the storage device includes at least one memory device and a controller coupled to the at least one memory device. The controller is configured to encrypt (encrypt) the first data with a first type of cryptographic algorithm, and to encrypt (encrypt) the second data with a second type of cryptographic algorithm. The first data is associated with a first security level, and the second data is associated with a second security level higher than the first security level. The second type of cryptographic algorithm has a greater encryption strength than the first type of cryptographic algorithm.

Description

Technical Field

[0001] The present disclosure relates to data security, and more particularly to data security in a storage device. Background Art

[0002] It is important to protect data in a storage device from unintentional overwrite, malicious attack, and copying. To meet security requirements, data stored in a storage device may be encrypted. Summary of the invention

[0003] The present invention discloses methods, devices, systems and technologies for managing data security in storage devices, such as solid-state drives (SSDs), and are applied, for example, in analog artificial intelligence (AI) systems.

[0004] One aspect of the present disclosure features a storage device, including: at least one memory device and a controller coupled to the at least one memory device, and the controller is used to: encrypt first data with a first type of cryptographic algorithm, and encrypt second data with a second type of cryptographic algorithm. The first data is associated with a first security level, and the second data is associated with a second security level higher than the first security level, and the second type of cryptographic algorithm has a greater encryption strength than the first type of cryptographic algorithm.

[0005] In some embodiments, a first ratio between the encrypted first data and the first data is smaller than a second ratio between the encrypted second data and the second data.

[0006] In some embodiments, the first type of cryptographic algorithm includes an Advanced Encryption Standard (AES) algorithm, and the second type of cryptographic algorithm includes a post-quantum cryptography (PQC) algorithm. In some embodiments, the second type of cryptographic algorithm includes a post-quantum cryptography (PQC) algorithm with fully homomorphic encryption (FHE). In some embodiments, the second type of cryptographic algorithm includes a lattice-based PQC algorithm.

[0007] In some embodiments, the controller is used to encrypt third data using a first type of cryptographic algorithm, and the third data is associated with a third security level that is less than the first security level, and the controller is used to encrypt the first data using a first key and encrypt the third data using a second key, and the size of the second key is less than the size of the first key.

[0008] In some embodiments, the controller is configured to store at least one of the encrypted first data or the encrypted second data in at least one memory device.

[0009] In some embodiments, the capacity of the first data is greater than the capacity of the second data. The capacity of the first data may be greater than the capacity of the second data by one or more orders of magnitude.

[0010] In some embodiments, the controller is used to control operations for the encrypted second data in at least one memory device.

[0011] In some embodiments, the operation on the encrypted second data includes at least one of the following: a computation between a first portion and a second portion of the encrypted second data, or a computation between the encrypted second data and other data encrypted using a second type of cryptographic algorithm.

[0012] In some embodiments, the controller is configured to transmit at least one of the encrypted first data or the encrypted second data to an external device.

[0013] In some embodiments, the controller includes: a first encryption engine for encrypting first data using a first type of cryptographic algorithm, and a second encryption engine for encrypting second data using a second type of cryptographic algorithm.

[0014] In some embodiments, the controller is configured to determine which security level the data is associated with and to encrypt the data based on the determined security level associated with the data.

[0015] In some embodiments, the controller is configured to: encrypt the first data using a first type of cryptographic algorithm in response to determining that the first data is associated with a first security level, and encrypt the second data using a second type of cryptographic algorithm in response to determining that the second data is associated with a second security level.

[0016] In some embodiments, the controller is configured to determine which security level data the data is associated with based on a security label for the data, the security label for the data corresponding to the security level associated with the data.

[0017] In some embodiments, the controller is configured to determine the security tag for the data by receiving the security tag for the data from a host device.

[0018] In some embodiments, the host device includes a security tag module for determining a security tag associated with the data.

[0019] In some embodiments, the controller is configured to determine a security tag for the data based on one or more characteristics of the data.

[0020] In some embodiments, the one or more characteristics of the data include at least one of the source of the data or the importance level of the data.

[0021] In some embodiments, the controller includes an error correction code (ECC) circuit, which includes at least one of the following aspects: one or more minimum sum (Min-Sum, MS) low-density parity-check (LDPC) decoders, or one or more bit-flipping-based lite LDPC decoders.

[0022] In some embodiments, at least one memory device includes one or more NAND flash memory chips and the storage device includes a solid-state drive (SSD).

[0023] Another aspect of the present disclosure is characterized by a storage device, including: at least one memory device and a controller coupled to the at least one memory device, and the controller is used to: determine which security level data is associated with at multiple security levels, and encrypt the data with a corresponding cryptographic algorithm of multiple cryptographic algorithms based on the security level associated with the data. The multiple cryptographic algorithms include at least two different types of cryptographic algorithms, which have different cryptographic strengths. Each of the multiple security levels is associated with a corresponding one of the multiple cryptographic algorithms, and a higher security level corresponds to a cryptographic algorithm with a higher cryptographic strength.

[0024] In some embodiments, the controller is used to perform at least one of the following: storing encrypted data in at least one memory device, transmitting the encrypted data to a host device, performing operations on the encrypted data to generate an encryption result, or transmitting the encryption result to the host device.

[0025] In some embodiments, a controller is used to determine which security level the data is associated with based on a security tag for the data, the security tag for the data corresponding to the security level associated with the data, and wherein the controller is used to determine the security tag for the data based on at least one of the following aspects: receiving the security tag for the data from a host device, or determining the security tag for the data based on one or more characteristics of the data.

[0026] Another aspect of the present disclosure features a method for managing data security in a storage device. The method includes: determining which security level is associated with data in the storage device at a plurality of security levels; and encrypting the data with a corresponding cryptographic algorithm of a plurality of cryptographic algorithms according to the security level associated with the data. The plurality of cryptographic algorithms include at least two different types of cryptographic algorithms having different cryptographic strengths, and each security level is associated with a corresponding one of the plurality of cryptographic algorithms, with a higher security level corresponding to a cryptographic algorithm having a higher cryptographic strength.

[0027] Another aspect of the present disclosure features a method for managing data security in a storage device. The method includes: encrypting first data in the storage device using a first type of cryptographic algorithm, and encrypting second data in the storage device using a second type of cryptographic algorithm. The first data is associated with a first security level, and the second data is associated with a second security level higher than the first security level, and the second type of cryptographic algorithm has an encryption strength greater than the first type of cryptographic algorithm.

[0028] Embodiments of the above technology include methods, systems, circuits, computer program products, and computer-readable media. In one example, a method may include the above actions. In another example, a computer program product is suitable for implementation in a non-transitory machine-readable medium, which stores instructions executable by one or more processors. The instructions are used to cause the one or more processors to perform the above actions. A computer-readable medium stores instructions. The instructions are used to cause the one or more processors to perform the above actions when executed by the one or more processors.

[0029] In order to better understand the above and other aspects of the present disclosure, the following embodiments are specifically cited and described in detail with reference to the accompanying drawings. Other features, aspects and advantages will become apparent from the description, drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1A schematic diagram showing an example system including a storage device having one or more encryption engines.

[0031] Figure 2 A schematic diagram showing another example system including a storage device having an encryption engine.

[0032] Figure 3 A schematic diagram showing another example system including a storage device having at least two encryption engines.

[0033] Figure 4 An example flowchart showing the procedure of a symmetric key cryptography system.

[0034] Figure 5 An example flowchart showing the procedure of an asymmetric key cryptography system.

[0035] Figure 6 An example flowchart showing the procedure of a fully homomorphic encryption (FHE) cryptography system.

[0036] Figure 7 A schematic diagram showing an example cryptographic algorithm for encrypting data associated with different security levels.

[0037] Figure 8 A flowchart showing an example procedure for managing data security in a storage device.

[0038] The same reference numbers and names in each figure represent the same components. It should also be understood that the various exemplary embodiments shown in the figures are only illustrative representations and are not necessarily drawn to scale.

[0039]

Symbol Explanation

[0040] 100, 200, 300: System

[0041] 110: Device

[0042] 112: Device Controller

[0043] 113: Processor

[0044] 114: Internal Memory

[0045] 120, 220, 320, 620: Host Device

[0046] 122: Host Controller

[0047] 130, 230, 330: ECC circuit

[0048] 132: ECC encoder

[0049] 134: ECC decoder

[0050] 140, 340: Encryption circuit

[0051] 150, 250, 350: Memory device

[0052] 202, 302: Interface

[0053] 210, 310, 610: Storage devices

[0054] 212, 312: Controller

[0055] 232, 332: MS LDPC decoder

[0056] 240, 342, 344: Encryption Engine

[0057] 314, 322: Safety label module

[0058] 334: Lightweight LDPC Decoder

[0059] 400, 500, 600: Flowchart

[0060] 402: Encryption Key

[0061] 410, 512, 522, 622, 722: Plain text

[0062] 420, 516, 526, 612, 614, 618, 626: ciphertext

[0063] 510: Receiver

[0064] 514: Private key

[0065] 518, 624: Public key

[0066] 520: Sender

[0067] 524: Symmetric key

[0068] 616: Operation

[0069] 700: Example

[0070] 710, 712, 714, 716, 718: Level

[0071] 720, 724, 726, 728: algorithm

[0072] 800: Procedure

[0073] 802, 804: Steps DETAILED DESCRIPTION

[0074] The data cryptography system can include three data states: data in motion,

[0075] Data at rest and data in use. In some embodiments, symmetric key cryptography is used to protect data at rest, such as using the same encryption key to both encrypt and decrypt data. In some examples, a self-enrypting drive (SED) may be a hard disk drive (HDD) or a solid-state drive that is designed to automatically encrypt or decrypt disk data without user input or disk encryption software. In some embodiments, symmetric key cryptography is used to secure data in motion, such as using a key pair (public and private keys) for data encryption and decryption. The public key can be used to encrypt data and can be freely given, while the private key is used to decrypt encrypted data (e.g., cypher text) and is protected as the only key that can decrypt the encrypted data.

[0076] Quantum computing can enable decryption of encrypted data, for example using one or more quantum algorithms, such as Shor's algorithm (e.g., for symmetric key cryptography) or Grover's algorithm (e.g., for asymmetric key cryptography). The shortcomings of Grover's algorithm can be addressed, for example, by increasing (e.g., doubling or tripling) the key length. Quantum-safe cryptography techniques can be used to address the shortcomings of quantum computing for data cryptography. For example, post-quantum cryptography (PQC) can be used to address the shortcomings of Shor's algorithm with respect to asymmetric key cryptography. PQC algorithms can include code-based cryptography, lattice-based cryptography, multivarite cryptography, hash-based cryptography, or supersingular elliptic curve isogeny cryptography.

[0077] In some embodiments, homomorphic encryption (HE) is used to ensure the security of data. Homomorphic encryption is a form of encryption that allows operations to be performed on encrypted data without decrypting it. The result of the operation is retained in an encrypted form, which, when decrypted, is identical in output to the result produced with the operation performed on the unencrypted data. Homomorphic encryption can be used for privacy-preserving outsorced storage and computation. This allows data to be encrypted and remain encrypted externally (e.g., in a commercial cloud environment for data processing). Homomorphic encryption avoids the need to process data in the clear, thereby preventing attacks that could allow hackers to access the data while it is being processed. For confidential data, such as health diagnostic information, homomorphic encryption can be used to enable new services, such as by removing privacy barriers that prevent data sharing or improving the security of existing services.

[0078] Homomorphic encryption includes various types of encryption that can perform different types of operations on encrypted data. Operations can be presented as Boolean or arithmetic circuits. Homomorphic encryption can include partially homomorphic, somewhat homomorphic, leveled fully homomorphic, or fully homomorphic encryption (FHE). For example, FHE is a cryptographic system that supports arbitrary computations on ciphertext and enables the construction of programs for any desired function that can be run on encrypted input to produce encrypted results. Because FHE does not need to decrypt its input, FHE can be run by untrusted third parties without revealing its input and internal state. In some embodiments, PQC is used to implement FHE. For example, the lattice cryptosystem is not only quantum safe, but also implements fully homomorphic encryption and can be used to ensure the security of data usage.

[0079] Various embodiments of the present disclosure provide techniques for managing data security in a storage device, such as in a solid-state drive. Unlike a storage device having one level or type of cryptographic system for all data, the present technology enables the execution of different levels of cryptographic systems at different security levels of data, such as by labeling the data with corresponding security levels. The security levels of data may include a non-confidential level, a confidential level, a highly confidential level, and a top secret level. The levels of cryptographic systems may include different types of cryptographic algorithms, such as an Advanced Encryption Standard (AES) algorithm, a post-quantum cryptography (PQC) algorithm, such as PQC with fully homomorphic encryption (FHE) (e.g., lattice PQC). AES may have a key capacity (or key length) of 128, 192, or 256 bits, where a larger capacity indicates a greater encryption strength. In some examples, non-confidential data may be stored as plain text without encryption; confidential data may be encrypted using an AES algorithm (e.g., AES with a lower strength such as AES-128); highly confidential data may be encrypted using an enhanced AES algorithm (e.g., AES with a higher strength such as AES-192 or AES-256); and top secret data may be encrypted using a PQC with FHE (PQC-FHE) algorithm. In this manner, top secret data may be protected against quantum attacks using the PQC algorithm. Similarly, because the cost of using the PQC algorithm for encryption is much higher than general encryption (e.g., AES), this technique enables only data with a top secret level to be selected for PQC encryption, which can provide protection for top secret data without significantly increasing the management burden (e.g., cost, computing, and storage resources) of the storage device.

[0080] In some embodiments, the storage device includes at least two types of encryption engines for encrypting data using different types of cryptographic algorithms, such as AES and PQC. In some embodiments, the storage device includes an Error Correction Code (ECC) circuit, and the ECC circuit may include one or more encoders / decoders, such as a low-density parity-check (LDPC) encoder / decoder. The LDPC decoder may include a minimum sum (Min-Sum, MS) LDPC decoder or a low-cost bit-flipping-based lite LDPC decoder. Compared to having only one encryption engine (such as an AES encryption engine), in order to compensate for the hardware management burden of the encryption part (such as a PQC encryption engine), the ECC circuit may include a smaller number of MS LDPC decoders, or include one or more low-cost bit-flipping-based lite LDPC decoders to replace one or more MS LDPC decoders.

[0081] In some embodiments, the security tag is determined directly by the host device (e.g., from the user) or may follow specific rules. For example, data from a specific computer and / or user or specific data may be marked as having the highest confidentiality level to be encrypted using a cryptographic algorithm with the highest encryption strength (e.g., PQC-FHE). Elements for implementing the security tag may be included in the host device, in the storage device, or in both the host device and the storage device.

[0082] The technology implemented herein can be applied to different types of storage devices, such as volatile memory devices or non-volatile memory devices, such as NAND flash memory, NOR flash memory, resistive random-access memory (RRAM), phase change memory (PCM) such as phase change random access memory (PCRAM), spin transfer torque (STT) magnetic random access memory (MRAM), or others. The technology can also be applied to charge trapping based memory devices, such as silicon-oxygen-nitrogen-oxygen-silicon (SONOs) memory devices and floating gate based memory devices. The technology can be applied to 2D memory devices or 3D memory devices. The technology may be applied to various memory types, such as single-level cell (SLC) devices, multi-level cell (MLC) devices such as 2-level cell devices, triple-level cell (TLC) devices, quad-level cell (QLC) devices, or penta-level cell (PLC) devices. Additionally or alternatively, the technology may be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC), or solid-state drives (SSD) (consumer SSD and / or enterprise SSD), hard disk drives (HDD), cloud computing or cloud distributed storage devices or systems, embedded systems, or others. These devices and systems may be applied to protect confidential government data, financial data, and / or military data.

[0083] Figure 1An example system 100 is shown including a storage device having one or more encryption engines. The system 100 includes a device 110 and a host device 120. The host device 120 includes a host controller 122 including at least one processor and at least one memory coupled to the at least one processor and storing program instructions for execution by the at least one processor to implement one or more corresponding operations.

[0084] In some embodiments, the device 110 is a storage device. For example, the device 110 may be an embedded multi-media card (eMMC), a secure digital (SD) card, a solid state drive (SSD), or other suitable storage. In some embodiments, the device 110 is a smart watch, a digital camera, or a media player. In some embodiments, the device 110 is a client device coupled to the host device 120. For example, the device 110 is an SD card used in a digital camera or a media player of the host device 120.

[0085] In some embodiments, the host device 120 is coupled to one or more devices 110 (eg, SSDs). Each device 110 may include a device controller 112 and one or more memory devices 150, each coupled to the device controller 112. The memory devices 150 may include memory chips, such as NAND flash memory chips.

[0086] Device controller 112 is a general purpose microprocessor or an application specific microprocessor. In some implementations, device controller 112 is a memory controller for device 110. The various techniques described in the following paragraphs are based on implementations where device controller 112 is a memory controller. However, the various techniques described in the following paragraphs can also be applied to implementations where device controller 112 is a type of controller other than a memory controller.

[0087] In some embodiments, the device controller 112 includes a processor 113 and an internal memory 114. The processor 113 is used to execute instructions and process data. The instructions include firmware instructions and / or other program instructions, which are stored as firmware code and / or other program code in the secondary memory, respectively. The data includes program data corresponding to the firmware and / or other program instructions executed by the processor, and other suitable data. In some embodiments, the processor 113 is a general-purpose microprocessor or a specific application microprocessor. The processor 113 can also be referred to as a central processing unit (CPU).

[0088] The processor 113 accesses instructions and data from the internal memory 114. In some embodiments, the internal memory 114 is a static random access memory (SRAM) or a dynamic random access memory (DRAM). For example, in some embodiments, when the device 110 is an eMMC, an SD card, or a smart watch, the internal memory 114 is an SRAM. In some embodiments, when the device 110 is a digital camera or a media player, the internal memory 114 is a DRAM.

[0089] In some embodiments, the internal memory 114 is a flash memory included in the device controller 112. The internal memory 114 stores instruction codes corresponding to instructions executed by the processor 113 and / or data required by the processor 113 during operation.

[0090] The device controller 112 transmits instruction codes and / or data from one or more memory devices 150 to the internal memory 114. In some embodiments, the memory device 150 is a storage device or non-volatile memory (NVM) for long-term storage of instructions and / or data, such as NAND flash memory or some other suitable non-volatile memory device. In embodiments where the memory device 150 is a NAND flash memory chip, the device 110 is a flash memory device, such as a flash memory card, and the device controller 112 is a NAND flash controller. For example, in some embodiments, when the device 110 is an eMMC or SD card, the memory device 150 is a NAND flash memory; in some embodiments, when the device 110 is a digital camera, the memory device 150 is an SD card; in some embodiments, when the device 110 is a multimedia player, the memory device 150 is a hard disk.

[0091] In some embodiments, the device controller 112 is used to receive data and commands from the host device 120 and send data to the host device 120. The device controller 112 is further used to send data and commands to the memory device 150 and receive data from the memory device 150. For example, the device controller 112 is used to send data and write commands to instruct the memory device 150 to store data at a specific address. In other examples, the device controller 112 is used to receive a read request (or read command) from the host device 120 and send a corresponding read command to the memory device 150 to read data from a specific address in the memory device 150.

[0092] As in Figure 1As shown in FIG. 1 , in some embodiments, the device controller 112 includes an ECC circuit 130. The ECC circuit 130 may include an ECC encoder 132 and an ECC decoder 134. In some embodiments, the ECC circuit 130 may be configured to be externally coupled to the device controller 112.

[0093] The ECC encoder 132 may be used to receive data to be stored in the memory device 150 and generate check bits, such as by encoding the data using an ECC encoding scheme. The check bits may be referred to as ECC data. The ECC encoder 132 may include a Reed Solomon encoder, a BCH (

[0094] The ECC decoder 134 may be used to decode data read from the memory device 150 to achieve the correction capability of the ECC method to detect and correct any bit errors that may occur in the data. The ECC decoder 134 may perform BCH decoding or LDPC decoding. In some examples, the ECC decoder 134 includes one or more MS LDPC decoders. In some examples, the ECC decoder 134 includes one or more bit-flipping based lightweight LDPC decoders. The MS LDPC decoder may have better decoding capability and faster decoding speed than the bit-flipping based lightweight LDPC decoder, and the lightweight LDPC decoder may have a lower cost than the MS LDPC decoder.

[0095] In some embodiments, for example Figure 1 As shown in , the device controller 112 includes an encryption circuit 140 including one or more encryption engines. Each encryption engine is used to encrypt data using a corresponding type of cryptographic algorithm (or encryption algorithm). The encryption engine may include one or more logic units or circuits or a combination thereof. Figure 3 and Figure 7 As described in more detail in , the device controller 112 can be used to encrypt data with different security levels using cryptographic algorithms with different cryptographic strengths (or encryption strengths). In this manner, data with a higher security level can be encrypted or secured with a corresponding cryptographic algorithm with a higher encryption strength. In some embodiments, the encryption circuit 140 is configured in the device 110 but is externally coupled to the device controller 112. The encryption circuit 140 can encrypt data from the host device 120 and transmit the encrypted data to the device controller 112 or the memory device 150 (which can be multiple).

[0096] In some embodiments, as referenced Figure 4As described, an encryption engine is used to encrypt data using a symmetric key cryptography algorithm, such as AES or Triple Data Encryption Standard (3DES or TEDS). The symmetric key cryptography algorithm can be used to secure data at rest.

[0097] In some examples, 3DES uses three 56-bit keys. In some examples, the AES algorithm has a 128-bit key, a 192-bit key, or a 256-bit key, where a larger key capacity represents greater encryption strength. The AES algorithm can be combined with the Galois / Counter Mode (GCM), which is also referred to as AES-GCM with a 256-bit key. Note that AES algorithms with different key sizes can be considered the same type of cryptographic algorithm.

[0098] Figure 4 An example flowchart 400 depicting the process of a symmetric key cryptography system is shown. In a symmetric key cryptography system, the same encryption key 402 is used to encrypt data (such as plaintext 410) and decrypt data (such as ciphertext 420) simultaneously. In some examples, both the sender (such as Figure 1 the master device 120) and the receiver (such as Figure 1 the device 110) share a single encryption key 402. The sender uses the encryption key 402 to encrypt the plaintext 410 to produce ciphertext 420. Then, the ciphertext 420 is sent to the receiver, and the receiver can apply the same encryption key 402 to decrypt the ciphertext 420 and recover the plaintext 410 from the master device. The symmetric key cryptography system can be used to protect data at rest.

[0099] In some embodiments, as described with reference to Figure 5 an encryption engine is used to encrypt data using an asymmetric key (or public key) cryptography algorithm. The asymmetric key cryptography algorithm can be used to secure data in motion. The asymmetric key cryptography algorithm can include, for example, the RSA (Rivest-Shamir-Adleman) asymmetric algorithm or the Elliptic Curve Cryptography (ECC) asymmetric algorithm. The RSA asymmetric algorithm can have a key capacity of 1024 bits to 2048 bits to maintain sufficient cryptographic strength. The ECC asymmetric algorithm can provide the same level of cryptographic strength with a smaller key capacity than the RSA asymmetric algorithm, providing improved security while reducing computational and storage requirements.

[0100] In some examples, an encryption engine is used to encrypt data using a post-quantum cryptography (PQC) algorithm, which is used to secure the data against cryptographic attacks by quantum computers.

[0101] The PQC algorithm can be implemented using an asymmetric key algorithm. The PQC algorithm can include: code-based cryptography, lattice-based cryptography, multivariate cryptography, hash-based cryptography, or Supersingular elliptic curve isogeny cryptography.

[0102] Figure 5 An example flowchart 500 of a procedure of an asymmetric key cryptography between a sender 520 (e.g., Figure 1 the main device 120) and a receiver 510 (e.g., Figure 1 the device 110). The asymmetric key cryptography is a key pair (public key 518 and private key 514) for encryption and decryption. The public key 518 is used to encrypt data (e.g., plaintext 522) and can be freely given. The private key 514 is used to decrypt the encrypted data (e.g., ciphertext 526). The private key 514 is safeguarded as the only key that can decrypt the encrypted data.

[0103] In some examples, the sender 520 uses a symmetric key 524 to encrypt the plaintext 522 to obtain a ciphertext 516. Both the ciphertext 516 and the symmetric key 524 can be encrypted using the public key 518 to obtain a ciphertext 526. The sender 520 can then send the ciphertext 526 to the receiver 510. The receiver 510 can first use the private key 514 to decrypt the ciphertext 526 to obtain the symmetric key 524 and the ciphertext 516. Then the receiver 510 can use the decrypted symmetric key 524 to decrypt the ciphertext 516 to obtain the plaintext 512. In this way, even if the receiver 510 does not store the symmetric key 524, the receiver 510 can obtain the symmetric key 524 by decrypting the ciphertext 526 transmitted from the sender 520.

[0104] In some embodiments, in some embodiments, as referenced Figure 6As described, the encryption engine is used to encrypt data using a homomorphic encryption algorithm, allowing operations to be performed on the encrypted data without first decrypting it. Homomorphic encryption cryptographic algorithms can be used to ensure the security of the data used. Homomorphic encryption includes multiple types of encryption methods that can perform different types of operations on the encrypted data. The operations can be presented as Boolean or arithmetic circuits. In some examples, a type of homomorphic encryption includes partial homomorphism, somewhat homomorphism, layered fully homomorphism, or fully homomorphic encryption (FHE). In some embodiments, the encryption engine is used to encrypt data using a PQC algorithm with FHE (or PQC-FHE), such as a lattice PQC algorithm that is not only quantum safe, but also fully homomorphic encryption. In some cases, learning with error (LWE) can be used in a cryptographic system to produce a secure encryption algorithm such as the PQC-FHE algorithm.

[0105] Figure 6 As shown in the main device 620 (eg Figure 1 host device 120) and storage device 610 (eg Figure 1 600 is an example flow chart of a procedure for a fully homomorphic encryption (FHE) cryptographic system between devices 110). The storage device 610 may be a solid state drive (SSD).

[0106] As in Figure 6 As shown in , a host device 620 may encrypt a plaintext 622 with a public key 624 using a FHE cryptographic algorithm (e.g., PQC-FHE or lattice PQC) to generate a ciphertext 626. The host device 620 sends the ciphertext 626 to a storage device 610. The storage device 610 may perform an operation 616 on the ciphertext 612 and the ciphertext 614 to obtain a new ciphertext 618, which may be a function of the ciphertext 612 and the ciphertext 614. In some examples, the ciphertext 612 and the ciphertext 614 may be different parts of the ciphertext 626. In some examples, the ciphertext 612 may be the ciphertext 626, and the ciphertext 614 may be another ciphertext encrypted by the host device 620 using the same FHE cryptographic algorithm. The storage device 610 and the host device 620 may have an agreement that allows the storage device 610 to perform an operation 616 on the ciphertext 612 and the ciphertext 614 without decrypting the ciphertext 612 and the ciphertext 614. The storage device 610 may further transmit the ciphertext 618 to the host device 620, and the host device 620 is used to decrypt the ciphertext 618 using the FHE cryptographic algorithm having a private key corresponding to the public key 624. In this manner, the FHE cryptographic algorithm can be used to ensure the security of the data used.

[0107] Each encryption engine is used to encrypt data using a corresponding type of cryptographic algorithm (or encryption algorithm). Symmetric key cryptographic algorithms, asymmetric key cryptographic algorithms, and homomorphic encryption algorithms can be considered different types of cryptographic algorithms. For example, AES and PQC (PQC with FHE) can be considered different types of cryptographic algorithms. AES (or 3DES) and RSA (or ECC asymmetric algorithm) can also be considered different types of cryptographic algorithms. RSA (or ECC asymmetric algorithm) and PQC (PQC with FHE) can also be considered different types of cryptographic algorithms.

[0108] Figure 2 Another example system 200 is shown including a storage device 210 having an encryption engine. The system 200 may be implemented as Figure 1 The system 100. Figure 2 As shown in FIG. 1 , the system 200 includes a main device 220 (eg, Figure 1 host device 120) and storage device 210 (e.g. Figure 1 The storage device 210 may include a controller 212 (e.g. Figure 1 device controller 112) and one or more memory devices 250 (e.g. Figure 1 The memory device 250 may include a NAND memory chip. The storage device 210 may include a solid state drive (SSD). The storage device 210 is used to communicate with the host device 220 through the interface 202.

[0109] In some embodiments, the storage device 210 includes an encryption engine 240 for encrypting data (e.g., from the host device 220) using a type of cryptographic algorithm, such as a symmetric key algorithm such as AES, an asymmetric key algorithm such as RSA or PQC, or a homomorphic encryption algorithm such as FHE. The encryption engine 240 can be implemented as Figure 1 The encryption circuit 140 is provided.

[0110] In some embodiments, the storage device 210 includes an ECC circuit 230 (eg, Figure 1 The ECC circuit 230 may include one or more ECC decoders (e.g. Figure 1 In some implementations, the ECC circuit 230 includes a plurality of MS LDPC decoders 232 to improve the performance of the ECC circuit 230 and the storage device 210.

[0111] Figure 3 Another example system 300 is shown including a storage device 310 having at least two encryption engines. The system 300 may be implemented as Figure 1The system 100. Figure 3 As shown in FIG. 1 , the system 300 includes a main device 320 (eg, Figure 1 The main device 120 or Figure 2 host device 220) and storage device 310 (e.g. Figure 1 The storage device 310 may include a controller 312 (e.g. Figure 1 device controller 112) and one or more memory devices 350 (e.g. Figure 1 The memory device 150 or Figure 2 The memory device 350 may include a NAND memory chip. The storage device 310 may include a solid state drive (SSD). The storage device 310 is used to communicate with the host device 320 through the interface 302.

[0112] Different from Figure 2 The storage device 210 includes an encryption engine 240, and the storage device 310 includes an encryption circuit 340 having at least two encryption engines, encryption engine 342 and encryption engine 344. The encryption circuit 340 can be implemented as Figure 1 The encryption circuit 340 may be configured to encrypt data with different security levels using different types of cryptographic algorithms through corresponding encryption engines. As described above, different types of cryptographic algorithms may have different cryptographic (or encryption) strengths. Different types of cryptographic algorithms may include two or more symmetric key algorithms such as AES, asymmetric key algorithms such as RSA or PQC, or homomorphic encryption algorithms such as FHE or PQC-FHE. The encryption engine 342 may be the same or similar to Figure 2 The encryption engine 344 may be different from the encryption engine 342 and different from the encryption engine 240. Figure 2 Encryption engine 240. Encryption engine 344 can be used to encrypt data with a higher encryption strength than encryption engine 342.

[0113] In some embodiments, for example Figure 3 As shown in FIG. 1 , encryption engine 342 is used to encrypt data using the AES algorithm, and encryption engine 344 is used to encrypt data using a PQC algorithm such as PQC-FHE. The PQC-FHE algorithm has a higher encryption strength than the AES algorithm and can be used to ensure data security at a higher security level, such as in Figure 7 More detailed description in .

[0114] In some embodiments, when the AES algorithm can use keys of different sizes, the encryption engine 342 can be used to encrypt data at different security levels using keys of different sizes. For example, an AES algorithm with a 256-bit key can be used to encrypt first data, an AES algorithm with a 192-bit key can be used to encrypt second data, and an AES algorithm with a 128-bit key can be used to encrypt third data. The first data can have a higher security level than the second data, and the second data can have a higher security level than the third data.

[0115] In some examples, using the AES algorithm, the encryption engine 342 encrypts data to obtain encrypted data. The first ratio between the encrypted data and the data using the AES algorithm is equal to 1. In some examples, using the PQC-FHE algorithm, the encryption engine 344 encrypts data to obtain encrypted data. The second ratio between the encrypted data and the data using the PQC-FHE algorithm is greater than 1. In some cases, the second ratio may be greater than 1 by one or more orders of magnitude, such as 30 to 100 or more, or greater than 1000. The encryption engine 344 may consume more computing resources than the encryption engine 342, such as higher cost computing power consumption and / or storage space. The encryption engine 344 may also have a lower encryption speed than the encryption engine 342.

[0116] The storage device 310 includes an ECC circuit 330 (eg Figure 1 The ECC circuit 330 may include one or more ECC decoders (e.g. Figure 1 In some embodiments, the ECC circuit 330 includes one or more MSLDPC decoders 332, which are smaller than Figure 2 In some embodiments, the ECC circuit 330 includes one or more bit-flipping based light LDPC decoders 334. In some embodiments, the ECC circuit 330 includes at least one MS LDPC decoder 332 and at least one light LDPC decoder 334.

[0117] In some embodiments, the controller 312 determines which security level the data is associated with at multiple security levels, and encrypts the data with a corresponding cryptographic algorithm of the multiple cryptographic algorithms based on the security level associated with the data. Each security level can be associated with a corresponding cryptographic algorithm (e.g., AES-128, AES-192, AES-256, or PQC-FHE). The relationship between the multiple security levels and the cryptographic algorithms can be stored in the storage device 310 (e.g., in the controller 312). The controller 312 can select a corresponding encryption engine, such as encryption engine 342 or encryption engine 344, based on the corresponding cryptographic algorithm associated with the determined security level.

[0118] Figure 7 An example 700 of an example cryptographic algorithm for encryption of data associated with different security levels is shown. Figure 7 As shown in FIG. 7 , each security level 710 may include: an unconfidential level 712, a confidential level 714, a highly confidential level 716, and a top secret level 718. Multiple cryptographic algorithms 720 may include: a first AES algorithm 724, a second AES algorithm 726, and a PQC-FHE algorithm 728. The second AES algorithm 726 may have a higher encryption strength than the first AES algorithm 724. The first AES algorithm 724 may be used to protect data at rest, while the second AES algorithm 726 may be used to protect data in motion and selectively protect data at rest.

[0119] In some examples, such as Figure 4 As shown in , the first AES algorithm 724, as a symmetric key cryptosystem, can be used to protect data at rest, such as by using the same key to encrypt and decrypt data simultaneously, such as in a self-encrypting disk (SED). In some examples, such as in Figure 5 As shown in FIG. 1 , the second AES algorithm 726 may be applied to protect mobile data. The second AES algorithm 726 may be used to use a symmetric key (e.g. Figure 5 The symmetric key 524) encrypts the original data (e.g. Figure 5 Next, the encrypted data (e.g. Figure 5 The ciphertext 526) can be transmitted to the storage device (e.g. Figure 5 The storage device may be a SSD. In some cases, the storage device may directly store the encrypted data without decryption. In some other cases, the storage device may decrypt the encrypted data to obtain the original data, and then encrypt the original data again using the first AES algorithm 724.

[0120] The PQC-FHE algorithm 728 may have the highest encryption strength (e.g., quantum-safe encryption) among multiple cryptographic algorithms. In some embodiments, such asFigure 7 As shown in FIG. 7 , first data having a non-confidential level 712 may be stored as plain text 722 without encryption, second data having a confidentiality level 714 may be encrypted using a first AES algorithm 724 (e.g., AES-128 or AES-192), third data having a high confidentiality level may be encrypted using a second AES algorithm 726 (e.g., AES-256), and fourth data having a highest confidentiality level 718 may be encrypted using a PQC-FHE algorithm 728. In this manner, the fourth data having the highest confidentiality level 718 may be protected against quantum computing attacks using the PQC-FHE algorithm 728.

[0121] As described above, because data encryption using the PQC-FHE algorithm 728 may consume a large amount of computing resources and storage space, the capacity of the fourth data (having the highest confidentiality level 718) may be smaller than the capacity of the first data, the capacity of the second data, or the capacity of the third data. For example, the capacity of the fourth data may be no more than 1% of the capacity of the first data, the capacity of the second data, or the capacity of the third data. Similarly, the capacity of the third data may be smaller than the capacity of the second data, and the capacity of the second data may be smaller than the capacity of the first data. Compared to Figure 2 The storage device 210 uses a single encryption algorithm, such as Figure 3 The storage device 310 can improve performance by arranging data with different security levels to use different encryption algorithms.

[0122] Continue to refer to Figure 3 In some embodiments, the controller 312 determines a security level associated with the data based on a security tag for the data. In some embodiments, the controller 312 determines a security tag for the data by receiving a security tag for the data from a host device 320. The host device 320 may include a security identification module 322 for determining a security tag associated with the data. The security identification module 322 may be implemented in software (e.g., program instructions) or hardware (e.g., a logic unit or logic circuit). In some cases, the security identification module 322 determines a security tag associated with the data based on user input. In some cases, as described below, the security identification module 322 determines a security tag for the data based on one or more features of the data or specific rules.

[0123] In some embodiments, the controller 312 may include a security tag module 314 for determining a security tag associated with the data. The security tag module 314 may be implemented in software (e.g., program instructions) or hardware (e.g., logic units or logic circuits). The security tag module 314 may be used to determine a security tag for the data based on one or more features of the data or specific rules.

[0124] One or more characteristics of the data may include the source of the data (e.g., a specific computer or user) or the importance level of the data (e.g., specific data). As an example, government confidential data, data from financial institutions (e.g., financial information, account information, transfer information), military data, or other confidential data may be marked as the highest secret level (highest security level) or the highly confidential level. In comparison, public data (e.g., newspapers or publications) may be marked as the unconfidential level (lowest security level). As another example, data from a company's senior management (such as the Chief Executive Officer (CEO), Chief Financial Officer (CFO), Chief Technology Officer (CTO)) may be marked as the highest secret level; in comparison, data from a company's manager or director may be marked as the highly confidential level, data from a company's employees may be marked as the confidential level, and data about the company's public information may be marked as the unconfidential level.

[0125] Figure 8 A flow chart of an example process 800 for managing data security in a storage device is shown. The storage device may be Figure 1 Device 110 or Figure 3 The storage device 310 may include at least one memory device (e.g. Figure 1 The memory device 150 or Figure 3 Memory device 350) and a controller (e.g. Figure 1 The device controller 112 or Figure 3 The at least one memory device may include one or more NAND flash memory chips, and the storage device may include a solid state drive (SSD). The process 800 may be executed by the controller.

[0126] In step 802, the controller determines which security level the data is associated with at a plurality of security levels. The plurality of security levels may include, for example, Figure 7 As shown in the , unclassified level, confidential level, highly confidential level and top secret level.

[0127] In some embodiments, the controller is configured to determine which security level data the data is associated with based on a security tag for the data, the security tag for the data corresponding to the security level associated with the data. In some embodiments, the controller is configured to determine which security level data the data is associated with based on a security tag for the data, the security tag for the data corresponding to the security level associated with the data. Figure 1 The main device 120 or Figure 3 The host device 320 receives the security tag for the data to determine the security tag for the data. Figure 3 As shown in FIG. , the main device may include a safety indicator module (eg Figure 3In some embodiments, the controller is used to determine the security tag for the data based on one or more characteristics or specific rules of the data. The controller may include a security tag module (e.g. Figure 3 The security label module 314 is used to determine a security label for the data. The one or more characteristics of the data may include at least one of the source of the data or the importance level of the data.

[0128] In step 804, the controller encrypts the data using a corresponding cryptographic algorithm of a plurality of cryptographic algorithms according to a security level associated with the data. The plurality of cryptographic algorithms include at least two different types of cryptographic algorithms having different cryptographic strengths. Each security level is associated with a corresponding one of the plurality of cryptographic algorithms, and a higher security level corresponds to a cryptographic algorithm having a higher cryptographic strength.

[0129] In some examples, the controller encrypts the first data using a first type of cryptographic algorithm and encrypts the second data using a second type of cryptographic algorithm. The first data is associated with a first security level (e.g. Figure 7 The second data is associated with a second security level higher than the first security level (e.g. Figure 7 The second type of cryptographic algorithm (e.g. Figure 7 PQC-FHE algorithm 728) has a greater performance than the first type of cryptographic algorithm (e.g. Figure 7 The encryption strength of the AES algorithm 726).

[0130] In some cases, a first ratio between the encrypted first data and the first data is less than a second ratio between the encrypted second data and the second data. The second ratio may be greater than the first ratio by one or more orders of magnitude, such as 30 to 100 times or more.

[0131] In some examples, the first type of cryptographic algorithm includes an Advanced Encryption Standard (AES) algorithm, and the second type of cryptographic algorithm includes a Post-Quantum Cryptography (PQC) algorithm. The second type of cryptographic algorithm includes a Post-Quantum Cryptography (PQC) algorithm with Fully Homomorphic Encryption (FHE), such as a lattice PQC algorithm.

[0132] In some embodiments, the controller is configured to encrypt the third data using the first type of cryptographic algorithm, and the third data is associated with a third security level (eg, Figure 7 The controller may be configured to encrypt the first data with a first key and encrypt the third data with a second key, wherein the capacity of the second key (eg, 128 bits) is smaller than the capacity of the first key (eg, 192 bits or 256 bits).

[0133] In some embodiments, the capacity of the first data is greater than the capacity of the second data. The capacity of the first data may be greater than the capacity of the second data by one or more orders of magnitude, such as more than 100 or 1000.

[0134] In some embodiments, the controller is used to control operations for the encrypted second data in at least one memory device (eg Figure 6 Operation 616), for example, Figure 6 The operation for the encrypted second data includes at least one of the following: an operation between a first portion and a second portion of the encrypted second data, or an operation between the encrypted second data and other data encrypted using the second type of cryptographic algorithm. The controller performs the operation on the encrypted second data to generate an encrypted result (e.g. Figure 6 In some implementations, the controller transmits the encrypted result to the host device.

[0135] In some embodiments, the controller is used to store at least one of the encrypted first data or the encrypted second data in at least one memory device. In some embodiments, the controller is used to transmit at least one of the encrypted first data or the encrypted second data to the host device.

[0136] In some embodiments, the controller includes a first encryption engine (e.g. Figure 3 An encryption engine 342) for encrypting the first data using a first type of cryptographic algorithm, and a second encryption engine (e.g. Figure 3 An encryption engine 344) is used to encrypt the second data using a second type of cryptographic algorithm.

[0137] In some embodiments, the controller includes an error correction code (ECC) circuit (e.g. Figure 1 The ECC circuit 130 or Figure 3 The ECC circuit 330 includes at least one of the following aspects: one or more minimum sum (MS) low density parity check code (LDPC) decoders (e.g. Figure 3 MS LDPC decoder 332), or one or more bit-flip based lightweight LDPC decoders (e.g. Figure 3The ECC circuits with these types of LDPC can provide a way to balance the hardware cost. That is, if the hardware cost is increased due to the encryption circuit (for example, using a higher cost encryption circuit, such as an encryption circuit with an encryption engine using a PQC algorithm), it can be compensated by using ECC circuits with these types of LDPC (lower cost ECC circuits), but the present invention is not limited to ECC circuits with these types of LDPC.

[0138] The present disclosure and other examples may be implemented as one or more computer program products, for example, one or more modules of computer program instructions encoded on a computer-readable medium that are executed by a data processing device or control the operation of the data processing device. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, or one or more combinations thereof. The term "data processing device" includes all devices, equipment and machines for processing data, including, for example, a programmable processor, a computer or multiple processors or computers. In addition to hardware, this device may include program code that establishes the execution environment of the computer program in question, such as program code constituting processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations thereof.

[0139] The system may include all devices, equipment and machines for processing data, including, for example, a programmable processor, a computer or multiple processors or computers. In addition to hardware, the system may include program code that establishes the execution environment of the computer program in question, for example, program code constituting processor firmware, protocol stack, database management system, operating system or one or more combinations thereof.

[0140] A computer program (also referred to as a program, software, software application, instruction code, or program code) may be written in any form of programming language, including compiled or interpreted languages, and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored in a portion of a file that stores other programs or data (for example, one or more instruction codes stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (for example, files storing one or more modules, subroutines, or portions of program code). A computer program may be configured to execute on one computer or on multiple computers. The multiple computers may be located at one location or distributed at multiple locations and interconnected by a communications network.

[0141] The procedures and logic flows described herein may be performed by one or more programmable processors executing one or more computer programs to perform the functions described herein. The procedures and logic flows may also be performed by special purpose logic circuitry, and the apparatus may also be implemented by special purpose logic circuitry, for example, a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0142] Processors suitable for executing computer programs include, for example, both general-purpose microprocessors and special-purpose microprocessors, and any one or more processors of any type of digital computer. Generally speaking, the processor will receive instructions and data from a read-only memory or a random access memory or both. The basic elements of a computer may include a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer may also include or be operably coupled to one or more mass storage devices for storing data to receive data from the one or more mass storage devices, or to transmit data to the one or more mass storage devices, or both. Examples of the one or more mass storage devices are magnetic disks, magneto-optical disks, or optical disks. However, a computer need not have such devices. Computer-readable media suitable for storing computer program instructions and data may include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks. The processor and memory may be supplemented by or incorporated into a dedicated logic circuit.

[0143] Although many details may be described herein, these details should not be interpreted as limitations on the claimed or claimable scope of the present invention, but rather as descriptions of features for specific embodiments. Certain features described herein in separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented in multiple embodiments separately or in any suitable sub-combination. Furthermore, although several features may be described above as acting in certain combinations and even initially claimed as such, one or more features from the claimed combination may be excluded from the combination in some cases, and the claimed combination may be for sub-combinations or variations of sub-combinations. Similarly, although several operations are depicted in a particular order in the drawings, it should not be understood that these operations must be performed in the particular order shown or in a sequential order, or that all described operations must be performed to achieve the desired result.

[0144] Only a few examples and implementations are described. Variations, modifications, and enhancements based on the examples and implementations and other implementations may be accomplished based on what is disclosed.

[0145] In summary, although the present invention has been disclosed above with preferred embodiments and exemplary details, it is to be understood that these examples are intended to illustrate rather than to limit the present invention. Those skilled in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached claims.

Claims

1. A storage device, include: at least one memory device; as well as a controller coupled to the at least one memory device and configured to: A first data is encrypted using a first type cryptographic algorithm, and a second data is encrypted using a second type cryptographic algorithm. The first data is associated with a first security level, the second data is associated with a second security level higher than the first security level, and the second type of cryptographic algorithm has a greater encryption strength than the first type of cryptographic algorithm.

2. The storage device according to claim 1, in, A first ratio between the encrypted first data and the first data is smaller than a second ratio between the encrypted second data and the second data.

3. The storage device according to claim 1, in, The first type of cryptographic algorithm includes an Advanced Encryption Standard (AES) algorithm, and the second type of cryptographic algorithm includes a post-quantum cryptography (PQC) algorithm.

4. The storage device according to claim 3, in, The second type of cryptographic algorithm includes a post-quantum cryptography (PQC) algorithm with fully homomorphic encryption (FHE).

5. The storage device according to claim 1, in, The controller is used to encrypt a third data using the first type of cryptographic algorithm, and the third data is associated with a third security level that is smaller than the first security level, and wherein the controller is used to encrypt the first data using a first key and to encrypt the third data using a second key, and wherein the size of the second key is smaller than the size of the first key.

6. The storage device according to claim 1, in, The controller is used for storing at least one of the encrypted first data or the encrypted second data in the at least one memory device.

7. The storage device according to claim 1, in, The capacity of the first data is greater than the capacity of the second data.

8. The storage device according to claim 1, in, The controller is used to control an operation for the encrypted second data in the at least one memory device.

9. The storage device according to claim 8, in, An operation for the encrypted second data includes at least one of the following: A computation between a first portion and a second portion of the encrypted second data, or a computation between the encrypted second data and other data encrypted using the second type of cryptographic algorithm.

10. The storage device according to claim 1, in, The controller is used for transmitting at least one of the encrypted first data or the encrypted second data to an external device.

11. The storage device according to claim 1, in, The controller includes: a first encryption engine for encrypting the first data using the first type of cryptographic algorithm, and A second encryption engine is used to encrypt the second data using the second type of cryptographic algorithm.

12. The storage device according to claim 1, in, The controller is used to determine which security level the data is associated with and encrypt the data based on the determined security level associated with the data.

13. The storage device according to claim 12, in, The controller is used to: In response to determining that the first data is associated with the first security level, encrypting the first data using the first type of cryptographic algorithm, and In response to determining that the second data is associated with the second security level, the second data is encrypted using the second type of cryptographic algorithm.

14. The storage device according to claim 12, in, The controller is used to: Which of the security level data the data is associated with is determined based on a security label for the data, the security label for the data corresponding to the security level associated with the data.

15. The storage device according to claim 14, in, The controller is used to determine the security tag for the data by receiving the security tag for the data from a host device.

16. The storage device according to claim 13, in, The controller is used to determine the security tag for the data based on one or more characteristics of the data.

17. The storage device according to claim 1, in, The controller includes an error correction code (ECC) circuit, and the error correction code circuit includes at least one of the following aspects: One or more Min-Sum (MS) low-density parity-check (LDPC) decoders, or one or more bit-flipping-based lite LDPC decoders.

18. A storage device, include: at least one memory device; as well as a controller coupled to the at least one memory device and configured to: Determining, at a plurality of security levels, which security level the data is associated with; as well as encrypting the data using a corresponding one of a plurality of cryptographic algorithms according to the security level associated with the data, The cryptographic algorithms include at least two different types of cryptographic algorithms having different cryptographic strengths, and Each of the security levels is associated with a corresponding one of the cryptographic algorithms, with a higher security level corresponding to a cryptographic algorithm having a higher cryptographic strength.

19. The storage device according to claim 18, in, The controller is configured to perform at least one of the following: storing the encrypted data in the at least one memory device, transmitting the encrypted data to a host device, Performing an operation on the encrypted data to produce an encrypted result, or The encryption result is transmitted to the host device.

20. The storage device according to claim 18, in, The controller is configured to determine which security level the data is associated with based on a security tag for the data, the security tag for the data corresponding to the security level associated with the data, and wherein the controller is configured to determine the security tag for the data based on at least a portion of: The security tag for the data is received from a host device or determined based on one or more characteristics of the data.

21. A method for managing data security in a storage device, the method include: Determining, at a plurality of security levels, which security level the data in the storage device is associated with; as well as encrypting the data using a corresponding one of a plurality of cryptographic algorithms according to the security level associated with the data, The cryptographic algorithms include at least two different types of cryptographic algorithms having different cryptographic strengths, and Each of the security levels is associated with a corresponding one of the cryptographic algorithms, with a higher security level corresponding to a cryptographic algorithm having a higher cryptographic strength.

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