Display device

Abstract

A display device includes: pixels connected to scan lines, data lines, and emission control lines; a start signal generator configured to generate: a first start signal corresponding to a first transmission control signal supplied in a write period of a frame period in which a data signal is supplied; and a second start signal corresponding to a second transmission control signal supplied in a maintenance period in which the data signal is maintained in the frame period, and having a width different from that of the first start signal; a selector configured to supply a first start signal or a second start signal based on a control signal from the controller; and an emission driver configured to supply the first emission control signal or the second emission control signal to the emission control line based on the first start signal or the second start signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0163721, filed on November 22, 2023, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to a display device and a method of driving the display device. Background Art

[0004] As information technology develops, the importance of display devices, which are a connecting medium between users and information, increases. Accordingly, display devices such as liquid crystal display devices and organic light emitting display devices are increasingly being used.

[0005] Recent display devices provide a high-speed driving function of providing a user with an image that changes at a high frame frequency and a low-speed driving function of providing a user with an image that changes at a low frame frequency. To this end, one frame may include a writing period in which a data signal is supplied and at least one sustaining period in which light is emitted while the data signal is maintained. When a brightness difference is generated between the writing period and the sustaining period, display quality may deteriorate. Summary of the invention

[0006] The embodiment provides a display device capable of reducing or minimizing a brightness difference between a writing period and a sustain period included in one frame period, and a method of driving the display device.

[0007] According to one aspect of the present disclosure, a display device is provided, including: pixels connected to scan lines, data lines, and emission control lines; a start signal generator configured to generate: a first start signal corresponding to a first emission control signal, the first emission control signal being supplied in a write period of a frame period in which a data signal is supplied; and a second start signal corresponding to a second emission control signal and having a width different from that of the first start signal, the second emission control signal being supplied in a sustain period of the frame period in which the data signal is maintained; a selector configured to supply the first start signal or the second start signal based on a control signal from a controller; and an emission driver configured to supply the first emission control signal or the second emission control signal to the emission control line based on the first start signal or the second start signal.

[0008] The first start signal may include a first sub start signal and a second sub start signal, wherein a time from when the first sub start signal is supplied to when supply of the second sub start signal is suspended is a width of the first start signal.

[0009] The selector may be configured to supply the first start signal to the emission driver during the write period, and to supply the second start signal to the emission driver during the sustain period.

[0010] The width of the first start signal and the width of the second start signal may be set so that light generated in the pixel during the writing period and during the sustaining period has a brightness difference equal to or less than a threshold value.

[0011] The width of the first start signal and the width of the second start signal may be set so that the pixel emits light longer during the writing period than during the sustaining period.

[0012] The width of the first start signal and the width of the second start signal may be set so that the pixel emits light for a shorter time during the writing period than during the sustaining period.

[0013] The display device may further include: a temperature sensor configured to sense a temperature of the display device, wherein the start signal generator is configured to change a width of the first start signal or a width of the second start signal based on the temperature.

[0014] The display device may further include: a timing controller configured to control the emission driver and including a start signal generator, a controller, and a selector.

[0015] The transmit driver may include a selector.

[0016] A pixel among the pixels may include: a light emitting element for generating light corresponding to an amount of current flowing from a first power line to which a first electrode is connected to the light emitting element to a second power line to which a second electrode is connected; a first transistor connected between the first electrode of the light emitting element and the first power line and configured to control the amount of current corresponding to a voltage of a first node; a second transistor connected between one of the data lines and the first node and including a gate electrode connected to a first scan line; a third transistor connected between the first transistor and the first electrode of the light emitting element and including a gate electrode connected to a fourth scan line; and a fourth transistor connected between the first electrode of the light emitting element and a gate electrode supplied with an initialization voltage. a third power line of a source and including a gate electrode connected to a second scan line; a fifth transistor connected between a fourth power line supplied with a reference power source and a first node and including a gate electrode connected to the third scan line; a sixth transistor connected between the first power line and the first transistor and including a gate electrode connected to an emission control line; a first capacitor connected between the first node and a second node which is a common node between the first transistor and the third transistor; and a second capacitor connected between the first power line and the second node, and wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor include N-type transistors.

[0017] The first transistor may include a first gate electrode connected to the first node and a second gate electrode connected to the second node.

[0018] The start signal generator may be configured to change a width of the first start signal or a width of the second start signal corresponding to a dimming level.

[0019] The start signal generator may be configured to supply the first start signal or the second start signal to the selector during the writing period or the sustaining period.

[0020] The start signal generator may be configured to supply the first start signal or the second start signal to the selector during the write period, and supply the second start signal to the selector during the sustain period.

[0021] According to another aspect of the present disclosure, there is provided a method for driving a display device, the method comprising: supplying a first emission control signal based on a first start signal by an emission driver during a write period of a frame period in which a data signal is supplied; and supplying a second emission control signal based on a second start signal by the emission driver during a sustain period of the frame period in which the data signal is maintained, wherein a first emission period of the write period corresponding to the first emission control signal and a second emission period of the sustain period corresponding to the second emission control signal have different widths.

[0022] The method may further include: generating a first start signal and a second start signal; supplying the first start signal to the emission driver using the selector during the write period; and supplying the second start signal to the emission driver using the selector during the sustain period.

[0023] The width of the first start signal and the width of the second start signal may be set so that light generated during the first emission period and during the second emission period has a brightness difference equal to or less than a threshold value.

[0024] The second transmission period may be longer than the first transmission period.

[0025] The first transmission period may be longer than the second transmission period.

[0026] The method may further include sensing a temperature of the display device, and changing a width of the first start signal or a width of the second start signal based on the temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0028] Figure 2 It is a graphic Figure 1 One or more embodiments of a scan driver and an emission driver are shown in FIG.

[0029] Figure 3 is a diagram illustrating a pixel according to one or more embodiments of the present disclosure.

[0030] Figure 4 The diagram shows the drive during the write period. Figure 3 One or more embodiments of the pixel method are shown in the figure.

[0031] Figure 5 The diagram shows the driving during the sustain period. Figure 3 One or more embodiments of the pixel method are shown in the figure.

[0032] Fig. 6A and Figure 6B is a diagram illustrating the luminance of a pixel during a writing period and during a sustaining period.

[0033] Figure 7 is a diagram illustrating a timing controller according to one or more embodiments of the present disclosure.

[0034] Figure 8 is a diagram illustrating a transmit driver according to one or more embodiments of the present disclosure.

[0035] Fig. 9 is a diagram illustrating a first start signal and a second start signal when a writing period is brighter than a sustaining period.

[0036] Fig. 10A and Fig. 10B is a diagram illustrating an embodiment in which a first start signal is supplied.

[0037] Fig.11 is a diagram illustrating a first start signal and a second start signal when a sustain period is brighter than a write period.

[0038] Fig.12 is a diagram illustrating brightness of a writing period and a sustaining period according to one or more embodiments of the present disclosure.

[0039] Fig.13A and Fig. 13B is a diagram illustrating a transmission control signal according to one or more embodiments of the present disclosure.

[0040] Fig.14 is a diagram of a timing controller according to one or more embodiments of the present disclosure.

[0041] Fig.15 is a graph illustrating brightness corresponding to the temperature of a display device. DETAILED DESCRIPTION

[0042] Embodiments will now be described more fully below with reference to the accompanying drawings. However, the embodiments may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art.

[0043] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intervening elements may also be present. The same reference numerals indicate the same elements throughout.

[0044] The aspects of some embodiments of the present disclosure and the methods for realizing these aspects can be more easily understood by referring to the detailed description and drawings of the embodiments. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Accordingly, processes, elements and techniques that are redundant, irrelevant or unrelated to the description of the embodiments or that are unnecessary for those of ordinary skill in the art to fully understand the aspects of the present disclosure can be omitted. Unless otherwise stated, in the entire drawings and written descriptions, the same reference numerals, characters or combinations thereof refer to the same elements, and therefore, their descriptions can be omitted.

[0045] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments illustrated herein. When describing an embodiment, the use of "can", "may", or "may not" corresponds to one or more embodiments of the present disclosure. The present disclosure covers all modifications, equivalents, and substitutions within the scope of the ideas and techniques of the present disclosure. Further, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various technical interlocks and drives are possible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0046] It will be understood that when an element, layer, area or component is referred to as "connected to" another element, layer, area or component, the element, layer, area or component can be directly connected to the other element, layer, area or component, or can be indirectly connected to the other element, layer, area or component so that one or more intervening elements, layers, areas or components can exist. In addition, this can be collectively referred to as direct or indirect coupling or connection and overall or non-integral coupling or connection. For example, when a layer, area or component is referred to as "electrically connected" to another layer, area or component, the layer, area or component can be directly electrically connected to the other layer, area or component, or one or more intervening layers, areas or components can exist. One or more intervening components can include switches, resistors and / or capacitors, etc. When describing an embodiment, unless explicitly described as directly connected, the expression of connection represents electrical connection, and "direct connection" refers to a component directly connecting another component without an intervening component.

[0047] In addition, expressions describing relationships between components (such as, "between") may be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0048] For purposes of this disclosure, expressions such as “at least one of” or “any of” or “one or more of” when following a list of elements modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, for example, XYZ, XYY, YZ, and ZZ), or any variation thereof. Similarly, expressions such as “at least one of A and B” may include A, B, or A and B. As used herein, “or” generally means “and / or,” and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, “A and / or B” may include A, B, or A and B. Similarly, expressions such as “at least one of”, “a plurality of”, “one of” and other prepositional phrases when following a list of elements modify the entire list of elements and do not modify the individual elements of the list.

[0049] It will be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, areas, layers and / or sections in this article, these elements, components, areas, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or superiority, and are only used to distinguish an element, member, component, area, region, layer, section or part from another element, member, component, area, region, layer, section or part. Therefore, the first element, component, area, layer or section described below can be referred to as the second element, component, area, layer or section without departing from the spirit and scope of the present disclosure. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used to distinguish different categories or groups of elements in this article. For simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0050] The terms used herein are only for the purpose of describing the embodiments and are not intended to limit the present disclosure. As used herein, the singular form "a" is intended to also include the plural form, and the plural form is also intended to include the singular form, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "including", "having" and "comprising" indicate the presence of stated features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or their groups.

[0051] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially at the same time, or in the reverse order of the described order.

[0052] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms rather than terms of degree, and are intended to take into account the inherent deviations of measured values ​​or calculated values ​​that would be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. Taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the stated values ​​and mean within the acceptable deviation range of the specific value determined by those of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Further, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0053] In some embodiments, known structures and devices may be described in conjunction with one or more functional blocks (e.g., block diagrams), units and / or modules in the accompanying drawings to avoid unnecessary confusion of various embodiments. Those skilled in the art will appreciate that these blocks, units and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections or other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, optionally driven by firmware and / or software. In addition, each block, unit and / or module may be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) that performs functions different from the functions of the dedicated hardware. In addition, in some embodiments, blocks, units and / or modules may be physically divided into two or more interactive discrete blocks, units and / or modules without departing from the scope of this disclosure. Furthermore, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless specifically defined as such herein.

[0055] Figure 1 is a diagram illustrating a display device according to one or more embodiments of the present disclosure. Figure 2 It is a graphic Figure 1 One or more embodiments of a scan driver and an emission driver are shown in FIG.

[0056] refer to Figure 1 The display device 100 in one or more embodiments may include a pixel unit 110 (or a display panel), a data driver 120 , a scan driver 130 , an emission driver 140 , a power supply unit 150 , and a timing controller 160 .

[0057] The display device 100 can display images at various image refresh rates (e.g., driving frequency or picture refresh rate) according to driving conditions. The image refresh rate means the frequency at which the data signal is written to the driving transistor of the pixel PX. For example, the image refresh rate may also be referred to as the picture scan rate or the picture refresh frequency, and may indicate the frequency at which the display picture is reproduced within one second.

[0058] In one or more embodiments, the output frequency of the data driver 120 relative to a horizontal line (for example, pixels PX connected to the same scan line can be sorted into a horizontal line or a pixel row) and / or the output frequency of the scan driver 130 that outputs the scan signal can be determined corresponding to the image refresh rate.

[0059] For example, Figure 1 One scan line (each of SL1 to SLn) shown in FIG. 1 may include Figure 2 . That is, the scan line SL1 may include a first scan line SL11, a second scan line SL21, a third scan line SL31, and a fourth scan line SL41. The scan line SLn may include a first scan line SL1n, a second scan line SL2n, a third scan line SL3n, and a fourth scan line SL4n. The frequency of the first scan signal (or write scan signal) output from the first scan driver 132 may be determined by the image refresh rate.

[0060] The image refresh rate for driving the moving image may be a frequency of about 60 Hz or higher (e.g., about 120 Hz or about 240 Hz, etc.). For example, the display device 100 may display images corresponding to various image refresh rates of about 1 Hz to about 240 Hz. However, this is merely exemplary, and the display device 100 may also display images at an image refresh rate of about 240 Hz or higher (e.g., about 480 Hz).

[0061] The pixel unit 110 may include pixels PX connected to scan lines SL1 to SLn, data lines DL1 to DLm, emission control lines EL1 to ELn, and power lines PL1 , PL2 , PL3 , and PL4 (n and m are natural numbers of 2 or more).

[0062] When the enabled first scan signal is supplied to the first scan lines SL11 to SL1n, the pixels PX may be selected in units of horizontal lines, and each of the pixels PX selected by the enabled first scan signal may be supplied with a data signal from a data line (a corresponding one of DL1 to DLm) connected thereto. The pixels PX supplied with the data signal may generate light having a brightness (e.g., a predetermined brightness) corresponding to a voltage of the data signal.

[0063] The scan driver 130 may receive a scan driving signal SCS from the timing controller 160. At least one scan start signal and / or a clock signal suitable for driving the scan driver 130 may be included in the scan driving signal SCS. The scan driver 130 may generate an enabled first scan signal, an enabled second scan signal, an enabled third scan signal, and an enabled fourth scan signal while shifting the scan start signal corresponding to the clock signal.

[0064] To this end, the scan driver 130 may include a first scan driver 132, a second scan driver 134, a third scan driver 136, and a fourth scan driver 138. Figure 2 According to the design, at least some of the scan drivers 132, 134, 136 and 138 may be integrated into one driving circuit or one module, etc.

[0065] The first scan driver 132 may receive the first scan start signal FLM11, and may generate an enabled first scan signal while shifting the first scan start signal FLM11 corresponding to (e.g., based on) a clock signal. The first scan driver 132 may sequentially supply the enabled first scan signal to the first scan lines SL11 to SL1n. In one or more embodiments, the first scan driver 132 may supply the enabled first scan signal during a write period in an effective area of ​​one frame.

[0066] The second scan driver 134 may receive the second scan start signal FLM21, and may generate an enabled second scan signal while shifting the second scan start signal FLM21 corresponding to the clock signal. The second scan driver 134 may sequentially supply the enabled second scan signal to the second scan lines SL21 to SL2n. In one or more embodiments, the second scan driver 134 may supply the enabled second scan signal during a write period in an effective area of ​​one frame. In one or more embodiments, the second scan driver 134 may supply the enabled second scan signal during a maintenance period included in an effective area and a blank area of ​​one frame.

[0067] For example, the second scan driver 134 may perform one scan during the write period of one frame (e.g., at least one enabled second scan signal may be supplied), and may perform at least one scan during the maintenance period of one frame according to the image refresh rate. When the image refresh rate is reduced (e.g., when the frame length is extended), the blank area of ​​one frame may be extended, and therefore, the number of maintenance periods included in the blank area may increase. That is, when the image refresh rate is reduced, the number of times the operation of repeatedly supplying the enabled second scan signal may increase.

[0068] The third scan driver 136 may receive the third scan start signal FLM31 and may generate an enabled third scan signal while shifting the third scan start signal FLM31 corresponding to the clock signal. The third scan driver 136 may sequentially supply the enabled third scan signal to the third scan lines SL31 to SL3n. In one or more embodiments, the third scan driver 136 may supply the enabled third scan signal during a write period in an effective area of ​​one frame.

[0069] The fourth scan driver 138 may receive the fourth scan start signal FLM41 and may generate an enabled fourth scan signal while shifting the fourth scan start signal FLM41 corresponding to the clock signal. The fourth scan driver 138 may sequentially supply the enabled fourth scan signal to the fourth scan lines SL41 to SL4n. In one or more embodiments, the fourth scan driver 138 may supply the enabled fourth scan signal during a write period in an effective area of ​​one frame.

[0070] Each of the enabled first scan signal, the enabled second scan signal, the enabled third scan signal, and the enabled fourth scan signal may be set to a gate-on voltage so that a transistor included in the pixel PX may be turned on. Figure 3 As shown in , each of the enabled first scan signal, the enabled second scan signal, the enabled third scan signal, and the enabled fourth scan signal supplied to the N-type transistor may be set to a high level voltage.

[0071] The data driver 120 may receive the output data Dout and the data driving signal DCS from the timing controller 160. The data driving signal DCS may include a sampling signal and / or a timing signal suitable for driving the data driver 120. The data driver 120 may generate a data signal based on the data driving signal DCS and the output data Dout. For example, the data driver 120 may generate an analog data signal based on the grayscale of the output data Dout. The data driver 120 may supply the data signal in units of one horizontal period.

[0072] The emission driver 140 may receive an emission driving signal ECS from the timing controller 160. A start signal and a clock signal suitable for driving the emission driver 140 may be included in the emission driving signal ECS. The emission driver 140 may generate a disabled emission control signal while shifting the start signal corresponding to the clock signal.

[0073] In one or more embodiments, Figure 2As shown in , the start signal may include a first start signal FLM1 and a second start signal FLM2. The first start signal FLM1 may be a signal for supplying a disabled emission control signal (or a first emission control signal) in a write period, and the second start signal FLM2 may be a signal for supplying a disabled emission control signal (or a second emission control signal) in a sustain period. The first start signal FLM1 and the second start signal FLM2 may have different widths. This will be referred to later Figures 7 to 15 Described in detail.

[0074] The emission driver 140 may generate a disabled emission control signal while shifting the start signal FLM1 or FLM2 corresponding to the clock signal. The emission driver 140 may sequentially supply the disabled emission control signal to the emission control lines EL1 to ELn. The disabled emission control signal may be set to a gate-off voltage so that the transistor included in the pixel PX may be turned off. For example, Figure 3 As shown in , the disabled emission control signal supplied to the N-type transistor may be set to a low level voltage.

[0075] In one or more embodiments, the emission driver 140 may supply a prohibited emission control signal during a write period and a maintenance period of a frame. For example, the emission driver 140 may perform at least one scan during a write period of a frame, and may perform at least one scan according to an image refresh rate during a maintenance period of a frame. When the image refresh rate is reduced (for example, when the frame length is extended), the blank area of ​​a frame may be extended, and therefore, the number of maintenance periods included in the blank area may increase. That is, when the image refresh rate is reduced, the number of operations of repeatedly supplying a prohibited emission control signal may increase.

[0076] The timing controller 160 may receive input data Din and a timing control signal TCS from a host system through an interface. For example, the timing controller 160 may receive input data Din and a timing control signal TCS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), or an application processor (AP) that may be included in the host system. Various signals including a clock signal may be included in the timing control signal TCS.

[0077] The timing controller 160 may generate a scan driving signal SCS, a data driving signal DCS, and an emission driving signal ECS based on the timing control signal TCS. The scan driving signal SCS, the data driving signal DCS, and the emission driving signal ECS may be supplied to the scan driver 130, the data driver 120, and the emission driver 140, respectively.

[0078] The timing controller 160 may readjust the input data Din to be suitable for the specification of the display device 100. In addition, the timing controller 160 may generate output data Dout by correcting the input data Din, and supply the output data Dout to the data driver 120. In one or more embodiments, the timing controller 160 may correct the input data Din corresponding to an optical measurement result measured in a process.

[0079] The power supply unit 150 may generate various power supplies suitable for driving of the display device 100. For example, the power supply unit 150 may generate a first driving power supply VDD, a second driving power supply VSS, an initialization power supply VINT, and a reference power supply VREF.

[0080] The first driving power source VDD may be a power source that supplies a driving current to the pixel PX. The second driving power source VSS may be a power source that is supplied with a driving current from the pixel PX. During a period in which the pixel PX is in an emission state, the first driving power source VDD may be set to a voltage higher than a voltage of the second driving power source VSS.

[0081] The initialization power source VINT may be a power source that initializes the gate electrode of the driving transistor included in each of the pixels PX and the first electrode (or anode electrode) of the light emitting element. The reference power source VREF may be a power source that is supplied to the gate electrode of the driving transistor included in each of the pixels PX.

[0082] The first driving power VDD generated by the power supply unit 150 may be supplied to the first power line PL1, the second driving power VSS generated by the power supply unit 150 may be supplied to the second power line PL2, the initialization power VINT generated by the power supply unit 150 may be supplied to the third power line PL3, and the reference power VREF generated by the power supply unit 150 may be supplied to the fourth power line PL4. The first power line PL1, the second power line PL2, the third power line PL3, and the fourth power line PL4 may be commonly connected to the pixel PX, but the present disclosure is not limited thereto.

[0083] In one or more embodiments, the first power line PL1 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. In one or more embodiments, the second power line PL2 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. In one or more embodiments, the third power line PL3 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. In one or more embodiments, the fourth power line PL4 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX.

[0084] In one or more embodiments of the present disclosure, the display device 100 may include a flat panel display device, a curved display device in which a portion of the pixel unit 110 is bent, a flexible display device in which a portion of the pixel unit 110 can be folded or bent, and a stretchable display device in which a portion of the pixel unit 110 can be expanded / contracted.

[0085] In one or more embodiments of the present disclosure, the display device 100 is a device that displays a moving image or a still image, and may include portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, portable multimedia players (PMPs), navigation systems, and ultra mobile computers (UMPCs). In one or more embodiments of the present disclosure, the display device 100 may include electronic devices such as televisions, notebook computers, monitors, billboards, and Internet of Things (IOT) devices.

[0086] Figure 3 is a diagram illustrating a pixel according to one or more embodiments of the present disclosure. Figure 3 , a pixel PXij located at the i-th horizontal line and the j-th vertical line is illustrated.

[0087] refer to Figure 3 , the pixel PXij in one or more embodiments may be connected to the corresponding signal lines SLi, DLj and ELi. For example, the pixel PXij may be connected to the i-th scan line SLi, the i-th emission control line ELi and the j-th data line DLj (i is a positive integer less than n, and j is a positive integer less than m). The i-th scan line SLi may include a plurality of scan lines SL1i, SL2i, SL3i and SL4i. The pixel PXij may be further connected to the power lines PL1, PL2, PL3 and PL4.

[0088] The pixel PXij may include a light emitting element LD and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0089] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2. For example, the first electrode (e.g., the anode electrode) of the light emitting element LD may be connected to the first power line PL1 via the third node N3, the third transistor T3, the second node N2, the first transistor T1, and the sixth transistor T6. The second electrode (e.g., the cathode electrode) of the light emitting element LD may be connected to the second power line PL2. The light emitting element LD may generate light having a brightness corresponding to the amount of current supplied from the pixel circuit.

[0090] The light emitting element LD may be selected as an organic light emitting diode. In addition, the light emitting element LD may be selected as an inorganic light emitting diode such as a micro light emitting diode (LED) or a quantum dot light emitting diode. In addition, the light emitting element LD may be an element composed of a combination of an organic material and an inorganic material. Figure 3 , it is illustrated that the pixel PXij includes a single light emitting element LD. However, in one or more other embodiments, the pixel PXij may include a plurality of light emitting elements LD, and the plurality of light emitting elements LD may be connected in series, in parallel, or in series / parallel with each other.

[0091] The pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, a first capacitor Cst, and a second capacitor Chold. One or more of the first transistor T1 to the sixth transistor T6 may be an oxide semiconductor transistor. For example, in one or more of the first transistor T1 to the sixth transistor T6, the active layer (or semiconductor layer) may include an oxide semiconductor layer. In one or more embodiments, one or more of the first transistor T1 to the sixth transistor T6 may be an N-type oxide semiconductor transistor.

[0092] The first electrode of the first transistor T1 (or the driving transistor) may be connected to the second electrode of the sixth transistor T6, and the second electrode of the first transistor T1 may be connected to the second node N2. In addition, the first gate electrode of the first transistor T1 may be connected to the first node N1, and the second gate electrode (or the back gate electrode) of the first transistor T1 may be connected to the second node N2. The first transistor T1 may control the amount of current supplied from the first driving power source VDD to the second driving power source VSS via the light emitting element LD corresponding to the voltage of the first node N1.

[0093] The first transistor T1 may be formed as a double-gate transistor including a first gate electrode and a second gate electrode. When the second gate electrode is connected to the second node N2, a gate-source voltage and a driving current of the first transistor T1 may be stably maintained.

[0094] The second transistor T2 may be connected between the data line DLj and the first node N1. In addition, the gate electrode of the second transistor T2 may be connected to the first scan line SLi. When the enabled first scan signal GW (or the high-level first scan signal GW) is supplied to the first scan line SL1i, the second transistor T2 may be turned on to electrically connect the data line DLj and the first node N1 to each other.

[0095] The third transistor T3 may be connected between the second node N2 and the third node N3. The second node N2 refers to a node to which the second electrode of the first transistor T1 and the first electrode of the third transistor T3 are electrically connected. The third node N3 refers to a node to which the first electrode of the light emitting element LD is connected. The gate electrode of the third transistor T3 may be connected to the fourth scan line SL4i. When the enabled fourth scan signal GE (or the fourth scan signal GE of a high level) is supplied to the fourth scan line SL4i, the third transistor T3 may be turned on.

[0096] When the third transistor T3 is turned on, the second node N2 and the third node N3 may be electrically connected to each other, and accordingly, the first transistor T1 and the light emitting element LD may be electrically connected to each other. When the third transistor T3 is turned off, the second node N2 and the third node N3 may be electrically disconnected from each other, and accordingly, a current path through which the driving current can flow through the light emitting element LD may be blocked.

[0097] The fourth transistor T4 may be connected between the third node N3 and the third power line PL3. In addition, the gate electrode of the fourth transistor T4 may be connected to the second scan line SL2i. When the enabled second scan signal GI (or the high-level second scan signal GI) is supplied to the second scan line SL2i, the fourth transistor T4 may be turned on to electrically connect the third power line PL3 and the third node N3 to each other.

[0098] When the third power line PL3 and the third node N3 are electrically connected to each other, the voltage of the initialization power source VINT from the third power line PL3 may be supplied to the third node N3. Then, the parasitic capacitor equivalently formed in the light emitting element LD is discharged, and accordingly, the black expression capability of the pixel PXij may be improved.

[0099] The fifth transistor T5 may be connected between the fourth power line PL4 and the first node N1. In addition, the gate electrode of the fifth transistor T5 may be connected to the third scan line SL3i. When the enabled third scan signal GR (or the third scan signal GR of a high level) is supplied to the third scan line SL3i, the fifth transistor T5 may be turned on to electrically connect the fourth power line PL4 and the first node N1 to each other. When the fourth power line PL4 and the first node N1 are electrically connected to each other, the voltage of the reference power supply VREF may be supplied to the first node N1.

[0100] The sixth transistor T6 may be connected between the first power line PL1 and the first electrode of the first transistor T1. In addition, the gate electrode of the sixth transistor T6 may be connected to the emission control line ELi. When the prohibited emission control signal EM (or the emission control signal EM of a low level) is supplied to the emission control line ELi, the sixth transistor T6 may be turned off, and the sixth transistor T6 may be turned on in other cases. When the sixth transistor T6 is turned on, a current path through which a drive current can flow through the pixel PXij may be formed.

[0101] The first capacitor Cst may be connected between the first node N1 and the second node N2. A voltage corresponding to the data signal may be stored in the first capacitor Cst.

[0102] The second capacitor Chold may be connected between the first power line PL1 and the second node N2. The second capacitor Chold may stabilize the voltage of the second node N2.

[0103] Figure 4 The diagram shows the drive during the write period. Figure 3 One or more embodiments of the method for displaying a pixel as shown in FIG. The writing period WP may be included in the effective area of ​​the frame.

[0104] refer to Figure 3 and Figure 4 , in the method of driving the pixel PXij, the writing period WP may include a first period P1, a second period P2, a third period P3, a fourth period P4 and a fifth period P5.

[0105] The first period P1 may be a period in which the first capacitor Cst is initialized. The second period P2 may be a period in which the threshold voltage of the first transistor T1 is compensated. The third period P3 may be a period in which the voltage of the data signal is stored in the pixel PXij. The fourth period P4 may be a period in which the light emitting element LD is initialized. The fifth period P5 may be a period in which the pixel PXij (or the light emitting element LD) emits light.

[0106] During the first period P1, the enabled second scan signal GI may be supplied to the second scan line SL2i, the enabled third scan signal GR may be supplied to the third scan line SL3i, and the enabled fourth scan signal GE may be supplied to the fourth scan line SL4i. In addition, the disabled emission control signal EM may be supplied to the emission control line ELi.

[0107] When the disabled emission control signal EM is supplied to the emission control line ELi, the sixth transistor T6 may be turned off. When the sixth transistor T6 is turned off, the electrical connection between the first power line PL1 and the first transistor T1 may be blocked, and accordingly, the light emitting element LD may be in a non-emission state.

[0108] When the enabled second scan signal GI is supplied to the second scan line SL2i, the fourth transistor T4 may be turned on. When the fourth transistor T4 is turned on, the voltage of the initialization power supply VINT may be supplied to the third node N3. When the enabled fourth scan signal GE is supplied to the fourth scan line SL4i, the third transistor T3 may be turned on. When the third transistor T3 is turned on, the voltage of the initialization power supply VINT of the third node N3 may be supplied to the second node N2.

[0109] When the enabled third scan signal GR is supplied to the third scan line SL3i, the fifth transistor T5 may be turned on. When the fifth transistor T5 is turned on, the voltage of the reference power supply VREF may be supplied to the first node N1. When the voltage of the reference power supply VREF is supplied to the first node N1 and the voltage of the initialization power supply VINT is supplied to the second node N2, the first capacitor Cst and the second capacitor Chold may be initialized. That is, the first period P1 may be a period in which the pixel PXij is initialized so as not to be affected by the data signal supplied in the previous frame period.

[0110] During the second period P2, supply of the disabled emission control signal EM to the emission control line ELi may be suspended (or the enabled (high level) emission control signal EM may be supplied), and the enabled third scan signal GR may be supplied to the third scan line SL3i. The enabled third scan signal GR supplied to the third scan line SL3i may be supplied during the first period P1 and the second period P2.

[0111] When the disabled emission control signal EM is temporarily supplied to the emission control line ELi, the sixth transistor T6 may be turned on, and accordingly, the voltage of the first driving power supply VDD may be supplied to the first electrode of the first transistor T1. When the enabled third scan signal GR is supplied to the third scan line SL3i, the fifth transistor T5 may be turned on, and accordingly, the voltage of the reference power supply VREF may be supplied to the first node N1.

[0112] The voltage of the reference power supply VREF may be set so that the first transistor T1 can be turned on, and accordingly, the voltage of the second node N2 may increase corresponding to the current supplied from the first transistor T1. The voltage of the second node N2 may increase to a value obtained by subtracting the absolute threshold voltage of the first transistor T1 from the voltage of the reference power supply VREF. That is, during the second period P2, a voltage corresponding to the threshold voltage of the first transistor T1 may be stored in the first capacitor Cst.

[0113] Meanwhile, the width of the second period P2 may be determined by the supply time of the enabled emission control signal EM and / or the supply time of the enabled third scan signal GR. That is, in one or more embodiments of the present disclosure, the compensation time (e.g., the second period P2) of the threshold voltage of the first transistor T1 may be controlled using the supply time of the enabled emission control signal EM and the enabled third scan signal GR.

[0114] During the third period P3, the disabled emission control signal EM may be supplied, and accordingly, the sixth transistor T6 may be turned off. During the third period P3, the enabled first scan signal GW may be supplied to the first scan line SL1i. When the enabled first scan signal GW is supplied to the first scan line SL1i, the second transistor T2 may be turned on. When the second transistor T2 is turned on, the data signal from the data line DLj may be supplied to the first node N1.

[0115] During the third period P3 , voltages of the first node N1 and the second node N2 may be expressed as shown in Equation 1.

[0116] Equation 1

[0117] VN1=Vdata

[0118] VN2=VREF-Vth1

[0119] In Equation 1, VN1 may refer to a voltage of the first node N1, VN2 may refer to a voltage of the second node N2, Vdata may refer to a voltage of a data signal, and Vth1 may refer to a threshold voltage of the first transistor T1.

[0120] In Equation 1, for convenience of description, it has been described that the second node N2 maintains the voltage VREF-Vth1 during the third period P3. However, the present disclosure is not limited thereto.

[0121] For example, during the third period P3, the voltage of the first node N1 may change from the voltage of the reference power supply VREF to the voltage Vdata of the data signal, and the voltage of the second node N2 may also change due to the coupling of the first capacitor Cst. However, the voltage of the second node N2 changes corresponding to the ratio of the capacitance of the first capacitor Cst and the second capacitor Chold, and accordingly, the voltage change of the second node N2 may be reduced or minimized. Hereinafter, for ease of description, it is assumed that the second node N2 maintains the voltage VREF-Vth1 during the third period P3.

[0122] During the fourth period P4, the supply of the disabled emission control signal EM may be maintained, and the enabled second scan signal GI may be supplied to the second scan line SL2i. When the enabled second scan signal GI is supplied to the second scan line SL2i, the fourth transistor T4 may be turned on. When the fourth transistor T4 is turned on, the voltage of the initialization power supply VINT may be supplied to the third node N3. When the voltage of the initialization power supply VINT is supplied to the third node N3, the first electrode of the light emitting element LD (or the parasitic capacitor of the light emitting element LD) may be initialized to the voltage of the initialization power supply VINT.

[0123] During the fifth period P5, the enabled emission control signal EM may be supplied to the emission control line ELi. When the enabled emission control signal EM is supplied to the emission control line ELi, the sixth transistor T6 may be turned on. When the sixth transistor T6 is turned on, the first power line PL1 and the first transistor T1 may be electrically connected to each other.

[0124] In addition, during the fifth period P5, the enabled fourth scan signal GE may be supplied to the fourth scan line SL4i. When the enabled fourth scan signal GE is supplied to the fourth scan line SL4i, the third transistor T3 may be turned on. When the third transistor T3 is turned on, the second node N2 and the third node N3 may be electrically connected to each other.

[0125] The first transistor T1 may supply a driving current corresponding to the voltage of the first node N1 from the first driving power source VDD to the second driving power source VSS via the light emitting element LD. Then, the light emitting element LD may generate light having a brightness corresponding to the driving current during the fifth period P5. The fifth period P5 may be an emission period.

[0126] Figure 5 The diagram shows the driving during the sustain period. Figure 3 One or more embodiments of the pixel method are shown in the figure.

[0127] refer to Figures 3 to 5, a frame period according to one or more embodiments of the present disclosure may include one writing period WP and at least one maintaining period MP.

[0128] The writing period WP is a period in which the voltage of the data signal is stored in the pixel PXij, Figure 4 The above-mentioned driving signal shown in can be supplied in the writing period WP. That is, the writing period WP may include Figure 4 The first period P1, the second period P2, the third period P3, the fourth period P4 and the fifth period P5 shown in the figure, and the enabled scan signals GW, GI, GR and GE and the disabled emission control signal EM can be supplied in each corresponding period (at least one period P1, P2, P3, P4 or P5).

[0129] The maintenance period MP is a period in which the pixel PXij is in a non-emission state during a portion of the period while maintaining the data signal supplied in the write period WP. At least one maintenance period MP may be included in a frame period. When the maintenance period MP is included in one frame period, the pixel PXij is in a non-emission state at certain intervals, and accordingly, the moving image quality can be improved.

[0130] like Figure 5 As shown in FIG. 1 , the maintenance period MP may include Figure 4 The first period P1, the second period P2, the third period P3, the fourth period P4 and the fifth period P5 shown in FIG. 1 correspond to the first period P1a, the second period P2a, the third period P3a, the fourth period P4a and the fifth period P5a.

[0131] During the first period P1a, the second period P2a, the third period P3a and the fourth period P4a of the maintenance period MP, the disabled emission control signal EM may be supplied to the emission control line ELi. When the disabled emission control signal EM is supplied to the emission control line ELi, the sixth transistor T6 may be turned off, and accordingly, the light emitting element LD may be in a non-emission state during the first period P1a, the second period P2a, the third period P3a and the fourth period P4a.

[0132] In the first period P1a and the fourth period P4a of the sustain period MP, the enabled second scan signal GI may be supplied to the second scan line SL2i. When the enabled second scan signal GI is supplied to the second scan line SL2i, the fourth transistor T4 may be turned on, and accordingly, the first electrode of the light emitting element LD may be initialized to the voltage of the initialization power supply VINT.

[0133] During the fifth period P5a of the sustain period MP, the enabled emission control signal EM may be supplied to the emission control line ELi. When the enabled emission control signal EM is supplied to the emission control line ELi, the sixth transistor T6 may be turned on. When the sixth transistor T6 is turned on, the first power line PL1 and the first transistor T1 may be electrically connected to each other.

[0134] The first transistor T1 may supply a driving current corresponding to the voltage of the first node N1 from the first driving power source VDD to the second driving power source VSS via the light emitting element LD. Then, the light emitting element LD may generate light having brightness corresponding to the driving current during the fifth period P5a.

[0135] Fig. 6A and Figure 6B is a diagram illustrating the brightness of a pixel during a writing period and during a sustaining period. Hereinafter, for ease of description, the brightness of a pixel during a writing period is referred to as brightness of a writing period, and the brightness of a pixel during a sustaining period is referred to as brightness of a sustaining period.

[0136] refer to Fig. 6A and Figure 6B , due to various reasons, the brightness of the pixel PX may be different from each other during the writing period WP and the maintenance period MP. For example, during the writing period WP, ​​the voltage of the data signal may be supplied to the first node N1, and the second node N2 and the third node N3 may be initialized by the voltage of the initialization power supply VINT. During the maintenance period MP, the voltage of the data signal may be maintained, and the third node N3 may be initialized.

[0137] Due to this difference in driving method, a brightness difference may occur in the pixel PX during the writing period WP and the maintenance period MP. Fig. 6A As shown in FIG. 1 , the pixel PX may generate light having a high brightness during the writing period WP compared to the maintaining period MP. Figure 6B As shown in , the pixel PX may generate light having high brightness during the sustain period MP compared with the write period WP.

[0138] like Fig. 6A and Figure 6B As shown in FIG. 1 , the brightness of the pixel PX during the writing period WP and the sustaining period MP may be different from each other, and may correspond to the kind of panel (e.g., resolution and size, etc.), process variation, and the voltage of the power supply (e.g., VREF or VINT) supplied to the panel, etc. The brightness difference between the writing period WP and the sustaining period MP may be recognized as flicker.

[0139] Figure 7is a diagram illustrating a timing controller according to one or more embodiments of the present disclosure. Figure 7 , only components suitable for the description of the present disclosure will be illustrated.

[0140] join Figure 7 , the timing controller 160 in one or more embodiments may include a start signal generator 162 , a selector 164 , and a controller 166 .

[0141] The start signal generator 162 may generate first and second start signals FLM1 and FLM2. The first start signal FLM1 may correspond to the disabled emission control signal EM supplied during the write period WP, ​​and the second start signal FLM2 may correspond to the disabled emission control signal EM supplied during the sustain period MP.

[0142] The width of the first start signal FLM1 and the width of the second start signal FLM2 may be set so that the brightness difference between the write period WP and the sustain period MP may be compensated. For example, the width of the first start signal FLM1 and the width of the second start signal FLM2 may be set so that light having substantially the same brightness may be generated in the pixel PX during the write period WP and the sustain period MP.

[0143] The selector 164 may supply the first start signal FLM1 or the second start signal FLM2 to the emission driver 140 corresponding to (e.g., based on) the control signal CS. For example, the selector 164 may output the first start signal FLM1 when the control signal CS of a first level (or a high level) is input, and may output the second start signal FLM2 when the control signal CS of a second level (or a low level) is input. The selector 164 may be a multiplexer.

[0144] The controller 166 may supply a control signal CS of a first level to the selector 164 during the write period WP, ​​and may supply a control signal CS of a second level to the selector 164 during the maintain period MP.

[0145] Meanwhile, it has been described that the selector 164 is included in the timing controller 160 . However, the present disclosure is not limited thereto. For example, the selector 164 may be included in the emission driver 140 .

[0146] Figure 8 is a diagram illustrating a transmit driver according to one or more embodiments of the present disclosure.

[0147] refer to Figure 8, the emission driver 140 may include a selector 142 and a shift register 144. When the selector 142 is included in the emission driver 140, the timing controller 160 may not include the selector 164. For example, the timing controller 160 may include only the start signal generator 162 and the controller 166.

[0148] The selector 142 may be supplied with the first start signal FLM1, the second start signal FLM2, and the control signal CS from the timing controller 160. The selector 142 may output the first start signal FLM1 when the control signal CS of a first level is input, and may output the second start signal FLM2 when the control signal CS of a second level is input.

[0149] The shift register 144 may be supplied with the first start signal FLM1 or the second start signal FLM2, and may sequentially supply the emission control signal EM having a width corresponding to the first start signal FLM1 or the second start signal FLM2 to the emission control lines EL1 to ELn. To this end, the shift register 144 may be supplied with a clock signal (not shown) from the timing controller 160.

[0150] Fig. 9 is a diagram illustrating a first start signal and a second start signal when a writing period is brighter than a sustaining period. Fig. 10A and Fig. 10B 16 is a diagram illustrating an embodiment in which the first start signal is supplied. The brightness difference between the write period WP and the sustain period MP may be pre-measured in the process, and the width of the first start signal FLM1 and the width of the second start signal FLM2 may be pre-stored in the start signal generator 162 so that the brightness difference can be compensated.

[0151] refer to Fig. 9 , when the writing period WP has a higher brightness than that of the sustaining period MP at the same emission time, the emission time of the sustaining period MP may be increased compared to the writing period WP.

[0152] To this end, the width W1 of the first start signal FLM1 may be wider than the width W2 of the second start signal FLM2. When the width of the first start signal FLM1 is set to the first width W1, the pixel PX may be in a non-emission state for a period (or time) of the first width W1 during the write period WP. In addition, when the width of the second start signal FLM2 is set to the second width W2, the pixel PX may be in a non-emission state for a period of the second width W2 during the maintain period MP.

[0153] Because the second width W2 is narrower than the first width W1, the emission time of the maintenance period MP can be longer than the emission time of the writing period WP. For example, the pixel PX can emit light for a period (or time) of the third width W3 (or the first emission period) during the writing period WP, ​​and can emit light for a period (or time) of the fourth width W4 (or the second emission period) during the maintenance period MP. The fourth width W4 can be wider than the third width W3, and accordingly, the pixel PX can emit light for a longer time during the maintenance period MP than during the writing period WP.

[0154] When the pixel PX emits light for a longer time during the maintenance period MP than during the writing period WP, ​​the brightness difference between the writing period WP and the maintenance period MP can be compensated. For example, the width of the first start signal FLM1 and the width of the second start signal FLM2 can be determined by experiment so that the pixel PX can generate substantially equal brightness to each other (or have a brightness difference within a threshold value (e.g., a predetermined threshold value)) during the writing period WP and the maintenance period MP.

[0155] A control signal CS of a first level may be supplied during a write period WP, ​​and the selector 142 or 164 may supply a first start signal FLM1 having a first width W1 to the shift register 144. Then, the shift register 144 may supply a disabled emission control signal EM having the first width W1 to the emission control lines EL1 to ELn. A control signal CS of a second level may be supplied during a maintain period MP, and the selector 142 or 164 may supply a second start signal FLM2 having a second width W2 to the shift register 144. Then, the shift register 144 may supply a disabled emission control signal EM having the second width W2 to the emission control lines EL1 to ELn.

[0156] Meanwhile, the first start signal FLM1 may include a first sub start signal FLM1a and a second sub start signal FLM1b. A width W1 of the first start signal FLM1 may be a time from when the first sub start signal FLM1a is supplied (low level voltage is supplied) to when supply of the second sub start signal FLM1b is suspended (high level voltage is supplied).

[0157] As reference Figure 4 As described, when the first sub start signal FLM1a and the second sub start signal FLM1b are supplied, the pixel PX may be in a non-emission state. In one or more embodiments, the width of the second start signal FLM1b is controlled so that the emission time of the pixel PX may be controlled during the writing period WP.

[0158] At the same time, Fig. 9, it is illustrated that the first start signal FLM1 is supplied even in the sustain period MP. However, the present disclosure is not limited thereto.

[0159] For example, Fig. 10A and Fig. 10B As shown in FIG. 1 , the start signal generator 162 supplies the first start signal FLM1 only in the write period WP and may not supply the first start signal FLM1 in the maintain period MP. During the period in which the first start signal FLM1 is not supplied, the start signal generator 162 may supply the first start signal FLM1 as shown in FIG. Fig. 10A The high level voltage shown or Fig. 10B The low level voltage shown in .

[0160] Fig.11 is a diagram illustrating a first start signal and a second start signal when a sustain period is brighter than a write period.

[0161] refer to Fig.11 , when the sustain period MP has a higher brightness than that of the writing period WP at the same emission time, the emission time of the sustain period MP may be reduced compared to the writing period WP.

[0162] To this end, the width W1a of the first start signal FLM1 may be narrower than the width W2a of the second start signal FLM2. When the width of the first start signal FLM1 is set to the first width W1a, the pixel PX may be in a non-emission state for a period (or time) of the first width W1a during the write period WP. In addition, when the width of the second start signal FLM2 is set to the second width W2a, the pixel PX may be in a non-emission state for a period of the second width W2a during the maintain period MP.

[0163] Because the second width W2a is wider than the first width W1a, the emission time of the maintenance period MP can be shorter than the emission time of the writing period WP. For example, the pixel PX can emit light for a period (or time) of the third width W3a during the writing period WP, ​​and can emit light for a period (or time) of the fourth width W4a during the maintenance period MP. The fourth width W4a can be narrower than the third width W3a, and accordingly, the pixel PX can emit light for a shorter time during the maintenance period MP than during the writing period WP.

[0164] When the pixel PX emits light for a shorter time during the maintenance period MP than during the writing period WP, ​​the brightness difference between the writing period WP and the maintenance period MP can be compensated. For example, the width of the first start signal FLM1 and the width of the second start signal FLM2 can be determined experimentally so that the pixel PX can generate brightness substantially equal to each other (or have a brightness difference within a threshold value (e.g., a predetermined threshold value)) during the writing period WP and the maintenance period MP.

[0165] A control signal CS of a first level may be supplied during a write period WP, ​​and the selector 142 or 164 may supply a first start signal FLM1 having a first width W1a to the shift register 144. Then, the shift register 144 may supply a disabled emission control signal EM having the first width W1a to the emission control lines EL1 to ELn. A control signal CS of a second level may be supplied during a maintain period MP, and the selector 142 or 164 may supply a second start signal FLM2 having a second width W2a to the shift register 144. Then, the shift register 144 may supply a disabled emission control signal EM having the second width W2a to the emission control lines EL1 to ELn.

[0166] Fig.12 is a diagram illustrating brightness of a writing period and a sustaining period according to one or more embodiments of the present disclosure.

[0167] refer to Fig.12 In one or more embodiments, as Fig. 9 or Fig.11 As shown in FIG. 1 , the widths W1 and W1a of the first start signal FLM1 and the widths W2 and W2a of the second start signal FLM2 are controlled so that the pixels PX can generate substantially equal brightness to each other (or have a brightness difference equal to or less than a threshold value) during the write period WP and the maintenance period MP. That is, the occurrence of flicker can be reduced or minimized, and accordingly, the display quality can be improved.

[0168] Fig.13A and Fig. 13B is a diagram illustrating a transmission control signal according to one or more embodiments of the present disclosure.

[0169] refer to Fig.13A and Fig. 13B In one or more embodiments of the present disclosure, the timing controller 160 may control the width of the emission control signal EM corresponding to the dimming level of the display device 100. The dimming level may include maximum brightness information related to the maximum brightness that can be displayed in the pixel unit 110. The maximum brightness may be the brightness measured when the entire pixel unit 110 emits light at the maximum brightness set in the display device 100.

[0170] When the dimming level is low (eg, when the maximum brightness is low), the timing controller 160 may set the emission time of the pixel to be relatively short using the start signals FLM1 and FLM2 .

[0171] In one or more embodiments, Fig.13AAs shown in , corresponding to the same emission time, when the brightness of the writing period WP is lower than that of the maintaining period MP, the timing controller 160 may set the emission time of the maintaining period MP to be shorter than the emission time of the writing period WP. For example, the pixel PX may emit light for a time of the third width W3b during the writing period WP, ​​and may emit light for a time of the fourth width W4b shorter than the third width W3b during the maintaining period MP.

[0172] In one or more embodiments, Fig. 13B As shown in , corresponding to the same emission time, when the brightness of the maintenance period MP is lower than that of the writing period WP, ​​the timing controller 160 can set the emission time of the maintenance period MP to be longer than the emission time of the writing period WP. For example, the pixel PX can emit light for a time of the third width W3c during the writing period WP, ​​and can emit light for a time of the fourth width W4c longer than the third width W3c during the maintenance period MP.

[0173] That is, in the present disclosure, regardless of the dimming level, the brightness difference between the writing period WP and the maintenance period MP can be similarly (or equally) maintained.

[0174] Fig.14 is a diagram of a timing controller according to one or more embodiments of the present disclosure. Fig.15 is a graph illustrating brightness corresponding to the temperature of a display device.

[0175] exist Fig.14 In, with Figure 7 Components similar to those shown in FIG. 1 are denoted by the same reference numerals, and repeated descriptions will be omitted.

[0176] refer to Fig.14 The timing controller 160 in one or more embodiments may include a start signal generator 162 a, a selector 164 , and a controller 166 . In one or more embodiments, the selector 164 may be included in the emission driver 140 .

[0177] In one or more embodiments, the display device may further include a temperature sensor 170. The temperature sensor 170 may sense the temperature of the display device 100 (or the pixel unit 110), and may supply the sensed temperature value TP to the start signal generator 162a.

[0178] The start signal generator 162a may change the width of at least one of the first start signal FLM1 and the second start signal FLM2 by reflecting the temperature value TP (e.g., based on the temperature value TP). The first start signal FLM1 may correspond to the disabled emission control signal EM supplied during the write period WP, ​​and the second start signal FLM2 may correspond to the disabled emission control signal EM supplied during the maintain period MP.

[0179] In one or more embodiments, the width of the first start signal FLM1 and the width of the second start signal FLM2 may be set so that the brightness difference between the write period WP and the maintenance period MP may be compensated. In one or more embodiments, the width of the first start signal FLM1 and the width of the second start signal FLM2 may be set so that the brightness difference between the write period WP and the maintenance period MP may be compensated corresponding to the temperature. For example, the width of the first start signal FLM1 and the width of the second start signal FLM2 may be set so that light having substantially the same brightness may be generated in the pixel PX during the write period WP and the maintenance period MP, regardless of the temperature.

[0180] For example, Fig.15 As shown in , when the temperature of the pixel unit 110 is about 10° C., the writing period WP and the maintaining period MP may have a first brightness difference LD1 during the same emission period. Fig.15 As shown in FIG. 1 , when the temperature of the pixel unit 110 is about 40° C., the writing period WP and the sustaining period MP may have a second luminance difference LD2 different from the first luminance difference LD1 during the same emission period.

[0181] When the temperature value TP is not reflected on the first start signal FLM1 and the second start signal FLM2 generated by the start signal generator 162a, the brightness of the write period WP and the maintenance period MP may be set differently corresponding to the temperature. In order to prevent this phenomenon, the start signal generator 162a may change the width of at least one of the first start signal FLM1 and the second start signal FLM2 corresponding to the temperature. For example, as the temperature increases, the width of the change of the first start signal FLM1 and / or the second start signal FLM2 may be large. Thus, the pixel PX can generate light with brightness similar to (or equal to) each other during the write period WP and the maintenance period MP, regardless of how the temperature of the display device 100 changes.

[0182] In a display device and a method of driving the display device according to the present disclosure, a width of an emission control signal supplied in a writing period and a width of an emission control signal supplied in a sustaining period are set differently, thereby reducing or minimizing a brightness difference between the writing period and the sustaining period.

[0183] Embodiments have been disclosed herein, and although specific terms are employed, such specific terms are used and interpreted only in a general and descriptive sense and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art as of the time of filing of this application, features, characteristics, and / or elements described in conjunction with a specific embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless specifically indicated otherwise. Accordingly, those skilled in the art will appreciate that various changes may be made in form and detail without departing from the spirit and scope of the present disclosure as set forth in the claims and their functional equivalents.

Claims

1. A display device, comprising: Pixels, connected to scan lines, data lines, and emission control lines; The start signal generator is configured to generate: a first start signal corresponding to a first emission control signal supplied in a writing period of a frame period in which a data signal is supplied; and a second start signal corresponding to a second emission control signal and having a width different from that of the first start signal, the second emission control signal being supplied in a sustain period of the frame period in which the data signal is sustained; a selector configured to supply the first start signal or the second start signal based on a control signal from a controller; as well as The emission driver is configured to supply the first emission control signal or the second emission control signal to the emission control line based on the first start signal or the second start signal.

2. The display device according to claim 1, wherein: The first start signal includes a first sub-start signal and a second sub-start signal, and A time in which supply of the second sub start signal is suspended from when the first sub start signal is supplied is the width of the first start signal.

3. The display device according to claim 1, wherein: The selector is configured to supply the first start signal to the emission driver during the write period, and to supply the second start signal to the emission driver during the sustain period.

4. The display device according to claim 1, wherein: The width of the first start signal and the width of the second start signal are set so that the pixel emits light longer during the writing period than during the sustaining period.

5. The display device according to claim 1, wherein: The width of the first start signal and the width of the second start signal are set so that the pixel emits light for a shorter time during the writing period than during the sustaining period.

6. The display device according to claim 1, further comprising: a temperature sensor configured to sense a temperature of the display device, The start signal generator is configured to change the width of the first start signal or the width of the second start signal based on the temperature.

7. The display device according to claim 1, further comprising: a timing controller configured to control the emission driver and comprising the start signal generator, the controller and the selector; or The transmit driver includes the selector.

8. The display device according to claim 1, wherein: The start signal generator is configured to change the width of the first start signal or the width of the second start signal corresponding to a dimming level.

9. The display device according to claim 1, wherein: The start signal generator is configured to supply the first start signal or the second start signal to the selector during the write period or the sustain period.

10. The display device according to claim 1, wherein: The start signal generator is configured to supply the first start signal or the second start signal to the selector during the write period, and to supply the second start signal to the selector during the sustain period.

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