On-chip termination signal generation circuit and memory system

Abstract

The on-chip termination signal generation circuit and the storage system are provided by the disclosure. The circuit is applied to the storage system, and the storage system comprises a memory with an on-chip termination control circuit. A preprocessing circuit in the on-chip termination signal generation circuit is used to receive a control signal, output a first signal and an indication signal in response to a clock signal. The control signal is used to indicate the state of adjusting the termination resistance of a data terminal. The active level period of the first signal is a first duration. A pulse stretching circuit is used to receive the first signal and the indication signal and output a second signal. The width of the active level of the second signal is selected to be generated according to the indication signal. A delay circuit is used to receive the second signal and perform time delay processing on the second signal, and output an on-chip termination signal. The on-chip termination control circuit receives the on-chip termination signal to adjust the state of the termination resistance of the data terminal. Through the above on-chip termination signal generation circuit, the accuracy of data writing is ensured.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more particularly to an on-chip termination signal generation circuit and storage system. Background Technology

[0002] With the continuous development of semiconductor technology, on-die termination (ODT) control circuits are usually set in memory to adjust the mode of termination resistance (RTT) and reduce signal reflection.

[0003] Therefore, how to design an ODT generation circuit to control the RTT state is the problem addressed by this disclosure. Summary of the Invention

[0004] The on-chip termination signal generation circuit and storage system disclosed herein are used to provide an on-chip termination signal generation circuit to achieve effective control of RTT.

[0005] In a first aspect, this disclosure provides an on-chip termination signal generation circuit for use in a storage system, the storage system including a memory with an on-chip termination control circuit; the on-chip termination signal generation circuit includes: a preprocessing circuit, a pulse broadening circuit, and a delay circuit;

[0006] The preprocessing circuit is configured to receive a control signal and, in response to a clock signal, output a first signal and an indication signal; wherein, the control signal is configured to indicate the state of the termination resistor at the data terminal; the effective level period of the first signal is a first duration; the indication signal is configured to indicate a first burst length; the first burst length is the current burst length of the memory;

[0007] The pulse broadening circuit is used to receive the first signal and the indication signal, and output a second signal; the width of the effective level of the second signal is generated according to the indication signal.

[0008] The delay circuit is used to receive the second signal, perform delay processing on the second signal, and output an on-chip termination signal. The on-chip termination control circuit receives the on-chip termination signal to adjust the state of the termination resistor at the data terminal.

[0009] In some embodiments, the delay circuit includes: a shift module and a delay module;

[0010] The shift module is used to receive the clock signal, perform alignment processing on the received second signal, and obtain a third signal; wherein the effective edge of the third signal is aligned with the effective edge of the clock signal.

[0011] The delay module is used to receive the third signal and perform delay processing on the third signal to obtain the on-chip termination signal.

[0012] In some embodiments, the first duration is a fixed value of the data write duration corresponding to the second burst length; the second burst length is the minimum value among the burst lengths supported by the memory;

[0013] Alternatively, the first duration may be a fixed value that is less than the data write duration corresponding to the second burst length.

[0014] In some embodiments, the pulse broadening circuit includes a plurality of first processing modules and a data selector;

[0015] The first processing module is used to receive the first signal and perform broadening processing on the first signal to obtain a fourth signal; wherein the effective level width of the fourth signal output by different first processing modules is different;

[0016] The data selector is used to receive the fourth signal and the indication signal, and to determine and output the second signal from among a plurality of fourth signals.

[0017] In some embodiments, if the first burst length is greater than the third burst length, then the first duration is the data writing duration corresponding to the third burst length; the third burst length is a value selected from the burst lengths supported by the memory, excluding the maximum value.

[0018] In some embodiments, if the first burst length is less than or equal to the third burst length, then the first duration is the write duration corresponding to the first burst length.

[0019] In some embodiments, the pulse broadening circuit includes M second processing modules, one third processing module, and a P-channel selector; wherein, M is the total number of burst lengths supported by the memory that are greater than the third burst length; and P is a positive integer greater than or equal to the sum of M and 1.

[0020] The second processing module is used to receive the first signal, perform broadening processing on the first signal, and output a first candidate signal; wherein the increase in effective level width is different for different second processing modules;

[0021] The third processing module is used to receive the first signal, perform widening processing on the first signal, and output the second candidate signal; the increase in the effective level width corresponding to the second candidate signal is a preset offset.

[0022] The P-channel selector is used to receive the first candidate signal, the second candidate signal, and an indication signal, and to determine and output an on-chip termination signal from M first candidate signals and one second candidate signal according to the indication signal.

[0023] In some embodiments, the preprocessing circuit includes a first output terminal, a second output terminal, and a third output terminal, wherein the first output terminal is used to output a first signal generated when the first burst length is greater than the third burst length; the second output terminal is used to output a first signal generated when the first burst length is less than or equal to the third burst length; and the third output terminal is used to output the indication signal.

[0024] In some embodiments, the pulse broadening circuit includes M fourth processing modules, one fifth processing module, and a K-channel selector; wherein, M is the total number of burst lengths supported by the memory that are greater than the third burst length; and K is a positive integer greater than or equal to M.

[0025] The fourth processing module is used to broaden the first signal output from the first output terminal to obtain a third candidate signal; wherein, the increase in effective level width is different for different fourth processing modules;

[0026] The fifth processing module is used to broaden the first signal output from the second output terminal to obtain a fourth candidate signal; and output the fourth candidate signal as the second signal; wherein, the increase in the effective level width of the fifth processing module is a preset offset.

[0027] The K-channel selector is used to receive the third candidate signals output by each of the M second processing modules, and to determine and output a second signal from the M third candidate signals or control the K-channel selector to stop working according to the received indication signal.

[0028] In a second aspect, this disclosure provides a memory system including a memory having on-chip termination control circuitry and an on-chip termination signal generation circuitry as described in any one of the first aspects.

[0029] This disclosure provides an on-chip termination signal generation circuit and storage system. The circuit is applied to a storage system including a memory with an on-chip termination control circuit. The on-chip termination signal generation circuit includes a preprocessing circuit for receiving a control signal and, in response to a clock signal, outputting a first signal and an indication signal. The control signal indicates the state of adjusting the termination resistor at the data terminal. The effective level period of the first signal is a first duration. A pulse widening circuit receives the first signal and the indication signal and outputs a second signal. The width of the effective level of the second signal is selected and generated according to the indication signal. A delay circuit receives the second signal, performs delay processing on the second signal, and outputs an on-chip termination signal. The on-chip termination control circuit receives the on-chip termination signal to adjust the state of the termination resistor at the data terminal. This on-chip termination signal generation circuit ensures the accuracy of data writing. Attached Figure Description

[0030] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0031] Figure 1 This disclosure provides a signal timing diagram;

[0032] Figure 2 This is a schematic diagram of the signal state of an on-chip termination signal generation circuit provided in this disclosure;

[0033] Figure 3 This is a schematic diagram of the signal state of another on-chip termination signal generation circuit provided in this disclosure;

[0034] Figure 4 A schematic diagram of the circuit structure of an on-chip termination signal generation circuit provided in an embodiment of this disclosure;

[0035] Figure 5 A schematic diagram of signal transformation provided in an embodiment of this disclosure;

[0036] Figure 6 A schematic diagram of another on-chip termination signal generation circuit provided in this embodiment of the present disclosure;

[0037] Figure 7 This is another schematic diagram of signal transformation provided in an embodiment of the present disclosure;

[0038] Figure 8 A schematic diagram of the circuit structure of another on-chip termination signal generation circuit provided in an embodiment of this disclosure;

[0039] Figure 9 A schematic diagram of the circuit structure of an on-chip termination signal generation circuit provided for an embodiment of this disclosure;

[0040] Figure 10 This is a schematic diagram of the circuit structure of another on-chip termination signal generation circuit provided in an embodiment of the present disclosure.

[0041] Explanation of reference numerals in the attached figures:

[0042] 101: Preprocessing circuit; 102: Pulse widening circuit; 103: Delay circuit;

[0043] 1021: First processing module; 1022: Data selector;

[0044] 1023: Second processing module; 1024: Third processing module; 1025: P-channel selector;

[0045] 1026: Fourth processing module; 1027: Fifth processing module; 1028: K-way selector;

[0046] 1031: Shift module; 1032: Delay module. Detailed Implementation

[0047] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure.

[0048] Currently, in order to ensure the accuracy of signal transmission and avoid memory malfunctions caused by signal reflection, a termination resistor is usually set at the data (dq) end of the memory.

[0049] Figure 1 This is a signal timing diagram provided in this disclosure. For example... Figure 1 As shown, Figure 1Specifically, this is a timing diagram of the memory receiving a write signal. In related technologies, when the memory receives a write command, the state of the termination resistor at the data terminal needs to be adjusted from RTT-PARK to RTT-WR before the data to be written is received at the data terminal. The time from receiving the write command to the termination resistor adjusting to RTT-WR is represented by tODTLon_WR, where tODTLon_WR = CWL + ODTLon_WR_offset. In the above formula, CWL (CAS Write Latency) is the time from the activation of the write command to the first data write. ODTLon_WR_offset can be understood as the enable offset, an adjustment value issued by the controller to indicate the switching time from RTT-PARK to RTT-WR. When ODTLon_WR_offset is 0, the switching time from RTT-PARK to RTT-WR is CWL. Furthermore, during the above state switching of the RTT, the RTT itself also requires a certain switching time, which is generally represented by tADC.

[0050] After data writing is complete, the RTT needs to be switched from the RTT-WR state to the RTT-PARK state. To ensure the timing requirements of the RTT state switching, the ODT signal generation circuit needs to generate the ODT_CMD signal (referred to as the on-chip termination signal in this disclosure) and send the generated on-chip termination signal to the ODT control circuit so that the ODT control circuit can switch the RTT resistance value before and after data writing. Furthermore, the effective level period of ODT-CMD needs to be offset by a certain amount based on the data writing duration. This offset can be represented by the following formula: ODT_offset

[0051] ODT_offset=ODTLoff_WR_offset-ODTLon_WR_offset

[0052] ODTLoff_WR_offset can be understood as the offset between the time when data reception ends and the time when the RTT-WR state is switched back to RTT-PARK, which is the shutdown offset mentioned in this disclosure.

[0053] It should be noted that the number of data bits transmitted in a single pulse varies depending on the BL mode. In different BL modes, the duration of the effective level of the aforementioned ODT_CMD signal must be greater than or equal to the data transmission duration corresponding to the BL mode. Furthermore, the aforementioned enable and disable offsets are set by the memory's controller, and their values ​​must meet the range specified in the protocol. Table 1 below shows the value ranges set for DDR5 memory.

[0054]

[0055] Table 1. Specified Offset Value Range

[0056] In Table 1 above, P indicates a valid value, and X indicates an invalid value. For example, the controller can set the values ​​for the on offset and the off offset to -4 and 4 respectively, but it is not allowed to set them to 2 and -2.

[0057] In one example, to achieve the aforementioned RTT state control, an on-chip termination signal generation circuit is typically included in the memory. The output of this on-chip termination signal is then used to control the RTT state. For example, Figure 2 This is a schematic diagram of the signal state of an on-chip termination signal generation circuit provided in this disclosure. Assuming the on-chip termination signal generation circuit includes a first circuit module, a second circuit module, and a third circuit module, and taking a current memory burst length of 16 and a corresponding data write duration of 8 tck as an example, the specific working principle is as follows: When the memory receives a write command, it triggers the generation of a signal used to indicate the adjustment of the RTT state, hereinafter referred to as the CMD_IN signal. After the first circuit module receives the aforementioned CMD_IN signal, it generates a Burst_out signal with a fixed effective level period (4 tck in the diagram), and the effective level period of the Burst_out signal can be less than or equal to the data write duration corresponding to the burst length supported by the memory. Furthermore, to facilitate subsequent circuit modules in processing the pulse widening of the Burst_out signal, the first circuit module also generates an indicator signal to indicate the current memory burst length, so that the width of the effective level period of the final output on-chip termination signal can be determined based on the indicator signal.

[0058] Subsequently, the first circuit module transmits the generated Burst_out signal to the second circuit module, which then performs a delay on the received Burst_out signal to obtain the ODT_shift signal. It should be noted that the purpose of this delay is to ensure that the final on-chip termination signal CMD_out generated by the on-chip termination signal generation circuit can accurately control the RTT adjustment from RTT-PARK to RTT-WR.

[0059] The third circuit module in the on-chip termination signal generation circuit is used not only to receive the aforementioned indication signal, but also to receive the ODT_shift signal. Based on the indication signal, it performs pulse widening processing on the ODT_shift signal and outputs the on-chip termination signal. In the diagram, compared to the Burst_out signal, the effective level width of the ODT_shift signal is increased by ODT_offset + 4tck. Here, 4tck can be understood as the difference between the data write duration corresponding to the current burst length of the memory and 4tck (i.e., the effective level width of the Burst_out signal). According to the ODT_shift signal, after receiving the write signal, the RTT state adjusts from RTT-PARK to RTT-WR after a duration of WL + ODTLon_WR_offset. Here, WL (Write Latency) characterizes the delay between the issuance of the write signal and the memory receiving the first data to be written. Furthermore, after maintaining BL / 2+ODT_offset in the RTT-WR state, the RTT switches back to the RTT-PARK state, that is, after WL+BL / 2+ODT_offset after the write signal is issued, it switches back to the RTT-PARK state.

[0060] However, the aforementioned on-chip termination signal generation circuit has the following technical problems. For example... Figure 3 As shown, Figure 3 This is a schematic diagram of the signal states of another on-chip termination signal generation circuit provided in this disclosure. When the memory receives two write signals in adjacent time periods, the first circuit module will receive the CMD_IN signal corresponding to each write signal at different time periods. Figure 3 The two low-level signals at the CMD_IN signal receiver represent the two CMD_IN signals mentioned above. When the two CMD_IN signals represent different burst lengths corresponding to the memory, taking the memory switching from burst length 1 to burst length 2 as an example, the output of the first circuit module (i.e., the Burst_out signal output in the figure) will output a signal including two Burst_out signals with fixed widths and effective levels. Figure 3 The CA signal in the diagram is the command address signal sent by the memory, which can be used to indicate the burst length used by the memory. The indication signal (represented by BL_en in the diagram) is generated by the first circuit module based on the burst length of the memory. Figure 3As can be seen, when the CA signal switches from low to high, the burst length changes from burst length 1 to burst length 2. The corresponding indicator signal output by the first circuit module also switches from low to high, instructing the third circuit module to perform width compensation for different effective levels. It should be noted that the high or low effective levels for each signal in this example are merely illustrative and are not specifically limited in practical applications.

[0061] from Figure 3 As can be seen, during the delay processing of the first Burst_out signal (i.e., the signal during the first low-level period) output by the second circuit module, the indicator signal received by the third circuit module has already switched from low to high level (i.e., the burst length of the memory needs to be switched at this time). Therefore, when the third circuit module receives the signal output from the output terminal of the second circuit module (i.e., the ODT_shift signal terminal), the signal generated by the second circuit module under burst length 1 needs to undergo pulse broadening processing under the indicator signal corresponding to the burst length 1 mode (i.e., the indicator signal at a low level in the figure). However, Figure 3 In the signal diagram shown, the third circuit module will widen the first ODT_shift signal at the output of the second circuit module according to the received high-level indication signal. That is, the ODT_shift signal output by the second circuit module under burst length 1 will be widened according to the indication signal corresponding to burst length 2. As a result, the third circuit module will generate an incorrect on-chip termination signal CMD_out according to the incorrect indication signal, which will affect the accuracy of the final generated signal. Figure 3 The dashed line between the ODT_shift output and the on-chip termination signal CMD_out is used to characterize the correspondence between the two signals. That is, the first falling edge of ODT_shift corresponds to the first falling edge of the on-chip termination signal CMD_out, and the first rising edge of ODT_shift corresponds to the point in the on-chip termination signal CMD_out indicated by the dashed line connecting the rising edge.

[0062] To avoid the situation where the received indication signal and the signal obtained by delay processing are not generated under the same burst length during the above pulse broadening process, in this embodiment of the disclosure, pulse broadening processing is performed first based on the indication signal, and then delay processing is performed on the broadened signal, thereby ensuring the timing accuracy of the on-chip termination signal output by the on-chip termination signal generation circuit.

[0063] The technical solutions of this disclosure and how they solve the aforementioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0064] Figure 4 This is a schematic diagram of the circuit structure of an on-chip termination signal generation circuit provided in an embodiment of this disclosure. The on-chip termination signal generation circuit provided in this embodiment is applied to a storage system, which includes a memory with an on-chip termination control circuit. Figure 4 As shown, the on-chip termination signal generation circuit includes: a preprocessing circuit 101, a pulse widening circuit 102, and a delay circuit 103; the preprocessing circuit 101 is used to receive a control signal and, in response to a clock signal, output a first signal and an indication signal; wherein, the control signal is used to indicate the state of adjusting the termination resistor of the data terminal; the effective level period of the first signal is a first duration; the indication signal is used to indicate a first burst length; the first burst length is the current burst length of the memory; the pulse widening circuit 102 is used to receive the first signal and the indication signal and output a second signal; the width of the effective level of the second signal is selected and generated according to the indication signal; the delay circuit 103 is used to receive the second signal, perform delay processing on the second signal, and output an on-chip termination signal; the on-chip termination control circuit receives the on-chip termination signal to adjust the state of the termination resistor of the data terminal.

[0065] For example, in this embodiment, the on-chip termination signal generation circuit includes a preprocessing circuit 101, a pulse widening circuit 102, and a delay circuit 103. The preprocessing circuit 101, the pulse widening circuit 102, and the delay circuit 103 operate under the same clock signal. It should be noted that the clock signal CLK in this disclosure is the internal clock signal of the memory.

[0066] When the storage system receives a write command signal indicating that data needs to be written to the memory, it generates a control signal CMD and transmits it to the preprocessing circuit 101. This informs the preprocessing circuit 101 that the state of the termination resistor at the memory data terminal needs to be adjusted. Triggered by the control signal CMD and the clock signal CLK, the preprocessing circuit 101 generates a first signal Burst_out. It should be noted that the effective output period of the first signal Burst_out by the preprocessing circuit 101 is a first duration. This first duration is a fixed value; that is, its value is independent of the current burst length of the memory.

[0067] Furthermore, in this embodiment, the preprocessing circuit 101 also generates an indication signal (represented by BL_en in the figure) and sends the indication signal BL_en to the pulse widening circuit 102. The indication signal BL_en can be used to indicate the current first burst length of the memory, so that the width of the effective level of the finally generated on-chip termination signal can be determined based on the indication signal BL_en.

[0068] After the preprocessing circuit 101 generates the indication signal and the first signal Burst_out, it sends the generated indication signal and the first signal Burst_out to the pulse widening circuit 102. After the pulse widening circuit 102 receives the first signal Burst_out and the indication signal, it adjusts the effective level width of the first signal Burst_out according to the indication signal BL_en, and then outputs the second signal Pulse_out.

[0069] In one possible implementation, when the pulse widening circuit 102 processes the first signal Burst_out, it adjusts the width of the effective level of the received first signal Burst_out according to the first burst length indicated by the indicator signal BL_en and a preset offset (i.e., ODT_offset mentioned in the related art). For example, after the pulse widening circuit 102 receives the indicator signal BL_en, it determines the difference (i.e., the first difference) between the first duration of the effective level period of the currently received first signal Burst_out and the data write duration (BL / 2) corresponding to the first burst length. Then, the pulse widening circuit 102 can widen the width of the effective level of the first signal Burst_out based on the effective level period corresponding to the first signal Burst_out. The widening length is the sum of the first difference and the preset offset. Thus, through the above widening process, it is ensured that the duration of the on-chip termination signal generation circuit controlling the RTT to be in the RTT_WR state is greater than or equal to the current data write duration.

[0070] Furthermore, in this embodiment, after acquiring the second signal Pulse_out, the delay circuit 103 performs delay processing on the received second signal Pulse_out. That is, through the delay processing of the delay circuit 103, it is determined that the on-chip termination signal CMD_out finally generated by the on-chip termination signal generation circuit can adjust the RTT from RTT-PARK to RTT-WR before the memory receives the first data to be written. In other words, the delay circuit 103 is mainly used to delay and determine the time for RTT to switch states. In order to ensure that the time for RTT to adjust from RTT-PARK to RTT-WR meets the requirement of WL+ODTLon_WR_offset (i.e., the second value mentioned above) mentioned in the related art, in one possible implementation, when the delay circuit 103 performs delay processing on the received second signal Pulse_out, it combines the second value to determine the delay time that needs to be delayed, and performs delay processing on the second signal Pulse_out according to the obtained delay time. The second value is the sum of the memory write latency and the memory termination resistor enable offset. WL is the memory write latency mentioned in this embodiment, and ODTLon_WR_offset is the termination resistor enable offset in this embodiment, which is the offset between WL and the time RTT is adjusted from RTT-PARK to RTT-WR.

[0071] Understandably, compared to the method in related technologies that performs delay processing first and then pulse widening processing, this embodiment first performs widening processing on the effective level period based on the indication signal and then performs delay processing. Thus, the pulse widening circuit 102 can perform pulse widening processing based on the first signal and the indication signal under the same burst length mode. This avoids the phenomenon that if the burst length of the memory changes when delay processing is performed first, the received indication signal during pulse widening may be the indication signal after the burst length change, while the signal to be widened is still the first signal Burst_out before the pseudo-burst length switch, which leads to the pulse widening error.

[0072] In some embodiments, when the width of the effective level of the first signal Burst_out generated by the preprocessing circuit 101 is less than the write duration corresponding to the first burst length, the pulse broadening value can be expressed by the following formula when pulse broadening processing is subsequently performed:

[0073] (BL / 2 + ODT_offset) - (BL / 2 - first difference) = ODT_offset + first difference

[0074] The first difference is the difference between BL / 2 and the width of the effective level of the first signal Burst_out. BL / 2 + ODT_offset can be understood as the width of the effective level of the final generated on-chip termination signal CMD_out. That is, it is equivalent to widening ODT_offset + the first difference based on the effective level period of the first signal Burst_out. Compared to the memory protocol, which specifies that ODT_offset can only take values ​​greater than or equal to 0, in this embodiment, ODT_offset can be a value less than 0, thus increasing the range of ODT_offset values. This, in turn, increases the range of ODTLoff_WR_offset and ODTLon_WR_offset values, so that the ODT control circuit can adapt to various different values ​​of the start and end offsets.

[0075] Figure 5 This is a schematic diagram of a signal transformation provided in an embodiment of this disclosure. Figure 5 As shown, Figure 5 In the diagram, the control signal CMD is illustrated using a low-level active state as an example. The control signal CMD is active in two different time periods. The first low-level state of the control signal CMD indicates that the current memory needs to operate in burst length 1 mode, and the second low-level state of the control signal CMD indicates that the current memory needs to operate in burst length 2 mode. The preprocessing circuit 101 generates... Figure 5 The first signal in the diagram is Burst_out (where the first signal is active low). The CA (command / address) signal and the indicator signal BL_en in the diagram can be found in [reference needed]. Figure 3 The description in the text will not be repeated here.

[0076] When the pulse widening circuit 102 receives the low-level indication signal BL_en and the first low-level signal Burst_out, it performs corresponding pulse widening processing. Furthermore, when the memory switches from burst length 1 mode to burst length 2 mode, the pulse widening circuit 102 performs pulse widening processing on the second low-level control signal CMD based on the high-level indication signal BL_en. This ensures that the pulse widening circuit 102 can perform pulse widening processing based on the indication signal BL_en and the corresponding generated first signal Burst_out under the same burst length mode, ensuring the accuracy of the second signal Pulse_out, and thus ensuring the accuracy of the final on-chip termination signal CMD_out.

[0077] Figure 6 This is a schematic diagram of another on-chip termination signal generation circuit provided in an embodiment of the present disclosure, as shown below. Figure 6 As shown, in Figure 4 Based on the structure shown, in this embodiment, the delay circuit 103 includes: a shift module 1031 and a delay module 1032; the shift module 1031 is used to receive a clock signal, perform alignment processing on the received second signal, and obtain a third signal; wherein, the effective edge of the third signal is aligned with the effective edge of the clock signal; the delay module 1032 is used to receive the third signal and perform delay processing on the third signal to obtain an on-chip termination signal.

[0078] For example, in this embodiment, the delay circuit 103 includes a shift module 1031 and a delay module 1032. Upon receiving the second signal Pulse_out, the shift module 1031 aligns the effective edge of the second signal Pulse_out with the effective edge of the clock signal CLK to obtain the aligned third signal CLK_align. Then, the shift module 1031 sends the obtained third signal CLK_align to the delay module 1032. Furthermore, the delay module 1032 performs a delay processing on the third signal CLK_align.

[0079] In one possible implementation, the delay duration of the third signal is the difference between the second value (WL+ODTLon_WR_offset) and the transmission loss during signal transmission. This ensures that, under the control of the finally generated on-chip termination signal, the time for RTT to adjust from RTT-PARK to RTT-WR can be before the first data to be written is received. Specifically, the transmission loss in this embodiment includes three parts: the first part is the loss time of the pulse widening circuit 102, that is, the loss time from when the pulse widening circuit 102 receives the first signal Burst_out to when the pulse widening circuit 102 outputs the second signal Pulse_out to the shift module 1031. The second part is the loss time from when the shift module 1031 receives the second signal Pulse_out to when the shift module 1031 outputs the third signal CLK_align to the delay module 1032. Furthermore, since the on-chip termination signal CMD_out generated by the on-chip termination circuit still requires a certain amount of time (i.e., absolute delay) to be transmitted to the receiving end of the on-chip termination signal CMD_out, the transmission loss must also include the aforementioned absolute delay. Therefore, after receiving the third signal CLK_align sent by the shift module 1031, the delay module 1032 uses the difference between the second value and the transmission loss as the delay time for the third signal CLK_align, thereby obtaining the final on-chip termination signal CMD_out. It is understood that in this embodiment, during delay processing, the loss time of the pulse widening circuit 102, the loss time of the shift module 1031, and the absolute delay are also considered to determine the delay time for the third signal CLK_align, in order to further ensure that the finally generated on-chip termination signal CMD_out can accurately control the RTT for state switching.

[0080] Figure 7 This is yet another signal transformation diagram provided as an embodiment of the present disclosure. The signal transformation diagram provided in this embodiment...

[0081] Based on Figure 6 The circuit structure shown corresponds to a signal diagram. For example... Figure 7 As shown, when the preprocessing circuit 101

[0082] After receiving the control signal CMD, the first signal Burst_out will be generated under the triggering of the clock signal CLK.

[0083] Subsequently, after receiving the first signal Burst_out, the pulse widening circuit 102 performs pulse widening on the basis of the first signal Burst_out when the width of the effective level period corresponding to the first signal Burst_out is less than the write duration corresponding to the current first burst length. The increase in the effective level period of the second signal Pulse_out compared to the first signal Burst_out is ODT_offset + first difference, where the first difference is the difference between the effective level period of the first signal Burst_out and the write duration corresponding to the first burst length.

[0084] After receiving the second signal Pulse_out, the shift module 1031 in the delay circuit 103 first generates a third signal CLK_align, which is aligned with the clock signal CLK. Specifically, the first valid edge of the third signal CLK_align is aligned with the valid edge of the clock signal CLK. Then, the third signal CLK_align output by the shift module 1031 is transmitted to the delay module 1032. The delay module 1032 delays the third signal CLK_align by a duration T, where T can be expressed by the following formula:

[0085] T=WL-(N+2)*2tck+ODTLon_WR_offset

[0086] Here, (N+2)*2tck can be understood as the aforementioned transmission loss. Furthermore, the loss time of the shift module 1031 and the loss time of the pulse widening circuit 102 are each 2tck, where 2tck is the duration of one clock cycle (this is only for illustrative purposes). N*2tck is the absolute delay. Therefore, the difference between the time of the first falling edge of the on-chip termination signal CMD_out and the write command reception time is WL-N*2tck+ODTLon_WR_offset. Afterwards, after the on-chip termination signal CMD_out is transmitted to the on-chip termination signal CMD_out receiver, the difference between the effective edge time of the corresponding signal (represented by the ODT_DQ pin in the figure) and the write command reception time is WL+ODTLon_WR_offset.

[0087] In some embodiments, the first duration corresponding to the first signal generated by the preprocessing circuit 101 is a fixed value of the data write duration corresponding to the second burst length; the second burst length is the minimum value among the burst lengths supported by the memory; or, the first duration is a fixed value less than the data write duration corresponding to the second burst length.

[0088] For example, the first duration of the first signal Burst_out output by the preprocessing circuit 101 is a fixed value, meaning that the duration of the effective level period corresponding to the first signal Burst_out is the same regardless of the burst length mode. This fixed value can be a value less than the data write duration corresponding to the second burst length, where the second burst length is the minimum burst length supported by the memory. For instance, assuming the memory supports burst lengths of 8 and 16, and the data write duration corresponding to a burst length of 8 is 4 tck and the data write duration corresponding to a burst length of 16 is 8 tck, then the aforementioned fixed value can be 2 tck. That is, regardless of whether the memory operates in a burst length mode of 8 or 16, the effective level period of the signal output by the preprocessing circuit 101 is always 2 tck.

[0089] Alternatively, the data write duration corresponding to the second burst length can be directly used as the first duration. For example, assuming that the burst length supported by the memory includes 8 and 16, and the data write duration corresponding to the burst length of 8 is 4tck and the data write duration corresponding to the burst length of 16 is 8tck, then the first duration can be 4tck. That is, regardless of whether the memory is working in the mode of burst length of 8 or 16, the effective level period of the signal output by the corresponding preprocessing circuit 101 is 4tck.

[0090] It is understood that in this embodiment, the first duration of the first signal finally output by the preprocessing circuit 101 is the same in multiple burst length modes. This not only increases the range of ODT_offset values ​​corresponding to the memory in multiple burst length modes, but also reduces the circuit complexity of the preprocessing circuit 101 since the preprocessing circuit 101 only needs to output one first signal.

[0091] Based on the above embodiments, Figure 8 This is a schematic diagram of another on-chip termination signal generation circuit provided in an embodiment of this disclosure. Figure 4 Based on the circuit structure shown, in this embodiment, the pulse broadening circuit 102 includes multiple first processing modules 1021 and a data selector 1022; wherein, the number of first processing modules can be the same as the number of burst lengths supported by the memory; the first processing module 1021 is used to receive a first signal and broaden the first signal to obtain a fourth signal; wherein, the width of the effective level of the fourth signal output by different first processing modules 1021 is different; the data selector is used to receive the fourth signal and an indication signal, and determine and output a second signal from multiple fourth signals.

[0092] For example, in this embodiment, when the first duration of the first signal Burst_out output by the preprocessing circuit 101 is a fixed value, and this fixed value is less than or equal to the data writing duration corresponding to the second burst length, that is, in each first burst length mode, the first duration (i.e., the fixed value) corresponding to the first signal Burst_out generated by the preprocessing circuit 101 exists with the data writing duration corresponding to the current first burst length, and the first difference is different for each first burst length, wherein the first difference can be 0. Therefore, the pulse widening circuit 102 in the on-chip termination signal generation circuit can be configured with multiple first processing modules 1021 and a data selector 1022. The first processing module 1021 is used to perform pulse widening processing on the first signal Burst_out output by the preprocessing circuit 101 and output a fourth signal. The duration of the effective level period corresponding to each first processing module 1021 is different, so as to ensure that the corresponding first processing module 1021 can be found in different first burst length modes. The effective level period of the fourth signal generated by the found corresponding first processing module 1021 is the sum of the data writing duration corresponding to the current first burst length and ODT_offset.

[0093] Furthermore, in this embodiment, the data selector 1022 can receive the fourth signals output by each of the N first processing modules 1021 and the indication signal BL_en output by the receiving preprocessing circuit 101, so as to determine the final output on-chip termination signal CMD_out based on the indication signal BL_en and the received fourth signals.

[0094] It is understood that in this embodiment, by setting the data selector 1022 and the first processing module 1021, it is ensured that the final output CMD_out meets the data write duration requirements corresponding to the burst length, thereby ensuring accurate control of the RTT state and ensuring that the memory can accurately write data.

[0095] In some embodiments, if the first burst length is greater than the third burst length, then the first duration is the data write duration corresponding to the third burst length; the third burst length is a value selected from the burst lengths supported by the memory, excluding the maximum value. If the first burst length is less than or equal to the third burst length, then the first duration is the write duration corresponding to the first burst length.

[0096] For example, in this embodiment, the preprocessing circuit 101 is used to generate a first signal Burst_out with a fixed duration for the effective level period when the current first burst length of the memory is greater than the third burst length, provided that the received control signal CMD is true. Here, the fixed value is the data write duration corresponding to the third burst length. That is, as long as the first burst length corresponding to the memory is greater than the third burst length, the duration of the effective level period generated by the preprocessing circuit 101 is always the aforementioned fixed value. Furthermore, since the first burst length is greater than the third burst length, the data write duration corresponding to the first burst length is greater than the data write duration corresponding to the third burst length. Compared to related technologies that directly use the data write duration corresponding to the first burst length as the duration of the effective level period of the generated first signal Burst_out, in this embodiment, the preprocessing circuit 101 generates a first signal Burst_out with an effective level period shorter than the data write duration corresponding to the first burst length when the first burst length is greater than the third burst length. The subsequent pulse broadening circuit 102 broadens the duration of the effective level period of the received first signal Burst_out, and the broadening width is the sum of the first difference and ODT_offset. Moreover, compared to related technologies where the value of ODT_offset can only be greater than or equal to 0, in this embodiment, ODT_offset can also be less than 0 to ensure that the sum of the first difference and ODT_offset is greater than or equal to 0. It should be noted that the third burst length in this embodiment refers to all burst lengths supported by the memory except for the largest burst length.

[0097] It is understood that the on-chip termination signal generation circuit provided in this embodiment can ensure that when the memory is working in a mode with a length greater than the third burst, the range of the preset offset ODT_offset is widened, thereby increasing the functionality of the ODT circuit and enabling the ODT circuit to be applied to more ranges of ODT_offset.

[0098] For example, assuming the memory supports burst lengths of 8 and 16, and the data write duration corresponding to a burst length of 8 is 4tck, and the data write duration corresponding to a burst length of 16 is 8tck, then the third burst length can be 8. When the memory operates in burst length 8 mode, the effective level duration of the first signal Burst_out output by the corresponding preprocessing circuit 101 is 4tck. When the memory operates in burst length 16 mode, the effective level duration of the first signal Burst_out output by the corresponding preprocessing circuit 101 is 4tck. Furthermore, the difference between the effective level width of the first signal Burst_out and the data write duration corresponding to burst length 16 is 4tck. Therefore, when the pulse widening circuit 102 performs pulse widening processing, the increase in the effective level duration is 4tck + ODT_offset.

[0099] Furthermore, in the burst length 16 mode, the range of values ​​for the corresponding ODT_offset can be found in Table 2.

[0100]

[0101] Table 2. Range of offset values ​​supported by embodiments of this disclosure

[0102] As shown in Table 2, in this embodiment of the present disclosure, compared with the offset values ​​supported in BL16 mode provided in Table 1, the value range of “X” in Table 1 in BL16 mode can also be effectively supported in this embodiment of the present disclosure, that is, the usage range of the opening offset and closing offset corresponding to the ODT control circuit is broadened.

[0103] In some embodiments, based on the above embodiments, the preprocessing circuit 101 is further configured to, if the first burst length is less than or equal to the third burst length, then the first duration is the write duration corresponding to the first burst length.

[0104] For example, in this embodiment, when the preprocessing circuit 101 receives the control signal CMD, if it determines that the first burst length corresponding to the current memory is less than or equal to the third burst length, the preprocessing circuit 101 can directly generate a first signal Burst_out with an effective level period length equal to the data write duration corresponding to the first burst length, based on the first burst length corresponding to the current memory. Then, the pulse widening circuit 102 performs widening processing on the received first signal Burst_out to ensure the accuracy of the effective level width of the finally generated on-chip termination signal CMD_out.

[0105] It is understood that the on-chip termination signal generation circuit in this embodiment can not only broaden the value range of ODT_offset when the first burst length is greater than the third burst length, but also generate the corresponding on-chip termination signal CMD_out according to the value requirements of ODT_offset specified in the protocol when the current first burst length is less than or equal to the third burst length, so as to realize the state adjustment of the on-chip termination resistor.

[0106] In some embodiments, based on the above embodiments, Figure 9 This is a schematic diagram of the circuit structure of another on-chip termination signal generation circuit provided in an embodiment of this disclosure. Figure 4 Based on the circuit structure shown, in this embodiment, the pulse widening circuit 102 includes M second processing modules 1023, one third processing module 1024, and one P-channel selector 1025; wherein, M is the total number of burst lengths supported by the memory that are greater than the third burst length; P is a positive integer greater than or equal to the sum of M and 1; the second processing module 1023 is used to receive the first signal, widen the first signal, and output the first candidate signal; the third processing module 1024 is used to receive the first signal, widen the first signal, and output the second candidate signal; the increase in the effective level width corresponding to the second candidate signal is; the P-channel selector 1025 is used to receive the first candidate signal, the second candidate signal, and an indication signal, and determine and output the on-chip termination signal CMD_out from the M first candidate signals and the second candidate signal according to the indication signal.

[0107] For example, in this embodiment, in Figure 4 Based on the circuit structure shown, under multiple different first burst lengths greater than the third burst length, the effective level period of the first signal Burst_out output by the preprocessing circuit 101 is the same, and the effective level period of the first signal Burst_out is the write duration corresponding to the third burst length. The preprocessing circuit 101 is further configured to, if it is determined that the first burst length is less than or equal to the third burst length, determine that the effective level period of the output first signal Burst_out is the write duration corresponding to the first burst length.

[0108] Among them, M second processing modules 1023 are used to receive the first signal Burst_out output by the preprocessing circuit 101, and perform pulse broadening processing on the received first signal Burst_out to obtain the first candidate signal output by the second processing module 1023.

[0109] Specifically, different second processing modules 1023 increase the width of the effective level differently when receiving the same first signal Burst_out, meaning the width of the effective level of the final output signal is different. The increase for each second processing module 1023 is the sum of a third difference and a preset offset ODT_offset. The third difference is the difference between the write duration corresponding to a burst length greater than the third burst length and the write duration corresponding to the third burst length.

[0110] In addition, the third processing module 1024 is also used to perform pulse widening processing on the received first signal Burst_out to obtain the second candidate signal, and the increase is a preset offset ODT_offset.

[0111] Furthermore, in this embodiment, the P-channel selector 1025 is used to receive the indication signal BL_en output by the preprocessing circuit 101. Under the control of the indication signal BL_en, when the first burst length is greater than the third burst length, the P-channel selector 1025 uses the second candidate signal as the final output second signal Pulse_out. And when the first burst length is less than or equal to the third burst length, the P-channel selector 1025 determines the final output second signal Pulse_out from M first candidate signals based on the indication signal BL_en. It should be noted that in this embodiment, M and P are both positive integers, and P is greater than the value of M+1.

[0112] It is understood that in this embodiment, in the pulse widening circuit 102 of the on-chip termination signal generation circuit, M second processing modules 1023 and one third processing module 1024 can be set so that the pulse widening circuit 102 can work when the first burst length is greater than the third burst length, and can also meet the situation in the related technology where only the ODT_offset needs to be widened, so as to realize the ODT function of the memory.

[0113] In some embodiments, the preprocessing circuit 101 includes a first output terminal, a second output terminal, and a third output terminal, wherein the first output terminal is used to output a first signal generated by the preprocessing circuit 101 when the first burst length is greater than the third burst length; the second output terminal is used to output a first signal generated by the preprocessing circuit 101 when the first burst length is less than or equal to the third burst length; and the third output terminal is used to output an indication signal.

[0114] For example, in this embodiment, when the preprocessing circuit 101 supports not only the output of the first signal Burst_out when the first burst length is greater than the third burst length, but also the output of the first signal Burst_out when the first burst length is less than or equal to the third burst length, the preprocessing circuit 101 can set three output terminals respectively. The first output terminal is the output port of the preprocessing circuit 101 when it determines that the first burst length is greater than the third burst length; the second output terminal is the output port of the preprocessing circuit 101 when it determines that the first signal Burst_out is less than or equal to the third burst length. Therefore, the first output terminal and the second output terminal will not output the first signal Burst_out at the same time. Furthermore, the third output terminal of the preprocessing circuit 101 can output an indication signal BL_en. It is understood that when the preprocessing circuit 101 is used, the pulse broadening circuit 102 can also determine whether the current first burst length is greater than the third burst length based on which output terminal is currently outputting the first signal. For example, when the first output terminal outputs the first signal Burst_out, the second signal Pulse_out can be selected based on the indicator signal BL_en. When the second output terminal outputs the first signal Burst_out, the pulse widening circuit 102 can directly widen the first signal Burst_out by a preset offset, thereby generating the second signal Pulse_out.

[0115] In some embodiments, Figure 10 This is a schematic diagram of the circuit structure of another on-chip termination signal generation circuit provided in an embodiment of this disclosure. Figure 4 Based on the circuit structure shown, the pulse broadening circuit 102 in this embodiment includes M fourth processing modules 1026, one fifth processing module 1027, and one K-channel selector 1028; wherein, M is the total number of burst lengths supported by the memory that are greater than the third burst length; K is a positive integer greater than or equal to M; the fourth processing module 1026 is used to broaden the first signal output from the first output terminal to obtain a third candidate signal; wherein, the increase in effective level width corresponding to different fourth processing modules is different; the fifth processing module is used to broaden the first signal output from the second output terminal to obtain a fourth candidate signal; and output the fourth candidate signal as the second signal; wherein, the increase in effective level width of the fifth processing module is a preset offset; the K-channel selector is used to receive the third candidate signals output by each of the M second processing modules, and determine and output the second signal from the M third candidate signals or control the K-channel selector to stop working according to the received indication signal.

[0116] For example, in this embodiment, based on the above embodiments, when the preprocessing circuit 101 includes three output ports, the pulse broadening circuit 102 can be configured with M fourth processing modules 1026, one fifth processing module 1027, and one K-channel selector 1028.

[0117] In this embodiment, the fourth processing module 1026 in the pulse broadening circuit 102 receives the first signal Burst_out output from the first output terminal and performs pulse broadening processing on the received first signal Burst_out. It should be noted that in this embodiment, when multiple fourth processing modules 1026 receive the same first signal Burst_out, the effective level width of their respective corresponding output third candidate signals is different; that is, the increase in the effective level corresponding to each fourth processing module 1026 is different. Furthermore, the increase in the effective level can be the sum of the third difference and the preset offset ODT_offset, where the third difference is the difference between the write duration corresponding to the first burst length and the write duration corresponding to the third burst length. The K-channel selector 1028 is used to receive the indication signal BL_en output by the preprocessing circuit 101. When the preprocessing circuit 101 determines that the first burst length is greater than the third burst length, the indication signal BL_en generated by the preprocessing circuit 101 can be used to instruct the K-channel data selector to determine the final output second signal Pulse_out from the third candidate signals output by each of the multiple fourth processing modules 1026. When the preprocessing circuit 101 determines that the first burst length is less than or equal to the third burst length, the first signal Burst_out generated by the preprocessing circuit 101 is output to the fifth processing module 1027 through the second output terminal. The fifth processing module 1027 then directly widens the preset offset ODT_offset based on the received first signal Burst_out. Furthermore, when the first burst length is less than or equal to the third burst length, the indicator signal BL_en generated by the preprocessing circuit 101 can be used to control the K-channel selector 1028 to stop working, thereby reducing circuit power consumption. In one possible implementation, when the first burst length is less than or equal to the third burst length, each of the fourth processing modules 1026 can also be controlled to stop working to avoid consuming power resources.

[0118] It is understood that in this embodiment, the preprocessing circuit 101 can provide two independent first signal output ports, namely the first output port and the second output port, so that the processing module corresponding to each output port can be set in the pulse widening circuit 102 respectively. Then, when one output port outputs the first signal, the processing module and / or selector connected to the other output port can be controlled to stop working, so as to save circuit power consumption.

[0119] This disclosure provides a memory system including a memory with on-chip termination control circuitry and an on-chip termination signal generation circuitry as provided in any of the preceding embodiments.

[0120] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0121] In the description of this disclosure, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure based on the specific circumstances.

[0122] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

[0123] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. An on-die termination signal generation circuit applied to a memory system including a memory having an on-die termination control circuit, characterized by, The on-chip termination signal generation circuit comprises a preprocessing circuit, a pulse stretching circuit and a delay circuit. The preprocessing circuit is configured to receive a control signal, output a first signal and an indication signal in response to a clock signal, wherein the control signal is used to indicate a state of adjusting a termination resistance of a data terminal, an effective level period of the first signal is a first time length, and the indication signal is used to indicate a first burst length. The pulse stretching circuit is configured to receive the first signal and the indication signal, and output a second signal, wherein a width of an effective level of the second signal is selected to be generated according to the indication signal. The delay circuit is configured to receive the second signal, perform time delay processing on the second signal, and output an on-chip termination signal, wherein the on-chip termination control circuit receives the on-chip termination signal to adjust the state of the termination resistance of the data terminal.

2. The on-chip termination signal generation circuit of claim 1, wherein, The delay circuit comprises a shift module and a delay module. The shift module is configured to receive the clock signal, perform alignment processing on the received second signal, and obtain a third signal, wherein an effective edge of the third signal is aligned with an effective edge of the clock signal. The delay module is configured to receive the third signal, perform time delay processing on the third signal, and obtain the on-chip termination signal.

3. The on-chip termination signal generation circuit of claim 1, wherein, The first time length is a fixed value of a data write time length corresponding to a second burst length, and the second burst length is a minimum value in burst lengths supported by the memory. Alternatively, the first time length is a fixed value less than the data write time length corresponding to the second burst length.

4. The on-chip termination signal generation circuit of claim 3, wherein, The pulse stretching circuit comprises a plurality of first processing modules and a data selector. The first processing module is configured to receive the first signal, perform stretching processing on the first signal, and obtain a fourth signal, wherein the fourth signals output by different first processing modules have different widths of effective levels. The data selector is configured to receive the fourth signal and the indication signal, determine a second signal from the plurality of fourth signals, and output the second signal.

5. The on-chip termination signal generation circuit of claim 1, wherein, If the first burst length is greater than a third burst length, the first time length is a data write time length corresponding to the third burst length, and the third burst length is a value selected from remaining values excluding a maximum value in the burst lengths supported by the memory.

6. The on-chip termination signal generation circuit of claim 5, wherein, If the first burst length is less than or equal to a third burst length, the first time length is a write time length corresponding to the first burst length.

7. The on-chip termination signal generation circuit of claim 6, wherein, The pulse stretching circuit comprises M second processing modules, a third processing module and a P-way selector, wherein M is a total number of values greater than the third burst length in the burst lengths supported by the memory, and P is a positive integer greater than or equal to a sum of M and 1. The second processing module is configured to receive the first signal, perform stretching processing on the first signal, and output a first candidate signal, wherein different second processing modules have different increasing amounts of effective level widths. The third processing module is configured to receive the first signal and perform a pulse stretching process on the first signal to output a second candidate signal; the second candidate signal corresponds to an effective level width that increases by a preset offset; The P-path selector is configured to receive the first candidate signal, the second candidate signal, and an indication signal, and determine and output an on-chip termination signal from the M first candidate signals and the one second candidate signal according to the indication signal.

8. The on-chip termination signal generation circuit of claim 6, wherein, The pre-processing circuit includes a first output end, a second output end, and a third output end, wherein the first output end is configured to output a first signal generated in a case where the first burst length is greater than the third burst length; the second output end is configured to output a first signal generated in a case where the first burst length is less than or equal to the third burst length; and the third output end is configured to output the indication signal.

9. The on-chip termination signal generation circuit of claim 8, wherein, The pulse stretching circuit includes M fourth processing modules, one fifth processing module, and one K-path selector; wherein M is a positive integer greater than or equal to the total number of burst lengths supported by the memory and greater than the third burst length; and K is a positive integer greater than or equal to M. The fourth processing module is configured to perform a pulse stretching process on the first signal output by the first output end to obtain a third candidate signal; wherein the increase in the effective level width corresponding to different fourth processing modules is different. The fifth processing module is configured to perform a pulse stretching process on the first signal output by the second output end to obtain a fourth candidate signal; and output the fourth candidate signal as a second signal; wherein the increase in the effective level width of the fifth processing module is a preset offset. The K-path selector is configured to receive the third candidate signals output by the M fourth processing modules respectively, and determine and output a second signal from the M third candidate signals or control the K-path selector to stop working according to the received indication signal.

10. A memory system, characterized by, The memory includes an on-chip termination control circuit and the on-chip termination signal generation circuit according to any one of claims 1-9.

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